Sie sind auf Seite 1von 5

1/5 www.interlockroc.org/wiki/index.php?

title=FT-8800R_tech_documentation&printable=yes
FT-8800R tech documentation
From Interlock Rochester Wiki
Contents
1 Links
2 Technical
2.1 Pinouts
3 Protocol
3.1 Head unit packet
3.2 Main unit Packet
4 Documentation
Links
FT-8800R Product Page (http://www.yaesu.com/indexVS.cfm?
cmd=DisplayProducts&ProdCatID=106&ProdID=873&DivisionID=65&isArchived=0)
Technical
Pinouts
6P6C Main Unit to Panel Unit Pinout
Pin Name Description
1 MOD Buffered Modulation (AF) Input (~2.2k source impedance)
2 POWERSWActive-low (pulled through 1K resistor) momentary power switch signal
3 9V 9VDC regulated supply voltage for Panel Unit
4 GND Ground
5 RXD Head unit Asynchronous serial (19.2 kbps 8N1) Receive
6 TXD Head unit Asynchronous serial (19.2 kbps 8N1) Transmit
6P6C Panel Unit microphone connector
Pin Name Description
1 SW2 Matrix keypad column input
2 SW1 Matrix keypad row input
3 9V 9VDC regulated supply voltage
4 GND Ground
5 MIC Electret microphone audio input
6 PTT Active-low push-to-talk switch
Protocol
Head unit packet
The head unit continuously sends a 13-octet packet to the main unit, with a brief delay between each packet. Testing confirms that if this packet is
not sent for some time (on the order of 1s), the main unit shutsdown. This "watchdog" basically activates if something were to break
2/5 www.interlockroc.org/wiki/index.php?title=FT-8800R_tech_documentation&printable=yes
communication between the head unit and the main unit. Although the raw line coding of the packet is with 8-bit data words, display information is
only encoded in the lower 7-bits of each word. The MSb is used as the synchronization bit and is 1 in the first octet only.
The head unit sends a fairly raw representation of the input switches and dials. It does not seem to do any high level processing. The packet
contains no CRC or any bits dependent on other bits outside of a single function group.
Except for the hyper-memory keys, the keypads are implemented with matrix multiplexing and/or resistor dividers. The head unit uses an ADC
and seems to pass these counts unmodified to the main unit which must deal with range checking. The specified count values below were recorded
with an actual unit, but it should be obvious what the "nominal" values are, and since the resistor dividers are on the schematic, it is easy to cross-
check.
Measured parameters
Parameter (Unit) Description Value
Communication Asynchronous communication 19.2 kbps 8-N-1 (8 data bits, no parity, 1 stop bit)
Head unit update period (ms)
Time between start of panel unit
TX packet to start of next packet
TBD (on order of 20)
Main unit update period (ms)
Time between start of main unit
TX packet to start of next packet
TBD (on order of 40)
Watchdog Time (s)
Minimum time between last update packet
from panel unit and when main unit shutdowns (powers off)
TBD
Panel Unit packet structure
Octet 0 1 2 3 4 5 6 7
0
Left encoder count since update
(2's complement - CW is positive)
SBO
1
Right encoder count since update
(2's complement - CW is positive)
SBZ
2
PTT input ADC
7Fh ~ PTT disabled
1Bh ~ PTT enabled
SBZ
3 Right squelch ring ADC (7Fh: open squelch) SBZ
4 Right volume control ADC (7Fh: max volume) SBZ
5
SW1 keypad matrix row ADC
00h: 1-A
1Ah: 4-B, UP
32h: 7-C, DOWN
4Ch: *-D
64h: P1-P4
7Fh: inactive
SBZ
6 Left squelch ring ADC (7Fh: open squelch) SBZ
7 Left volume control ADC (7Fh: max volume) SBZ
SW2 keypad matrix column ADC
06h: UP/DWN
1Bh: 1-*,P1
3/5 www.interlockroc.org/wiki/index.php?title=FT-8800R_tech_documentation&printable=yes
8 33h: 2-0,P2
4Ch: 3-#,P3
67h: A-D,P4
7Fh: inactive
SBZ
9
Panel right-side (multiplexed) buttons
00h: SCN
20h: HM
40h: V/M
60h: LOW
7Fh: none
SBZ
10
Panel left-side (multiplexed) buttons
00h: LOW
20h: V/M
40h: HM
60h: SCN
7Fh: none
SBZ
11 RENCB LENCB SET key WIRES SBZ
12
Hyper-memory key
00: No key
01-06: hyper selection
Main unit Packet
The main unit continuously sends a 42-byte packet to the panel unit. This packet essentially contains a raw bitmap indicating what LCD display
segments should be illuminated. There seems to be no other higher level coding included in this packet. Although the raw line coding of the packet
is with 8-bit data words, display information is only encoded in the lower 7-bits of each word. The MSb is used as the synchronization bit.
Testing confirms there is no CRC or other dependent bits in the packet. Each bit has been demonstrated to be independent. Although the main
unit will only activate segments in certain ways, the panel is essentially a dumb terminal and will accept any type of bitmap combination.
The following table maps the "Yaesu" natural order assignments to one of the "conventional" 14-segment pin assignments. It should be noted that
the Yaesu assignments were not per any Yaesu documentation and simply chosen in alphabetic order based on the ordering of bits in the control
packet. The "conventional" ordering is based on LED segment datasheets. There is another assignment nomenclature that uses G1, and G2 for the
horizontal segments. Unlike with the 7-segment case there doesn't seem to be any prevailing standard that is near universal. The third column maps
bits. The bit assingment is based on numbering the Yaesu case in order, but skipping the unused 8th bits in each byte, but including the unused bits
that are used for other segments, since those form a regular pattern in every case. The last column (Rep 2) is a simple ordering from 0 to n.
Segment Mapping Table
Current NewPacket bit Rep 1 Rep 2
A C 0 2 0
B J 1 8 1
C B 2 1 2
D H 3 7 3
E A 4 0 4
F N 5 12 5
G P 6 13 6
H K 8 9 7
I D 9 3 8
4/5 www.interlockroc.org/wiki/index.php?title=FT-8800R_tech_documentation&printable=yes
The 14-segment
display segment
assignments as seen
in the update packet
structure
J G, L 10 6, 10 9
K M 12 11 10
L E 13 4 11
M F 14 5 12
.
Packet definitions
Signal Description
Most segments are duplicated on left-and-right (indicated by subscript)
Digits are numbered least-significant to most significant (right to left)
starting at 0.
The 14-segment displays used only have 13 addressable segments. There is only one
addressable vertical segment.
F Frequency/Alpha 14-Segment displays
C Channel 7-segment displays
SM S-Meter segments (right-to-left)
BUSY Busy channel indicator
MAIN "Main" Band indicator
PMS Preferential Memory Scan Flag (Left-pointing arrow)
SKIP Skip Memory channel flag
ENC Tone encoder flag
DEC Tone decoder flag
DCS Digital Code Squelch flag
9600 9600bps Packet mode flag
PL Low TX Power flag
PM Medium TX Power flag
TX Transmitter active flag
SET Set mode active flag
LOCK Keypad lock flag
APO Auto power-off enable flag
PLUS Plus repeater shift flag
MINUS Minus repeater shift flag
Main Unit packet structure
Octet 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 U? APO PM
L
F
L
.0.DP SM
L
.8 F
L
.0.A FL
L
.0.B SBO F
L
.0.C F
L
.0.D F
L
.0.E F
L
.0.F F
L
.0.G PL
L
F
L
.0.H SBZ
2 F
L
.0.I F
L
.0.J SM
L
.7 F
L
.0.K F
L
.0.L F
L
.0.M SM
L
.6 SBZ F
L
.1.A F
L
.1.B F
L
.1.C F
L
.1.D F
L
.1.E F
L
.1.F F
L
.1.G SBZ
4 9600
L
F
L
.1.H F
L
.1.I F
L
.1.J SM
L
.5 F
L
.1.K F
L
.1.L SBZ F
L
.1.M SM
L
.4 F
L
.2.A F
L
.2.B F
L
.2.C F
L
.2.D F
L
.2.E SBZ
6 F
L
.2.F F
L
.2.G AM F
L
.2.H F
L
.2.I F
L
.2.J SM
L
.3 SBZ F
L
.2.K F
L
.2.L F
L
.2.M U? U? U? U? SBZ
8 F
L
.3.DP A? SM
L
.2 F
L
.3.A F
L
.3.B F
L
.3.C F
L
.3.D SBZ F
L
.3.E F
L
.3.F F
L
.3.G DCS
L
F
L
.3.H F
L
.3.I F
L
.3.J SBZ
10 SM
L
.1 F
L
.3.K F
L
.3.L F
L
.3.M SM
L
.0 F
L
.4.A F
L
.4.B SBZ F
L
.4.C F
L
.4.D F
L
.4.E F
L
.4.F F
L
.4.G MUTE
L
F
L
.4.H SBZ
12 F
L
.4.I
F
L
.4.J BUSY
L
F
L
.4.K F
L
.4.L F
L
.4.M MT
L
SBZ
F
L
.5.A F
L
.5.B F
L
.5.C F
L
.5.D F
L
.5.E F
L
.5.F F
L
.5.G
SBZ
14 U? F
L
.5.H F
L
.5.I F
L
.5.J U? F
L
.5.K F
L
.5.L SBZ F
L
.5.M U? U? U? U? U? U? SBZ
16 U? U? PM
R
F
R
.0.DP SM
R
.8 F
R
.0.A FL
R
.0.B SBZ F
R
.0.C F
R
.0.D F
R
.0.E F
R
.0.F F
R
.0.G PL
R
F
R
.0.H SBZ
18 F
R
.0.I F
R
.0.J SM
R
.7 F
R
.0.K F
R
.0.L F
R
.0.M SM
R
.6 SBZ F
R
.1.A F
R
.1.B F
R
.1.C F
R
.1.D F
R
.1.E F
R
.1.F F
R
.1.G SBZ
20 9600
R
F
R
.1.H F
R
.1.I F
R
.1.J SM
R
.5 F
R
.1.K F
R
.1.L SBZ F
R
.1.MSM
R
.4 F
R
.2.A F
R
.2.B F
R
.2.C F
R
.2.D F
R
.2.E SBZ
5/5 www.interlockroc.org/wiki/index.php?title=FT-8800R_tech_documentation&printable=yes
22 F
R
.2.F F
R
.2.G DCS
R
F
R
.2.H F
R
.2.I F
R
.2.J SM
R
.3 SBZ F
R
.2.K F
R
.2.L F
R
.2.M U? U? U? U? SBZ
24 F
R
.3.DP A? SM
R
.2 F
R
.3.A F
R
.3.B F
R
.3.C F
R
.3.D SBZ F
R
.3.E F
R
.3.F F
R
.3.G MUTE
R
F
R
.3.H F
R
.3.I F
R
.3.J SBZ
26 SM
R
.1 F
R
.3.K F
R
.3.L F
R
.3.M SM
R
.0 F
R
.4.A F
R
.4.B SBZ F
R
.4.C F
R
.4.D F
R
.4.E F
R
.4.F F
R
.4.G MT
R
F
R
.4.H SBZ
28 F
R
.4.I F
R
.4.J BUSY
R
F
R
.4.K F
R
.4.L F
R
.4.M KEY2 SBZ F
R
.5.A F
R
.5.B F
R
.5.C F
R
.5.D F
R
.5.E F
R
.5.F F
R
.5.G SBZ
30 SET F
R
.5.H F
R
.5.I F
R
.5.J LOCK F
R
.5.K F
R
.5.L SBZ F
R
.5.MU? U? U? U? U? U? SBZ
32 MAIN
R
TX
R
PLUS
R
MINUS
R
ENC
R
DEC
R
PMS
R
SBZ SKIP
R
C
R
.0.C C
R
.0.B C
R
.0.G C
R
.0.AC
R
.0.E C
R
.0.F SBZ
34 C
R
.0.D C
R
.2.DC
R
.1.C C
R
.1.B C
R
.1.GC
R
.1.A C
R
.1.E SBZ C
R
.1.F C
R
.1.D C
R
.DSHC
R
.2.C C
R
.2.B C
R
.2.G C
R
.2.ASBZ
36 C
R
.2.E C
R
.2.F MAIN
L
TX
L
PLUS
L
MINUS
L
ENC
L
SBZ DEC
L
PMS
L
SKIP
L
C
L
.0.C C
L
.0.B C
L
.0.G C
L
.0.A SBZ
38 C
L
.0.E C
L
.0.F C
L
.0.D C
L
.2.D C
L
.1.C C
L
.1.B C
L
.1.G SBZ C
L
.1.A C
L
.1.E C
L
.1.F A? U? U? U? SBZ
40 U? U? C
L
.2.C C
L
.2.B C
L
.2.G C
L
.2.A C
L
.2.E SBZ C
L
.2.F DISPB0 DISPB1 DISPB2 U? U? U? SBZ
Documentation
Operations Manual (http://luebsphoto.com/files/FT-8800R_USA_EXP_OM_ENG_EH018M100.pdf)
Retrieved from "http://www.interlockroc.org/wiki/index.php/FT-8800R_tech_documentation"
This page was last modified on 28 November 2011, at 08:14.

Das könnte Ihnen auch gefallen