1

USMAN INSTITUTE OF TECHNOLOGY

HAMDARD UNIVERSITY
DEPARTMENT OF ELECTRICAL ENGINEERING
VLSI DESIGN (EE-411)
SPRING-2014
Engr. Zohaib Jawaid
Engr. Kashif Ali Arshad
Engr. S. Aimen Naseem
Engr. Sameer Ahmad
EXPERIMENT # 01: Introduction to FPGA (Spartan 3E) and VERILOG
Name of Student: _____________________________________________________________
Roll No.: _________________________________Group:_____________________________
Date of Experiment : _____________________________________________
Report Submitted on : _____________________________________________
Marks Obtained : ______________________________________________
Remarks if any : ______________________________________________
Signature : _____________________________________________
2
INTRODUCTION TO FPGA (SPARTAN 3E)
Overview:
FPGA (SPARTAN 3E) is a complete, ready-to-use circuit development platform based on a Xilinx
Spartan 3E FPGA. Its onboard high-speed USB2 port, 16Mbytes of RAM and ROM, and several
I/O devices and ports make it an ideal platform for digital systems of all kinds, including
embedded processor systems based on Xilinxs Micro Blaze. The USB2 port provides board
power and a programming interface, so the Nexys2 board can be used with a notebook computer
to create a truly portable design station It can host countless FPGA-based digital systems, and
designs can easily grow beyond the board using any or all of the five expansion connectors. Four
12-pin Peripheral Module (Pmod) connectors can accommodate up to eight low-cost Pmods to
add features like motor control, A/D and D/A conversion, audio circuits, and a host of sensor and
actuator interfaces
Features:
500K-gate Xilinx Spartan 3E FPGA
USB2-based FPGA configuration and high-speed data transfers (using the free Adept
Suite Software)
USB-powered (batteries and/or wall-plug can also be used)
16MB of Micron PSDRAM &16MB of Intel Strata Flash ROM
Xilinx Platform Flash for nonvolatile FPGA configurations
Efficient switch-mode power supplies (good for battery powered applications)
50MHz oscillator plus socket for second oscillator
60 FPGA I/Os routed to expansion connectors (one high speed Hirose FX2 connector
and four 6-pin headers)
8 LEDs, 4-digit 7-seg display, 4 buttons, 8 slide switches
Ships in a plastic carry case with USB cable
3
User I/O
The Nexys2 board includes several input devices, output devices, and data ports, allowing many
designs to be implemented without the need for any other components.
Inputs: Slide Switches and Pushbuttons
Four pushbuttons and eight slide switches are provided for circuit inputs. Pushbutton inputs are
normally low, and they are driven high only when the pushbutton is pressed. Slide switches
generate constant high or low inputs depending on their position. Pushbutton and slide switch
inputs use a series resistor for protection against short circuits (a short circuit would occur if an
FPGA pin assigned to a pushbutton or slide switch was inadvertently defined as an output).
Pin Configuration:
4
5
INTRODUCTION TO VERILOG:
In electronics, a hardware description language or HDL is any language from a class of
computer languages for formal description of electronic circuits. The two most widely-used and
well-supported HDL varieties used in industry are:
VERILOG
VHDL
VERILOG is a HARDWARE DESCRIPTION LANGUAGE (HDL). A hardware description
language is a language used to describe a digital system: for example, a network switches, a
microprocessor or a memory or a simple flip-flop. This just means that, by using a HDL, one can
describe any (digital) hardware at any level. VERILOG is used by several companies in the
commercial chip design and manufacturing sector today. VERILOG allows a designer to develop
a complex hardware system, e.g., a VLSI chip containing millions of transistors, by defining it at
various levels of abstraction
Simulation and Synthesis
Simulation tools typically accept full set of VERILOG language constructs.
Synthesis tools typically accept only a subset of the full VERILOG language constructs.
Modules
Modules are basic building blocks of VERILOG. Description of the logic being modeled is
placed inside modules. Module definition starts with keyword module. Ends with the keyword
endmodule.
For Example Module is declared: Module dff (q,qn,d,clk)
Modules communicate with the outside world through ports. Module port is similar to pins in
hardware.
Nets
Nets represent connections between hardware elements. Just as in real circuits, nets have values
continuously driven onto them by the outputs of devices that they are connected to. net a is
connected to the output of and gate. Net a will continuously Assume the value computed at the
output of gate g], which is b anded with c. Nets are declared primarily with the keyword wire.
Nets are one-bit values by default unless they are declared explicitly as vectors. The term wire
and net are often used interchangeably. The default value of a net is z. Nets get the output value.
of their drivers. If a net has no driver, it gets the value z.
Example
Wire a; // Declare net a for the above circuit
Wire b, c; //Declare two wires b, c for the above circuit
Wire d = 'b0; // Net d is fixed to logic value 0 at declaration
6
SOFTWARE INTRODUCTION:
Steps for Configuration:
STEP 1:
To create a New Project
Select File > New Project. The New Project Wizard appears.
STEP 2:
Type tutorial or any other name in the Project Name field.
Verify that HDL is selected from the Top Level Source Type list
Enter or browse to a location for the new project. A tutorial subdirectory is created
automatically
7
STEP 3: Add New Source
STEP 4: Select VERILOG Module and Enter File Name and specify its location
8
STEP 5: Assign input and output variables
STEP 6: Summary
STEP 7: Click on Next
for n # of inputs
9
STEP 8: Summary
STEP 9: Project is now created
STEP 10: write desired program in .v file and save it
Program here
10
STEP 11:in user constraint click create area constraints to assign pin locations
11
STEP 12:
Click to synthesize- XST to check program.
click on implement design
click Generate Programming file in the .bit format
12
DIGILENT ADEPT
Digilent Adept is a powerful application which allows for configuration and data transfer with
Xilinx logic devices.
It Configure the Xilinx logic devices and Initialize a scan chain, program FPGAs, CPLDs, and
PROMs, organize and keep track of your configuration files. It also used to Transfer data and
from the onboard FPGA on your system board. It Organize and quickly connect to your
communications modules.
STEP 13:
following first figure of this step indicate when no device is connected.
Connect Device and Click Browse option of FPGA block
STEP 14: Browse Project and select .bit file then click Program.
Device connected
13