PS2 Keyboard interface circuit in Verilog

Hi I have written a code in Verilog for interfacing PS2 keyboard to FPGA

it seems to work fine on ModelSim but I am not very good at designing testbe
nches
I am uploading my code here please see it and give your suggestions
If you have a test bench for checking PS 2 Keyboard interface code please cr
oss check my code against it and share
Logic
Design : PS2 Keyboard
1
S. Yoder ND
,
2013
CSE 20221: Logic Design
PS/2 Keyboard Protocol
Interface to the
Basys
Board
Logic
Design : PS2 Keyboard
2
S. Yoder ND
,
2013
Basys
Board
pin assignments
Logic
Design : PS2 Keyboard
3
S. Yoder ND
,
2013
Basys
Board Connector

The Basys Board can interface to either a mouse

or keyboard
Logic
Design : PS2 Keyboard
4
S. Yoder ND
,
2013
PS/2 I/O Signals

clock
: used for synchronization to indicate when
data is valid.

Bidirectional, i.e., from keyboard to host or vice versa

Data
:

From keyboard: 8
-
bit (byte)
scan code
to indicate
which key was pressed.

From host: keyboard configuration commands

In this course we will only consider the direction

from keyboard to host.
Logic
Design : PS2 Keyboard
5
S. Yoder ND
,
2013
PS/2 Timing Specifications
Logic
Design : PS2 Keyboard
6
S. Yoder ND
,
2013
Signal Protocol
0
1
2
3
4
5
6
7
8
9
10
clk
start
bit
d0
d1
d2
d3
d4
d5
d6
d7
parity
bit
stop
bit
LSB
MSB
Notes
data is valid on negative edge of clock
clock frequency: 20

30 Khz
parity is odd
scan code
Logic
Design : PS2 Keyboard
7
S. Yoder ND
,
2013
Scan Codes in Hex
Logic
Design : PS2 Keyboard
8
S. Yoder ND
,
2013
Sequence of Events

key pressed: 11
-
bit code is sent

start bit, 8
-
bit scan code, odd parity bit, stop bit

key
released: two 11
-
bit codes are sent

first scan code is FO

second scan code is the released key code

key held down: 11

-
bit code sent every 100
ms.

scan code is pressed key code

Logic
Design : PS2 Keyboard
9
S. Yoder ND
,
2013
Scan Codes in Hex
Logic
Design : PS2 Keyboard
10
S. Yoder ND
,
2013
Example: key d is pressed
0
1
2
3
4
5
6
7
8
9
10
clk
start
bit
d0
d1
d2
d3
d4
d5
d6
d7
parity
bit
stop
bit
LSB
MSB
scan code
scan code for d = 23
10
= 00100011
2
1 1 0 0 0 1 0 0 0
Logic
Design : PS2 Keyboard
11
S. Yoder ND
,
2013
Additional Events

Shift, Caps Lock, Ctrl: scan code is sent like any

other key, host must keep track of the mode.

Extended keys: E0 is sent, followed by the scan

code. When an extended key is released, EO FO
is sent.
Logic
Design : PS2 Keyboard
12
S. Yoder ND
,
2013
Design Process Steps
1.
Identify inputs and outputs and describe their function.
2.
Write a functional (behavioral) description that incorporates the I/O.
3.
Sketch a block diagram of the system. This should include the FSM controller
and all interacting signals, modules and hardware devices

this is the
architecture.
4.
Identify all the unique states. Refer to the functional description to help iden
tify
the different states
5.
Draw the state diagram(s). There may be multiple FSMs.
6.
Write the Verilog modules for each block identified in step 3.
7.
Verify consistency between the Verilog description and the documentation
generated in steps 1

5.
8.
Write test benches for each module.
9.
Simulate and verify correct functionality.
10.
Make necessary design changes.
11.
Integrate the module in a
top
-
level module
and repeat steps 8

10.
12.
Implement the prototype and verify and validate the design.
Logic
Design : PS2 Keyboard
13
S. Yoder ND
,
2013
Block Diagram
Keyboard
keyClk
data
11
-
bit shift register
8
-
bit data register
d0
d7
System
Controller
scan code
d0
d7
sysClk
bitcounter
clear
load
d0 ... d7
reset
TC
Logic
Design : PS2 Keyboard
14
S. Yoder ND
,
2013
System Controller States

Initial

reset counter, wait for start bit

Start

enable counter, shift in data, wait for stop bit

CheckCode

evaluate scan code for FO

must eventually consider EO and special keys like shift

SaveCode

load scan code into register

ReadCode

code is read by display driver and displayed on seven

-
segment
display
Logic
Design : PS2 Keyboard
15
S. Yoder ND
,
2013
System Controller State Diagram
Initial
Start
C
heck
Code
Save
Code
load
TC
(terminal count)
FO
!FO
ClearCounter
Reset
startBit
CodeRdy
This diagram is not guaranteed to be correct
Read
Code
note: scan code == F0
when key is released
EnableCounter
Logic
Design : PS2 Keyboard
16
S. Yoder ND
,
2013
Handling Scan Code on Key Released

In the previous state diagram the second sending of the scan code
for the key when it is released is left up to external circuitry to handle.

The following two slides include additional states for handling FO and
the repeat of the scan code for the key that is released.
Logic
Design : PS2 Keyboard
17
S. Yoder ND
,
2013
Alternative Approach for Key Released

Initial

reset counter, wait for start bit

Start

enable counter, shift in data, wait for stop bit

checkCode

evaluate scan code for FO

must eventually consider EO and special keys like shift

SaveCode

load scan code into register

keyUp

ignore FO on key released

keyPressed

indicate scan code is ready for key that was pressed

Ignore

ignore scan code that occurs after FO on key released

Logic
Design : PS2 Keyboard
18
S. Yoder ND
,
2013
System Controller State Diagram
Initial
Start
C
heck
Code
Save
Code
load
TC
(terminal count)
FO
keyUp
set KeyedUp
!
KeyedUp & !FO
ClearCounter
Reset
startBit
key
Pressed
CodeRdy
This diagram is not guaranteed to be correct
ignore
clr KeyedUp
KeyedUp
EnableCounter
Logic
Design : PS2 Keyboard
19
S. Yoder ND
,
2013
set/reset flip
-
flop implementation
Logic
Design : PS2 Keyboard
20
S. Yoder ND
,
2013
set/reset testbench
Simulation Results
Note that set has priority over reset.
Refer to code to see why.
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