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TECHNICAL PUBLICATION
Topology Planning and Routing
Dean Wiltshire, SDD product architect - Mentor Graphics Corporation
September 2006
PROBLEM STATEMENT
This paper discusses the disconnect between the
digital design engineers vision of bus structures on
the PCBs and the failure of tools to capture and route
this vision in an efficient manner.
HISTORICAL BACKGROUND
Bus Structure Vision
For digital designs of PCBs, there has never been a
complete set of design tools to capture the engineers
vision for bus structures and their flow between
associated components. The most common way to
communicate the vision seems to be a paper sketch of
the bus structure, representing associated
components and trace routing.
Routing the Vision
Historically, auto routing algorithms are based on
routing with layers bias a golden rule initially
established when through-hole components
dominated. While these layer bias algorithms
elegantly embrace todays dense surface mount
device (SMD), they are still layer biased and are
unable to lend themselves to matching the engineers
vision of packed bus traces flowing in non-bias
directions between associated components.
There are two choices for routing a PCB: By hand or
auto-route. In order to follow the paper sketch, routing
is traditionally done by hand. Hand routing provides
the greatest level of control and is preferred by most
designers since it tends to use fewer vias and
potentially fewer layers. However, hand routing a
PCB can take weeks to months to complete.
The other choice, auto routing, can yield faster results.
However, while placement may have followed the
engineers sketch, theres no way to communicate this
sketch to the auto-routers. And if there were, auto-
routers are not designed to follow meandering, 64-bit
wide paths with an objective of keeping the bus traces
together. Todays auto-routers would route the bus but
with layer bias, longer trace lengths, more vias,
possibly more layers and without keeping the bus
traces together.
Finally, the auto-router may not complete all the
signals, leaving the designer to complete the
remaining connections by hand. These last
connections can be a challenge and erode the
schedule advantages of auto-routing, therefore, to
truly capture the engineers vision, time consuming
hand routing is deployed with the undesirable, added
schedule impact.
PLANNING
While designing and capturing the logic, the engineer
has envisioned the bus structure and its relationship
among the components. This vision is considered
Intellectual Property (IP), typically a very valuable
asset to their organization. The problem is capturing
this IP.
Often, engineers attempt to capture and communicate
this IP in a word document or on a paper napkin.
While many aspects of Electronic Design Automation
(EDA) are, in fact, automated, this process has not
had effective tool support. A hand drawing on a
napkin has been the most efficient to date!
While quick, the napkin may or may not physically
map to the PCB. This is a problem because of size
issues, such as width of the physical bus,
mechanical parameters of the card,
physical size and pin outs of components.
Therefore, the original IP may be
completely invalid because it is physically
impossible to follow; EDA tools must not
only replace, but also improve upon the
napkin! They must effectively capture the
IP and communicate accurate,
usable/reusable IP throughout the design
process.
PAGE 1
Figure 2: Shows historical auto-route results on the left and desired routing on the
right.
Figure 1: Shows an example of a typical Engineering sketch of a
bus structure.
TOPOLOGY PLANNING
Topology Planning is a new tool from Mentor Graphics
which allows the engineer to define and capture their
bus structure vision and effectively communicate it
throughout the PCB design. To effectively plan bus
structures, they must first be logically defined. Bus
definitions can come forward from captured logic in the
schematic and/or bus definitions defined within a
constraint editor. With buses defined, the design is
ready for Topology Planning, using:
Actual card outline
Correctly represented components
Board stack-up
True logical/physical representation of buses
This information allows for an efficient, accurate bus
structure planning, allowing the valuable IP to be
captured and followed throughout the design flow.
The placement of components affects the bus
structure and the bus structure affects the placement
of components. Therefore, Topology Planning
supports the placement of components by defined
buses. During placement, designers can filter and
place those components that share a bus, as shown in
Figure 4. By selecting a bus, the component list is
filtered to include unplaced and/or placed components
associated to the selected bus name. It is important to
understand that the placement of components and
drawing bus paths work in any order, so the engineer
or designer can fit their preference on which to do first.
As they draw their bus paths, designers create order in
the placement and are able to visually see and dictate
how the bus is routed. Designers can draw their bus
paths with a few key components placed, all
components placed or no components placed. These
tools are designed to aid them with flexibility, not force
a procedure.
Net lines show the connections between component
pins and are used to place components. Net lines
provide real-time feedback of component connections
to associated components. As more components are
placed, more net lines are brought into the display.
For complex designs, the density, overlapping and
twisting of net lines can cause more confusion than
guidance. Topology Planning provides a solution by
offering the display of net lines from drawn buses to
components. The results are a clear representation of
buses to components relationships.
PAGE 2
Figure 3: The P in the bus path represents a packed bus,
meaning; the routed traces are as compressed as possible and
follow these paths, on the specified layers.
Figure 4: U1002 is being placed from bus PCI2. Note the netlines
render to a PCI2 bus path and component pins.
Figure 5: Shows a general flow of interconnects between
components. Topology Planning provides a better understanding
the relationship between groups of signals and their components.
Topology Planning guides the actual auto routing of
the buses and is rich in capability. Most of these
capabilities are found in the Bus Path dialog, shown in
Figure 6.
To begin with, the Bus
Path dialog lists each
bus, its number of bits
and supports the
creation of bus paths.
Sorting is allowed on
bus names and bits. As
a bus is selected in the
dialog, the component
pins and netlines of that
bus are highlighted for
the placed components,
existing bus paths and
areas.
With the selected bus
name also comes the
option of draw found
on action key F3. By
default, the Bus Path
dialog offers drawing of
a packed bus on the
active signal layer and
of the complete bit
count of the bus.
Before or during the
drawing of the bus path,
the options for layer, bit
count (not to exceed the
total bits) or the path
type maybe changed.
Using the Display Dialog, the designer can select the
desired layer and draw horizontal, vertical or 45
degree bus paths. While drawing, the user can
change layers, or change the bit count to represent
the necking up/down of a bus path or support bus
splits. As mentioned, packed bus paths are the
default, yet the designer has the option to specify tune
bus paths or unpacked areas.
With a click on the design, the drawing of the bus
paths is started. A second click creates a bus path
segment. The width of the bus path accurately
represents the bit counts, trace widths and clearances.
With respect for impedance parameters, the width of
the Bus Path may change depending on the layer
where it is drawn.
To change layers while drawing a bus, simply click a
different signal layer and keep drawing. Of course this
layer change represents the need for the bus to
change layers and therefore, inserts as many vias as
there are bits.
The drawing of bus paths is not restricted by layer
bias rules. Bus paths guide the Topology Router
without regard to layer bias. This provides guidance
and flexibility to address densities for different sections
of a PCB.
Why stay with the typical layer bias of every other
layer horizontal in this area? There is likely wasted
space on these horizontal layers. With Topology
Planning, this corner can be optimally organized
without having negative ramifications in other areas of
the PCB.
Bus paths may accommodate any count of bits up to
the total defined in the bus. This provides great
flexibility in planning the bus structures. For example,
while drawing a 64-bit bus the decision was made to
split into two 32-bit paths and put them on different
layers. At any point, these bus paths can be merged
into a larger bus path, or further reduced to smaller bit
count buses.
PAGE 3
Figure 6: The Bus Path dialog
offers information and control over
drawing Bus Paths and Areas.
Figure 7: Shows that the upper left corner of the PCB has mostly
vertical interconnects.
To continue the example, one of the 32-bit bus paths
was split into two 16-bit paths. This was done to
efficiently connect to a BGA.
Tune
The next option to discuss is the bus path type of
tune. An entire bus path or one to many segments
can be identified as tune. These bus paths segments
are where delay tuning occurs along the bus path.
The engineer specifies where tuning delays are
routed. Delays are specified as a constraint and,
whether they are for a single bit or all bits in a bus
path, they are tuned within the tune bus path
segments.
Unpacked Bus Areas
Not all bus structures will fit into a packed bus
path option. If, for example, there are two
BGAs close together that share a 64-bit bus,
there may not be enough room to compress all
the connections
from one BGA
into a packed
bus path before
decompressing
to connect to
the other BGA.
In this scenario
it is better to go
with an
unpacked area for the
bus. An unpacked
area doesnt
dictate a packed
structure. Instead,
it specifies layers,
layer bias per
selected layer
and area for the
selected bus bits
to route.
PAGE 4
Figure 10: Shows T bus path segments planned and then tune delay
from the Topology Router.
Figure 8: Shows Topology Planning and Routing supporting this and other
complex structures.
Figure 9: Shows the split of a 16-bit
bus into two 8 bits bus paths followed by Topology Routing results.
Figure 11: The left image of Figure
11 shows a 64-bit unpacked bus
area being planned, including layer
and bias selection per layer. The
right image shows the Topology
routing results.
Netline Assignments
By default, netlines spanning from buses use the
Minimum Spanning Tree (MST) algorithm to determine
which nets are assigned to a bus path. If the drawn
bus is issuing fewer bits than the overall bit count,
MST may not the desired netlines. To supply the
necessary control, the Netline assignment capability
is provided on action key F12. When selected the
display is reduced to just the bus, all the associated
component pins and netlines as shown in Figure 12.
Select the component pin and the desired bus path
and the netline is assigned to the path and another
netline is swapped out. Automatically, there are no
more netlines assigned to the bus path than the bit
count associated to the bus path.
Planning to Prevent Cross Talk
Topology Planning and Routing removes the overriding
layer bias rules inherent with typical auto-routers.
While routing can lead to more efficient interconnects,
it can also lead to increased crosstalk problems
between signals. Long, straight parallel runs of signals
with minimum clearance can lead to poor signal
performance. To combat this problem, those victim
and aggressor signals should be separated from one
another. This is done by either establishing enough
space between the parallel signals to prevent one
signal influencing the performance of another or route
a ground signal in between the two.
Rather than trying and find space after the
interconnects are completed, it is better to plan to
prevent crosstalk before routing is started. Otherwise,
the necessary space for a spacer or ground signal
may not be available for a completely routed PCB.
Furthermore, when Topology Routing is complete,
routing of shielding includes wrapping the end caps of
bus traces as they change layers. In figure 13, the
green traces represent the shielding traces.
Additionally, the shielding traces follows the traces up
to the component pins and if needed, also drop vias
along the shielding route to the ground plane with a
specified frequency.
Target Areas
Target Areas are a useful for both Topology Planning
of buses and managing non-bus connections. For bus
planning, there are scenarios where the bus path may
connect to component pins before desired.
A target area is associated to the desired bus
component pins and tells the auto-router that it must
route from the component pins to the layer specific
target area. When the target area is placed on or near
the bus path, then the bus is routed to target area, not
the component pins.
Figure 12: When Netline assignment is selected the display is
reduced to just the bus, all the associated component pins and
netlines, allowing for a focused effort to optimize the netlines to bus
paths.
PAGE 5
Figure 13: A bus path can be planned and drawn with a width to
include shielding as specified for the bus path in the Bus Path
dialog.
Figure 14: A Bus path on layer 2 (pink) passing the related
component pins and tying to a target area on layer 1, with the target
area tying to the related bus component pins. This is done to allow
an unrelated bus path on layer 1 to pass before the component pins.
Tying it all Together
Topology Planning can be used at a high level to
specify initial placement and specific bus structures or
plan all bus and non-bus connections on the PCB.
The tool is flexible enough to support either and
anything in between. For very detailed Topology
Planning, the planning of a single bus can include:
Tune
Packed bus path segments with splits, joins,
layer changes
Unpacked Areas
Target Areas
Netline assignments.
Additionally, Topology Planning can be used to
manage effect escapes from very large BGA devices.
The BGA pins are on a surface layer of the PCB, yet
the buses approach the device on several layers and
need particular groups of pins to escape from the BGA
on particular layers to meet the bus paths. Using
packed and unpacked areas with some target areas
allows for effective strategies.
TOPOLOGY ROUTING
Topology Routing is also a new tool from Mentor
Graphics which allows quick, guided auto routing
driven from Topology Planning. The results are similar
to hand routing, yet occur rapidly. The strength of the
route quality is found in the transition points from the
bus path to the component pins, where bus paths
change layers and splits occur. Some buses can be
highly complex with splits, layer transitions and many
different devices to delivery routes, but the Topology
Router is designed to perform well with these levels of
difficulty, producing hand route-like quality at a fraction
of the time. Topology Routing respects the layer
specifications, via locations, shielding, and packed,
tune and unpacked settings to deliver a flowing,
compact routing result.
Figure 16 shows the options for Topology Router in
the Auto-route dialog. It starts with Straight Line
Interconnects, followed by the option of Fanout,
Bus Route, Bus Shielding and Tune Delay.
These are the passes that auto-route topology
planned buses. The details for each pass type are:
Straight Line Interconnect: Routes between the
component pins and target areas and must be
used if target areas are incorporated during
Topology Planning.
Fanout: Same as the Fanout found in auto-route
and fans out components pins of buses. This
pass is optional for Topology Routing, depending
on the overall route strategy for the design.
Bus Route: This is the pass that routes the
packed, tune paths and unpacked areas for
buses as detailed in Topology Planning. Initially,
tune segments are routed like packed buses. If
shielding or spacers are specified during
Topology Planning, they are routed with the bits
of the bus through the bus trunk, but not up to the
Figure 15: Topology Planning (top) and Topology Routing (bottom).
PAGE 6
component pins. Also, this pass includes fanout
as it routes a bus.
Bus Shielding: This pass finishes shielding,
routing the shielding traces around the bus end-
caps, up to the component pins and inserts vias
at a specific frequency to the indicated shielding
plane.
Tune Delay: This is the same pass found in auto-
route, and tunes the buses at the tune path
segments drawn during Topology Planning.
The Topology Router offers control over all of the
selected buses to route under Items to Route, Buses
with Paths etc. As shown in Figure 16, there is an
Excluded and Included list of bus names to
accommodate specific routing efforts. Other standard
settings offered in the auto-route dialog can also be
applied in to a route scheme.
One of the major benefits of Topology Routing is that it
routes to the plan specified during Topology Planning.
With the Topology Planning being persistent, the detail
of the traces are not needed while designing. This
allows for quick what-if scenarios for connecting
buses. If the initial plan doesnt work, delete the
specific bus routes, modify the bus paths and quickly
re-route the bus. For a focused route, incorporate the
Items to Route as shown in Figure 16.
Another important benefit of Topology Routing is that it
can occur with a single bus path. The entire PCB
doesnt need to have all buses planned to see the
results of a focused effort. Quick feedback from
focused Topology Routing is typically provided in less
than a minute. This focused feedback provides the
opportunity to optimize Topology Planning yielding
the best design without a drag on the design schedule.
With a good plan, Topology Routing returns good
results, but does not always route all bits. The routes
not completed are routed through the bus trunk,
leaving a trace end close the desired component pin.
Figure 17 shows three of the seven failures out of 192
total connections for a 64-bit bus planned with splits
and different bit size paths on different layers. Look at
the distance between the end of the trace and
component pin. These few failures hand route quickly.
PLANNING AND ROUTING STRATEGIES
There are many parameters and details to consider
while designing PCBs. Organizations have different
flows, skill levels and yield requirements that influence
PCB design strategies. So, with so many influences
along with unique design logic, no one strategy works
for all PCB designs. Several different high-level
scenarios and strategies for employing Topology
Planning and Topology Routing in a workflow are
highlighted below.
Scenario 1: Planning only the critical Buses
It may make sense for an organization to plan
just the PCI bus and DDR2 bus on a PCB repre-
senting 15% of the total connections, and not
plan the 40 or so other buses unique to the
design. The PCI and DDR2 buses are planned
by the engineer using Topology Planning and
Routing. The other 85% of the connections could
be completed with the layer bias auto-router. The
auto-route scheme might use the fanout pass for
all component pins and tie power and ground to
the planes, followed by iterations of the passes
route, via-min, spread until the all the connections
are complete.
Scenario 2: Planning all Buses
Referencing the same design, perhaps all 42
buses are planned. This still covers only 50% of
the overall connections. Another 30% of the
connections are power and ground and need
PAGE 7
Figure 16: Topology Routing is an option supported within the Auto
Route dialog.
Figure 17: If Topology Routers fails to connect all the bits of the bus
to component pins, it leaves the failed connection(s) close to the
associated component pin.
fanouts from surface mounted pads to vias
connecting to power or ground plane layers.
There are also critical signals covering clocks
and other assorted control lines representing 5%
of the connections. The remaining 15% are
general connections.
The critical signals might be routed first using
highly restricted auto-route passes that follow the
signal constraints for layers and delay, or they
might be hand routed. Once the
engineer/designer is satisfied with the routing of
these critical signals, they are locked so no other
passes can manipulate their routing.
Next, it may be best to focus on Topology
Routing, to route all the planned buses, incorpo-
rating the necessary passes as detailed in the
Topology Routing section of this paper. Once the
buses are routed, determine if they can be
pushed about with the insertion of vias from other
signals. If not, lock the buses or at least those
that are shielded. Follow this with the fanout of
power and ground connections.
Once this is complete, only the general signals
remain. General signals are not logically
grouped, dont have any timing rules and dont tie
to a power or ground plane, and tend to go in
every direction.
Heres the challenge, the 85% routed connec-
tions are not layer-bias traces, and they dont
follow strict horizontal and vertical layer rules, so
a typical auto-route wont help with the general
signals. Unless there are at least two extra
layers open for layer bias route passes. If so,
finish the 15% of general signal connection with
the layer bias Auto-route passes. However, if
those two extra layers are not available, there is
another way. Target areas from Topology
Planning and the passes Straight Line
Interconnect with No Via, No Bias are the
appropriate tools to complete the general signals.
As the Topology Router completes buses,
flowing, unrouted areas of open space are typi-
cally available between bus paths. Target areas
allow designers to select the general signals
component pins and allow them to escape to
these layer specific open spaces. Dynamically
group them and specify their target location and
layer.
By grouping the general signals in the direction of
the netline and placing them in flowing spaces in
the same direction, there is a good chance of
completing the connects. Once the escapes are
established, use the No Vias, No Bias route
pass to route between the related Target Areas.
Or, Multi-Plow can be used to hand route multiple
connections at once. The last few connections
will probably require hand routing, but overall this
approach will yield hand route results in a frac-
tion of the design time.
One other major factor to consider is the stackup and
via strategy. Some organizations require through-hole
via fanouts for all component pins. Depending on the
density of the PCB, this may prevent the use of
packed and tuned bus paths. There may be far too
many obstacles (vias) to keep an 8-bit packed bus
together. The best Topology Planning strategy at this
point would be unpacked bus areas. Unpacked bus
areas allow appropriate planning for this via rule, then
finish the remaining connections with layer biased
auto routing.
SUMMARY
Topology Planning allows for the accurate capture of
IP with easy to use design tools. This IP is then
applied throughout the remainder of the design flow
and routed with Topology Router in a fraction of the
time typically required to achieve a hand routed PCB
designs.
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