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A macrocell array is an approach to the design and manufacture of ASICs. It is a prefabricated array of higher-level logic functions such as flip-flops, registers, and the like. Drawbacks are somewhat low density and performance than other approaches to asic design.
A macrocell array is an approach to the design and manufacture of ASICs. It is a prefabricated array of higher-level logic functions such as flip-flops, registers, and the like. Drawbacks are somewhat low density and performance than other approaches to asic design.
A macrocell array is an approach to the design and manufacture of ASICs. It is a prefabricated array of higher-level logic functions such as flip-flops, registers, and the like. Drawbacks are somewhat low density and performance than other approaches to asic design.
consists of a D flip-flop. Macrocell array From Wikipedia, the free encyclopedia For other uses, see Macrocell (disambiguation). Macrocell arrays in PLD Programmable logic devices, such as programmable array logic and complex programmable logic devices, typically have a macrocell on every output pin. Macrocell arrays in ASIC A macrocell array is an approach to the design and manufacture of ASICs. Essentially, it is a small step up from the otherwise similar gate array, but rather than being a prefabricated array of simple logic gates, the macrocell array is a prefabricated array of higher-level logic functions such as flip-flops, ALU functions, registers, and the like. These logic functions are simply placed at regular predefined positions and manufactured on a wafer, usually called master slice. Creation of a circuit with a specified function is accomplished by adding metal interconnects to the chips on the master slice late in the manufacturing process, allowing the function of the chip to be customised as desired. Macrocell array master slices are usually prefabricated and stockpiled in large quantities regardless of customer orders. The fabrication according to the individual customer specifications may be finished in a shorter time compared with standard cell or full custom design. The macrocell array approach reduces the mask costs since fewer custom masks need to be produced. In addition manufacturing test tooling lead time and costs are reduced since the same test fixtures may be used for all macrocell array products manufactured on the same die size. Drawbacks are somewhat low density and performance than other approaches to ASIC design. However this style is often a viable approach for low production volumes. A standard cell library is sometimes called a "macrocell library". [1][2] References ^ Norman Einspruch. "Application Specific Integrated Circuit (ASIC) Technology" (http://books.google.com /books?id=YmGeGQrxmo8C&pg=PA10&lpg=PA10&dq=asic+macrocell&source=bl&ots=DRNEcVzKWj& sig=4JXWvLSpaoVWskr5l3bfAyapJBo&hl=en&sa=X&ei=DM65UcOcHoqZ0QGUg4GIBQ& ved=0CEYQ6AEwAzgK#v=onepage&q=asic%20macrocell&f=false). Academic Press. 1991. p. 10. 1. ^ "ASIC Macro Cells" (http://www.epson.jp/device/semicon_e/product/asic/macrocell/) 2. Retrieved from "http://en.wikipedia.org/w/index.php?title=Macrocell_array&oldid=594057596" Categories: Gate arrays This page was last modified on 5 February 2014 at 15:38. Macrocell array - Wikipedia, the free encyclopedia http://en.wikipedia.org/wiki/Macrocell_array 1 of 2 5/16/2014 10:40 PM Text is available under the Creative Commons Attribution-ShareAlike License; additional terms may apply. By using this site, you agree to the Terms of Use and Privacy Policy. Wikipedia is a registered trademark of the Wikimedia Foundation, Inc., a non-profit organization. Macrocell array - Wikipedia, the free encyclopedia http://en.wikipedia.org/wiki/Macrocell_array 2 of 2 5/16/2014 10:40 PM