AIM:

To design and implement the 8 bit ALU in FPGA / CPLD

HARDWARE REQUIRED:
Spartan 3E FPGA
Cool runner 2 CPLD
SOFTWARE REQUIRED:
Xilinx 9.1 ISE
THEORY:
In computing, an arithmetic logic unit (ALU) is a digital circuit that performs arithmetic and
logical operations. The ALU is a fundamental building block of the central processing unit of a
computer, and even the simplest microprocessors contain one for the purposes such as
maintaining timers. The processors found inside modern CPUs and graphics processing units
(GPUs) accommodate very powerful and very complex ALUs; a single component may contain
a number of ALUs. Most ALUs can perform the following operations:
Bitwise logic operations (AND, NOT, OR, XOR)
Integer arithmetic operations (addition, subtraction, multiplication and division)
Bit-shifting operations (shifting or rotating a word by a specified number of bits to the left or
right, with or without sign extension). Shifts can be seen as multiplications and divisions by a
power of two.
The inputs to the ALU are the data to be operated on (called operands) and a code from the
control unit indicating which operation to perform. Its output is the result of the computation.
Some of the arithmetic functions like addition, subtraction, multiplication and division and some
logic functions like AND, OR, XOR and NOT are performed here in the program. The arithmetic
and logic unit gets the input data from the input ports, maybe 4 to 32 bits depending on the
application and operation and display the output via the output ports on the LED.
BLOCK DIAGRAM:

PROCEDURE:
Step 1: Define the inputs and outputs.
Step 2: Define wires if required.
Step 3: Declare a case statement and inside the case define all the required operations under
each case. Choosing a specific case, is based on the select input.
Step 4: When a particular case is chosen, only that operation is performed and the output is
displayed.
Step 5: To continue the process for all the cases for a given input, use test bench and define
particular period for each case.
PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity alu is
port( clk : in std_logic;
a : in std_logic_vector(3 downto 0);
b : in std_logic_vector(3 downto 0);
sig : in std_logic_vector(3 downto 0);
c : out std_logic_vector(7 downto 0);
carry : out std_logic);
end alu;
architecture Behavioral of alu is
signal reg1,reg2 : integer;
signal tmp : std_logic_vector(8 downto 0);
signal delay : std_logic_vector(2 downto 0):= 000;
begin
process(a,b,sig)
variable cnt :integer range 0 to 16 := 0;
begin
if rising_edge(clk) then
c <= "00000000";
carry addition
tmp(4 downto 0) <= conv_std_logic_vector((conv_integer(a) + conv_integer(b)),5);
c(3 downto 0) <= tmp(3 downto 0);
carry subtraction tmp(4 downto 0) <= conv_std_logic_vector((conv_integer(a)
conv_integer(b)),5);
c(3 downto 0) <= tmp(3 downto 0);
carry Multiplication
c Division
c(3 downto 0)
reg1 <= conv_integer(a);
reg2 <= conv_integer(b);
delay
if(reg2 = 0) then
delay <= "011";
else
delay
if(reg1 >=reg2) then reg1 <= reg1-reg2; cnt:=cnt + 1; delay <= "010";
else
tmp(3 downto 0) <= conv_std_logic_vector(cnt,4);
delay tmp(3 downto 0) <= "0000";
delay cnt := 0;
delay
end case;
when 0100 => and gate
c(3 downto 0) or gate
c(3 downto 0) xor gate
c(3 downto 0) nand gate
c(3 downto 0) nor gate
c(3 downto 0) xnor gate
c(3 downto 0)<= a(3 downto 0) xnor b(3 downto 0);
when "1010" =
c(3 downto 0)
end case;
end if;
end process;
end Behavioral;
UCF FILE :
#PACE: Start of Constraints generated by PACE
#PACE: Start of PACE I/O Pin Assignments
NET a LOC = p5 ;
NET a LOC = p4 ;
NET a LOC = p3 ;
NET a LOC = p2 ;
NET b LOC = p9 ;
NET b LOC = p8 ;
NET b LOC = p7 ;
NET b LOC = p6 ;
NET c LOC = p29 ;
NET c LOC = p28 ;
NET c LOC = p27 ;
NET c LOC = p25 ;
NET c LOC = p23 ;
NET c LOC = p22 ;
NET c LOC = p21 ;
NET c LOC = p20 ;
NET carry LOC = p38 ;
NET clk LOC = p44 ;
NET sig LOC = p15 ;
NET sig LOC = p14 ;
NET sig LOC = p12 ;
NET sig LOC = p10 ;
#PACE: Start of PACE Area Constraints
#PACE: Start of PACE Prohibit Constraints
#PACE: End of Constraints generated by PACE
OUTPUT WINDOW :


Family Spartan 3E
Device XC3S500E
Package FT256
Speed - 4

PARALLEL ADDER
--------------------------------------------------------------------------
--------
-- Company:
-- Engineer:
--
-- Create Date: 14:06:55 10/07/2010
-- Design Name:
-- Module Name: add - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------
--------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity paralleladder is
Port ( in1 : in STD_LOGIC_VECTOR (7 downto 0);
in2 : in STD_LOGIC_VECTOR (7 downto 0);
sum : out STD_LOGIC_VECTOR (7 downto 0);
carry : out std_logic_vector(1 downto 0));
end paralleladder;

architecture Behavioral of paralleladder is

signal temp : std_logic_vector(8 downto 0):="100000000";
signal temp1 : std_logic_vector(9 downto 0):="1000000000";
signal a1, a2 : integer;
signal temp3, temp2 : std_logic_vector(9 downto 0);
begin
process
begin
a1 <= conv_integer(temp)-conv_integer(in1);
a2 <= conv_integer(temp)-conv_integer(in2);
temp2 <= conv_std_logic_vector((a1 + a2),10);
temp3 <= conv_std_logic_vector((conv_integer(temp1) -
conv_integer(temp2)),10);
sum(7 downto 0) <= temp3(7 downto 0);
carry(1 downto 0) <= temp3(9 downto 8);
end process;
end Behavioral;
Aim
To implement VHDL code for 2 bit and 4 bit magnitude comparator.
Tool required
Mentor Graphics
FPGA advantage 8.1ps
Model sim 6.3a
Theory
A digital comparator or magnitude comparator is a hardware electronic device that takes two
numbers as input in binary form and determines whether one number is greater than, less than or
equal to the other number. Comparators are used in a central processing units (CPU) and
microcontrollers. Examples of digital comparator include the CMOS 4063 and 4585 and the TTL
7485 and 74682-'89.


A magnitude comparator is a combinational circuit that compares two numbers A & B to
determine whether:
A > B, or
A = B, or
A < B
Inputs
First n-bit number A
Second n-bit number B

Outputs
3 output signals (GT, EQ, LT), where:
1. GT = 1 IF A > B
2. EQ = 1 IF A = B
3. LT = 1 IF A < B
GT = Greater than; EQ = Equal To; LT = Less Than

2 bit magnitude comparator
A 2 bit magnitude comparator consists of 2 inputs of 2 bit each and 3 outputs.
Truth Table
A1 A0 B1 B0 A>B A=B A<B
0 0 0 0 0 1 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 1 0 0
0 1 0 1 0 1 0
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 1 0 0
1 0 0 1 1 0 0
1 0 1 0 0 1 0
1 0 1 1 0 0 1
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 1 0
Table(5.1a)
Logic Equation
A<B = A1B1 + A1A0B0 + A0B1B0
A>B = A1B1 + A0B1B0 + B0A1A0
A=B = A0B0 + A1A0B1B0 + A1A0B1B0

4 bit magnitude comparator
A 2X4 decoder consists of 2 inputs of f bit each and 3 outputs.
Consider two 4-bit binary numbers A and B such that
A = A
3
A
2
A
1
A
0

B = B
3
B
2
B
1
B
0

Here each subscript represents one of the digits in the numbers.

Equality
The binary numbers A and B will be equal if all the pairs of significant digits of both numbers
are equal, i.e.,
A
3
= B
3
, A
2
= B
2
, A
1
= B
1
and A
0
= B
0

Since the numbers are binary, the digits are either 0 or 1 and the boolean function for equality of
any two digits A
i
and B
i
can be expressed as
.
x
i
is 1 only if A
i
and B
i
are equal.
For the equality of A and B, all x
i
variables (for i=0,1,2,3) must be 1.
So the quality condition of A and B can be implemented using the AND operation as
(A = B) = x
3
x
2
x
1
x
0

The binary variable (A=B) is 1 only if all pairs of digits of the two numbers are equal.
Inequality
In order to manually determine the greater of two binary numbers, we inspect the relative
magnitudes of pairs of significant digits, starting from the most significant bit, gradually
proceeding towards lower significant bits until an inequality is found. When an inequality is
found, if the corresponding bit of A is 1 and that of B is 0 then we conclude that A>B.
This sequential comparison can be expressed logically as:


(A>B) and (A < B) are output binary variables, which are equal to 1 when A>B or A<B
respectively.
VHDL code for 2 bit magnitude comparator
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY comp IS
port(a1,a0,b1,b0:in std_logic;
y0,y1,y2:out std_logic);
END ENTITY comp;
ARCHITECTURE comp_data OF comp IS
BEGIN
process(a0,a1,b0,b1)
begin
if(a1>b1) then
y0<='0';
y1<='1';
y2<='0';
elsif(b1>a1) then
y0<='1';
y1<='0';
y2<='0';
elsif(a1=b1) then
if(a0>b0) then
y0<='0';
y1<='1';
y2<='0';
elsif(b0>a0) then
y0<='1';
y1<='0';
y2<='0';
elsif(a0=b0) then
y0<='0';
y1<='0';
y2<='1';
end if;
end if;
end process;
END ARCHITECTURE comp_data;
Output:

Result window of 2 bit magnitude comparator

VHDL code for 4 bit magnitude comparator

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY MAG4BH IS
PORT(A0,A1,A2,A3,B0,B1,B2,B3: IN STD_LOGIC; X,Y,Z:OUT STD_LOGIC);
END ENTITY MAG4BH;
ARCHITECTURE MAG4BH_ARCH OF MAG4BH IS
BEGIN
PROCESS(A0,A1,A2,A3,B0,B1,B2,B3)
BEGIN
IF(A0>B0) THEN
Z<='1';
X<='0';
Y<='0';
ELSIF(A0<B0) THEN
Z<='0';
X<='0';
Y<='1';
ELSIF(A0=B0) THEN
IF(A1>B1) THEN
Z<='1';
X<='0';
Y<='0';
ELSIF(A1<B1) THEN
Z<='0';
X<='0';
Y<='1';
ELSIF(A1=B1)THEN
IF(A2>B2) THEN
Z<='1';
X<='0';
Y<='0';
ELSIF(A2<B2) THEN
Z<='0';
X<='0';
Y<='1';
ELSIF(A2=B2) THEN
IF(A3>B3) THEN
Z<='1';
X<='0';
Y<='0';
ELSIF(A3<B3) THEN
Z<='0';
X<='0';
Y<='1';
ELSE
Z<='0';
X<='1';
Y<='0';
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE MAG4BH_ARCH;
Output:


Result window of 4 bit magnitude Comparator



Result
The VHDL code for 2 bit and 4 bit magnitude comparators were implemented and simulated
successfully.