J Supercond Nov Magn (2011) 24: 10871093

DOI 10.1007/s10948-010-0857-y
ORI GI NAL PAPER
Implementation of Molecular Transistor Electrodes
by Electromigration
A.S. Stepanov E.S. Soldatov O.V. Snigirev
Received: 5 September 2010 / Accepted: 6 September 2010 / Published online: 21 September 2010
Springer Science+Business Media, LLC 2010
Abstract Gaps with a size of less than 5 nm have been
fabricated in 15-nm-thick and 200-nm-wide gold strips de-
posited on sapphire substrates. Preparation conditions pro-
viding a sufcient adhesion of such electrodes as well as
the parameters for the electromigration process used to fab-
ricate the gaps have been found which allow a successful
gap implementation. Such gaps transform gold strips to the
source-drain electrodes of planar single electron transistors
based on nanoparticles or molecules.
Keywords Single-molecule transistor Electromigration
Nanogap Deposition of Au on Al
2
O
3
1 Introduction
Recently, Intel Corporation successfully implemented the
32-nm half-pitch CMOS technology in their integrated cir-
cuit (IC) production lines; AMD Corporation is working on
the same goal [1]. Evidently, the constantly growing de-
mands to the main properties of IC require the use of even
smaller dimensions of the basic elements. The implementa-
tion of 22 nm and also 16 nm circuits are actively discussed
A.S. Stepanov O.V. Snigirev
IMP, RRC Kurchatov Institute, Moscow, Russia
A.S. Stepanov
e-mail: stepanov@cryolab.ru
E.S. Soldatov O.V. Snigirev ()
M.V. Lomonosov Moscow State University, Moscow, Russia
e-mail: oleg.snigirev@phys.msu.ru
E.S. Soldatov
e-mail: esold@phys.msu.ru
[2, 3]. Nevertheless, according to the International Tech-
nology Roadmap for Semiconductors (ITRS) [4], the tech-
nologies with smallest feature sizes below 22 nm are cur-
rently marked as Beyond CMOS. There are fundamental
physical reasons which justify this denition; the de-Broglie
wavelength of the electrons is becoming comparable with
the IC elements size, but also a number of technical rea-
sons. The latter include the inuence of impurities in the
(semiconducting) material which could drastically disperse
the properties of otherwise identical cells on the wafer, dif-
culties with lithographic processes, and generation of heat
in the semiconductor substrates of microprocessors [5].
Fortunately, additional physical quantum effects appear
at this nanoscale, for example, single-electron correlated
tunneling, a dimensional quantization of energy, and other
effects. They allow creating basic IC elements using new ap-
proaches. One of them could be using a single electron tran-
sistor as one of the basic cells of the post-CMOS electronics.
The rst structure which has been studied in this way was the
molecular single electron transistor (SET) created with the
aid of a scanning tunneling microscope (STM) [6]. Such a
transistor consisted of a carborane molecule C
2
B
10
H
12
sep-
arated by tunnel barriers from the conducting substrate on
one side and from the STM tip on the other side (Fig. 1).
The deposited thin lm metal electrode functioned as a gate
in this prototype. This so developed three-dimensional (3D)
transistor demonstrates a single-electron mode of operation
and inuence of the STM current on the gate voltage even at
room temperature.
However, an SET can only be applicable if it can be pre-
pared in a planar two-dimensional (2D) topology; this is a
very challenging task (see, for example, [7, 8]). As shown
in Fig. 1, the molecular transistor consists of a central is-
land (molecular cluster or nanoparticle), connected via tun-
nel junctions to conducting electrodes. The size of this cen-
1088 J Supercond Nov Magn (2011) 24: 10871093
tral island determines the maximum temperature at which
the device can still be used. To operate an SET at 300 K
with the aim to develop a device which could be compatible
with the usual semiconductor devices, and thus has some re-
alistic perspectives to be used in the future; the size of the
island must be of the order of 3 nm or less.
The required small sizes of the investigated objects cause
a number of severe problems. First of all, there are prob-
lems of technological character as modern industry cannot
produce devices having dimensions of several nanometers.
Some specic techniques were suggested and tested for fab-
rication of a prototype of the planar SET. These techniques
made use of the evaporation of an additional metal layer
in the gap [9, 10], of electrochemical deposition or etching
[11, 12], or of electromigration [13, 14], and were studied
and developed in different laboratories.
One of the most difcult tasks on the way to planar
SET fabricationpreparing the source-drain electrodes of
the SET, which must be separated by the nanogap in which a
molecule or nanoparticle could be placed at the next step
has been solved in this work by the electromigration tech-
nique. The essence of the electromigration effect is increas-
ing the mobility of the conductor atoms by a large electrical
current. At a sufciently large current density, there is some
probability of damaging the electrodes at locations at which
defects are situated. The preparation of a gap between the
electrodes is based on this effect. Gold was selected as a
Fig. 1 Schematic image of the 3-D single electron transistor based on
cluster molecule
material for the electrodes due to its being inert to chemical
reactions, and stability of the structure after gap preparation.
2 Technology
In our work, we used samples which were prepared by the
technology of a two-layer polymer mask [15]. The double-
layer technology consists of several stages.
2.1 Substrate Preparation
A 3-inch silicon wafer was cleaned successively in ace-
tone, alcohol, and in 10% solution of HCl. In a Leybold
Z-400 thin-lm deposition system, a 400-nm-thick silicon
oxide layer was deposited on the substrate by magnetron-
ion sputtering. The sputtering was done in an Ar and O
2
atmosphere with partial pressures of 1.2 10
2
mbar and
3 10
3
mbar, respectively. The deposition rate was 2 /s.
After sputtering, the substrate was diced with a diamond cut-
ter into chips of 9 mm9 mmsize. Thus, the dielectric layer
was formed on each chip at the rst step.
2.2 Bilayer Polymer Mask Formation
Polymer Deposition Following the deposition of a silicon
oxide layer, a layer of copolymer MicroChem 8.5EL11 was
deposited on each chip using a resist spinner at a speed of
4,000 rpm and a spinning time of 60 seconds. Then the
copolymer was baked on a ceramic tile (Dataplate 721-2)
at a temperature of 160 C for 10 minutes.
In the following step, the chip was exposed to UV irradi-
ation (290 nm wavelength at an intensity of 2527 mW/cm
2
for 5 seconds) to increase the resist sensitivity to the devel-
oper. After that, the second layer of polymer MicroChem
950C2 was deposited on the resist spinner at a speed of
5,000 rpmfor 60 seconds. Baking of the polymer upper layer
was carried out at the temperature of 180 C for 30 minutes.
Thus, the two-layer polymer lm was formed on the chip
(Fig. 2a).
Fig. 2 Stages of the
manufacture of samples:
(a) deposition of a two-layer
polymer structure, (b) mask
exposure and development,
(c) deposition of metal, (d) lift-
off process of polymer mask
J Supercond Nov Magn (2011) 24: 10871093 1089
UV Exposure and Development The so prepared samples
were stored for 1 day for the relaxation of mechanical
stresses in the deposited resist layers. After this, a coarse
structure of lead electrodes (line width more than 10 m)
was produced. The chips were exposed to the UV lamp with
an intensity of 2527 mW/cm
2
at 290 nm through a quartz
photomask shown in Fig. 3a for 2 minutes while the cen-
tral part of the chip with a size of 80 m80 m was not
exposed.
After that, the chip was developed in a solution of toluene
and alcohol (1:10) at 20 C for 1 minute and 45 seconds.
2.3 Electron Beam Exposure and Development
The area of 80 80 square microns in the center of the chip
was used for the formation of a ne structure with a line
width of less than 1 m. The mask shown in Fig. 3b presents
the billet structure in which the electrodes of the molecular
transistor will be prepared, having a line width of 200 nm.
This area was patterned in a scanning electron microscope
Cambridge Instruments Stereoscan-240. The beam current
Fig. 3 The masks for UV exposure a rough structure of lead elec-
trodes (a), and for electron beamexposure of the ne structure in center
of the chip (b)
was 16 pA, the accelerating voltage was 30 kV. After the
exposure, the chips were developed in the mixture of toluene
and alcohol (1:10) at a temperature of 20 C and as a result,
we obtained the bilayer resist mask on the whole chip which
determines the sample geometry (Fig. 2b).
2.4 Gold Evaporation, Lift-off Process
The thin-lm deposition system Leybold 560 was used for
the evaporation of metals onto the chips. The rst experi-
ments have shown an only poor adhesion of the deposited
Au to the SiO
2
layer. To avoid this problem, an additional
dielectric layer of Al
2
O
3
which was obtained by oxidizing
a 15-nm-thick aluminum lm deposited on top of the SiO
2
layer, was formed. The oxidation time was 20 minutes at a
pressure of 810
3
mbar. The deposition of 15 nmthick Au
lm by thermal evaporation at a pressure of 4 10
7
mbar
and at a rate of 1 A/s on the aluminum oxide surface pro-
vided the necessary adhesion for manufacturing the samples
by the lift-off process. The sample after Au deposition is
shown in Fig. 2c.
After the evaporation, the chips were immediately placed
in acetone that was heated up to 60 C. The complete dis-
solution of the polymer mask took about 45 minutes and
provided the removal of the gold lm at the unexposed loca-
tions of the chips (Fig. 2d).
In this way, the narrow gold lines required for preparing
the electrodes of the molecular transistor by the method of
electromigration were produced (Fig. 4).
In Fig. 4, the submicron region in the center of the sample
is shown, in which the gold electrodes on Al
2
O
3
buffer layer
were formed. The Au bridge has 3 mlength, 200 nmwidth,
and 15 nm thickness. The typical value of bridge resistance
was about 500 Ohms at room temperature, which gives the
specic resistance value close to 5 10
5
Ohm cm. This
value of the specic resistance indirectly conrms the high
quality of the Au lm.
Fig. 4 SEM image of the
fabricated chip submicron
area (a), and one of the narrow
thin-lm Au bridges prepared
for electromigration process (b)
1090 J Supercond Nov Magn (2011) 24: 10871093
3 Electromigration Technique
As was mentioned in the introduction, the source-drain elec-
trodes of molecular SET can be obtained by tearing open
the thin lm bridge in order to form the nanogap. To tear
open the thin-lm bridge, the electromigration method can
be used. This technique requires passing a current of cer-
tain value in the nanobridge, and a readout system capable
of providing a fast feedback to avoid the total destruction of
the bridge. The block diagram of the developed measuring
setup is shown in Fig. 5.
The setup was built on the basis of a personal computer
using an ADC board Advantech PCI-1713 and a DAC board
Advantech PCI-1720 as well as a Keithley 6487 picoam-
pere meter. The established unit allows the characterization
of the sample during the electromigration process every 10
microseconds and allows one to decrease signicantly the
current in a short time interval of about 20 microseconds. It
allows us to control accurately and effectively the process of
the gold lm electromigration.
Fig. 5 Block diagram of the electromigration setup
In our work, we used the following electromigration al-
gorithm. At the rst stage, we measure the initial resistance
R0 of the thin-lm bridge with the slow (2 measurements/s)
IV-curve measurements using the Keithley instruments. At
the second stage, the program calculates a resistance R1 that
is 1% higher than the resistance R0. It will prove the begin-
ning of electromigration and serves as a threshold for the
feedback system for resetting the voltage across the bridge
to zero. At the third stage, the voltage on the chip rises to
45 V with a speed of 120 mV/s and with the help of the
ADC and DAC boards, the resistance is measured in real
time every 10 s.
If the resistance is higher than the threshold value, the
voltage is set to zero and the procedure is cyclically repeated
until the value R1 reaches 23 kOhm. Then the electro-
migration is stopped. It is known from literature that such
samples with having a resistance of 23 kOhm are in a
metastable state and due to a relaxation process, the nanogap
can be formed in the bridge. Our experiments conrm such
a scenario: after a time delay of 3040 minutes, nanogaps
were observed in the samples under SEM imaging.
The IV-curves measured during the electromigration
process for determining R0 are shown in Fig. 6. We can
see that the resistance during the electromigration process
signicantly changes (from 500 Ohm at 1-st iteration to 2
3 kOhm at the last 48th iteration).
During the process of electromigration, the current den-
sity in the thin lm bridge reached 10
6
A/cm
2
. It is very
important for the gap formation by the electromigration
process to take into account the inuence of the Joule heat-
ing of the area in which the gap will form [16] because
Fig. 6 Changing of initial resistance R0 of thin lm bridge during electromigration process
J Supercond Nov Magn (2011) 24: 10871093 1091
signicant heat release can lead to melting of the thin lm
bridge. In the literature, there are some publications that
demonstrate the importance of an effective heat removal
from the bridge during electromigration [17]. In our ex-
periments, we took into account this factor in designing
Fig. 7 SEMimage of thin-lmbridge at the intermediate stage of elec-
tromigration
the gold-electrode topology. As one can see in Fig. 4b, the
200 nmwidth bridge in which the gap will formis connected
to wider electrodes which will prevent the gold bridge from
melting. Such a technological approach allows us to obtain
a signicant yield (up to 15%) of gaps which are several nm
wide (but less than 5 nm).
In designing the experimental setup with the fast feed-
back, we also took into account that the characteristic time
for the signicant restructuring of the gold lm (moving
about 10
5
atoms) during the electromigration process is
about 1050 ms [18]. This means that the setup of electronic
system should have a response time much smaller than 1 ms
to provide an effective control over the restructuring of the
gold lm.
Our algorithm of electromigration process and the rapid
response time of the electronic unit permit a precise control
of the gold thin-lm bridge restructurization at any step of
the electromigration process. It allowed us a highly accurate
control of increasing the thin-lm bridge resistance. The im-
age of the lm at the intermediate stage of electromigration
is shown in Fig. 7. One can see that the lm was changed in
comparison with the initial state (see Fig. 4b) because of the
lm material motion and the lm restructuring. As a result,
Fig. 8 SEM image of 5 nm gap between Au electrodes lying on Al
2
O
3
1092 J Supercond Nov Magn (2011) 24: 10871093
Fig. 9 SEM image of nanoparticle placed into nanogap
the formation of local constrictions provided the increase in
the bridge resistance.
The next SEM scan (see Fig. 8) shows the gap ob-
tained in the center of the bridge in after the bridge resis-
tance reached the value of 3 kOhm and the external volt-
age applied to the bridge was switched off for a few tens of
minutes.
A gap of nanometer-scale (smaller than 5 nm) (see Fig. 8)
was formed in 15% of the cases. The resistance of the
gap was higher than 10 GOhm, which conrms the forma-
tion of the nanosize gap. Such gaps can be used for the
preparation of the room-temperature single electron tran-
sistor. In the preliminary experiment, 6 nm gold nanopar-
ticles covered by a dithiol (C
2
H
4
(SH)
2
) shell are placed be-
tween the electrodes creating the main frame of a molecular
transistor (Fig. 9). A magnetic or semiconducting nanopar-
ticle could also be inserted in the nanogap by this tech-
nique.
4 Results
We successfully prepared narrow gaps in 15-nm-thick and
200-nm-wide gold lms using an electromigration process.
A key requirement for this process is the very fast control of
the current in the gold lm to prevent the lm from melting.
Another requirement is a thin Al
2
O
3
buffer layer on top of
the silicon dioxide substrate to improve the adhesion of the
gold lm.
Acknowledgements This work was supported by the Russian Fund
of Basic Research (Project #09-07-00272-a), the International Scien-
tic Technological Center (Project # 3457), and the Federal Target Pro-
gram Scientic and Teaching Specialists of the Innovative Russia for
20092013 (Contract # 02.740.11.0229).
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