Tutorial 10

Serial RS-232, ISE 9.2 and ModelsimXE on the Digilent Sartan-3E

!oard
-Introduction
This lab will be an introduction on how to establish an interconnection between PC and
FPGA kit through serial RS-232 interface using h!er ter"inal a#ailable on the
la!to!$PC% The board will be a &igilent S!artan-3' starter kit%
-(b)ecti#e
The ob)ecti#e is to control the fre*uenc of a si"!le +-bit counter through RS-232 !ort
using h!er-ter"inal% The counter i"!le"ented here is a +-bit counter o!erated at fi#e
different fre*uencies si"ilar to the one in Tutorial ,,% The ai" is not to i"!le"ent
co"!le- digital designs but to show the user a "ethod to interface a la!to! or PC with an
FPGA kit using a#ailable RS-232 !ort on the board with a!!ro!riate interacti#e signals%
.IS/0(1' !rotocol is e"!loed in the !resent !ro)ect to establish the co""unication%
-Prere*uisites
0asic knowledge about digital design and FPGAs%
Ac*uaintance with 2ilin- IS' 3%2i tool%
(S re*uire"ent 4 .indows 2P or .indows 2555%
-A!!lication
This docu"ent is used b students6 who are learning FPGA design and #erification%
- +-bit Counter &esign (#er#iew
The +-bit counter is i"!le"ented at fi#e different fre*uencies using the sste" clock
running at 75 8h9% The fre*uencies are 75 8h9$ 2:36 75 8h9$ 2:236 75 8h9$ 2:2+6 75
8h9$ 2:276 75 8h9$ 2:2; <the fre*uencies are chosen to "ake the counter action #isible
through the ='&s6 e-ce!t for the highest fre*uenc which is solel to #erif the design in
8odelSI8>%
The fre*uencies are controlled using in!ut signal FR'?@'1CA which in turn is
controlled using the fi#e kes <B,C6 B2C6 B3C6 B+C D B7C> on the keboard%
The out!ut of the +-bit counter is connected to the four of the a#ailable se#en ='&s
<=&56 =&,6 =&26 =&3>%
An asnchronous reset is also !ro#ided to the design which is connected to one of the
sliding switches <S.5>%
,
The @ART core is taken fro" htt!E$$www%o!encores%org$c#sweb%sht"l$"iniuart$%
2
-RS-232 Serial Interface
,% Characteristics
@ses a 3 !in connector &0-3 <older PCs use 27 !ins &0-27 and newer la!to!s do
not ha#e serial !ort an"ore6 so a @S0 to serial con#erter is re*uired>%
Allows bidirectional full-du!le- co""unication <the PC can send and recei#e
data at the sa"e ti"e>%
Can co""unicate at a "a-i"u" s!eed of roughl ,5F0tes$s%
2% &0-3 Connector
&0-3 connector <"ale> a!!ears as shown in Figure ,%
"igure 1# D$-9 %onne&tor
The !in nu"bering on the connector is as followsE
"igure 2# 'in (um!ering )male &onne&tor*
"igure 3# 'in (um!ering )+emale &onne&tor*
3
Pin &escri!tion of RS-232 "ale connectorE
'in
(o.
(ame Dir (otes,Des&rition
, &C& I1 &ata Carrier &etect% Raised b &C' when "ode" snchroni9ed%
2 R& I1 Recei#e &ata <R&6 R->% Arri#ing data fro" &C'%
3 T& (@T Trans"it &ata <T&6 T->% Sending data fro" &T'%
+ &TR (@T &ata Ter"inal Read% Raised b &T' when !owered on% In auto-
answer "ode raised onl when RI arri#es fro" &C'%
7 G1& - Ground
; &SR I1 &ata Set Read% Raised b &C' to indicate read%
G RTS (@T Re*uest To Send% Raised b &T' when it wishes to send% '-!ects
CTS fro" &C'%
H CTS I1 Clear To Send% Raised b &C' in res!onse to RTS fro" &T'%
3 RI I1 Ring Indicator% Set when inco"ing ring detected - used for auto-
answer a!!lication% &T' raised &TR to answer%
Ta!le 1# 'in Des&rition )male &onne&tor*
The three i"!ortant ones a"ong the 3 !ins areE
!in 2E R& <recei#e data>%
!in 3E T& <trans"it data>%
!in 7E G1& <ground>%
@sing )ust 3 wires6 one can send and recei#e data%
3% Serial Co""unication
&ata is sent one bit at a ti"e% (ne wire is used for each direction% Since co"!uters
usuall need at least se#eral bits of data6 the data is seriali9ed before being sent% &ata is
co""onl sent b chunks of H bits% The =S0 <data bit 5> is sent first6 the 8S0 <bit G>
last%
+% Asnchronous Co""unication
This interface uses an asnchronous !rotocol which "eans that no clock signal is
trans"itted along with data% The recei#er has to ha#e a wa to ti"e itself to the inco"ing
data bits%
+
In the case of RS-2326 it is done in the following waE
,% 0oth side of the cable agree in ad#ance on the co""unication !ara"eters
<!ara"eters shown in Figure +>% It is done "anuall before co""unication starts
<which will be e-!lained later>%
"igure -# Serial %ommuni&ation 'arameters
2% The trans"itter sends a I,I when the line is idle%
3% The trans"itter sends a IstartI <a I5I> before each bte is trans"itted6 so that the
recei#er can understand that data is co"ing%
+% After the IstartI6 data co"es in with the agreed s!eed and for"at6 so the recei#er
can inter!ret it%
7% The trans"itter sends a Isto!I <a I,I> after each data bte%
For e-a"!le6 a 5-77 bte when trans"itted a!!ears in the following waE
"igure .# 0/.. $0te Transmission
0te 5-77 is 5,5,5,5, in binar%
0ut since it is trans"itted =S0 <bit-5> first6 the line toggles like thatE ,-5-,-5-,-5-,-5%
Another e-a"!leE
"igure 1# 0/%- $0te Transmission
7
/ere the data is 5-C+6 which is difficult to inter!ret% It an illustration to show how
i"!ortant it is for the recei#er to know at which s!eed the data is sent%
7% (!eration S!eed
The s!eed is s!ecified in baud6 i%e% how "an bits-!er-seconds can be sent% For e-a"!le6
,555 bauds would "ean ,555 bits-!er-seconds6 or that each bit lasts one "illisecond%
Co""on i"!le"entations of the RS-232 interface <like the one used in PCs> do not
allow )ust an s!eed to be used% (ne has to settle to so"e IstandardI s!eed%
Co""on #alues areE
,255 bauds%
3;55 bauds%
3H+55 bauds%
,,7255 bauds%
At ,,7255 bauds6 each bit lasts <,$,,7255> J H%GKs% If one trans"its H-bit data6 it lasts for
H - H%GKs J ;3Ks% 0ut each bte re*uires an e-tra start and sto! bit6 so one actuall needs
,5 - H%GKs J HGKs% That translates to a "a-i"u" s!eed of ,,%7 F0tes !er second%
At ,,7255 bauds6 so"e PCs with fault chi!s re*uire a IlongerI sto! bit <,%7 or 2 bits
long> which "akes the "a-i"u" s!eed dro! to around ,5%7F0tes !er second%
;% Phsical =aer
The signals on the wires use a !ositi#e$negati#e #oltage sche"e%
I,I is sent using -,5L <or between -7L and -,7L>%
I5I is sent using M,5L <or between 7L and ,7L>%
So an idle line carries so"ething like -,5L%
-.IS/0(1' Protocol
The .IS/0(1' Sste"-on-Chi! <SoC> Interconnect Architecture is a !ortable interface
for use with se"iconductor IP cores% Its !ur!ose is to foster design reuse b alle#iating
sste"-on-a-chi! integration !roble"s% It is acco"!lished b creating co""on logical
interfaces% This i"!ro#es the !ortabilit and reliabilit of the sste"6 and results in faster
ti"e-to "arket for the end user% .IS/0(1' is not an IP core but is a s!ecification for
creating IP cores%
.IS/0(1' Sste"-on-Chi! Interconnect !rotocol can be used as an interface to all
cores that re*uire interfacing to other cores inside a chi! <FPGA6 ASIC6 etc%>%
;
The .IS/0(1' architecture sits between the PC and @ART interface as shown below
in Figure G%
"igure 2# S0stem $lo&3 Diagram
The .IS/0(1' !rotocol is a set of handshake signals carried out in a sste"atic
e-change fashion in order to "aintain snchroni9ation between two sste"s%
The handshake signals and their res!ecti#e order as used in this !rotocol are as shown
below in Figure H%
"igure 4# 5IS6$7(E 'roto&ol Signal E/&hange
PC UART FPGA
WISHBONE
Protocol
Serial
Communication
Rx_int = !"
Tx_int = !"
STB = !"
WR = !"
A##R = $%%&
#ATA = $''&
AC( = !"
STB = %"
AC( = %"
S)STE* UART
+a,t AC( ,i-nal i, not im.lemente/ in t0e
WISHBONE State *ac0ine o1 t0e .re,ent
/e,i-n
G
-Present @ART &esign &escri!tion
This @ART <@ni#ersal Asnchronous Recei#er Trans"itter> is designed to "ake an
interface between a RS-232 line and a .IS/0(1' bus%
It is built to be #er s"all <to fit in s"all FPGAs>6 but also efficient%
It is not suited to interface a "ode" as there is no control handshaking <CTS$RTS>%
It integrates two se!arate clocks6 one for .IS/0(1' bus6 the other for bit strea"
generation%
This has the ad#antage to let the user o!erate at an desired fre*uenc <li"ited onl b
RS-232 interface> for the baud rate% There are full functionalit @ARTs a#ailable on
o!encores%co" but the full functionalit is not re*uired for thi !ro)ect% For this !ro)ect6
the !ro!osed NlightO @ART will be sufficient%
Design suorts#
,% .IS/0(1' interface in H-bit data bus
2% Two clocksE one for .IS/0(1' interface6 one for RS-232 bit strea"
generation
3% 0aud rate di#isor fro" , to ;773; <generic !ara"eter set at integration ti"e>
Design does not suort#
,% FIF( in!ut$out!ut
2% Control handshaking
I( PortsE
.IS/0(1' Interface SignalsE
Port .idth &irection &escri!tion
.0PC=FPI , In!ut 0lockCs clock in!ut
.0PRSTPI , In!ut Asnchronous Reset
.0PA&&RPI 2 In!ut @sed for register selection
.0P&ATPI H In!ut &ata in!ut
.0P&ATP( H (ut!ut &ata out!ut
.0P.'PI , In!ut .rite or read ccle selection
.0PST0PI , In!ut S!ecifies transfer ccle
.0PACFP( , (ut!ut Acknowledge of a transfer
Ta!le 2# 5IS6$7(E Inter+a&e Signals
(ther Internal SignalsE
Port .idth &irection &escri!tion
IntT-P( , (ut!ut Trans"it Interru!t
IntR-P( , (ut!ut Recei#e Interru!t
0RPC=FPI , (ut!ut Clock for serialisation$unserialisation
Ta!le 3# 7ther Internal Signals
H
'-ternal <off-chi!> ConnectionsE
Port .idth &irection &escri!tion
T-&PPA&P( , (ut!ut The serial out!ut signal
R-&PPA&PI , In!ut The serial in!ut signal
Ta!le -# E/ternal %onne&tions
ClocksE
1a"e Source Rates <8/9> Re"arks &escri!tion
8a- 8in Resolut
ion
.0PC=FPI .IS/0(1'
bus
=i"ited b
target host
1one .IS/0(1'
clock
0RPC=FPI @ser 1one 0audrate clock
Ta!le .# %lo&3s
RegistersE
,% Register =istE
1a"e Address .idth Access &escri!tion
Recei#e buffer 5 H R Contain bte recei#ed
Trans"it buffer 5 H . Contain bte to trans"it
Status , H R Recei#e buffer full $
Trans"itter bus
Reser#ed 2 H
Reser#ed 3 H
Ta!le 1# Register 8ist
2% Status RegisterE
0it Q Access &escri!tion
5 R Trans"itter buffer state J IntT-P( !in
B5C 4 0us% CanCt acce!t inco"ing bte
B,C 4 Acce!t a bte to trans"it
, R Recei#er buffer state J IntR-P( !in
B5C 4 0uffer e"!t
B,C 4 0uffer contain a recei#ed bte
Ta!le 2# Status Register
Reset LalueE 2222225,b
3
@ART &esign (!eration
The @ART (!eration is #er basicE
@!on a write to the data in!ut bus .0P&ATPI6 the core will auto"aticall seriali9e and
e"it the bte on the T-&PPA&P(% It will hold IntT-P( low as long as it cannot acce!t
an inco"ing bte% Therefore a rising edge on IntT-P( can trigger the interru!t line of a
"icrocontroller to e"it another bte%
@!on rece!tion of a bit strea" on R-&PPA&P(6 the core will de-serialise the
infor"ation and assert IntR-P( !in% This announces that the recei#ed bte can be read on
the data out!ut bus .0P&ATP(% As soon as the bte is read6 IntR-P( is negated%
.IS/0(1' 0us
The design is H-bit .IS/0(1' co"!atible% It doesnCt use the .0PCACPI !in as it will
ne#er insert wait states%
Initiali9ation
The design doesnCt need to be reset6 as it is read to use u!on !ower on%
/owe#er6 a snchronous assertion of .0PRSTPI will abort an !ending trans"it$recei#e
and will set the core in idle state%
0audrate &i#isor
A generic L/&= !ara"eter allows the user to introduce a di#isor between 0RPC=FPI
clock and the bit strea" fre*uenc% In addition6 the core inserts a + di#isor for sa"!ling
!ur!ose for the recei#er%
ThusE
0audrate J Fre*<0RPC=FPI> $ 0R&ILIS(R $ +
where 0R&ILIS(R is the generic !ara"eter%
For e-a"!le to instantiate the co"!onent in a L/&= unit6 writeE
@, E 8ini@ART
generic "a! <0R&ILIS(R JR ,53>
!ort "a! <clk6 rst6 adr6 %%%>S
for a di#ision of ,53%
,5
0elow are gi#en so"e di#isor #alues for co""on baudratesE
0audrate toleranceE
The recei#er will acce!t a slight #ariation between the e-!ected baudrate and the
effecti#e bit strea" baudrate that isE
8in fre* 1o"inal 0audrate -2%;5T
8a- fre* 1o"inal 0audrate M7%35T
'*ui#alent in !eriod E
8in !eriod 1o"inal !eriod -7%35T
8a- !eriod 1o"inal !eriod M2%;5T
Going beond these li"its will "ake the recei#er unable to de-serialise correctl
<illustrated in Figure 3 >%
"igure 9# $audrate Toleran&e Margin Illustration
,,
$RDI9IS7R $audrate
25H5 ,255
,5+5 2+55
725 +H55
2;5 3;55
,35 ,3255
;7 3H+55
0RPC=FPI at ,58/9
$RDI9IS7R $audrate
,32 2+55
3; +H55
+H 3;55
32 ,++55
2+ ,3255
,; 2HH55
H 7G;55
+ ,,7255
2 235+55
, +;5H55
0RPC=FPI at ,%H+328/9

Start 0it 5 0it , 0it 2 0it 3 0it +
M2%;T
0it ; 0it G Sto!
0te
5-+2
-7%3T
0it 7
1o"inal e-!ected
baudrate
8a- !eriod for the
bit strea"
8in !eriod for the
bit strea"
Architecture
The block diagra" of the design is as gi#enE
"igure 10# $lo&3 Diagram o+ the S0stem Design
,2
WISHBONE
Bu,
inter1ace
WISHBONE
SIGNA+S
Trans"itter
Recei#er
R-&PPA&PI
R-&PPA&PI
T-&PPA&P(
2+
0RPC=FPI
IntT-P(
IntR-P(
0audrate
&i#isor
Initial Set-u! and (ut!ut
Connect the &igilent S!artan-3' kit to a la!to!$PC as shown below%
"igure 11# :S$ %onne&tion
Then connect the serial !ort <&C' ter"inal> a#ailable on the FPGA board to the another
@S0 !ort a#ailable on the la!to!$PC using a @S0-to-Serial con#erter as shown below%
"igure 12# :S$-to-Serial %on;erter
,3
"igure 13# RS-232 Inter+a&e
Switch on the board and configure the de#ice using the 2ilin- IS' 3%2i tool%
(!en the h!er ter"inal as shown below%
"igure 1-# 60er Terminal 'ath
,+
The following window will !o! u!%
"igure 1.# 60er Terminal
Gi#e an a!!ro!riate na"e and !ress (F% Then the following window will show u!%
Select the a!!ro!riate co" !ort and !ress (F%
"igure 11# %om 'ort Sele&tion
The following window will show u!% 8ake the !ort settings as shown below or set the
baudrate to a desired rate de!ending on the design !ara"eters% As the baudrate in the
!resent design is configured for 3;55 baud6 the following settings are been chosen%
,7
"igure 12# 60er Terminal Settings
(nce the !ort settings are "ade !ress (F and the following ter"inal will show u!% 1ow
tr !ressing an of the following fi#e kesE B,C6 B2C6 B3C6 B+C D 7 and obser#e the change
in the fre*uenc of the counter b looking at the four ='&s <=&56 =&,6 =&2 D =&3>
o!eration s!eed%
"igure 14# 7utut
,;
-'-ercise
,% The state diagra" used in the !resent design to dis!la the interacti#e signal (F
has been !ur!osefull designed in less o!ti"u" "anner6 tr to "odif the state
diagra" and "ake it "ore efficient and also tr to "ake the interacti#e signals
"ore readable si"ilar to those shown below%
Solution is !ro#ided%
2% Tr to get "ore creati#e and i"!ro#e the user interface b !ro#iding ani"ations
<using ASCII artworks 4 like those shown below> along with the interacti#e
signals%
.-.
| \ __
( `\ / |
\ \ / |
| | `\ / /
| |\ \ /` / /
| | \ \ ./' / /
| | \ \ / _/| |
| | \ \ /' _/ | |
| | \ \ /' / / )
| ( \ \ / / / /
( \ \ \ / / / /
\ \ ) ) / / / /
\ \ | | / / / /
\ \ | | / / / /
\ \ | | / / / /
\ \ | | ( / / /'
\ \| | | / /' /'
\ \ /`. |`. \/' /'
\ `-;-;-; /'
`\ <
> .-"-. .-\
/ .' ,__ ` \
| | \ /\
| |__ \ |_ \
_.------.._| o\ | |o`|\_
,-`. `. | | | |''`'-._._
_.-'. `:_|.__|/`'.-- - ;_ `
' ' ``--.```--.. \/`..--''' ; `-.
.-``. -.,-..__._.._._.__. ;`-.
' `. `; | | | .'
`. `-.| | | _'
`.._ . `--''`_.-'
``--._`-...-'"
;: ;
. `:
: : .
__.'_ .' :
_.--' `-._.'
.-'.. .. `.
: .-. .--.`. :
: : : : : :
: :`;; :`; ; :
`.`O;' `O;.' :
.' .---. .--. ;
. : '._ :' ;
:: : .-`-.; . .'
.': `. ``` `. :-'
: : `-.__ ._ _.'
: ; : ;```
: `. _.-.' . ``-._
: `.-' : : `-.
: _.: ` `-._ `,
`._.-' ; `.`-. ;_, _.,
: `.: ;' ;-' ;
: ``.___.' :
: ;_..--'
`. ;
`-.__ ...'
: : :
:-:__;
: : :
.-~~~--..__: : :___..---..
.'.' : `,
:,' : `; ;
`: _.'`._ :,'
`~~~'----'' `'-.____....'
___
__ _/:::>__
/:/_/::/ _/::>
_/:(/:::\_/::/
_):::::::::::::\
_/::::::::::::::::\____
/ \:::::::::/ \
| ::/\ :::::::: / \:: |
/ ::/ \ :::::: / |:::/
/:::| \::::::::/ |:::\
/::::| \::::::/ |::::\
,------: \::::/ :------,
/ ___ \0 / \ 0 / ___ \
: ,-' ) ` `---' `---' ( `-, :
\_ \ ' ` \_ _/
\____\ \/
\ _______\________
\ ,-'
)
\ ,- ,----------- _/
\ ,-' \\ ) _/
(___________/__________\\ /
:;;;\___________________)
______,:;;;;;;;;:______
,;;;;;;;;;;;;;;;;;;;;;;;;\_
/;;;;;;;;;;;;;;;;;;;;;;;;;;;\_
/;;;;;;__;;;; ;;;;;; ;;;;;;;;;;\
,G
/intE @se 0RA8 or an efficient "e"or to store the desired artworks <checkoutE
htt!E$$www%heartnsoul%co"$asciiPart$asciiPcartoonPcharacters%ht" for interesting ASCII
Artworks>% If ou are interested in a "ore ad#anced !ro)ect that utili9es gra!hics and
0RA86 contact the author%
-Author 0io
1a"eE Lallabh Srikanth &e#ara!alli
Graduate student at @18 in 'C' de!art"ent%
'-"ailE #sde#araUun"%edu%
,H