CMOS ANALOG DESIGN USING ONE-

REGION MOSFET MODELING

SOLUTIONS TO PROBLEMS








Chapter 1 Introduction to Analog CMOS Design







Collaborators:
Henrique Hayasaka, Paulo Mrcio Moreira e Silva, Roddy Romero,
and
Thiago Jos de Oliveira




2010

1.1
a) Ohms Law applied to the channel element of width W and length dy
=

(
1
(

)
)
Thus,
=

b) Rearranging equation (P1.1.1)

()
and integrating the eq. above from source to drain [0,L]

0
=

()

Assuming the mobility constant along the channel it follows that

()

1.2
a) Substituting the inversion charge density given by

() =

)
in (P.1.1.2) it follows

or

[(

0
)(

) (

2
2
)]
or

2
(

)] (

)

b)

)
2

)
2

[2(

0
) (

)](

)



1.3
The resistance R of a MOSFET operating at low

with

= 0 is given
by
1

0
)

where RSH is the sheet resistance of the transistor.
For

0
= 1 and with the parameters of the 0.35 m technology

= 3.3
For a 10 resistance
1

=
1
10
=

1
3.3

Thus,

= 333
Considering L = 0.5m, the area WL is 83 m which is approximately 67
times the area of a minimum-dimension transistor.
Similarly for a resistance of 1k

= 3.33
For W= 3.3 m and L=1 m the area WL is 3.3 m which is
approximately 3 times the area of a minimum-dimension transistor.
Finally, for 100k

= 0.033
For W=2.5m and L=75 m, the area WL is 187.5m which is
approximately 150 times the area of a minimum-dimension transistor.



1.4
By definition the transconductances are the partial derivatives of the
current with respect to the terminal voltages, thus
I
D
=

Assuming that

I
D
= 0
Thus,

To make explicit the dependence of the drain current on the substrate
potential we substitute VGB by VG-VB and VSB by VS-VB in the expressions of
the drain current to obtain

(SI)

2
[

+ ( 1)

]
2


(WI)

=
0

(
(

(1))

)

In SI

= [

( 1)] = 2

( 1)] =

=
( 1)

( 1)] = ( 1)

= 0
Similarly, in WI

=
1

(
(

(1))

) =

=
1

(
(

(1))

) =

= 0

=
1

(
(

(1))

) =
( 1)

For VDS=0

= 0

In SI

= 2

In WI

1.5
Both the (long channel) strong (S) and weak (W) inversion model of the
MOSFET have the functional form

[(

) (

)]

where the function g is independent of the geometry. In SI g is a quadratic
function while in WI it is an exponential function. For the series association of
transistors (see Fig. below)

Series association of transistors
the condition of series association

= (

[(

) (

)]
= (

[(

) (

)]
allows us to calculate the potential at the intermediate node X as
(

) =
(

) +(

)
(

+(

Substituting the expression above in the drain current equation, it follows that

=
(

+(

[(

) (

)]

When WS=WD we have simply LEQ=LD+LS (as for the series association
of resistors with uniform ( length independent) technological parameters.



1.6
At threshold (see Eq. 1.3.12) IWI = IF(SI)

and

using (P1.2.3) we obtain

()
=

(2

)
2
2..

2
. Thus,

+
()
= 2
()
=

/(

)
4

2
=
10
6
41.24000.026
2

2
= 770

=
0.3410
12

77010
9
= 4.4
= 50

= 220
1.7
a)

= 2

= 628

= 16.3
For the BJT:

ln|

| = 0.671
For the MOSFET, using the strong inversion model with

= 0):

2
(

0
)
2

=
0
+
2

( )

0
= 0.8; = 1.35;

= 8010
6

2

Table 1.1, updated with values of VGS:
W/L IF(A) VG(V)
0 0.8
500 6.6 0.82
100 33.2 0.91
50 66.4 1.01
10 332 1.85
Strong inversion model
b)
For the BJT: =

= 770

For the MOSFET: =

= 10
628

Table 1.1, updated with voltage gains:
W/L IF(A)
a
ID(A)
b
Av(V/V)
a
Av(V/V)
b

0 22 - -285
500 6.6 28.6 -952 -220
100 33.2 55.2 -189 -114
50 66.4 88.4 -95 -71
10 332 354 -19.0 -18
a
Strong inversion model;
b
Accurate all-region MOSFET model.



1.8
The transconductance gmg including WCJ in the load is given by

= 2(

)
Substituting the above expression of gmg

in (P1.8.1) repeated below

(2.
1
2

)

we obtain

=
2(

)
(

)

Thus,
= (
2

) (1
2

)
Assuming that fT = 4GB, CL = 1pF, Cox =2fF/m
2
, CJ = 1fF/ m, and L=
m , the value of W calculated with the formula above is 30% larger than the
value obtained neglecting the parasitic drain-bulk capacitance.

1.9

2
=
1
2

= 1 +

2
= (1 +

1 +

)/2

Relative error (A-B)/A between the two models of IF/(tgms) vs. if
The maximum error is 25%, and it occurs at if=1.78.


1.10

= 1 +

2
;

(
1

+
1
2
1

Integrating between a generic voltage VS and the pinch-off voltage VP we
obtain

) =

Considering the transistor symmetry it follows that

) =