97.

477 (W) 2003

Analog Integrated Electronics
Assignment #2
written by
Leonard MacEachern, Ph.D.
c 2003 by Leonard MacEachern. All Rights Reserved.
1
Assignment Guidelines
The purpose of this assignment is to practice solving problems related
to Millers Theorem, two-stage ampliers and the frequency response of
switched-capacitor lters, and common-mode rejection ratio.
This assignment is due at the start of class on March 28
th
, 2003. Late
assignments will NOT be accepted.
Check the course web page for any further information relating to this
assignment.
2
The mind has exactly the same
power as the hands; not merely
to grasp the world, but to
change it.
Colin Wilson
Question #1
Millers theorem
1
is useful for simplifying certain amplier congurations.
A commonly encountered situation is a small signal model with a feedback
capacitance.
1.1 Millers Theorem
In 1919, J.M. Miller was trying to calculate the input impedance of vacuum
tubes. He noticed that the apparent input capacitance was related to the
gain of the tube under certain conditions [1]. In 1968, Cherry and Hooper
successfully formalized the relation between the gain and the increased ap-
parent capacitance [2]. The increased capacitance was called the Miller
capacitance, and the eect leading to this eective capacitance was called
the Miller Eect. In 1979, Millman gave the Miller Eect to the masses,
in the form of the Miller Theorem, and the dual to the Miller Theorem,
as described in [3].
The Miller Theorem (and its dual to a lesser extent) is a useful tool
for analyzing ampliers that have feedback elements. It is often used when
explaining amplier compensation, and the related phenomenon of pole-
splitting. As shown in the following sections, the application of Millers
is not always straightforward. First, the derivation of Millers Theorem is
presented.
1
Dont confuse Millers Theorem with Millmans Theorem. Millmans Theorem
concerns circuit simplication through combining of voltage sources.
3
Millers Theorem Derivation
Millers Theorem is shown schematically in Figure 1.1. In Figure 1.1(a),
a series impedance exists between the input port and the output port.
This series impedance is replaced by two shunt impedances as shown in
Figure 1.1(b). Millers Theorem allows us to choose the correct values of
the replacement impedances.
+
-
+
-
Z
fb
(s)
i
1
(s) i
2
(s)
v
1
(s) v
2
(s)
Z
1
(s) Z
2
(s)
(a) A two port circuit representation. There is
an impedance in series with the input and
output nodes.
+
-
+
-
i
1
(s) i
2
(s)
v
1
(s) v
2
(s)
Z

1
(s) Z

2
(s)
(b) Using Millers Theorem, the series
impedance between the input and output
ports is removed, and shunt impedances are
added across the ports to compensate.
Figure 1.1: The Miller Theorem transformation.
In order for the two-port shown in Figure 1.1(a) to be electrically equiv-
alent to the two-port shown in Figure 1.1(b), the current-voltage response
at the input and output ports must be the same.
Application of Kirchos current law at the positive terminal for the
input port of the network shown in Figure 1.1(a) gives the expression,
i
1
(s) =
v
1
(s)
Z
1
(s)
+
v
1
(s) v
2
(s)
Z
fb
(s)
. (1.1)
We expect that the same current should ow into the input port of the
network shown in Figure 1.1(b) for the same v
1
(s) and v
2
(s). Writing
Kirchos current law at the positive terminal for the input port of the
network shown in Figure 1.1(b) gives the expression,
i
1
(s) =
v
1
(s)
Z

1
(s)
. (1.2)
4
Since equations (1.1) and (1.2) must give the same result for i
1
(s), we set
them equal and solve for Z

1
(s), yielding,
1
Z

1
(s)
=
1
Z
1
(s)
+

1
v
2
(s)
v
1
(s)

1
Z
fb
(s)
. (1.3)
We can nd the expression for Z

2
(s) in a similar fashion. Application
of Kirchos current law at the positive terminal for the output port of the
network shown in Figure 1.1(a) gives the expression,
i
2
(s) =
v
2
(s)
Z
2
(s)
+
v
2
(s) v
1
(s)
Z
fb
(s)
. (1.4)
The same current should ow into the output port of the network shown
in Figure 1.1(b) for the same v
2
(s) and v
1
(s). Writing Kirchos current
law at the positive terminal for the output port of the network shown in
Figure 1.1(b) gives the expression,
i
2
(s) =
v
2
(s)
Z

2
(s)
. (1.5)
Equations (1.4) and (1.5) must give the same result for i
2
(s); we set them
equal and solve for Z

2
(s), yielding,
1
Z

2
(s)
=
1
Z
2
(s)
+

1
v
1
(s)
v
2
(s)

1
Z
fb
(s)
. (1.6)
Taken together, equations (1.3) and (1.6) enable the replacement of the
series impedance shown in Figure 1.1(a) with the two shunt impedances
shown in Figure 1.1(b).
The series impedance shown in Figure 1.1(a) may be entirely due to
a capacitance. An alternate form of Millers Theorem is often used when
dealing with capacitances admittances are used instead of impedances.
Recall that the admittance, Y (s) is given in terms of impedance as Y (s) =
1/Z(s), and equations (1.3) and (1.6) can be re-written as
Y

1
(s) = Y
1
(s) +

1
v
2
(s)
v
1
(s)

Y
fb
(s) (1.7)
Y

2
(s) = Y
2
(s) +

1
v
1
(s)
v
2
(s)

Y
fb
(s) . (1.8)
5
Alternate forms of (1.3) and (1.6)-(1.8) express the impedance and ad-
mittance transformations in terms of the two-port gain, A
v
(s) = v
2
(s)/v
1
(s),
yielding,
1
Z

1
(s)
=
1
Z
1
(s)
+ (1 A
v
(s))
1
Z
fb
(s)
(1.9)
1
Z

2
(s)
=
1
Z
2
(s)
+

1
1
A
v
(s)

1
Z
fb
(s)
(1.10)
for the impedance relations, and
Y

1
(s) = Y
1
(s) + (1 A
v
(s)) Y
fb
(s) (1.11)
Y

2
(s) = Y
2
(s) +

1
1
A
v
(s)

Y
fb
(s) . (1.12)
for the admittance relations.
An interesting alternative derivation of the Miller Theorem equations
can be found in [4].
1.2 The Question
Obtain and read a copy of [5]. You can download this paper using a com-
puter on campus by accessing the IEEE database via http://ieeexplore.
ieee.org/Xplore/DynWel.jsp. Once youve read the paper, answer the
following questions:
1. Figure 1(a) in the paper shows a current source labeled i
i
and a
resistor labeled R
i
. What might these components represent in an
actual circuit?
2. Derive equation (2) from the paper.
3. Derive equations (4a), (4b), and (4c) using Maple or Matlab, or by
hand.
4. Explain pole-splitting in your own words, using the discussion in
[5] as a reference. Describe the conditions under which pole-splitting
occurs, and when it doesnt.
6
5. Explain the authors statement a careless application of the Miller
eect may give inaccurate results on the bottom of page 71.
6. If you know the dominant pole of an amplier is at the input node,
and a Miller capacitance is added, does the dominant pole stay at the
input node? Explain.
7
Creative minds have always
been known to survive any kind
of bad training.
Anna Freud
Question #2
Use two rst order lter sections of the form shown in Figure 2.1 to realize
the transfer function with Bode plots shown in Figure 2.2.
-
+
v
i
v
o
Z
1
Z
2
Figure 2.1: Bilinear transfer function building block.
Answer the following:
1. What are the poles of the transfer function?
2. What are the zeros of the transfer function?
3. What is the DC gain of the transfer function?
4. What is the transfer function in the Laplace domain?
5. Write the total transfer function as the product of two bilinear transfer
functions.
6. Choose an appropriate circuit for Z1 and Z2 for each of the rst order
stages. For your circuits, nd the values of the Rs and Cs.
8
10
1
10
1
10
3
10
3
10
4
10
4
10
6
10
6

|T(j)|dB |T(j)|
1
100
40dB
A
o
Figure 2.2: Bode plots for the magnitude of the desired transfer function.
7. Draw the nal two-stage lter with Z1 and Z2 for each stage replaced
with the appropriate components. Write the value of each component.
8. What kind of lter is this (i.e. bandpass, lowpass, highpass, or band
reject)?
9. Does it matter how the total transfer function is partitioned into two
bilinear transfer functions? Explain why or why not.
10. Convert your circuit to a switched capacitor circuit. Use a switching
frequency of 10MHz. All resistors must be converted to capacitors (to
do so, you will need to choose the proper networks for Z1 and Z2).
9
When you make the nding
yourself - even if youre the last
person on Earth to see the light
- youll never forget it.
Carl Sagan
Question #3
For the cascade current mirror shown in Figure 3.1, determine the low fre-
quency small-signal output resistance (looking into the i
out
node) assuming
all devices operate in saturation, the MOSFET capacitances can be ignored,
channel length modulation is negligible, and body eect is negligible.
M
1
M
2
M
3
M
4
i
in
i
out
1 : B
1 : B
Figure 3.1: A cascode current mirror.
Obtain and read a copy of [6]. You can download this paper using a com-
puter on campus by accessing the IEEE database via http://ieeexplore.
10
ieee.org/Xplore/DynWel.jsp. Once youve read the paper, determine
the improvement in CMRR attained when a cascode current mirror is used
to bias a dierential pair instead of a simple current mirror. The circuit
conguration is shown in Figure 3.2. Express the improvement in CMRR
as the ratio between the CMRR with a simple current sink and the CMRR
with the cascode current sink.
Hint: Use equation (8) from [6].
M
1
M
2
M
3
M
4
i
in
i
out
1 : B
1 : B
M
n1
M
n2
M
p1
M
p2
V
DD
v
+ v

v
o
Figure 3.2: A cascode current mirror used as the current sink for a dier-
ential pair.
11
Bibliography
[1] J. Miller, Dependence of the input impedance of a three-electrode vacuum tube
upon the load in the plate circuit, National Bureau of Standards Scientic Papers,
vol. 15, pp. 367385, June 1919.
[2] E. Cherry and D. Hooper, Amplifying Devices and Low-Pass Amplier Design. New
York: Wiley, 1968.
[3] J. Millman, Microelectronics: Digital and Analog Circuits and Systems. New York:
McGraw-Hill, 1979.
[4] M. Davidovic, A simple proof of millers theorem, IEEE Transactions on Educa-
tion, vol. 42, no. 2, pp. 1545, May 1999.
[5] W.-H. Ki, L. Der, and S. Lam, Re-examination of pole splitting of a generic single
stage amplier, IEEE Transactions on Circuits and Systems I: Fundamental Theory
and Applications, vol. 44, no. 1, pp. 704, Jan. 1997.
[6] R. Jiang, H. Tang, and K. Mayaram, A simple and accurate method for calculating
the low frequency common-mode gain in a mos dierential amplier with a current-
mirror load, IEEE Transactions on Education, vol. 43, pp. 362364, August 2000.
12