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Spring 2001 EE 8223 Analog IC Design Page 82

Using an active load, i.e., MOSFET(s), to replace a passive load resistor can
dramatically reduced the required chip area for the circuit while also helping
produce much higher gains (due to the potentially high small-signal
resistance an active load can provide).
An active load can be implemented using a gate-drain connected (a.k.a.
diode-connected) MOSFET or a current source/sink.
Amplifiers with gate-drain connected active loads tend to achieve large
frequency bandwidths but low gain due to their relatively low output
impedance. See Figure 22.1 for examples of MOS amplifiers using gate-
Amplifiers with current source/sink active loads tend to achieve higher gain
due to the high output impedance, but at the expense of bandwidth.
The cascode amplifier is well suited for achieving both gain and large
bandwidth.
Back to the gate-drain connected active load amplifier, let us consider its
frequency response in more detail. See the common-source amplifier in
Figure 22.5. In this schematic the device capacitances associated with M1
and M2 are explicitly shown. Consequently, the circuit has two RC time
constants one at the input and the other at the output.
Spring 2001 EE 8223 Analog IC Design Page 83
The input RC time constant is given by
( )
gb gs MI s in
C C C R + +
1

where
( )

,
_

+
2
1
1 1
1 1
m
m
gd v gd MI
g
g
C A C C
Note the influence of Miller capacitance and driving source resistance, R
S
,
on this circuits input time constant,
in
.
At the output,
( )
2 1 2
2
1
db db MO gs
m
out
C C C C
g
+ + +
where

,
_

,
_

1
2
1 1
1
1
1
m
m
gd
v
gd MO
g
g
C
A
C C .
Therefore the amplifiers frequency response is described by
( )

,
_

,
_

out in
m m
v
f
f
j
f
f
j
g g
f A
1 1
2 1
where f
in
= (1/2
in
) and f
out
= (1/2
out
).
Spring 2001 EE 8223 Analog IC Design Page 84
However, if R
S
is 0, then
in
is neglected, but now the right-half plane zero,

z1
, associated with C
gd1
must be considered. Recall that right-half plane
zeroes exhibits the same phase response as a left-hand plane pole. This is
detrimental to stability when external feedback is applied!
With R
s
= 0, the amplifiers frequency response now becomes
( )
( )
1
1
1
1
1
p
z
Leq m
in
o
s
s
R g
v
v

,
where
1
1
1
gd
m
z
C
g

and
( )
( )
1 2 1 2
2
2 1
1
1
1
1 1
gd db db gs
m
o o
gd Leq Leq
p
C C C C
g
r r
C C R
+ + +

,
_

+
.
Review example 22.2 in the text. In this example large bandwidth is
achieved, but the voltage gain is low.
Spring 2001 EE 8223 Analog IC Design Page 85
( )
2 1
1
2 1 1
||
o o
m
o o m
i
o
v
g g
g
r r g
v
v
A
+

For strong inversion saturation operation,
Spring 2001 EE 8223 Analog IC Design Page 86
( ) ( )
D D
D
i
o
v
I I
I
v
v
A
1 2 2
2 1
1
2 1
1

Understand this result! Voltage gain goes up as bias current decreases.

The frequency response of the current source load amplifier is strongly
affected by the large RC time constant at the output (due to the large output
resistance).
( ) ( )
2 1 1 2 2 1
||
db db gd gd o o out
C C C C r r + + +
Note also that the input time constant is subject to Miller effect.
Spring 2001 EE 8223 Analog IC Design Page 87
The Cascode Amplifier
Advantages of the cascode amplifier configuration include high gain (due to
high output resistance) and improved bandwidth due to reduced Miller
capacitance associated with the input time constant.
The total voltage gain of the cascode amplifier is the product of the input
transistors common-source gain, A
v1
, and the common-gate gain, A
v2
, of the
cascode transistor (M2 in the above schematic). First consider A
v1
:
( )
1 2 , 1
1
1
||
o s in m
in
d
v
r r g
v
v
A
Using the results developed on pp. 80-81 of your notes,

,
_

+
1
]
1

,
_

+
2
3
2
1
1
2
3
2
1 1
1 || 1
1
o
o
m
m
o
o
o
m
m v
r
r
g
g
r
r
r
g
g A
Spring 2001 EE 8223 Analog IC Design Page 88
The common-gate voltage gain of M2,
1 d
out
v
v
, is described by (neglecting
body effect),
2
3
2
3
3 2
2 3
2
2
1
2
1
1 1
1
o
o
o
o
o m
o o
o
m
d
out
v
r
r
r
r
r g
r r
r
g
v
v
A
+
+

+
+

This result is readily obtained using the small-signal model of M2, including
o1
) and M3 (r
o3
).
Then the total voltage gain of this cascode amplifier is given by
3 1 2 1 o m v v v
r g A A A
Note that if a cascode current source (say composed of M3 & M4, see Figure
22.20) is used to load the cascode amplifier, then the total voltage gain
would increase dramatically due to increased output resistance. The new
voltage gain would be described by
) || (
4 3 3 1 2 2 1 o o m o o m m v
r r g r r g g A
for strong inversion saturation operation.
Spring 2001 EE 8223 Analog IC Design Page 89
Now consider the frequency response of the cascode amplifier (circuit of
Figure 22.18(a)). Three time constants are associated with this amplifier.
The capacitance elements of these time constants are lumped together into
C
1
, C
2
, and C
3
in the schematic shown below.
C
1
, C
2
, and C
3
are described, respectively, by
1
]
1

,
_

+ + + +
2
3
2
1
1 1 1 1
1 1
o
o
m
m
gd gs MI gs
r
r
g
g
C C C C C
1
1
]
1

,
_

,
_

+ + + + +
1
2
3
2
1
1 2 2 1 2
1 1
o
o
m
m
gd gs sb db
r
r
g
g
C C C C C
L gd db db gd
C C C C C C + + + +
3 3 2 2 3
where C
L
is load capacitance that the cascode amplifier must drive. Note
that the cascode amplifiers Miller capacitance, C
MI
, associated with the C
1
(and subsequently the input time constant) is much less than that of simple
common-source amplifier with current source load. Why? Because
in d
v v
1
is much less in the cascode amplifier than in the simple common-
source amplifier with current source load. In fact, ( )
2 1 1
||
o o m
r r g compared
to ( )( )
2 3 2 1
1
o o m m
r r g g + .
Spring 2001 EE 8223 Analog IC Design Page 90
The three time constants of the cascode amplifier are given by
( )
1 1 1
C C R
L L in
+ ,
3 3
C r
o out
,
where C
L1
is the output capacitance of the circuit driving the cascode
amplifier and
( )
2 1
2
3
2
2 1 2 , 1
|| 1
1
|| C r
r
r
g
C r r
o
o
o
m
o s in d

1
]
1

,
_

+ .
Typically,
in
and
out
are the dominant time constants since, r
in,s2
the small-
signal resistance to AC ground from the source of M2, is relatively low.
One drawback of the cascode configuration, however, is the reduced voltage
swing at the output compared to the simple common-source amplifier with
current source load. The design of the biasing scheme for generating V
GG3
and V
GG2
influences V
OUT(max)
and V
OUT(min)
, respectively.