International Journal of Computer Trends and Technology (IJCTT) volume 4 Issue 7July 2013

ISSN: 2231-2803 http://www.ijcttjournal.org Page 2184

Automated Solution for Data Monitoring (Dashboard)
of ASIC Design Flow
Kariyappa B S
1
, Aravind
2
, Dhananjaya A
3
, Vineet Puri
4

1
Professor,
2,3
M.tech in VLSI and Embedded System, Dept of ECE,
R V College of Engineering, Bangalore, India
4
Design Engineer, Infineon Technologies Pvt ltd, Bangalore, India


Abstract Application Specific Integrated Circuit (ASIC) design
flow consists of several steps involved with Electronic Design
Automation (EDA) tools. For an ASIC designer it is very
important to know the status of design development. Finding the
status of the actual design is currently a manual work. It is
difficult to track the status and error information using log/report
files generated by the tool at different stages of design flow.
Therefore it is necessary to develop an automated tool to solve
these issues and hence to reduce the designer effort significantly.
In this paper smart data monitoring (dashboard) system is
developed as an automated solution using PERL scripting
language. The 8-bit Arithmetic Logic Unit (ALU) is designed for
the verification of developed dashboard system. The log/report
files are generated at each stages of the design. The information
like errors, warnings, time of execution and report parameters are
extracted from the design runs and stored in to database using the
dashboard system. The stored design status information and
report results are visualized in a single window dashboard view at
each stages of the design flow. The developed dashboard system is
generic and can be used for any kind of ASIC design. Thus
monitoring multiple design products using dashboard, the time
and effort required for checking design status is reduced
significantly.

Keywords Electronic Design Automation (EDA), Application
Specific Integrated Circuit (ASIC), Register Transfer Level
(RTL), Geometric Data Stream (GDS);

I. INTRODUCTION
Fast changing semiconductor industry incorporating new
phenomenon More than Moore (MtM)[1] set by International
Technology Roadmap for Semiconductors (ITRS). The MtM
explores a new area of micro/nano electronics, which reaches
beyond the boundaries of conventional semiconductor
technologies and applications. This migrate integration of IC
from the system board-level into the System in Package (SiP)
or onto the System on Chip (SoC). Thus increases complexity
in ASIC design, design flow and EDA tools used. ASIC design
flow consists of several implementation flows and requires
EDA tool [2] for each flow. The tracking of design status and
extraction of parameter values at different flow for each tool is
manual. It is necessary to communicate the progress of the
design across the design team and to see the historical data in
order to gain insight about any critical issues in the design.
This can be achieved with the automated monitoring system
(Dashboard system) instead of getting the manual updates from
the log and report files which are generated from different tools.
The dashboard is a design flow environment that helps to
understand complete design status at any point of
implementation cycle. The dashboard gives designer map,
blueprint and guides the designer to take proper decisions. The
key features of the dashboard system are
Communication Provides communication between
different flow engineers.
Tracking Easily track the bugs in design.
Predictability Using dashboard, designer can easily
predict design status.
Reproducibility From tracking and predictability
features, user can easily fix bugs in a design and
reproduce back design in time.
Effective Runtime/memory/CPU usage.
The main motivation of designing dashboard is to help
ASIC design engineers to produce the design tape out as early
to meet the time to market. Since ASIC flow or RTL to GDS [5]
flow has many steps and also generates many log/report files, it
saves the time of designer from manual search of bugs and
reports data. It helps the designer to know the effect of power,
area and timing information for each and every step of design
flow.
Application of project is building a wrapper [9] throughout
the design flow to parse the relevant information and display
them smartly as a consolidated data for each and every flow.
II. METHODOLOGY
The complete top level architecture is as shown in Fig. 1.
For a digital design which is developed in Verilog/VHDL/
System Verilog, the complete RTL to GDS flow will be
executed. For each execution of the flow log/report files are
generated which contains error, warning, area, power and
timing information. On parsing the log/report files the above
mentioned parameters are extracted and stored in the designed
database. The database contents are displayed in the webpage.
In this automated system, designer get to know parameter
values, if any parameters dont meet the specification, then
designer can be easily modify the design and rerun the design
flow.
International Journal of Computer Trends and Technology (IJCTT) volume 4 Issue 7July 2013
ISSN: 2231-2803 http://www.ijcttjournal.org Page 2185


Fig. 1 Top Level Architecture

Fig. 2 Design Steps of Dashboard System
The steps involved in the design of data monitoring
(Dashboard) System are as shown in Fig. 2. The steps
involved in the design of dashboard are as follows:
Execution Flow In this step, for an ASIC Design,
functional verification and RTL2GDS flow is
executed. As a result log/report files are generated.
Design Database Different database tables are
designed to store the extracting values. These are
database tables developed using MySQL queries.
Extract and Dump In this step, all the generated
log files are analysed and relevant data is extracted
using PERL parsers. The extracted data is stored in
respective table of the database using database
interface (DBI) model.
Creation of HTML page Webpage is developed
using HTML and JavaScript. This webpage is used to
display the stored data.
Rendering webpage For a particular request of the
user, the request processed by Apache server and
calls the CGI (common gateway interface) engine
which is written in Perl. The CGI engine select the
data related to request from database and renders the
data from database to the webpage. The dashboard is
capable of generating intellectual reports for the
design status and gives a single window view for the
complete design.

International Journal of Computer Trends and Technology (IJCTT) volume 4 Issue 7July 2013
ISSN: 2231-2803 http://www.ijcttjournal.org Page 2186

III. SOFTWARE REQUIREMENT
A. PERL (Practical Extraction and Reporting Language)
PERL is a high-level, general-purpose, interpreted,
dynamic programming language. Perl is an interpreted
language optimized for scanning arbitrary text files, extracting
information from those text files, and printing reports based
on that information. It's also a good language for many system
management tasks. The language is intended to be practical
(easy to use, efficient, complete) rather than beautiful (tiny,
elegant, minimal). It combines some of the best features of C,
sed, awk, and sh.
B. HDL (Verilog)
Verilog, standardized as IEEE 1364, is a hardware
description language (HDL) used to model electronic systems.
It is most commonly used in the design and verification of
digital circuits at the register-transfer level of abstraction. It is
also used in the verification of analog circuits and mixed-
signal circuits.
C. Design Compiler (Synopsis)
The Design Compiler (DC) tool is the core of the
Synopsys synthesis products. Design Compiler optimizes
designs to provide the smallest and fastest logical
representation of a given function. It comprises tools that
synthesize HDL designs into optimized technology-dependent,
gate-level designs. It supports a wide range of flat and
hierarchical design styles to optimize both combinational and
sequential designs for speed, area, and power.
D. IC Compiler (Synopsis)
IC Compiler (ICC) is a single, convergent netlist-to GDSII
or netlist-to-clock-tree-synthesis design tool for the chip
designers developing deep submicron designs. It takes input
as a gate-level netlist, a detailed floorplan, timing constraints,
physical and timing libraries, and foundry-process data.
Finally output is generated either as a GDSII-format file of the
layout or a Design Exchange Format (DEF) file of placed
netlist data ready for a third-party router. IC Compiler can
also output the design at any time as a binary Synopsys
Milkyway database for used with other Synopsys tools.
IV. RESULTS
The ALU design has been developed using Verilog-HDL,
verified functionality of design and synthesized in Synopsis
Design compiler using typical libraries of 90 nm technology.
The synthesized Verilog netlist and their respective design
constraint files (SDC) are imported to Synopsis IC compiler
and are used to generate automated layout from standard cells
and placement and routing. The simulation wave form and
final layout of ALU design is shown in Fig. 3 and Fig. 4
respectively. The log/report files are generated at each level of
design stage, these data files are fed as input to the dashboard
system.

Fig. 3 Simulation of ALU Design


Fig. 4 Layout of ALU Design
Later dashboard parse these files and populate the
information on its webpage, the information will be available
in terms of comparative tables and automated graphs as shown
in Fig. 5 and Fig. 6 respectively. The ALU design is
synthesized at different frequency by varying period
constraint, stored design status, report parameter values at
different frequency ID and stored information displayed as in
Fig. 5. Selecting frequency IDs checkbox gives the
comparative tables of area, power etc parameters values which
help to compare the parameter values between selected
frequency IDs. It also provide automated graph Fig. 6 which
help the designer to know effect of power, area over the
frequency ID.
Select single checkbox ID (dc_alu_100MHz id) and click
on get detail button, which provide details of selected ID i.e.
target runs executed for dc run and detailed report parameter
values. The snap shot of dc_alu_100MHz id is shown in Fig. 7.
The target runs includes steps followed DC run, numbers of
errors, warnings, time of log file creation and status result.
Also, report data gives details of area, power, timing, cell
count and clock gating parameters. Thus it makes easier for
the designer to compare the previous run with present run and
to see the improvement and act accordingly.
International Journal of Computer Trends and Technology (IJCTT) volume 4 Issue 7July 2013
ISSN: 2231-2803 http://www.ijcttjournal.org Page 2187


Fig. 5 ALU Design Status Shown on Dashboard

Fig. 6 Power Value Trend fromDifferent Frequency Runs

Fig. 7 Detail for dc_alu_100MHz ID
V. CONCLUSIONS
In this paper, the data monitoring (Dashboard) system for
ASIC design flow is presented. This Dashboard system is an
automated extraction and tracking for ASIC design flow
environment. Complete RTL to GDS flow is executed for the
ALU model and log/report files are generated at each stages of
the design flow. The design status and intellectual report
values are viewed in the dashboard system. Also, dashboard
provides historical information over time. This allows the
ASIC designer to do comparisons across different runs as well
as to see whether the results are truly closing on getting the
design done. The dashboard system can be used for any kind
of digital design and it is a generic solution for tracking and
extraction of ASIC design status. This provides simple and
user friendly web based view to identify status, list of errors
and warnings of the design, which reduces the huge effort and
manual work of ASIC designer.


ACKNOWLEDGMENT
This work has been fully supported by Infineon
Technologies Bangalore and RVCE E & C Department
Bangalore. The author wishes to acknowledge the fruitful
discussions with Mr. Annaluru Raghu, Ravi Rajendra Prasad
of Infineon Technologies, Dr. Uttara Kumari, the HOD and Dr.
B.V. Uma, the Dean of M. Tech E & C Department RVCE
Bangalore.

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