1

Hello, in
two impo
reverse r
current. N
current to

(Refer Sl
See, it is
reverse r
that this i
off when
path also

Now com
layers P
1
and N
3
i
compared
as P
2.
So
reverse v
other wo


my last clas
ortant param
recovery tim
Now, what i
o 25% of the
lide Time: 1
s here, it is
recovery cha
is the triangl
n the current
o. So, t
rr
is an
ming to SCR
N
1
P
2
N
2.

is a very th
d to N
2.
N
1
i
o, therefore
voltage that j
rds B
AK
is p
Dep
India
ss I discusse
meters for d
me, t
rr
and th
is reverse re
e peak of the
:34)
t
rr
the time
arge is the ar
le area of th
become 0 fr
n indication o
R, the silico
P
1
is anode
hin layer hig
is the thickes
J
3
or the rev
junction J
3
c
ositive, junc
Powe
Prof. B
partment of
an Institute
L
d the diode a
iode that ar
he reverse re
covery time
e reverse reco
between the
rea, the shad
e triangle i
rr
from positive
of the maxim
on controlled
, N
2
is catho
ghly doped,
st among all
verse voltag
an block is v
ction J
1
and J
er Electronic
B. G. Fernan
Electrical E
of Technolo
ecture - 5
and silicon c
re to be used
ecovery cha
? It is a tim
overy curren

e negative 0
ded area her
into t
rr
divid
e value. It w
mum frequen
d rectifier is
ode and P
2
i
P
2
is slight
l the 4, dopin
ge that j
3
can
very small. S
J
3
are forwar
cs
ndes
Engineering
ogy, Bomba
controlled re
d in high fr
arge or the p
me between th
nt.
0 crossing to
re. We are c
ded by 2. Re
will become 0
ncy at which
s a minority
s gate. So, t
tly thicker a
ng level is m
n block is v
So, when the
rd biased and
g
ay
ectifier, SCR
requency cir
peak of the
he negative

o say 25% o
considering,
emember, dio
0, it continue
h the diode c
y carrier dev
there are 3 ju
also the dop
minimum the
very small. I
e device is fo
d J
2
is revers
R or thyristor
rcuits are; o
reverse reco
0 crossing o
of i
rr,
peak r
we are assu
ode does no
es in the neg
can operate.
vice. There
unctions; J
1,
ping level is
ere and p
1
is
I will repea
forward biase
e biased.
r. The
one is
overy
of the
rr and
uming
t turn
gative
are 4
,
J
2,
J
3
s less
same
at, the
ed, in
2

Yesterda
one is for

(Refer Sl

See here
leakage c
junction
Device g
negative
Current i
mode is
increases
the volta
about wh
when the

The appl
reverse b
Therefor
the break
appears a








ay I showed
rward blocki
lide Time: 4
e, from p to
current. So,
J
2
that is V
goes into con
resistance z
is determine
a forward, a
s the break d
ge at which
hen the devi
e device is re
lied voltage
biased, j
2
is
e, the entire
k down volta
across the th
you the SC
ing mode, V
:52)
q is a forw
if I
G
is 0 and
V
BO
appears
nduction mod
zone. Havin
ed by the loa
again a stab
down voltage
device goes
ice is forwa
everse biased
should be
forward bia
e reverse vol
age of junctio
yristor shou
CR character
V
AK
is positiv
ward blockin
d if the appl
across junc
de. Which p
ng gone into
ad. So, again
ble mode of
e of junction
s into conduc
ard biased or
d?
less than V
B
sed. Reverse
ltage appear
on J
1.
So, in
ld be less th
ristics. There
ve, I
G
or dev

ng mode, a
lied voltage
ction J
2,
J
1
a
ath it takes?
o conduction
n it is a stab
operation. S
n J
2
goes on r
ction mode b
r the operat
BR.
In the re
e voltage th
rs across jun
any circuit t
an the V
BR
r
e are 3 zone
vice current i
very small
is higher tha
and J
2
are, J
? It takes QR
n mode, cur
ble mode of
So, I told yo
reducing. In
by supplyin
tion in the f
everse bias
hat a junction
nction J
1.
So
the V
BR
or m
rating of the
es in the for
is very small

current tha
an the break
J
1
and J
3
are
R, it is unstab
rrent is limi
f operation, f
ou that is a
n other words
g the gate cu
first quadran
mode, junct
n J
3
can blo
o, the V
BR
is
maximum rev
SCR.
rward bias m
l. It is stable
at is flowing
k down volta
e forward bi
ble because i
ited by the
forward bloc
finite I
G
or
s, you can re
urrent. So, th
nt. What hap
tion J
1
and j
ock is very s
s an indicati
verse voltage
mode,
.
g is a
age of
iased.
it is a
load.
cking
as I
G

educe
hat is
ppens
j
3
are
small.
on of
e that
3

(Refer Sl

Now I st
N
2
then w
currents I
emitter o
current f
function
every 10

See, I
CBO
current g
for a tran
transistor

Similarly
thyristor?
and catho
current. Y











lide Time: 8
arted explain
we derived t
I
CBO1
and I
CB
open circuite
flowing from
of temperat
degree rise
O1
increases
gain approxim
nsistor T
1
? A
r T
1.

y, alpha
2
inc
? It is an em
ode current
Yesterday w
:05)
ning two tra
the expressio
BO2.
What is
ed. This asp
m collector to
ture, it incre
in the tempe
with the tem
mately equa
Alpha
1
incre
reases with
mitter current
of the thyris
we have deriv
ansistor analo
on for I
A
an
I
CBO1
? It is
pects, we ha
o base with
eases with t
erature.
mperature. W
al to I
C
divid
eases with I
the cathode
t of transisto
stor? Cathod
ved that equa

ogy, I said th
node current
a reverse cu
ave studied
emitter ope
temperature,
What are alp
ded by I
E.
Alp
I
A.
Why I
A
?
current of t
or T
2.
What i
de current is
ation.
here are two
in terms of
urrent flowin
in transistor
en circuited.
, it could ap
pha
1
and alp
pha
1
increas
I
A
is nothin
the thyristor
is the relatio
s the sum of

o transistors
gate current
ng from colle
r course. I
CB
Remember,
pproximately
ha
2
? They a
ses with I
E.
S
ng but the e
. Why catho
onship betwe
f anode curr
P
1
N
1
P
2
and
t and the lea
ector to base
BO
is the re
, it is very s
y be double
are common
So, what hap
emitter curre
ode current o
een anode cu
rent plus the
N
1
P
2
akage
e with
everse
strong
ed for
n base
ppens
ent of
of the
urrent
e gate
4

(Refer Sl

See here,
transistor
what hap
also incr
minus alp
increases
upper tra
this is fr
increases
sum of I
A
alpha
2
wi

See this
increased
because
increases
increases
sort of a
oscillator
to stabiliz

So theref
current.
infinity,
maximum
results in


lide Time: 10
, I
E1
the emi
r T
2
is a cath
ppens with a
eases. Here
pha
1
plus al
s. I will repe
ansistor is no
om the expr
s. If I
A
incre
A
plus I
G.
So
ill further in
s is this exp
d, alpha
1
inc
both alpha
1
s. This is so
s. I
A
increase
positive fee
rs, we use th
ze it.
fore, due to
So, when a
of course th
m value of a
n large anode
0:40)
itter current
hode current
a finite I
G
? A
is the expre
lpha
2
. So if I
eat, I said alp
othing but th
ression that
eases alpha
2

, if this curre
crease I
A.
pression. Sin
creases and t
1
plus alpha
ome sort of
e will result
dback, you w
his positive f
the positive
alpha
1
plus
hat equation
anode curren
e current her
of transistor
that is sum
A pulse of cu
ession, I
A
is
I
G
increases
phaincrease
he anode cu
we have de
also increa
ent increases
nce I
G
incre
therefore alp
a
2
, they hav
f a positive
in increase
would have
feedback. Al
e feedback,
alpha
2
appr
n is not vali
nt is determ
re.

r T
1
is anode
of I
A
plus I
G
urrent is app
equal to alp
suddenly, I
s with I
E,
the
urrent I
A.
I to
erived yester
ases because
s alpha
2
also
eases sudden
pha
2
increase
ve increased
feedback. S
of alpha
1
an
studied in y
most all the
a small I
G
roaches 1, b
id when alp
mined by the
e current itse
G.
This we h
plied to the g
pha
2
into I
G
I
A
increases.
e emitter cur
old you that
rday. So the
e the emitter
o will increa
nly, that inc
es. So, that r
d, denominat
So initially,
nd alpha
2
. T
your control
other system
will result i
because the
ha
1
plus alp
e load. Henc

elf. I
E2,
the e
have derived
gate circuit.
plus I
CBO1
p
Now, if I
A

rrent. The em
t if I
G
increa
refore, if I
A
r current of
se. So, incre
creases I
A.
N
results in aga
ator decrease
because I
G
That again in
theory class
ms, we use n
in a large I
A
e equation s
pha
2
equal t
ce, a small I
emitter curre
d yesterday. N
If I
G
increas
plus I
CBO2
by
increases, a
mitter curren
ases I
A
incre
A
increases a
transistor T
ease in alpha
Now, since
ain increase
es. Therefor
G
is increase
ncreases I
A.
S
s. Only may
negative feed
A
here, the a
says I
A
bec
to 1, becaus
I
G,
a gate cu
ent of
Now,
ses I
A

y one
alpha
1

nt for
eases,
alpha
1

T
2
is a
a
1
and
I
A
is
in I
A

re, I
A

ed, I
A

Some
be in
dback
anode
comes
se the
urrent
5

(Refer Sl

So, this i
trigger th
than the l

(Refer Sl

See here,
gate has
which is
It is like
happens
lide Time: 14
is one of the
he thyristor,
latching curr
lide Time: 15
, the latching
no control.
less than the
this, withou
if there is a l
4:51)
e ways to trig
I
G
should be
rent.
5:28)
g current, th
To turn off
e holding cu
ut holding, h
large dv by d
gger the thyr
e present till
his is the latc
f the thyristo
rrent and ho
how can you
dt across the

ristor. What
l the current

ching current
or, the devic
olding curren
u latch? So, t
e device?
is the condi
t through the
t, I
L.
Having
ce current s
nt is always l
this is the w

ition? If ther
e device is e

g gone into c
should be re
less than the
way to remem
re is a finite
equal to or h
conduction m
duced to a v
e latching cu
mber. Now,
I
G
to
higher
mode,
value
urrent.
what
6

You are f
figure (0
between
dv by dt,
C
j2,
I
j2
wi
.
Now, thi
by transi
approach
you apply
without I

(Refer Sl

So for su
applied v
positive
higher th
across th
conductio

I told you
they appr
result in
device ag
direct lig



forward bias
00:16:22), tra
emitter and
, I
j2
will incr
ill increase
s will result
istor action.
h 1, device w
y a large dv
I
G.
That is be
lide Time: 1
ummarizing,
voltage is hi
I
G
also you
han the latchi
he device. T
on mode bec
u that I
CBO1

roximately d
increase in a
gain goes int
ght radiation.
sed the devic
ansistor anal
base of T
1
b
rease. I
j2
wil
in the highe
Now, if th
will turn on. S
by dt, a pos
ecause of the
8:09)
, when the d
igher than th
can trigger
ing current.
This is anot
cause of the
and I
CBO2,
th
double for ev
alpha
1
and al
to conductio
.
ce, a large po
logy. Now,
base and aga
ll increase be
er leakage cu
ey get ampl
So, it is not
sitive dv by
e junction ca
device is fo
he forward
r the device
The third wa
ther way of
temperature
hese are the
very 10 deg
lpha
2
and in
on mode. Th
ositive dv by
there are ju
ain collector
ecause of th
urrent I
CBO1
lified by tra
only a positi
dt across the
apacitors.

orward biase
break over
. But I
G
sho
ay to trigger
f triggering
e effect.
strong funct
gree rise in te
case, alpha
1
here is yet an
y dt is appea
unction capa
r of T
1
and so
his dv by dt a
and I
CBO2
an
ansistor actio
ive I
G
will tr
e device, it w
ed, device go
V
BO,
if the
ould be pres
r the thyristo
the thyristo
tion of the te
emperature.
1
plus alpha
2
nother way o
aring across
acitors, there
o on. Now,
and because
nd this curre
on and if al
rigger the thy
will go into

oes into con
ere is no gat
sent till the
or is a large d
or also or t
emperature.
So if they i
2
approach 1
of triggering
it, so just se
e is one capa
if there is a
e of this capa
ent gets amp
lpha
1
plus a
yristor, in ca
conduction m
nduction mo
te current I
G
anode curre
dv by dt app
thyristor ma
They doubl
increase, this
, I
A
increase
g the thyristo
e this
acitor
large
acitor
plified
alpha
2

ase, if
mode
ode if
G.
By,
ent is
plying
ain to
e for,
s will
es and
or, by
7

(Refer Sl

See here
that will
thyristor
applicatio
through t

So, you
transmiss
ways or t
ways of
are (0

Now, wh
flowing,
current b
pulse is a












lide Time: 20
, I am radiat
increase a j
goes into
ons because
the conventi
trigger the
sion, HVDC
thyristors are
triggering th
0:21:18)
hat about th
immediately
builds up, wh
applied.
0:01)
ting light in
junction tem
conduction
e as the volt
onal wires, l
thyristor b
C. What exac
e triggered b
he thyristor
he switching
y device wil
hat is known
the junction
mperature, le
mode. So t
age level in
lead wires.
by the direc
ctly the HVD
by direct ligh
or thyristor
characterist
ll not start co
n as the dela

n, to this jun
akage curren
this method
ncreases, it m
ct light radi
DC is? We
ht radiation H
goes into co
tics? In the
onducting. T
ay time, t
d.
S
nction light
nts will incr
d, the last o
may be diffi
iation, this
e will see so
HVDC syste
onduction m
forward blo
There is a fin
See here, som

is being rad
rease, they g
one is used
icult to pass
is used in
ometime late
ems. So, tha
mode if 1 of
ocking mode
nite time del
mewhere at
diated. Defin
get amplified
in high vo
s the gate cu
high voltag
er. So, one o
at is about va
f the 5 condi
e, when I
G
lay before d
this point, a
nitely,
d and
oltage
urrent
ge dc
of the
arious
itions
starts
device
a gate
8

(Refer Sl

See, ther
increase
determin
which is

(Refer Sl

Now, wh
Why it w
cathode p
to near g
lide Time: 2
e is a finite t
in current i
ned by the lo
approximate
lide Time: 22
hat happens i
will fail? See
periphery. In
ate cathode p
1:52)
time, only af
s determine
oad. Again h
ely say 1.5 to
2:40)
if rate of rise
, during the
nitially the d
periphery an
fter which th
d by the loa
here voltage
o 2 volts.
e in current i
initial turn o
device was b
nd it slowly s

he anode cur
ad, this near
e V
AK
starts

is very high?
on that occur
blocking, no
spreads with
rrent starts in
rby dt and a
decreasing
? If di by dt
rs, the initia
ow it starts c
h a finite vel

ncreasing. A
attains a val
and attains

is very high
al turn on occ
conducting a
ocity to the
Again this cu
lue given by
a very low v
, device may
curs near the
and it is con
entire juncti
urrent,
y, not
value
y fail.
e gate
nfined
ion.
9

Now in case, di by dt is very high, I told you the conduction is confined to a very small area, gate
cathode periphery in the beginning, current is increasing at a very fast rate, so definitely there
will be hot spots or over heating of the junction. So, if there are hot spots or over heating of the
junction, it may, device may get damaged. So remember, see it is here, I have written. Initial
turn on the device occurs near the gate cathode periphery. Before the turn on, device is blocking
and then it spreads with the finite velocity across the entire junction.

Now di by dt is high, there is a very small area that is available, current is confined to a small
area, so definitely there will be hot spots or over heating of the junction and therefore the
junction or the device will fail. So therefore, during turn on, di by dt has to be controlled. How to
control this di by dt? We will see some time later. Now what happens once the device has gone
into conduction mode? J
1
and J
2
were, sorry J
1
and J
3
were forward biased, J
2
was blocking, now
there is the junction J
2
breaks down, now it is highly saturated with minority carriers. Remember,
I will repeat, J
2
is saturated with minority carriers. See, it has a very special effect, the reverse
recovery current in a diode and because of minority carriers, they require a finite time to
recombine or to get neutralized. Definitely, similar effect will be there in the thyristor. I will
discuss it sometime later. Now, since J
2
is highly saturated with minority carriers, gate as no
further control. That is the reason I have been saying that having gone into condition mode, you
can withdraw the gate.

In fact, one should withdraw the gate signal because if the gate current is continuously flowing, it
has no control but then it will amount to power dissipation in the junction J
3
and because of
temperature arise, it may fail. Of course, it has a maximum power dissipation capability. So that
is about the conduction mode.

Now, how do you turn off the device? For turning it off, one has to reduce or current through the
device should be reduced below the holding value. Now, if the input is AC, beyond pi, voltage
will become negative. Input voltage becomes negative. So, there are chances of current also
reducing and becoming 0. If the input is DC, having triggered the thyristor and gone into
condition mode, how will you turn off the device?

So, device can be turned off by temporarily applying a negative voltage with other L and C
elements or in other words you have to reverse, you have to apply a reverse voltage across the
device. What happens? I
A
starts decreasing, becomes 0, it continues to conduct in a negative
direction, all most same thing that are happened in the diode.










10

(Refer Sl

See here
highly sa
can be tu
be or onl

(Refer Sl

Now, V
A
reverse c
reverse c
Then, fir
lide Time: 2
, whatever y
aturated with
urned off by
ly L, it depen
lide Time: 29
AK
is still po
current has re
current whic
rst J
1
blocks
8:33)
you can take
h minority c
temporarily
nds.
9:06)
ositive, till j
eached a pea
ch is a peak
s and then J
e down this
carriers, gate
applying a n
junction J
1

ak, somethin
k, junctions
J
3,
I will rep

explanation
e has no con
negative vol

J
3
starts to b
ng known as
begin to blo
peat, when
n, this is abo
ntrol. Then,
ltage using o
become rev
s I
RR,
you hav
ock both J
1
the peak, w

out the turn
SCR cannot
or in addition

verse biased.
ve seen in a
and J
3,
they
when the rev
on process.
t be turned o
n to L and C
. Now, whe
a diode, when
y begin to b
verse curren
. J
2
is
off or
C may
n the
n this
block.
nt has
11

attained a
J
1
blocks
less heav

When thi
current, w
See, I wi
recovery
leakage i
decays an
had only

By the w
is the rea
they requ
time. See

(Refer Sl

Anode cu
the negat
higher co
fast and
charge ca

So, there
thyristor
were atta
they have
is compl
a peak, nega
just before
vily doped co
is happens, r
will cause a
ill repeat tha
current cau
inductance e
nd it attains
one junction
way, J
2
is still
ason, gate as
uire a finite t
e this part is
lide Time: 32
urrent starts
tive current
ompared to
it attains a l
arriers in tha
efore SCR sh
till junction
ained the blo
e to recombi
leted, positiv
ative peak, b
J
3
? J unction
ompared to N
reversed cur
voltage over
at the revers
uses a volta
effect that du
s a very low
n, here we h
l forward bia
s no control
time to recom
for not there
2:36)
decreasing,
or the reve
that for diod
ow value bu
at junction. T
hould not be
n J
2
has attai
ocking mod
ine, it takes
ve dv by dt
both junction
n J
3
or N
3
is h
N
2.
So, J
1
blo
rrents starts
r shoot acros
se currents s
age over sho
ue to the stra
w value. This
ave two junc
ased because
having gone
mbine or to g
e. See, I wil
V
AK
is still
erse current
de and once
ut then junct
They take a c
e forward bia
ined the blo
e, J
2
is still
considered
t should not
ns, they begi
highly doped
ocks first, the
decaying. N
ss the device
tarts decayin
oot, L di by
y inductance
s process is
ctions.
e there were
e into conduc
get neutraliz
ll explain to

l positive, it
attains a pe
e J
1
and J
3
ha
tion J
2
is stil
considerable
ased or posit
cking mode
forward bia
amount of ti
t be applied
in to block.
d, where J
1
is
en J
3
blocks.
Now, this fas
e due to the l
ng towards
y dt effect a
e and this re
almost the s
large numb
ction mode
zed and this t
you with the
becomes 0,
eak value of
ave blocked
ll forward bi
e amount of t
tive voltage
, forward bl
ased because
ime. Till thi
d across the
J
1
blocks ju
s between P
1

st decaying c
leakage cond
0 now and t
across the d
verse recove
same as the
bers of minor
that is what
takes consid
e figure.

V
AK
starts
f I
RR
and th
d, this curren
iased. There
time.
should not a
locking mod
e there are m
s occurs or t
e thyristor b
st before J
3.
1
and N
1
and
current, a re
ductance eff
this fast dec
device due t
ery current, I
diode. Ther
rity carriers.
I told you. N
derable amou
falling. This
his value is m
nt starts deca
e are still res
appear acros
de. J
1
and J
3
minority car
till this proc
because J
2
a
Why
N
1
is
everse
fect.
cay of
to the
I said
re we
That
Now,
unt of
s, I
RR,

much
aying
sidual
ss the
,
they
rriers,
cesses
as not
12

attained
conductio
have bro
from ther

(Refer Sl

Now, wh
I
A
curren
withstand
capable o
here and
J
3
is not a

















a blocking
on mode. So
oken, this ju
re I am not, p
lide Time: 35
hat is t
q
? It is
nt, the anod
ding forward
of withstand
it becomes
attaining the
mode and
o see, this is
st indicates
positive volt
5:39)
s a minimum
de current
d voltage, w
ding forward
if the SCR i
blocking m
in case if y
time period
that this is
tage or SCR
m time interv
has become
ithout turnin
d voltage wit
s getting for
mode. So, this
you apply a
d t
q
. What ex
a break bec
R, a positive v

val between
e 0 and the
ng on. See th
thout turning
rward biased
s has to be en
a positive dv
xactly t
q
I w
cause this ti
voltage appe
on state, I
A
e instant w
he instant of
g on. In case
d somewhere
nsured.
v by dt dev
will define. S
ime could b
ears across th

current beco
when thyristo
f current bec
e, dv by dt b
e here, it wil
vice will go
ee, at this po
be significan
he thyristor.
omes 0. See
or is capab
coming 0 and
becomes po
ll turn on bec
o into
oint I
nt and
here,
ble of
d it is
sitive
cause
13

(Refer Sl

Now, wh
current to
blocking
during tu
you have
voltage a
naturally
current m
turn it of

Again, an
current, r
drop, off
sides. di
required
sometime
will expl











lide Time: 36
hat are the i
o assess its s
voltage sam
urn on and d
e to reverse
across the thy
y, it is fine.
may go, beco
ff forcibly.
nother impor
reverse bloc
f state curren
by dt turn o
to design p
e later. Snub
ain to you.
6:43)
important pa
suitability w
me like diod
during turn o
bias it, only
yristor to tur
It may happ
ome 0 and th
rtant parame
cking voltage
nt. Again th
on or during
protection ci
bber circuit
arameters w
with the powe
de, constant
off. Why dur
y you are or
rn it off. Som
pen naturall
hyristor will
eter is reappl
e to assess t
hese 2 to cal
turn on and
ircuit, what
which prote

ith the thyri
er circuit, sa
voltage dro
ring turn off
in other wo
mehow, you
ly sometime
l turn off its
lied dv by dt
the suitabilit
lculate the h
d during turn
is known a
ects the devi
istor? Simila
ame thing as
op to determ
f? You have
ords, forcibly
u have to red
e, it we will
own and if
t. See here, t
ty with a po
heat sinks or
n off and rea
as a snubber
ice against d

ar to diode,
s in the case
mine the hea
e to apply a
y you have t
duce that cur
l see. In cer
the input is
these are the
ower circuit,
r to determin
applied dv b
r circuit. I w
di by dt and
average for
of diode, re
at sinks, di b
negative vol
to apply neg
rrent if it hap
rtain applica
DC, you ha
e average for
, on state vo
ne the heat
by dt. These
will come to
d dv by dt, h
rward
everse
by dt
ltage,
gative
ppens
ations
ave to
rward
oltage
sinks
2 are
o that
how I
14

(Refer Sl

I square
switching
explained
will go in
other wo
there is a

See I wil
by dt is a
a large v
there is a
point sho

So, how
control th
No, you
avoided f











lide Time: 39
R rating sim
g capability,
d to you tha
nto conducti
rds device s
a di by dt and
ll repeat, the
a voltage spi
oltage spike
a current lim
ould lie withi
do I addres
he rate of ch
use a resis
for higher fr
9:20)
milar to dio
, the importa
at because of
ion mode. A
hould be pro
d there is alw
ere is always
ike that may
e could dama
mit and there
in SOA, safe
ss these two
hange of volt
ter and a ca
requency. He
ode and agai
ant paramete
f the J
2
junc
Also, voltage
otected if the
ways some st
s some strain
y appear acro
age the thyri
is a power li
e operating a
o issues or w
tage? Natura
apacitor. Se
ere it may be

in device tu
er. Now, how
ction capacit
e across the
ere is a spuri
trained attain
ned attains in
oss the thyris
istor because
imit. I have
area.
which passi
ally use a ca
ee, the other
e required, n
urn off time
w do I limit
tance if ther
thyristor sho
ious spike th
ns.
n the circuit
stor. So, in a
e all that dev
told you tha
ive element
apacitor. Can
r day I told
no choice.

t
q
to assess
di by dt and
re is a large
ould not exc
hat could hap
t and if there
addition to th
vices, there i
at at any give
will I use t
n I directly u
d you that re
s high frequ
d dv by dt?
dv by dt, d
ceed its rate
ppen whene
e is di by dt,
he normal su
is a voltage
en time oper
to suppress
use the capac
esister shou
uency
I had
device
or in
ver if
, L di
upply
limit,
rating
or to
citor?
uld be
15

(Refer Sl

So, one w
we know
you turn
Assume
current w
Now, wh
starts cha
thyristor.

So, by co
voltage a
and 2 res
Now, wh
transferre
this way
dischargi

See, in a
devices,
has to ca
discharge

So in thi
capacitor
diode. So
SCR and
flowing d
considere
lide Time: 42
way to contr
w that capaci
n it off, wha
that initially
was flowing
hat happens?
arging. Capa
.
ontrolling or
across the thy
sistors. Why
hen you turn
ed to the loa
y. Now, if t
ing current in
addition to
again it depe
arry. So, R
e current sho
is combinat
r or during t
o, current sta
d during turn
during turn
ed as the turn
2:08)
rol dv by dt i
itor does not
atever the c
y the thyrist
through the
? All the cur
acitor voltag
r by choosin
yristor. See
am I using
n on the devi
ad. In other w
there is no
n addition to
the load cu
ends on the
should be r
ould be contr
ion, what h
the turn off
arts flowing
n on, capacit
on, because
n off snubbe
is to have a R
t allow insta
urrent that
tor is on, so
e device det
rrent that wa
ge will increa
ng suitable v
, there are ot
2 resistors a
ice again, w
words, capac
resistor or
o the others,
urrent and th
circuit confi
rated such th
rolled during
happens is o
f time, durin
through D
1
or R
1
R
2
and
e we have to
ers.

RC snubber
antaneous vo
was flowing
voltage acr
termined by
as flowing, s
ase and that
value of R a
ther combina
and a diode h
whatever the
citor has to d
if the resist
current will
his could be
iguration tha
hat discharg
g turn on.
only R
1
com
ng the turn o
R
1
and C, du
d maybe, you
o control di
, snubber cir
oltage chang
g, it starts f
ross this is
y the load, n
starts getting
voltage is n
and C, you c
ations also.
here? Now,
charge store
discharge. S
tor is very
l flow throug
e the revers
at capacitor d
ged current i
mes in series
off time bec
uring chargi
u would like
by dt anyw

rcuit. Now, i
ge. So, what
flowing thro
as slow as
now you wa
g diverted he
nothing but v
can control t
See here, I h
what happe
ed in the cap
o, capacitor
small, wha
gh the SCR.
se recovery
discharge cu
is controlled
s during the
cause R
2
is
ing or during
e to reduce t
ay. So, this
it does not a
t happens? W
ough this ci
1.5 or 2 vol
ant to turn i
ere and capa
voltage acros
the rate of ri
have used a d
ns in this cir
pacitor, it w
will dischar
at happens i
current of
urrent also d
d during tur
e charging o
bypassed by
g turn off tim
the current th
is, this or th
allow,
When
ircuit.
lts. A
it off.
acitor
ss the
ise of
diode
rcuit?
will be
rge in
is the
other
device
rn on,
of the
y this
me of
hat is
his is
16

Now, how
Which p
connect i
L and RC

(Refer Sl


How abo
are vario
current is
come in
signal is

So, if yo
high and
across th
determin

So defini
features,
circuit fr
transform
transform

See here
of the tra
a pulse a
d phi by
only, ther
w do I contr
assive eleme
it in series as
C will protec
lide Time: 47
out the gatin
ous types of
s higher than
series with t
applied, gate
u see in this
d this is very
he thyristor,
ned by the oth
itely, we nee
you isolate
rom the po
mer that is us
mer? It has to
, I have just
ansformer, w
at the rising e
dt and there
re is a voltag
rol di by dt?
ent will I us
s shown in t
ct the device
7:24)
ng requireme
f snubbers o
n the latching
the load and
e and the cat
s circuit V
AK
y low, pleas
the forward
her circuit h
ed to isolate
the control c
wer circuit?
sed in gate d
o just pass th
shown a tra
what happens
edge and at t
e is d phi by
ge induced h
? Now, shou
se? Definitel
this figure. T
against di b
ent? I will ju
or protective
g current tha
d gate is, gat
thode termin
K,
not during
se V
AK
is no
d blocking
here, power c
e the control
circuit from
? One way
drive circuit
he pulses.
ansformer he
s? Transform
the falling e
y dt. So, ther
here.
uld not allow
ly, we need
This will not
by dt as well
ust briefly to
e circuits. N
at is essentia
te control ele
nal. The volt
g conduction
ot during th
mode or wh
circuit.
l circuit from
the power c
to use is
is known as
ere. If I give
mer is nothin
dge. After a
re is only du
w a fast rising
to use an in
allow a fast
as dv by dt.
ouch up on
Now, I
G
shou
al. I told you
ement is the
tage that is re
n, not during
e on time, t
hen it is re
m the power
circuit. Now
what is kn
s the pulse tr
e this sort of
ng but a diff
all, this work
uring d phi b
g current thr
nductor, a sm
t rising curre


these issues
uld be prese
that anode a
e gate eleme
equired is ve
g on time, th
the voltage
everse biased
r circuit. Thi
w, how do I i
nown as a t
ransformer.
f a wave for
ferentiator. S
ks as a differ
by, if the d p
rough the de
mall inducto
ent. So these
s. Similarly,
ent till the a
and cathode,
ent, a gate co
ery small.
his could be
that is appe
d, its compl
is is one of
solate the co
transformer.
Why it is a
rm to the pri
So, I will get
rentiator. Th
phi by dt is
evice.
r you
e two,
there
anode
, they
ontrol
e very
earing
letely
those
ontrol
The
pulse
imary
t only
ere is
there
17

It so happ
this regio
saturated
then, SCR
even if I

Now, ho
need to u
sharp pul
I get 2 sh
very low
sharp pul
series of

(Refer Sl
There is
narrow p
saturated
circuit. T
current a

So, induc
switch at
was flow
small res
winding
circuit or
frequency
edge of t
pens that tra
on there is n
d in this regio
R requires a
keep a broad
w do I addr
use the trans
lse here and
harp pulses.
w reverse bre
lse in the po
pulses and u
lide Time: 5
a pulse tran
pulses, they
d. So, they ar
Transistor is
re flowing th
ctive circuit,
t this point,
wing during t
sistor is also,
has some re
r in the coll
y of this pu
the signal. S
ansformer ma
no d phi by
on. So, there
a gate pulse t
d pulse here
ress this issu
sformer. Tra
a negative s
So, that was
eak down vo
ositive. So, w
use this circu
1:57)
nsformer, thi
are very sm
re reproduce
on during th
hrough the tr
, current, yo
you have to
this period. S
, people conn
sistance and
lective circu
lses. I told y
So, I am usi
ay get satura
dt and there
e is a sharp p
till the curre
, at the outpu
ue? I have t
ansformer is
sharp pulse a
s the negativ
oltage. So, I
what is bein
uit.
s pulses are
mall pulses.
ed in the seco
his period an
ransformer.
u cannot bre
o provide a p
So, you conn
nect here. I a
d in addition
uit, it all dep
you, there w
ing this diod
ated in this re
efore no vol
pulse here a
ent through th
ut I get just 2
to provide is
s nothing bu
at the falling
e sharp puls
I have to bl
g done is in

applied to t
. So, I am
ondary, same
nd is off duri

eak the indu
path for the
nect a transi
am not conn
you may co
pends on V
C
will be negat
de to block
egion and if
ltage. So, I a
and there is a
the device is
2 sharp plus
solation. In
ut a differen
g edge. So, e
se that should
lock negativ
nstead of hav
the base of t
assuming th
e pulses. See
ing this perio
uctive circuit
magnetizing
istor across t
nect a resiste
onnect some
CC,
the resist
tive spike in
that negativ
f transformer
assume that
another shar
higher than
es.
order to pro
ntiator. Throu
even if there
d be blocked
ve gate pulse
ving 1 broad

the transisto
hat transform
e, transform
od. When th
t but then wh
g current tha
the inductor
er because I a
load resistan
tance of the
n the second
ve spike. On
rs get saturat
transformer
rp pulse here
n the latching
ovide isolati
ugh a dc, I
e is a broad p
d because J
3
e and I have
d pulse, you
r. These are
mer will no
mer is an indu
he transistor i
hen you ope
at is flowing
. See, genera
am assuming
nce in the em
winding an
dary at the fa
nly apply a
ted in
r gets
e. But
g. So,
ion, I
get a
pulse,
has a
e just
have
e very
ot get
uctive
is on,
en the
g, that
ally a
g that
mitter
nd the
alling
large
18

number of series pulses. We require large number of series pulses because if the load is highly
inductive, with one pulse thyristor may not turn on.

See, there are various types of loads and gating requirement depends strongly on the type of
loads. It does not depend only on thyristor. After all, current through the device, is determined by
the load. So, gating requirement also varies with the load. So invariably, a high frequency gating
pulses are used to trigger the thyristor in general. But then, in our entire analysis, we will assume
that 1 sharp pulse will trigger the thyristor.

See I will repeat, gating requirement is a strong function of load because anode current is
determined by the load and gate pulses should be there till I
A
is equal to I latching. So invariably,
high frequency gate pulses are applied, but then for our analysis, we will assume that a sharp
pulse is sufficient to trigger the thyristor. So, with that I conclude todays lecture. More on this,
we will see in our next class.

Thank you.