DCS- II

Lab File


- Anupam Sobti
17/EC/09
INDEX
S.No. Name of the Experiment Sign
1. 4-bit Encoder, Decoder and
Binary to gray converter
2. Flip-flop, register and latch
3. Divide by 5 FSM
4. Traffic Light Controller
5. Binary and BCD Counter
6. Data De-multiplexer
7. Data Coder-Decoder
8. Serial In Parallel Out Shift Register
9. ALU
Experiment 1
Aim: Design of combinational circuit 2-4 encoder and
decoder and a binary to gray code converter.

VHDL Code: (Decoder)















library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity decoder is
Port ( enable : in STD_LOGIC;
input : in STD_LOGIC_VECTOR (1 downto 0);
output : out STD_LOGIC_VECTOR (3 downto 0));
end decoder;

architecture arch_decoder of decoder is

begin

process(enable,input)
begin

if(enable = '0') then
output <= (OTHERS => '0');
else case input is
when "00" =>
output <= (0=>'1', OTHERS => '0');
when "01" =>
output <= (1=>'1', OTHERS => '0');
when "10" =>
output <= (2=>'1', OTHERS => '0');
when "11" =>
output <= (3=>'1', OTHERS => '0');
when OTHERS =>
NULL;
end case;
end if;
end process;

end arch_decoder;

Simulation Result:






VHDL Code : (Encoder)













library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity encoder is
Port ( input : in STD_LOGIC_VECTOR (3 downto 0);
output : out STD_LOGIC_VECTOR (1 downto 0);
enable : in STD_LOGIC);
end encoder;

architecture arch_encoder of encoder is

begin

process(input,enable)
begin

if(enable = '0') then
output <= "ZZ";
else case input is
when "0001" =>output <= "00";
when "0010" => output <= "01";
when "0100" => output <= "10";
when "1000" => output <= "11";
when OTHERS => output <= "ZZ";
end case;
end if;
end process;

end arch_encoder;

Simulation Results:







VHDL Code: (Binary to Gray Code converter)













library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity binary2gray is
Generic(N: INTEGER := 3);
Port ( binary : in STD_LOGIC_VECTOR (N-1 downto 0);
gray : out STD_LOGIC_VECTOR (N-1 downto 0));
end binary2gray;

architecture Behavioral of binary2gray is
signal i: INTEGER :=0;
begin

gray(N-1) <= binary(N-1);
F: FOR i in N-2 downto 0 GENERATE
begin
gray(i) <= binary(i) xor binary(i+1);
end GENERATE F;

end Behavioral;

Simulation Results:


Experiment 2
Aim: Model a flip-flop, register and a latch with synchronous
and asynchronous rate.
VHDL Code: (D Flip Flop with asynchronous and synchronous reset)


















library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity DFlipFlop is
Port ( clk : in STD_LOGIC;
D : in STD_LOGIC;
Q : out STD_LOGIC;
sreset : in STD_LOGIC;
asreset : in STD_LOGIC);
end DFlipFlop;

architecture arch_dff of DFlipFlop is

begin

process(clk,D,sreset,asreset)

begin

if(asreset = '1') then

Q <= '0';

elsif(clk'EVENT and clk = '1') then

if(sreset = '1') then
Q <= '0';
else Q <= D;
end if;

end if;

end process;

end arch_dff;

Simulation Results:


VHDL Code: (Register)












library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity my_register is
Generic( N : INTEGER := 8);
Port ( clk : in STD_LOGIC;
load : in STD_LOGIC;
asreset : in STD_LOGIC;
sreset : in STD_LOGIC;
input : in STD_LOGIC_VECTOR (N-1 downto 0);
output : out STD_LOGIC_VECTOR (N-1 downto 0));
end my_register;

architecture arch_register of my_register is

begin

process(clk,asreset,sreset,input)
begin
if(asreset = '1') then
output <= (OTHERS => '0');
elsif (clk'EVENT and clk = '1') then
if(sreset = '1') then
output <= (OTHERS => '0');
elsif( load = '1') then
output <= input;
end if;
end if;
end process;

end arch_register;

Simulation Result:


VHDL Code (Latch)













library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity latch is
Generic(N: INTEGER := 8);
Port ( clk : in STD_LOGIC;
asreset : in STD_LOGIC;
sreset : in STD_LOGIC;
input : in STD_LOGIC_VECTOR (N-1 downto 0);
output : out STD_LOGIC_VECTOR (N-1 downto 0));
end latch;

architecture arch_latch of latch is

begin

process(asreset,sreset,input,clk)
begin
if(asreset = '1') then
output <= (OTHERS => '0');
elsif(clk='1') then
if(sreset = '1') then
output <= (OTHERS => '0');
else output <= input;
end if;
end if;
end process;

end arch_latch;
Simulation Result:
















Experiment 3
Aim: Design of a state machine: Circuit to detect if an incoming
serial number is divisible by 5. Simulate the incoming serial
number with a clock and Data in which is set to high or low. The
incoming data is entering from the right. Use VHDL.

Finite State Machine


Description of States:
Each state represents the remainder when divided by 5. So the output is
1 only when the remainder is 0, i.e., the number is completely divisible by
5.


VHDL Code:




















library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Divide_By_5_FSM is
Port ( clk : in STD_LOGIC;
i,reset : in STD_LOGIC;
o : out STD_LOGIC);
end Divide_By_5_FSM;

architecture Behavioral of Divide_By_5_FSM is

TYPE state IS(state0, state1, state2, state3, state4);
SIGNAL pr_state,nx_state: state;
SIGNAL temp: STD_LOGIC;

begin

process(clk,reset)
begin
if(reset = '1') then
pr_state <= state0;
elsif(clk'EVENT and clk = '1') then
pr_state <= nx_state;
end if;
end process;

process(pr_state,i)
begin
case pr_state is
when state0 => temp <= '1'; if(i = '0') then nx_state <= state0;
else nx_state <= state1;
end if;
when state1 => temp <= '0'; if(i = '0') then nx_state <= state2;
else nx_state <= state3;
end if;
when state2 => temp <= '0'; if(i = '0') then nx_state <= state4;
else nx_state <= state0;
end if;
when state3 => temp <= '0'; if(i = '0') then nx_state <= state1;
else nx_state <= state2;
end if;
when state4 => temp <= '0'; if(i = '0') then nx_state <= state3;
else nx_state <= state4;
end if;
when OTHERS => NULL;
end case;
end process;

o <= temp;

end Behavioral;
Simulation Results:


Experiment 4
Aim: Design of a traffic lights controller.
Description of the controller:
The controller has three modes of operation:
1. Regular Mode
2. Night Mode
3. Testing Mode
In the regular mode of operation, traffic light controller is made such
that Green Light occurs T
RG
seconds after the Red light, indicating
Go. T
GY
seconds after the same, light goes Yellow, indicating the
traffic to slow down. Then, after a time delay of T
GR
seconds the
light becomes Red and the traffic is Stopped.
In this experiment, only the regular mode of the traffic lights is
implemented. The FSM is as under:






Simulation Results


VHDL Code
library ieee;
use ieee.std_logic_1164.all;

entity tlc_olld is
port(clk:in std_logic;
red:out std_logic;
yellow:out std_logic;
green:out std_logic);
end tlc_olld;

architecture tlc_arch of tlc_olld is
type state is (SRED,SYELLOW,SGREEN);
begin
process(clk)
variable tlcstate :state:=SRED;
variable count:integer:=0;
begin
if clk='1' then
case tlcstate is when SRED=> if count=10 then
tlcstate:=SGREEN;
count:=0;
else
count:=count+1;
red<='1';
yellow<='0';
green<='0';
end if;
when SYELLOW=> if count=2 then
tlcstate:=SRED;
count:=0;
else
count:=count+1;
red<='0';
yellow<='1';
green<='0';
end if;
when SGREEN=> if count=10 then
tlcstate:=SYELLOW;
count:=0;
else
count:=count+1;
red<='0';
yellow<='0';
green<='1';
end if;
when others => tlcstate:=SRED;
count:=0;
end case;
end if;
end process;
end architecture;
Experiment 5
Aim: Binary and BCD Counter
VHDL Code:














Simulation Results:


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity binarybcdcounter is
Generic( N: INTEGER := 4);
Port ( clk : in STD_LOGIC;
binarycount : out STD_LOGIC_VECTOR (N-1 downto 0);
bcdcount : out STD_LOGIC_VECTOR (N-1 downto 0));
end binarybcdcounter;

architecture Behavioral of binarybcdcounter is

begin

process(clk)
variable bcdcounttemp :STD_LOGIC_VECTOR(N-1 downto 0) := (OTHERS => '0');
variable binarycounttemp :STD_LOGIC_VECTOR(N-1 downto 0) := (OTHERS => '0');
begin
if(clk'EVENT and clk = '1') then
binarycounttemp := STD_LOGIC_VECTOR(unsigned(binarycounttemp)+1);
bcdcounttemp := STD_LOGIC_VECTOR(unsigned(bcdcounttemp)+1);
end if;
if(bcdcounttemp = "1010") then
bcdcounttemp := (OTHERS => '0');
end if;
binarycount <= binarycounttemp;
bcdcount <= bcdcounttemp;

end process;
end Behavioral;
Experiment 6
Aim: Data Multiplexer: Data is received on a high-speed 4 bit input
bus and is output on three 4-bit output bus one after other.
VHDL Code:














Results:
The output is tristated in
case of no output.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity data_demultiplexer is
Port ( datain : in STD_LOGIC_VECTOR (3 downto 0):="1111";
dataout1 : out STD_LOGIC_VECTOR (3 downto 0);
dataout2 : out STD_LOGIC_VECTOR (3 downto 0);
dataout3 : out STD_LOGIC_VECTOR (3 downto 0);
sel : in STD_LOGIC_VECTOR (1 downto 0));
end data_demultiplexer;

architecture arch_datademux of data_demultiplexer is

begin

process(sel,datain)

begin
case sel is when "00" => dataout1 <= datain;
dataout2 <= (OTHERS => 'Z');
dataout3 <= (OTHERS => 'Z');
when "01" => dataout1 <= (OTHERS => 'Z');
dataout2 <= datain;
dataout3 <= (OTHERS => 'Z');
when "10" => dataout1 <= (OTHERS => 'Z');
dataout2 <= (OTHERS => 'Z');
dataout3 <= datain;
when OTHERS => dataout1 <= (OTHERS => 'Z');
dataout2 <= (OTHERS => 'Z');
dataout3 <= (OTHERS => 'Z');
end case;
end process;
end arch_datademux;
Experiment 8
Aim: Serial In Parallel Out Shift Register
VHDL Code:












Simulation Results:

library ieee;
use ieee.std_logic_1164.all;

entity sipo is
port(sin,clk,rst,enable:in std_logic; o:out
std_logic_vector(3 downto 0));
end sipo;

architecture sipo_arch of sipo is
signal temp:std_logic_vector(3 downto 0);
begin
process(clk)
begin
if rst='1' then
temp<="0000";
else
if(clk'EVENT and clk='1' and enable='1') then
temp(3)<=temp(2);
temp(2)<=temp(1);
temp(1)<=temp(0);
temp(0)<=sin;
end if;
end if;
end process;
o<=temp;
end architecture;
Experiment 9
Aim: ALU using VHDL
VHDL Code:














Simulation Results:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity arithlu is
port(a,b:in std_logic_vector(6 downto 0);
z:out std_logic_vector(6 downto 0);
sel:in std_logic_vector(3 downto 0);
c:in std_logic);
end arithlu;

architecture alu_d_arch of arithlu is
begin
process(a,b,sel)
begin
case sel is
when "0000"=> z(6 downto 0)<=a and b;
when "0001"=> z(6 downto 0)<=a or b;
when "0010"=> z(6 downto 0)<=a xor b;
when "0011"=> z(6 downto 0)<=not a;
when "0100"=> z<=a+b;
when "0101"=> z<=a-b;
when "0110"=> z<=a+1;
when "0111"=> z<=a-1;
when "1000"=> z(6 downto 1)<=a(5 downto 0);
z(0)<='0';
when "1001"=> z(5 downto 0)<=a(6 downto 1);
z(6)<='0';
when others=> z<=(others=>'Z');
end case;
end process;
end architecture;