UNIT-I

OPERATING POINT AND Q POINT:

The term biasing appearing in the title of this chapter is an all-inclusive term for
the application of dc voltages to establish a fixed level of current and voltage. For
Transistor amplifiers the resulting dc current and voltage establish an operating point on
the characteristics that define the region that will be employed for amplification of the
applied signal. Since the operating point is a fixed point on the characteristics, it is also
called the quiescent point (abbreviated Q-point). y definition, quiescent means !uiet,
still, inactive. Figure ".# shows a general output device characteristic with four operating
points indicated. The biasing circuit can be designed to set the device operation at any of
these points or others within the active region. The maximum ratings are indicated on the
characteristics of Fig. ".# by a hori$ontal line for the maximum collector current I
Cmax
and
a vertical line at the maximum collector-to-emitter voltage V
CEmax
. The maximum power
constraint is defined by the curve P%
max
in the same figure. &t the lower end of the scales
are the cutoff region, defined by IB ', and the saturation region, defined by VCE less
than V
CEsat
.
The (T device could be biased to operate outside these maximum limits, but the
result of such operation would be either a considerable shortening of the lifetime of the
device or destruction of the device. %onfining ourselves to the active region, one can
select many different operating areas or points. The chosen Q-point often depends on the
intended use of the circuit. Still, we can consider some differences among the various
points shown in Fig below to present some basic ideas about the operating point and,
thereby, the bias circuit.
)f no bias were used, the device would initially be completely off, resulting in a Q-point
at A*namely, $ero current through the device (and $ero voltage across it). Since it is
necessary to bias a device so that it can respond to the entire range of an input signal,
point A would not be suitable. For point B, if a signal is applied to the circuit, the device
will vary in current and voltage from operating point, allowing the device to react to (and
possibly amplify) both the positive and negative excursions of the input signal. )f the
input signal is properly chosen, the voltage and current of the device will vary but not
enough to drive the device into cutoff or saturation. +oint C would allow some positive
and negative variation of the output signal, but the pea,to- pea, value would be limited
by the proximity of VCE - './IC - ' m&. 0perating at point C also raises some concern
about the nonlinearities introduced by the fact that the spacing between IB curves is
rapidly changing in this region. )n general, it is preferable to operate where the gain of the
device is fairly constant (or linear) to ensure that the amplification over the entire swing
of input signal is the same. +oint B is a region of more linear spacing and therefore more
linear operation, as shown in Fig. ".#. +oint D sets the device operating point near the
maximum voltage and power level. The output voltage swing in the positive direction is
thus limited if the maximum voltage is not to be exceeded. +oint B therefore seems the
best operating point in terms of linear gain and largest possible voltage and current
swing. This is usually the desired condition for small-signal amplifiers but not the case
necessarily for power amplifiers,
0ne other very important biasing factor must be considered. 1aving selected and
biased the (T at a desired operating point, the effect of temperature must also be ta,en
into account. Temperature causes the device parameters such as the transistor current
gain (-ac) and the transistor lea,age current (ICEO) to change. 1igher temperatures
result in increased lea,age currents in the device, thereby changing the operating
condition set by the biasing networ,. The result is that the networ, design must also
provide a degree of temperature stability so that temperature changes result in minimum
changes in the operating point. This maintenance of the operating point can be specified
by a stability factor, S, which indicates the degree of change in operating point due to a
temperature variation. & highly stable circuit is desirable, and the stability of a few basic
bias circuits will be compared.
For the (T to be biased in its linear or active operating region the following must
be true2
#. The base3emitter 4unction must be forward-biased (p-region voltage more positive),
with a resulting forward-bias voltage of about '.5 to '.6 ..
7. The base3collector 4unction must be reverse-biased (n-region more positive), with
the reverse-bias voltage being any value within the maximum limits of the device.
0peration in the cutoff, saturation, and linear regions of the (T characteristic are
provided as follows2
1. Linear-region operation:
ase3emitter 4unction forward biased
ase3collector 4unction reverse biased
2. Cutoff-region operation:
ase3emitter 4unction reverse biased
3. Saturation-region operation:
ase3emitter 4unction forward biased
ase3collector 4unction forward biased
DIFFERENT TYPES OF BIASING
1.Fixed Bias:
The fixed-bias circuit provides a relatively straightforward and simple introduction to
transistor dc bias analysis. 8ven though the networ, employs an npn transistor, the
e!uations and calculations apply e!ually well to a pnp transistor configuration merely by
changing all current directions and voltage polarities. The current directions are the actual
current directions, and the voltages are defined by the standard double-subscript notation.
For the dc analysis the networ, can be isolated from the indicated ac levels by replacing
the capacitors with an open circuit e!uivalent. )n addition, the dc supply V
CC
can be
separated into two supplies to permit a separation of input and output circuits. )t also
reduces the lin,age between the two to the base current I
B
. The separation is certainly
valid that V
CC
is connected directly to
B
and
C

Fixed Bias circi!:
E"i#a$e%! circi! &' Fixed (ias circi!:
F&r)ard Bias &' Base*E+i!!er:
%onsider first the base3emitter circuit loop. 9riting :irchhoff;s voltage e!uation
in the cloc,wise direction for the loop, we obtain

<ote the polarity of the voltage drop across B as established by the indicated
direction of IB. Solving the e!uation for the current IB will result in the following2
The e!uation is certainly not a difficult one to remember if one simply ,eeps in mind that
the base current is the current through B and by 0hm;s law that current is the voltage
across B divided by the resistance B. The voltage across B is the applied voltage
VCC at one end less the drop across the base-to-emitter 4unction (VBE).
)n addition, since the supply voltage VCC and the base3emitter voltage VBE are constants, the selection
of a base resistor, B, sets the level of base current for the operating point.
CollectorEmitter Loop
The collector3emitter section of the networ, appears in Fig. ".= with the indicated
direction of current I
C
and the resulting polarity across
C
. The magnitude of the collector
current is related directly to I
B
through

)
%
>?)

)t is interesting to note that since the base current is controlled by the level of
B
and I
C
is related to I
B
by a constant _, the magnitude of IC is not a function of the
resistance
C
. %hange
C
to any level and it will not affect the level of I
B
or I
C
as long as
we remain in the active region of the device. 1owever, as we shall see, the level of
C
will determine the magnitude of V
CE
, which is an important parameter.
&pplying :irchhoff;s voltage law in the cloc,wise direction around the indicated
closed loop of Fig. ".= will result in the following2
.
%8
@)
%
A
%
- .
%%
> '
.
%8
>.
%%
-)
%
A
%
and which states in words that the voltage across the collector3emitter region of a
transistor in the fixed-bias configuration is the supply voltage less the drop across
C
.&s a
brief review of single- and double-subscript notation recall that
.
%8
>.
%
-.
8
where V
CE
is the voltage from collector to emitter and V
C
and V
E
are the voltagesfrom
collector and emitter to ground respectively. ut in t!is case" since V
E
_ ' .,
we have
.
%8
>.
%
)n addition, since
.
8
>.

-.
8
and .
8
>' then
.
8
>.

:eep in mind that voltage levels such as VCE are determined by placing the
red(positive) lead of the .oltmeter at the collector terminal with the blac, (negative) lead
at the emitter terminal as shown in Fig. ".5. VC is the voltage from collector to ground
and is measured as shown in the same figure. )n this case the two readings are identical,
but in the networ,s to follow the two can be !uite different. %learly understanding the
difference between the two measurements can prove to be !uite important in the
troubleshooting of transistor networ,s.
Load-Line Analysis
The analysis thus far has been performed using a level of - corresponding with
the resulting Q-point. 9e will now investigate how the networ, parameters define the
possible range of Q-points and how the actual Q-point is determined. The networ, of
Fig. ".##a establishes an output e!uation that relates the variables I
C
and V
CE
in the
following manner2
V
CE =
V
CC
- I
C
R
C

The output characteristics of the transistor also relate the same two variables I
C
and
VCE as shown in Fig
)n essence, therefore, we have a networ, e!uation and a set of characteristics that
employ the same variables. The common solution of the two occurs where the constraints
established by each are satisfied simultaneously. )n other words, this is similar
to finding the solution of two simultaneous e!uations2 one established by the networ,
and the other by the device characteristics.
The device characteristics of I
C
versus V
CE
are provided in Fig. ".##b. 9e must
now superimpose the straight line defined by 8!. (".#7) on the characteristics. The
most direct method of plotting 8!. (".#7) on the output characteristics is to use the
fact that a straight line is defined by two points. )f we c!oose IC to be ' m&, we are
specifying the hori$ontal axis as the line on which one point is located. y substituting
I
C
- ' m& into 8!. (".#7), we find that
# V
CE
> V
CC
- (')
C
and
V
CE
> V
CC IC$' Ba
Fixed bias load line
)f we now c!oose V
CE
to be ' ., which establishes the vertical axis as the line on which
the second point will be defined, we find that I
C
is determined by the following e!uation2
' > .
%%
- )
%
A
%
as appearing on the above fig.
y 4oining the two points defined by above e!uations , the straight line
established by 8!. (".#7) can be drawn. The resulting line on the graph of Fig. ".#7 is
called the loa% line since it is defined by the load resistor
C
. y solving for the resulting
level of IB, the actual Q-point can be established as shown in Fig. ".#7.
)f the level of I
B
is changed by varying the value of B the Q-point moves up or
down the load line as shown in.Fig(a) )f V
CC
is held fixed and
C
changed, the load line
will shift as shown in Fig.(b). )f I
B
is held fixed, the Q-point will move as shown in the
same figure. )f
C
is fixed and V
CC
varied, the load line shifts
,O--E,TOR TO BASE BIAS ,IR,UIT:
&n improved level of stability can also be obtained by introducing a feedbac, path
from collector to base as shown in Fig.. &lthough the Q&point is not totally independent
of beta (even under approximate conditions), the sensitivity to changes in beta or
Temperature variations is normally less than encountered for the fixed-bias or emitter-
biased configurations. The analysis will again be performed by first analy$ing the base3
emitter loop with the results applied to the collector3emitter loop.
BaseEmitter Loop
Figure ".C= shows the base3emitter loop for the voltage feedbac, configuration. 9riting
:irchhoff;s voltage law around the indicated loop in the cloc,wise direction will result in
V
CC
& I
C

C
& I
B

B
& V
BE
& I
E

E
$ '
)t is important to note that the current through
C
is not I
C
but I
C
(where I
C
$'I
C
( I
B
).
1owever, the level of I
C
and I
C
far exceeds the usual level of IB and the approximation
I
C
D I
C
is normally employed. Substituting I
C*$
I
C
D?I
B
and I
E$
I
C
will result in
V
CC
& ?I
B

C &
I
B

B
& V
BE&
?I
B

E
$ '
Eathering terms, we have
V
CC
& V
BE &
?I
B
(
C
(
E
) - I
B

B$
'
and solving for I
B
yields

VOLTAGE-DIVIDER BIAS
)n the previous bias configurations the bias current I
CQ
and voltage V
CEQ
were a
function of the current gain (?) of the transistor. 1owever, since ? is temperature
sensitive, especially for silicon transistors, and the actual value of beta is usually not well
defined, it would be desirable to develop a bias circuit that is less dependent, or in fact,
independent of the transistor beta.
The voltage-divider bias configuration of Fig. is such a networ,. )f analy$ed on an
exact basis the sensitivity to changes in beta is !uite small. )f the circuit parameters are
properly chosen, the resulting levels of I
CQ
and V
CEQ
can be almost totally independent of
beta. Aecall from previous discussions that a Q-point is defined by a fixed level of I
CQ
and
V
CEQ
as shown in. The level of I
BQ
will change with the change in beta, but the operating
point on the characteristics defined by I
CQ
and V
CEQ
can remain fixed if the proper circuit
parameters are employed.
&s noted above, there are two methods that can be applied to analy$e the voltagedivider
configuration. The reason for the choice of names for this configuration will become
obvious in the analysis to follow. The first to be demonstrated is the e+act met!o% that
can be applied to any voltage-divider configuration. The second is referred to as the
appro+imate met!o% and can be applied only if specific conditions are satisfied. The
approximate approach permits a more direct analysis with a savings in time and energy. )t
is also particularly helpful in the design mode to be described in a later section. &ll in all,
the approximate approach can be applied to the ma4ority of situations and therefore
should be examined with the same interest as the exact method.
Exact Analysis
The input side of the networ, of the self bias circuit can be redrawn as shown in Fig shown
below for the dc analysis. The ThFvenin e!uivalent networ, for the networ, to the left of the base
terminal can then be found in the following manner2
&lthough the above 8! initially appears different from those developed earlier, note
that the numerator is again a difference of two voltage levels and the denominator is
the base resistance plus the emitter resistor reflected by (?@ #) certainly very similar
to 8!. (".#6).
0nce I
B
is ,nown, the remaining !uantities of the networ, can be found in the
same manner as developed for the emitter-bias configuration. That is,
Approximate Analysis
The input section of the voltage-divider configuration can be represented by the networ,.
The resistance
i
is the e!uivalent resistance between base and ground for the transistor
with an emitter resistor
E
. The reflected resistance between base and emitter is defined
by
i
$',(#)
E
. )f
i
is much larger than the resistance
7
, the current I
B
will be much
smaller than I
7
(current always see,s the path of least resistance) and I
7
will be
approximately e!ual to I
#
. )f we accept the approximation that I
B
is essentially $ero
amperes compared to I
#
or I
7
, then I
#
> I
7
and
#
and
7
can be considered series elements.
The voltage across
7
, which is actually the base voltage, can be determined using
the voltage-divider rule (hence the name for the configuration). That is,
Since i$ (?@ #)E - ?E the condition that will define whether the approximate
approach can be applied will be the following2

)n other words, if ? times the value of E is at least #' times the value of 7, the
approximate approach can be applied with a high degree of accuracy.
0nce VB is determined, the level of VE can be calculated from

and the emitter current can be determined from
The collector-to-emitter voltage is determined by
V
CE
=V
CC
& I
C

C
& I
E

E
but since IE- IC,
VCEQ $ VCC & IC'C(- E)
-&ad -i%e A%a$.sis:
The similarities with the output circuit of the emitter-biased configuration result in
the same intersections for the load line of the voltage-divider configuration. The load
line will therefore have the same appearance as that of Fig with
The level of I
B
is of course determined by a different e!uation for the voltage-divider
bias and the emitter-bias configurations.
FET BIASING:
Fixed Bias ,&%'i/ra!i&%:
SE-F BIAS ,ONFIGURATION:

0OSFET BIASING
The n-channel B0SF8T is to be biased in the saturation region, at an operating
point of %esire% %rain current" %rain voltage" an% gate voltage. The use of the !uadratic
)G-.ES relationship for a B0SF8T in saturation (e!uation =.C in laboratory assignment
=) re!uires ,nowledge of the mobility, oxide capacitance per unit area, the width and
length of the device, and the threshold voltage. For discrete components, these values
vary too much for the !uadratic relationship to be a good predictor. 0ne can measure
these !uantities in the laboratory, but the idea here is to get a design that wor,s without
,nowing all of the device parameters beforehand. For this example, let us assume that we
loo,ed up the data sheet of a discrete B0SF8T device that we are interested
in, and determined that its threshold voltage, .tn, is in the range of #.-to-C.. Aemember
that .ES must exceed the threshold voltage, .tn, for current to flow.
9e assume .tn > C.'. (worst case .tn in range of #.-C.). 9e set .ES > C.7=. so that we have
.ES-.tn > '.7=. of worst-case gate-source overdrive voltage. <ext, a C.6=. gate voltage is
arbitrarily chosen. Eiven that we want .ES > .E3.S> C.7=., this dictates that .S>'.=.. Hsing
0hm;s law, we get the source resistance, ASS > '.=./#m& > ='' I.
Ba,ing sure the condition for saturation, .GS J> .ES - .tn, is satisfied, the drain voltage is
chosen to be C.=. (.GS > C.=. 3 '.=. > C.'.). 9ith a supply voltage, .dd>=., and drain current
of #m&, this re!uires a #.= :I resistance (AG) between the supply and the drain terminal. <ext,
in order to set the gate voltage to at C.6=., we use a voltage divider as
shown in Fi/re 1-1 to derive .E > C.6=. from the supply, .dd>=.. The resistor ratio of Ab#2 Ab7
needs to be #2C. Therefore we set Ab#>#' :I and Ab7>C' :I. <ote that the bias networ, re!uires
#7= K& from the =. supply.
The sensitivity of the !uadratic )G-.ES characteristic of a B0SF8T in saturation is not as
severe as that of the exponential )-. characteristic of a diode. This means that .ES has to vary a
great deal more than say, .b, the applied voltage across a diode, for the same range of currents.
Sometimes, due to tolerances in fabrication, it can be tric,y to achieve the exact biasing current.
1owever, a simple solution is to ma,e one of the gate resistors, say Ab7, a potentiometer. This
allows one to tune and monitor the desired B0SF8T performance.