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2 MARKS QUESTIONS & ANSWERS


Unit 1
1. Define Computer Architecture.
Computer Architecture deals ith the structure a!d "eha#ior o$ a computer
i!cludi!% the i!$ormatio! $ormats&
2. Define processor clock and clock rate
Processor clock'
(rocessor circuits are co!trolled ") a timi!% si%!al called processor cloc*+the
cloc* de$i!es re%ular time i!ter#al called cloc* c)cle&
Clock Rate:
Cloc* rate+R,-.p c)cles.sec/h01
Where p is le!%th o$ o!e cloc* c)cle
3. Eplain the relation of throu!hput "ith eecution and response time
#hrou!hput:
The total amou!t o$ or* do!e i! a %i#e! time
2et us co!sider 2 cases'
-&1 Replaci!% the processor i! a computer ith a $aster #ersio!
2&1 Addi!% additio!al processor to a s)stem that uses multiple processors $or
separate tas*&
E3'4a!dli!% a! airli!e reser#atio! s)stems&
5ecreasi!% respo!se time almost ala)s impro#es throu%hput&So+i! case - "oth
respo!se time & throu%hput i!creases&I! case2 !o!e o$ the tas* %ets or* do!e
$aster+so throu%hput i!creases&4oe#er+ the dema!d $or processi!% i! the 2!d case
as almost as lar%e as the throu%hput+the s)stem mi%ht $orce re6uests to 6ueue
up&I!t this case i!creasi!% the throu%hput could also i!crease the respo!se
time+si!ce it ould decrease the aiti!% time i! 6ueue&Thus+i! ma!) real computer
s)stems+cha!%i!% either e3ecutio! time or throu%hput o$te! a$$ects the other&
3. .Define $%P& Rate and #hrou!hput Rate.
MI(S'
O!e alter!ati#e to time as the metric is MI(S/Millio! I!structio! (er Seco!d1
MI(S,I!structio! cou!t./E3ecutio! time 3-7777771&
This MI(S measureme!t is also called Nati#e MI(S todisti!%uish it $rom some
alter!ati#e de$i!itio!s o$ MI(S&
MI(S Rate'
The rate at hich the i!structio!s are e3ecuted at a %i#e! time&
Throu%hput'
The total amou!t o$ or* do!e i! a %i#e! time&
Throu%hput rate'
The rate at hich the total amou!t o$ or* do!e at a %i#e! time&
'. (hat is $)*+P&,(hat is its si!nificant,
(opular alter!ati#e to e3ecutio! time is Millio! 8loati!%9poi!t Operatio!s (er Seco!d
+a""re#iated me%a$lops orM82O(S "ut ala)s pro!ou!ced :me%a$lops;&The $ormula
$or M82O(S is simpl) the de$i!itio! o$ the acro!)m'
.
M82O(S,Num"er o$ $loati!%9poi!t operatio!s i! a pro%ram./E3ecutio!
time3-7777771&
A M82O(S rati!% is depe!de!t o! the pro%ram&5i$$ere!t pro%rams re6uire the
e3ecutio! o$ di$$ere!t !um"er o$ $loati! poi!t operatio!s&Si!ce M82O(S ere
i!te!ded to measure $loati!%9poi!t per$orma!ce+the) are !ot applica"le outside that
ra!%e&Compilers+as a! e3treme e3ample+ha#e aM82O(S rati!% !ear 7 !o matter
ho $ast the machi!e is+"ecause compilers rarel) use $loati!%9poi!t arithmetic&
-. Define CP%
The term Cloc*C)cles(erI!structio! Which is the a#era%e !um"er o$ cloc*
c)cles each i!structio! ta*es to e3ecute+ is o$te! a""re#iated as C(I&
C(I, C(U cloc* c)cles.I!structio! cou!t&
.. &tate and eplain the performance e/uation,
Suppose that the a#era%e !um"er o$ "asic steps !eeded to e3ecute o!e
machi!e i!structio! is S+ here each "asic step is completed i! o!e cloc* c)cle& I$
the cloc* c)cle rate is R c)cles per seco!d+ the pro%ram e3ecutio! time is %i#e! ")
T , /N 3 S1 . R
This is o$te! re$erred to as the "asic per$orma!ce e6uatio!&
0. (hat do 1ou mean 21 ali!ned and unali!ned address,
ali%!ed address'
< I! the case o$ =2"it ord le!%th+ !atural ord "ou!daries occur at address
7+>+?@@@@the ord locatio!s ha#e ali%!ed address&
< I! %e!eral+ ords are said to "e ali%!ed i! memor) i$ the) "e%i! at a ")te address
that is a multiple o$ the !um"er o$ ")tes i! a ord&
< 8OR EAAM(2E'
I$ the ord le!%th is -B/2")tes1+ ali%!ed ords "e%i! at ")te address 7+ 2+ >
u!ali%!ed address'
< There is !o $u!dame!tal reaso! h) ords ca!!ot "e%i! at a! ar"itrar) ")te
address& The ords are said to ha#e u!ali%!ed address&
While the most commo! case is to use ali%!ed address+ some computers allo the
u!ali%!ed ord address
3. (hat is the assem2l1 lan!ua!e notation, 4i5e eample.
To represe!t machi!e i!structio!s a!d pro%ram& e use assem"l) 2a!%ua%e
$ormat&
8or e3ample'
The stateme!t speci$ies a! i!structio! that causes the tra!s$er descri"ed a"o#e+
$rom memor) locatio! 2OC to processor re%isterR-&
Mo#e 2OC+ R-
The co!te!ts o$ 2OC are u!cha!%ed ") the e3ecutio! o$ this i!structio!+ "ut the old
co!te!ts o$ re%ister R- are o#erritte!&
The seco!d e3ample o$ addi!% to !um"ers co!tai!ed i! processor re%isters R-
.
a!d R2 a!d placi!% their sum i! R= ca! "e speci$ied ") the assem"l) la!%ua%e
stateme!t a!d the assem"l) la!%ua%e stateme!t ca! speci$) R2 a!d placi!% their
sum i!R=&
Add R-+ R2+ R=&
6. (hat is strai!ht line se/uencin!,
(rocess o$ $etchi!% a!d e3ecuti!% a! i!structio!C o!e at a time i! order o$
i!creasi!% address ith the help o$ i!$ormatio! i! pro%ram cou!ter&
17. &pecif1 the se/uence of operation in5ol5ed "hen an instruction is
eecuted.
a1 I!structio! 8etch
"1 I!structio! 5ecode
c1 Opera!d 8etch
d1 E3ecute
11. "hat are Condition Codes 8CC9, Eplain the use of them.
Co!ditio! Codes are the list o$ possi"le co!ditio!s that ca! "e tested duri!%
co!ditio!al i!structio!s&CC is used to test the co!ditio! /D+ ,+E1&
Fased o! this result+ Gump i!structio!s mo#e to speci$ied loop&CC $la%s represe!t
the #alue o$ processor that *eeps the i!$ormatio! a"out the results o$ #arious
operatio!s $or use ") co!ditio!al "ra!ches
12. (hat are addressin! modes,
H The di$$ere!t a)s i! hich the locatio! o$ a! opera!d is speci$ied i! a!
i!structio! is re$erred to as addressi!% modes&
H It is a rule $or i!terpreti!% or tra!slati!% addresses $ield o$ a! i!structio!
i!to a! e$$ecti#e address $rom here the opera!d is actuall) re$ere!ced&
13. Define a2solute addressin!,
A"solute addressi!% is de$i!ed as the opera!d is i! a memor) locatio!& The
address o$ this locatio! is %i#e! e3plicitl) i! the i!structio!& It ma) also called as
direct addressi!%&
Assem"ler s)!ta3' 2OC
Addressi!% $u!ctio!' EA,2OC
Where+
EA,E$$ecti#e address
1'. Define inde mode,
I!de3 mode is de$i!ed as the e$$ecti#e address o$ the opera!d is %e!erated
") addi!% a co!sta!t #alue to the co!te!ts o$ a re%ister&
&1m2olic Representation:
A/Ri1
Where+ A is a co!sta!t #alue
Ri is the !ame o$ the re%ister&
Addressin! function:
EA,IRiJKA
.
1-. (hat are ;um2er ;otations,
Whe! deali!% ith !umerical #alues+ it is o$te! co!#e!ie!t to use the $amiliar
decimal !otatio!& These #alues are stored i! the computer as "i!ar) !um"ers& I!
some situatio!s it is more co!#e!ie!t to speci$) the "i!ar) patter!s directl)& Most
assem"lers allo !umerical #alue to "e speci$ied i! di$$ere!t a)s&
8or e3ample the !um"er L= hich is represe!ted ") the ?9"it "i!ar) !um"er
7-7---7-& I$ this #alue is to "e used as a! immediate opera!d+ it ca! "e %i#e! as a
decimal !um"er&
A55 ML=+ R-
or as a "i!ar) !um"er ide!ti$ied ") a pre$i3 s)m"ol such as a perce!t si%!
A55 MN7-7---7-+ R-
Fi!ar) !um"ers ca! "e ritte! more compactl) as 4e3adecimal& The he3 !otatio!
o$ a $irst te! patter! 7777+777-+@@&&-77- are represe!ted ") the di%it 7+-+2@@&&L
as i! FC5 &The remai!i!% si3 >9"it patter!s are represe!ted as A+F+C+5+E+8& a he3
represe!tatio! is ide!ti$ied ") a dollar si%! pre$i3
A55 MOP5+ R-
1.. *ist out the methods used to impro5e s1stem performance.
The methods used to impro#e s)stem per$orma!ce are
(rocessor cloc*
Fasic (er$orma!ce E6uatio!
(ipeli!i!%
Cloc* rate
I!structio! set
Compiler
10. (hat is <1te Addressa2ilit1,
F)te Addressa"ilit) is used $or assi%!i!% successi#e memor) address to
successi#e memor) locatio!& This t)pe o$ assi%!i!% is used i! moder! computers&
O!e ")te,? "its&
E3'=2"its
Address'7+>+?&&&&
13. (hat is meant 21 <id=Endian and *ittle Endian.
The !ame "i%9E!dia! is used he! loer ")te addresses are used $or the most
si%!i$ica!t ")tes /the le$t most ")tes1 o$ the ord&
The !ame little9E!dia! is used he! loer ")te addresses are used $or the less
si%!i$ica!t ")tes /the ri%ht most ")tes1 o$ the ord&
16. (hat is meant 21 condition codes. *ist out the t1pes.
-& Ne%ati#e/N1
2& Qero/Q1
=& O#er$lo/O1
>& Carr)/C1
.
27. *ist out the additional modes used 21 the processor.
AutoI!creme!t 'The E$$ecti#e Address o$ the opera!d is the co!te!ts o$ a
re%ister speci$ied i! the i!structio!& A$ter accessi!% the opera!d+the co!te!ts o$ a
re%ister are automaticall) I!creme!ted to poi!t to the !e3t item i! a list&
ER' /R-1K
Auto5ecreme!t' The co!te!t o$ a re%ister speci$ied i! the i!structio! are
$irst automaticall) decreme!ted a!d are the! used as the e$$ecti#e address o$ the
opera!d
ER' 9/R-1
20. (hat do 1ou mean 21 Re!ister transfer,
I!structio! e3ecutio! i!#ol#es a se6ue!ce o$ steps i! hich data are
tra!s$erred $rom o!e re%ister to a!other& 8or each re%ister+ to co!trol si%!als are
used to place the co!te!ts o$ that re%ister o! the "us or to load the data o! the "us
i! to the re%ister&
To tra!s$er the co!te!ts o$ the re%ister R- to R>
/-1E!a"le the output o$ R- ") setti!% R-out to -& This places the co!te!ts o$ R- o!
the process "us&
/21E!a"le the i!put o$ Re%ister R> ") setti!% R>i! to -&This loads data $rom
processor "us i! to Re%ister R>&
U;%# =2
1. *ist out rules for <ooth recoded multiplier,
-& Start $rom 2SF chec* each "it o!e ") o!e&
2& Cha!%e the $irst o!e as 9-&
=& S*ip all succeedi!% o!es /record them as 0ero s1 u!til )ou see a 0ero+
Cha!%e this 0ero as o!e&
2. *ist out the rules for mul >di5 of floatin! point num2er,
$ultipl1 rule:
-& Add the e3po!e!t a!d su"tract -2S+
2& Multipl) the ma!tissa a!d determi!e the si%! o$ the result&
=& Normalise the resulti!% #alue+ i$ !ecessar)&
Di5ide rule:
-& Su"tract the e3po!e!ts a!d add -2S+
2& 5i#ide the ma!tissa a!d determi!e the si%! o$ the result+
=& Normalise the resulti!% #alue+ i$ !ecessar)&
3. (rite short notes on,
a1 Ruard "its&
"1 Tru!catio!&
.
'. Define the follo"in! terms.
-1 O#er$lo
21 U!der$lo
+5erflo":
I! the si!%le precisio!+ i$ the !um"er re6uires a e3po!e!t %reater the! K-2S
or i! a dou"le precisio!+ i$ the !um"er re6uires a! e3po!e!t $orm the o#er$lo
occurs&
Underflo":
I! a si!%le precisio! +i$ the !um"er re6uires a! e3po!e!t less tha! 92B or i! a
dou"le presitio!+i$ the !um"er re6uires a! e3po!e!t less tha! 9-722 to represe!t
its !ormali0ed $orm the u!der$lo occurs&
-. (hat is the principle of 2ooth multiplication,
Footh multiplicatio! is !othi!% "ut additio! o$ properl) shi$ted multiplica!d
patter!s&
It is carried out ") $olloi!% steps'
a1 Start $rom 2SF& Chec* each "it o!e ") o!e&
"1 Cha!%e the $irst o!e as 9-&
c1 S*ip all e3ceedi!% o!e s /record them as 0eros1 till )ou see a 0ero& Cha!%e this
0ero as o!e&
d1 Co!ti!ue to loo* $or !e3t o!e ithout distur"i!% 0eros+ precede usi!% rules "1+
a!d c1
.. Con5ert the follo"in! 2inar1 num2ers into 2ooth recorded form.
-1--7-7 Footh recrded $orm ,79--9-7
21-> Footh recorde $orm,-779-7&
0. *ist the t"o techni/ues used for speedin! up the multiplication process:
The to tech!i6ues used $or spreadi!% up the multiplicatio! process are
-1Fit pair recordi!% or modi$ied Footh al%orithm
21Carr) sa#e additio! o$ summa!ds&
3. (hat are the ad5anta!es of <ooth al!orithm,
-& It ha!dles "oth positi#e a!d !e%ati#e multipliers u!i$orml)&
2& It achie#es some e$$icie!c) i! the !o& o$ additio!s re6uired
Whe! the multiplier has a $e lar%e "loc*s o$ -s&
6. #he speed !ained ho"e5er 21 skippin! o5er 1?s depends on
The data&
Talue Represe!ted , K-&7--7&&3
.
17. (rite format for floatin! point in %EEE sin!leprecision format.
0 10001000. 0010110..
Talue Represe!ted , K7&77-7--7&&32
L
a1 U!Normali0ed Tersio!
0 10000101. 0110
2
B
"1 Normali0ed Tersio!
11. Define n=2it ripple=carr1 adder.
A cascaded co!!ectio! o$ ! $ull adder "loc*s ca! "e used to add to !9"it
!um"ers& Si!ce the carries must propa%ate or ripple+ throu%h the cascade+ the
co!$i%uratio! is called ! "9"it ripple carr) adder&
-2& *ist out the rules for add>su2 of floatin! point num2er,
-& Choose the !um"er ith the smaller e3po!e!t a!d shi$t its ma!tissa ri%ht a
!um"er o$ steps e6ual to the di$$ere!ce i! e3po!e!ts&
2& Set the e3po!e!t o$ the result e6ual to the lar%er e3po!e!t&
=& (er$orm additio! .su"tractio! o! the ma!tissa a!d determi!e the si%! o$ the
result&
>& Normali0e the resulti!% #alue+ i$ !ecessar)&
1. (hat is pipelinin!,
Unit = 3
A pipeli!i!% ma) "e #isuali0ed as a collectio! o$ se%me!ts called pipe sta%es
throu%h hich "i!ar) i!$ormatio! $los& Each se%me!t per$orms partial processi!%
as dictated ") the tas*& The result o"tai!ed i! each se%me!t is tra!s$erred to the
!e3t se%me!t i! the pipeli!e& The $i!al result is o"tai!ed a$ter the data passes
throu%h all the se%me!ts&
2. Eplain latenc1 and throu!hput.
2ate!c) ' Each I!structio! ta*es certai! amou!t o$ time to complete& This is called
as late!c)& It is the time di$$ere!ces he! a! i!structio! is issued a!d he! it is
completed&
Throu%hput ' The !um"er o$ i!structio!s completed i! a %i#e! time is called
Throu%hput&
3. (hat are the ma@or characteristics of a pipeline,
-& (ipeli!i!% ca!!ot "e impleme!ted i! a si!%le tas*& As it or*s ") splitti!%
multiple tas* i!to a !um"er o$ su"tas* a!d operati!% o! them simulta!eousl)&
2& The speedup or e$$icice!t) is achie#ed ") usi!% the pipeli!i!% depe!ds o! the
!um"er o$ pipe sta%es a!d the !um"er o$ a#aila"le tas* that ca! "e su"di#ide&
'. (hat is a pipe sta!e,
Each step i! a pipeli!e is called as a pipe sta%e
-. "hat is instruction pipeline,
The t)pe o$ pipeli!e hich or*s ") partitio!i!% the i!structio! e3ecutio!&
.. (hat are the 5arious sta!es in a pipelin! eecution.
I!structio! 8etch
I!structio! 5ecode
Opera!d $etch
Opcode E3ecutio!
Write "ac*
0. Define Pipeline AaBards,
The pipeli!e architectures or*s smoothl) as lo!% as it is a"le to ta*e up !e tas*
i! e#er) machi!e c)cle& I! practice there are suitautio! he! the !e3t i!structio!
ca! "e e3ecuted i! the $olloi!% machi!e c)cle& These e#e!ts called as pipeli!e
ha0ards&
3. &tate different t1pes of haBards that can occur in pipeline.
The t)pes o$ ha0ards that ca! occur i! the pipeli!i!% ere+
-& 5ata ha0ards&
2& I!structio! ha0ards&
=& Structural ha0ards&
5ata ha0ards'
A data ha0ard is a!) co!ditio! i! hich either the source or the desti!atio!
opera!ds o$ a! i!structio! are !ot a#aila"le at the time e3pected i! pipeli!e& As a
result some operatio! has to "e dela)ed+ a!d the pipeli!e stalls&
I!structio! ha0ards'
The pipeli!e ma) "e stalled "ecause o$ a dela) i! the a#aila"ilit) o$ a! i!structio!&
8or e3ample+ this ma) "e a result o$ miss i! cache+ re6uiri!% the i!structio! to "e
$etched $rom the mai! memor)& Such ha0ards are called as I!structio! ha0ards or
Co!trol ha0ards&
Structural ha0ards'
The structural ha0ards is the situatio! he! to i!structio!s re6uire the use o$ a
%i#e! hardare resource at the same time& The most commo! case i! hich this
ha0ard ma) arise is access to memor)&
6. (hat is superscalar processor,
Super scalar processor e3ploits parallelism hich has Multiple EU U!it each o$
hich is pipeli!ed a!d it co!stitutes i!depe!de!t I!structio! pipeli!e& The processor
has (CU desi%!ed to $etch a!d decode se#eral i!structio!s co!curre!tl) hich is
issued to pipeli!e EUU!its that E3ecutes se#eral i!structio! is the same&
17. (hat do 1ou mean 21 out=of order eecution, %s it Desira2le,
I! a pipeli!ed processor ith se#eral i!structio!s is process co!curre!tl) it is
(ossi"le $or i!structio! to $i!ish out o$ se6ue!ce+ o!e i!structio! $i!ishes "e$ore
A!other hich is issued earlier& as $or as mai! computatio! is co!cer!ed !o
4a0ards ill happe! "ut i$ a! i!terrupts occurs it creates the pro"lem&
11. (hat are AaBards,
A ha0ard is also called as hurdle &The situatio! that pre#e!ts the !e3t
i!structio! i! the i!structio! stream $rom e3ecuti!% duri!% its desi%!ated Cloc*
c)cle& Stall is i!troduced ") ha0ard& /Ideal sta%e1
12. *ist out Carious 2ranchin! techni/ue used in micro pro!ram control
unit,
a1 Fit9Ori!%
"1 Usi!% Co!ditio!al Taria"le
c1 Wide Fra!ch Addressi!%
13. Compare hard"ired control unit and micropro!rammed control unit
Attitude
4ardired Co!trol
Micro (ro%rammed co!trol
Speed
8ast
Slo
Co!trol $u!ctio!
Impleme!ted i! hardare
Impleme!ted is so$tare
8le3i"ilit)
Not $le3i"le+ to accommodated !e s)stem speci$icatio!s or !e i!structio!s&
More $le3i"le+ to accommodate !e s)stem speci$icatio!s or !e i!structio!s
redesi%! is re6uired&
A"ilit) to ha!dle lar%e comple3 i!structio! set
Some hat di$$icult
Easier
A"ilit) to support&
Ter) di$$icult
Eas)
5esi%! process
Somehat complicated
Orderl) a!d S)stematic
Applicatio!s
Mostl) RISI Micro processor
Mai!$rames+ Some Micro (rocessors
I!structio! si0e
Usuall) u!der -77 i!structio!s
Usuall) o#er -77 i!structio!s&
Chip area E$$icie!c)
Uses least area
Uses more Area
1'. (hat is micro pro!rammin! and micro pro!rammed control unit,
Micropro%rammi!% is a method o$ co!trol u!it desi%! i! hich the co!trol
u!it selectio! a!d se6ue!ci!% i!$ormatio! are stored i! ROM a!d RAM s called
co!trol store or co!trol memor)&Micro pro%rammed co!trol u!it is a %e!eral
approach used $or impleme!tatio! o$ co!trol u!it& 4ere co!trol si%!als are
%e!erated ") a pro%ram similar to machi!e la!%ua%e pro%rams
1-. (hat is meant 21 hard"ired control,
& It is the o!e that co!tai!s co!trol u!its that use $i3ed lo%ic circuits to
i!terpret i!structio!s a!d %e!erate co!trol si%!als $rom them&
< 4ere+ the $i3ed lo%ic circuit "loc* i!cludes com"i!atio!al circuit that
%e!erates the re6uired co!trol outputs $or decodi!% a!d e!codi!% $u!ctio!s&
1.. (hat is the necessit1 of !roupin! si!nals,
< It is used to reduce the !um"er o$ the "its i! the microi!structio!&
< It is used to o#ercome the dra"ac* o$ assi%!i!% i!di#idual "its to each
co!trol si%!al results i! lo!% microi!structio!s+ "ecause the !um"er o$ the re6uired
si%!als is usuall) lar%e+moreo#ero!l) a $e "its are used i! a!) %i#e! i!structio!&
10. *ist the techni/ues used for !roupin! of the control si!nals,
a1 Tertical or%a!i0atio!
"1 4ori0o!tal or%a!i0atio!
13. Define Do2 &e/uencin!.
It is a process o$ scheduli!% tas* that are aaiti!% i!itiatio! i! order to a#oid
collisio! a!d achie#e hi%h throu%hput&
16. (rite control si!nals for storin! a "ord in memor1.
R-
out
+ MAR
i!
R2
out
+ M5R
i!
+rite
M5R
out E
+ WM8C
27. (hat are the pro2lems faced in %nstruction Pipeline.
-& Resources Co!$ilicts
2& 5ata 5epe!de!c)
=& Fra!ch 5i$$iculties
21. (hat is Re!ister Renamin!,
I$ a temporar) re%ister assumes the role o$ the perma!e!t re%ister hose data it is
holdi!% a!d is %i#e! the same !ame is called as the Re%ister Re!ami!%
22. Ao" data haBard can 2e pre5ented in pipelinin!,
5ata ha0ards i! the i!structio! pipeli!i!% ca! pre#e!ted ") the $olloi!%
tech!i6ues&
< Opera!d 8orardi!%
< So$tare Approach
23. Eplain the 5arious approaches used to deal "ith Conditional
pipelinin!,
V A co!ditio! "ra!ch i!structio! i!troduces the added ha0ard caused ") the
depe!de!c) o$ "ra!ch co!ditio! o! result o$ a precedi!% i!structio!&
V Fra!chi!% i!structio! represe!t a"out 27 perce!t o$ the d)!amic i!teractio! cou!t
o$ most pro%rams&
V The d)!amic cou!t is the !um"er o$ i!structio! e3ecutio!+ ta*i!% i!to accou!t the
that same pro%ram i!structio! are e3ecuted ma!) times "ecause o$ loops&
These "ra!chi!% Wu!ctio!s ca! le ha!dled ") $olloi!% a)s+
-& 5ela)ed "ra!ch&
2& Fra!ch predictio!&
=& 5)!amic "ra!ch predictio!
U;%# '
1. (hat is memor1 s1stem,
E#er) Computer co!tai!s se#eral t)pes o$ de#ices to store the i!structio!s a!d data $or
its operatio!& These stora%e de#ices plus the al%orithm impleme!ts ") hardare a!d so$tare
!eeded to ma!a%e the stored i!$ormatio! $rom the memor) s)stem o$ computer&
2. 4i5e the classification of memor1
a& Cpu Re%ister
"& Mai! memor)
c& Seco!dar) Memor)
d& Cache&
3. Define &tatic $emories and D1namic $emories.
Memories that co!sist o$ circuits capa"le o$ retai!i!% their state as lo!% as poer is applied
are *!o!s static memories& I! 5)!amic Memories such cells do !ot retai! their state
i!de$i!itel)&
'. (hat is read access time,
A "asic per$orma!ce measure is the a#era%e time to read a $i3ed amou!t o$ i!$ormatio! $or
i!sta!ce+ o!e ord $orm the memor)& This parameter is called the read access time&
-. Define RA$
I! stora%e locatio! ca! "e accessed i! a!) order a!d access time is i!depe!de!t o$ the
locatio! "ei!% accessed+ the memor) is termed as ra!dom access memor)&
.. (hat is R+$,
Memories hose co!te!t ca!!ot "e altered o!li!e i$ the) ca! "e altered at all are read
o!l) memories&
0. (hat are PR+$s,
Semi co!ductor ROMs hose co!te!ts ca! "e cha!%ed o$$li!e9ith some di$$iculties is
called (ROMs&
3. (hat is &RA$ A;D DRA$,
SRAM'Static ra!dam access memor)& It te!ds to "e $aster&the) re6uire !o re$reshi!%
5RAM'5)!amic ra!dom access memor)& 5ata is stored i! the $orm o$ char%es& So
co!ti!uous re$reshi!% is !eeded&
6. (hat is 5olatile memor1,
A memor) is #olatile i$ the loss o$ poer destro)s the stored i!$ormatio!& I!$ormatio!
ca! "e stored i!de$i!itel) i! a #olatile memor) ") pro#idi!% "atter) "ac*up or other mea!s to
mai!tai! a co!ti!uous suppl) o$ poer&
17. (hat are the cate!ories of memories:
a& SRAM
"& 5RAM
11. (hat is flash memor1.
A rece!t semico!ductor tech!olo%) called $lash memor) o$ a same !o!9#olatilit) as a
(ROM+ "ut it ca! "e do!e a "it at a time&
12. (hat is cache memor1,
Memor) ord are stored i! cache data memor) a!d are %rouped i!to small pa%es called
cache "loc*s or li!e& The co!te!ts o$ the cache s data memor) are thus copies o$ a set o$ mai!
memor) "loc*s&
13. $ention t"o s1stem or!aniBation for caches.
To s)stem or%a!i0atio! $or caches are
a& loo* aside
"& loo* throu%h
1'. (hat is RA$<U& memor1,
The *e) $eature o$ Ram"us tech!olo%) is a $ast si%!ali!% method used to tra!s$er i!$ormatio!
"etee! chip usi!% !arro "us&
1-. (hat is "rite=throu!h protocol,
8or rite operatio!+the cache locatio! a!d the mai! memor) locatio! are updated
simulta!eousl)&
1.. 4i5e the difference 2et"een EEPR+$ and )lash memor1,
The primar) di$$ere!ce "etee! EE(ROM a!d $lash memor) is that $lash restricts rites
to multiple *ilo")tes "loc*s+ i!creasi!% the memor) capacit) per chip ") reduci!% area o$
co!trol&
10. Differences 2et"een cache memor1 and 5irtual memer1
-& I! caches+ replaceme!t is primaril) co!trolled ") the hardare& I! TM+ replaceme!t
is primaril) co!trolled ") the os&
2& The Num"er o$ "its i! the address determi!es the si0e o$ TM+ here as cache si0e is
i!depe!de!t o$ the address si0e&
=& Fut there is o!l) o!e class o$ cache&
13. Uses of Cirtual $emor1.
(rotectio!' TM is o$te! used to protect o!e pro%ram $rom others i! the s)stem
Fase a!d Fou!ds' this method allos relocatio!& User processes ca!!ot "e alloed to cha!%e
these re%isters+ "ut the OS must "e a"le to do so o! a process sitch&
16. %nterlea5ed $emor1.
Fa!*s o$ memor) are o$te! o!e ord ide + so "us idth !eed !ot "e cha!%ed to
access memor)& 4oe#er se#eral i!depe!de!t areas o$ memor) ca! "e accessed
simulta!eousl) ") usi!% i!terlea#ed memor)&
27. (hat is "rite 2ack protocol,
I! this scheme+ o!l) the "loc* i! cache is modi$ied& The mai! memor) he! the "loc*
must "e replaces i! the cache& This re6uires the use o$ a dirt) "it to *eep trac* o$ "loc*s+ that
ha#e "ee! modi$ied&
U;%# = -
1. $ention the !roup of lines in the s1stem 2us,
VAddress li!es
V5ata li!es
VCo!trol li!es
2. (hat is 2us master and sla5e master,
I!put output operatio!s i!#ol#e data tra!s$ers "etee! IO de#ice a!d
memor)&I! all the precedi!% operatio!s memor) is passi#e or sla#e de#ice ith
respect to s)stem "us tra!sactio!s&Where as the cpu ca! co!trol the s)stem "us+i&e
ser#e as a "us master&
3. (hat is the use of %+ controller,
The ma%!etic dis*s a!d other seco!dar) memor) !eed to "e co!!ected to
the s)stem "us #ia i!ter$acecircuits called Io co!trollers&
That per$orms series to parallel a!d parallel to series $ormat co!#ersio!s a!d other
co!trol $u!ctio!s&It ca! i!ter$ace ma!) IO de#ice to s)stem "us&
'. Differentiate s1nchronous and as1nchronous communication,
I! s)!chro!ous commu!icatio! each item is tra!s$erred duri!% the time slot
*!o to "oth the source a!d desti!atio!&5ata tra!s$er is slo&
I! as)!chro!ous commu!icatio! data tra!s$er is $aster a!d ca! "e used $or
lo!% dista!ce commu!icatio!&Each item "ei!% tra!s$erred is accompa!ied ") the
co!trol si%!als&
-.(hat is stro2e si!nal,
The data read).re6uest si%!als are used to load data $rom the source u!it to
the "us o$ $rom the "us to the desti!atio! u!it&such co!trol si%!als are called stro"e
si%!als&
..(hat is 2us ar2itration,
The possi"ilit) e3ists that se#eral master or sla#e u!its co!!ected to a
shared "us ill re6uest access to the "us at the same time&A selectio! mecha!ism
called "us ar"itratio! is there$ore re6uired to e!a"le the curre!t master hich ill
still re$er to a "us co!troller to decide amo!% such competi!% re6uest&
0.$ention the t1pes of 2us ar2itration,
V5ais) chai!i!%
V(olli!%
VI!depe!de!t re6uesti!%
3.(hat is %+ control method,
It re$ers the data tra!s$er "etee! the IO de#ice a!d the memor) or
"etee! the IO de#ice a!d the cpu&e%&testi!% the ststus o$ de#ice a!d to determi!e
i$ the) are re6uired ser#ice ") the cpu&
6.(hat is D$A,
The C(U a!d IO co!troller i!teract o!l) he! the cpu )ield the co!trol o$ the
memor) "us to the IO co!troller i! respo!se to the re6uest $rom the latter&This
le#el o$ IO co!trol is called direct memor) access a!d IO de#ice i!ter$ace co!trol
circuit is called 5MA co!troller&
17.(hat are the ad5anta!e and disad5anta!es of 2us,
A5T'
-&2o cost
2&Tersatilit)&
5IS9A5T'
-&It creates a commu!icatio! "ottle!ec*
2&2imiti!% the ma3imum I.O throu%hput a!d "a!didth limitatio!&
11.(hat are the t1pes of 2uses,
(rocessor memor) "us
I.O Fuses
12."hat are the i>o data transfer method usin! memor1 2usses
Three methods used $or data tra!s$er "etee! io de#ices a!d cpu
-& pro%ram i.o or polli!%
2&i!terrupt dri#e! i.o
=&direct memor) access
13. Differentiate s1nchronous and as1nchronous communication.
I! S)!chro!ous commu!icatio! each item is tra!s$erred duri!% the time slot *!o!
to "oth source a!d desti!atio!
5ata tra!s$er is slo
I! As)!chro!ous commu!icatio! data tra!s$er is $aster a!d ca! "e used $or lo!%
dista!ce commu!icatio!& Each item "ei!% tra!s$erred accompa!ied ") the co!trol
si%!als&
1'. Ao" the interrupt is handled durin! eception,
V cpu ide!ti$ies source o$ i!terrupt
V cpu o"tai!s memor) address o$ i!terrupt ha!dles
V 4X(ER2INK Yhtt p ' . . &i!d i astu d ) c h a !!el&co m . r esource s .-2 B 2 B 9 C S9 9 Comput e r9
Architecture9To9mar*s&asp3Y Zt YUtopYp c a!d other cpu status i!$ormatio! are
sa#ed
V (c is loaded ith address o$ i!terrupt ha!dler a!d ha!dli!% pro%ram to ha!dle it&
1-. Difference 2et"een as1nchronous 2us and s1nchronous 2us.
S)!chro!ous "us a!d As)!chro!ous'
-& S)!chro!ous "us o! other ha!d co!tai!s s)!chro!ous cloc* that is used to
#alidate each a!d e#er) si%!al&
It is also s)!chro!i0i!% cloc* that is used to #alidate each a!d e#er) si%!al& he! it
is speci$ied cloc* speed is set $or all time&
2 &S)!chro!ous "uses are a$$ected !oise o!l) he! cloc* si%!al occurs&
As)!chro!ous "uses ca! mista*e !oise pulses at a!) time $or #alid ha!dsha*e
si%!al&
=& A master that recei#es the "us %ra!t si%!al a!d it re6uesti!% the "us must !ot
propa%ate it o! do! the deis%! chai!&
The s)stem co!trol hich recei#es the "us %ra!t si%!al i! TME "us &The other !ame
$or S)!chro!ous is TME "us&
>& S)!chro!ous "us desi%!ers must co!trol ith meta sta"ilit) he! attempti!%
di$$ere!t cloc* si%!al 8re6ue!cies&
As)!chro!ous "us desi%!er must deal ith e#e!ts that li*e s)!chro!ousl)&
P& S)!chro!ous "us o$ meta sta"ilit) arises i! a!) $lip $lop& he! time ill "e
#iolated&
It must co!te!d ith meta sta"ilit) he! e#e!ts that dri#e "us tra!sactio!&
B& S)!chro!ous $lip$lop ca! ra!%e $rom !a!oseco!ds to microseco!ds its ra!%e is
$rom 279>P !a!oseco!ds&
Whe! $lip $lop e3perie!ces e$$ects ca! occur i! do!stream circurit) u!less proper
desi%! tech!i6ue hich are used&
-B& (hat is )ull=Aand&hake
A cha!%e o$ state i! o!e si%!al is $olloed ") a cha!%e i! other si%!al& It pro#ides
the hi%hest de%ree o$ $le3i"ilit) a!d relia"ilit)&
-S& (hat is interrupt latenc1[
Sa#i!% re%ister also i!creases the dela) "etee! the time a!d i!terrupt
re6uest is recei#ed a!d state o$ e3ecutio! o$ the i!terrupt ser#ice routi!e& This
dela) is called i!terrupt 2ate!c)&
13. Define CentraliBed Ar2itration.
It mea!s that all de#ices aiti!% to use the "us ha#e !o e6ual respo!si"ilit)
i! carr)i!% out the ar"itratio! process&
16. Define Distri2uted Ar2itration.
It mea!s that all de#ices aiti!% to use the "us ha#e e6ual respo!si"ilit) i!
carr)i!% out the ar"itratio! process ithout usi!% ce!tral ar"iter&
27. Define <us $aster.
The de#ice that is alloed to i!itiate data tra!s$ers o! the "us at a!) %i#e!
time
1. $ARE&
Unit =1
<A&%C &#RUC#URE& +) C+$PU#ER&
-& E3plai! the "asic $u!ctio!al u!its o$ a simple computer& /-B1
2& E3plai! the "asic I.O operatio!s o$ moder! processors& /-B1
=& Write "rie$l) a"out stac* a!d 6uue&
>& E3plai! #arious addressi!% modes $ou!d i! moder! processors /-B1
P& E3plai! #arious assem"ler directi#es used i! assem"l) la!%ua%e pro%ram /7?1
B& 5iscuss #arious issues to "e co!sidered hile assi%!i!% the ISA o$ a processor 7?1
S& What are stac* a!d 6ueues[ E3plai! its use a!d %i#e its di$$ere!ces /-71
?& Write a assem"l) la!%ua%e to $i!d the "i%%est !um"er amo!% %i#e! three !um"ers /7B1
L& 5escri"e detail a"out i!structio! a!d i!structio! se6ue!ci!% /-B1
-7& 5escri"e detail a"out the per$orma!ce o$ the s)stem&/-B1
Unit =2
AR%#A$E#%C U;%#
-& /a15iscuss the pri!ciple o$ operatio! o$ carr)9loo* ahead adders& /7?1
/"15iscuss the !o!9restori!% di#isio! al%orithm& /7?1
2& /a1 Multipl) the $olloi!% pair o$ si%!ed 2s compleme!ts !um"ers usi!% "it pair
recoded multiplier' Multiplica!d , --77-- Multiplier , -7--77& /7?1
/"15escri"e the al%orithm $or i!te%er di#isio! ith suita"le e3ample& /7?1
=& With a !eat s*etch+ E3plai! i! detail a"out lo%ic desi%! $or $ast adders& /-B1
>& 5escri"e ho the $loati!%9poi!t !um"ers are represe!ted a!d used i! di%ital
arithmetic operatio!s& Ri#e a! e3ample& /-B1
P& /a1 E3plai! the represe!tatio!s o$ $loati!% poi!t !um"ers i! detail& /7B1
/"1 Ri#e the "loc* dia%ram o$ the hardare impleme!tatio! o$ additio! a!d su"tractio!
o$ si%!ed !um"er a!d e3plai! its operatio!s& /-71
B& /a1 5esi%! a multiplier that multiplies to >9"it !um"ers& /7B1
/"1 E3plai! the or*i!% o$ $loati!% poi!t adder a!d su"tractor& /-71
S& E3plai! the Footh Al%orithm $or multiplicatio! o$ Si%!ed to\s Compleme!t
!um"er
Unit = 3
<A&%C PR+CE&&%;4 U;%#
-& Ri#e the or%a!i0atio! o$ t)pical hardired co!trol u!it a!d e3plai! the $u!ctio!s
per$ormed ") the #arious "loc*s& /-B1
2& 5iscuss the #arious ha0ards that mi%ht arise i! a pipeli!e& What are the remedies
commo!l) adopted to o#ercome.mi!imi0e these ha0ards& /-B1
=& E3plai! i! detail a"out i!structio! e3ecutio! characteristics& /-B1
>& With a !eat "loc* dia%ram+ e3plai! i! detail a"out micro pro%rammed co!trol
u!it a!d
E3plai! its operatio!s& /-B1
P& /a1E3plai! the e3ecutio! o$ a! i!structio! ith dia%ram& /7?1
/"1 E3plai! the multiple "us or%a!i0atio! i! detail& /7?1
S& /a1 E3plai! the $u!ctio! o$ a si3 se%me!t pipeli!e shoi!% the time it ta*es to
process
ei%ht tas*s& /-71
/"1 4i%hli%ht the solutio!s o$ i!structio! ha0ards& /7B1
?& /a1E3plai! the i!structio! c)cle hi%hli%hti!% the su"9c)cles a!d se6ue!ce o$ steps
to
"e $olloed& /7?1
/"1Illustrate memor) read a!d rite operatio!& /7?1
L& E3plai! the co!cept o$ Superscalar Architecture&
-7& 5escri"e the "asic structure o$ the pipeli!e processor a!d e3plai! ho it carried
out
i! $loati!% poi!t adder&
--& Ri#e! the se6ue!ce o$ co!trol si%!als to "e %e!erated to $etch a! i!structio!
$rom memor) i! a si!%le9"us or%a!i0atio!
Unit = '
$E$+RF &F&#E$
-& 5iscuss the #arious mappi!% tech!i6ues used i! cache memories& /7?1
2& /a1E3plai! the co!cept o$ #irtual memor) ith a!) o!e #irtual memor)
ma!a%eme!t
tech!i6ue& /7?1
/"1Ri#e the "asic cell o$ a! associati#e memor) a!d e3plai! its operatio!& Sho
ho associati#e memories ca! "e co!structed usi!% this "asic cell& /7?1
=& Ri#e the structure o$ semico!ductor RAM memories& E3plai! the read a!d rite
operatio!s i! detail& /-B1
>& /a1E3plai! the or%a!i0atio! o$ ma%!etic dis*s i! detail& /7?1
/"1Write a short !ote o! (CI /7?1
P E3plai! the co!cept o$ memor) hierarch)& /7B1
B& E3plai! a"out the seco!dar) stora%e de#ces
S& 5escri"e the per$orma!ce co!sideratio! o$ cache memor)&
?& Ri#e the structure o$ semico!ductor ROM memories& E3plai! read a!d rite
operatio!&
L& E3plai! the #irtual memor) address tra!slatio! a!d T2F ith !ecessar) dia%ram&
-7& E3plai! the "asic co!cepts o$ memor) s)stem&
Unit = -
%>+ +R4A;%GA#%+;
-& E3plai! the $u!ctio!s to "e per$ormed ") a t)pical I.O i!ter$ace ith a t)pical
i!put output i!ter$ace& /-B1
2& /a15iscuss the 5MA dri#e! data tra!s$er tech!i6ue& /7?1
/"15iscuss the operatio! o$ a!) to i!put de#ices /7?1
=& E3plai! i! detail a"out i!terrupt ha!dli!%& /-B1
>& E3plai! i! detail a"out sta!dard I.O i!ter$ace& /-B1
P& 5escri"e the $u!ctio!s o$ SCSI ith a !eat dia%ram& /-B1
B& /a1What is the importa!ce o$ I.O i!ter$ace[ Compare the $eatures o$ SCSI a!d
(CI I!ter$aces&/7?1
/"1 E3plai! the use o$ #ectored i!terrupts i! processes& Wh) is priorit) ha!dli!%
desired i! i!terrupt co!trollers[ 4o does the di$$ere!t priorit) scheme or*[ /7?1
S& Write !ote o! the $olloi!%&
] Fus ar"itratio!
] (ri!ter process commu!icatio!
] USF
] 5MA /-B1
?& E3plai! ho 5MA tra!s$er is accomplished ith a !eat dia%ram&
L& Write short !otes o!+
i1(CI
ii1SCSI
-7& 5escri"e Fus Ar"itratio!&
--& E3plai! the use o$ #ectored i!terrupts i! processors& Wh) is priorit) ha!dli!%
desired i! i!terrupt co!trollers[ 4o do the priorit) schemes or*[