Synthesis and Simulation

using HDLs
EDA Tools
Logic Synthesis
Logic Synthesis provides a link between a HDL and a netlist
Verilog was designed as a simulation language
VHDL was designed as a documentation and description language.
Both Verilog and VHDL were developed in the early 1980s
Logic synthesis tools were developed later
Graphic or text design entry methods are used to create a HDL behavioral model
State diagrams, Graphical datapath descriptions, Truth tables, RAM/ROM
templates and gate level schematics may also be used
Logic Synthesis
After HDL description Logic synthesizer and a cell library are necessary to
proceed
Most synthesis software companies produce only software
Most ASIC vendors produce only cell libraries
Logic Synthesis
Behavioral model is simulated to check the design meets the requirements
Logic synthesizer is used to generate a netlist, a structural model
Which contains only references to logic cells
Following logic synthesis the design is simulated again
Results are compared
Layout generation from the structural model produced by logic synthesis
Inside a Logic Synthesizer
The logic synthesizer parses HDL description and builds an internal data structure
Logic minimization tries to minimize the structure
Logic optimization used a series of factoring, substitution, and elimination steps to simplify the
equations
Logic optimization attempts to minimize area and speed also.
The technology-decomposition step builds a generic network from the optimized logic network.
The generic network is in a technology-independent form
Next, The technology mapping
While performing logic mapping, the algorithms attempt to minimize area
Verilog and Logic Synthesis
Verilog logic description starts with the keyword module
MODULE mychip_asic();
------
(Code to model ASIC I/O)
------
ENDMODULE
Top down approach
Top down approach
Verilog Modeling
MODULE mux (sel,a,b,z);
INPUT sel,a,b;
OUTPUT z;
REG z;
ALWAYS @ (sel,a,b)BEGIN
IF(sel) z<=a;
ELSE z<=b;
END
ENDMODULE
Delays in Verilog
Synthesis tools ignore delay values
Blocking and Non-blocking Assignments
Blocking assignment
Non-Blocking assignment
Combinational Logic in Verilog
Multiplexers in Verilog
Verilog Case Statement
Decoders in Verilog
Priority Encoder in Verilog
Arithmetic in Verilog
Sequential Logic in Verilog
D-Flip Flop
ALWAYS@ (POSEDGE clock) Q= D;
D- Latch
ALWAYS @ (clock or D) if(clock) Q=D;
Component Instantiation in Verilog
VHDL and Logic Synthesis
IEEE VHDL nine valued system
Combinational Logic Synthesis in VHDL
Multiplexers in VHDL
Decoders in VHDL
Adders in VHDL
Sequential Logic in VHDL
With a sensitivity list with and a EVENT plus a specific level
Sequential Logic in VHDL
No sensitivity list with a wait until statement
Component Instantiation in VHDL
Performance Driven Synthesis
Many logic synthesizers allow the use of directives.
These directives become complex when we need to describe complex timing
constraints
Suppose if we want to improve timing performance of a Mux, First we define a
pathcluster.
Next, we specify the required time for a signal to reach the output nodes
Finally, we specify the arrival time of the signal at all the inputs as 0ns
The logic optimization step will specify the logic network and then map it to a cell
library while attempting to meet the timing constraints
FSM Synthesis
There are three ways to synthesize FSMs
Omit any special synthesis directives and let the logic synthesizer operate on the state
machine as though it were random logic
Use directives to guide the logic synthesis tool to improve or modify state assignment
Use a special state machine compiler, separate from the logic synthesizer, to optimize
the state machine
Memory Synthesis
There are several approaches to memory synthesis:
Random logic using Flipflops and Latches
Register files in datapaths
RAM standard components
RAM compilers
Simulation
Engineers used to prototype system to check their designs
Breadboarding was feasible when it was possible to construct systemsfrom a
few off-the-self TTL parts
It is impractical for prototyping an ASIC
Types of Simulation
Behavioral Simulation
Functional Simulation
Static Timing Simulation
Gate-Level Simulation
Switch-Level Simulation
Transistor-Level or Circuit Level Simulation
Formal Verification
Logic synthesizer translate Behavioral model to a structural model
Formal verification can prove in the mathematical sense that two
representations are equivalent
If they are not, the software tell why and how the two representations differ
Transistor Level Simulation
Sometimes we need to simulate circuits more accurate than switch level
simulation
We turn to simulators that can solve circuit equations exactly, given models
for the nonlinear transistors, and predict the analog behavior
This type of Transistor level simulation is costly
If is impossible to simulate more than a hundred logic cells using a circuit
level simulation
Queries
EDA Tools