IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 11, NO.

2, MARCH 2012 355

Floating Body Effect in Partially Depleted Silicon
Nanowire Transistors and Potential Capacitor-Less
One-Transistor DRAM Applications
Myeongwon Lee, Taeho Moon, and Sangsig Kim
AbstractWe present a capacitor-less 1T-DRAMcell on SiO
2
/Si
substrates using a silicon nanowire (SiNW) as the channel mate-
rial. The SiNWs are fabricated by a top-down route that is fully
compatible with the current Si-based CMOS technology. Based on
the observation of the oating body effect of a partially depleted
(PD) silicon nanowire transistor (SNWT), its 1T-DRAM function-
ality and reliability characteristics are investigated. By virtue of
the top-down route providing a printable form of the inverted tri-
angular SiNWs, the PD SNWT 1T-DRAM cell can be applied on
insulating plastic substrates for potential applications of exible
electronics.
Index TermsCapacitor-less, oating body effect, partially de-
pleted (PD), silicon nanowire transistor (SNWT), 1T-DRAM.
I. INTRODUCTION
C
ONVENTIONAL dynamic random access memory
(DRAM) cells, which consist of an access transistor and a
capacitor storage node (1T/1C), face physical and technological
challenges as the device feature size continues to shrink [1].
The main issue lies in the scaling of the storage capacitor.
Indeed, for each generation of DRAM technology nodes, the
capacitor cannot shrink with transistor scaling because it must
stay large in order to obtain a sufcient storage capacitance of
30 fF/cell [2]. The oating body cell (FBC) or, most com-
monly, capacitor-less 1T-DRAM cell, which exploits the inher-
ent oating body effect of partially depleted (PD) SOI devices
to replace the DRAM capacitor, is considered to be the most
promising successor of the conventional DRAM cell in terms of
its simple cell structure and cell size scaling [3][9]. The main
feature of the capacitor-less 1T-DRAMcell is that it temporarily
Manuscript received August 30, 2011; accepted November 2, 2011. Date of
publication November 16, 2011; date of current version March 9, 2012. This
work was supported in part by the Future-Based Technology Development Pro-
gram (Nano Fields) through the National Research Foundation of Korea (NRF)
funded by the Ministry of Education, Science, and Technology under Grant
2010-0019197, the World Class University under Grant R32-2008-000-10082-
0, the IT R&D program of MKE/KEIT under Grant 10030559 [development of
next generation high performance organic/nano materials and printing process
technology], the Seoul R&BDProgramunder Grant PA090914, and the KSSRC
program [development of printable integrated circuits based on inorganic semi-
conductor nanowires]. The review of this paper was arranged by Associate
Editor R. Lake.
The authors are with the Department of Electrical Engineering, Korea
University, Seoul 136-713, Republic of Korea (e-mail: yimy02@korea.ac.kr;
taeho78@korea.ac.kr; sangsig@korea.ac.kr).
Color versions of one or more of the gures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identier 10.1109/TNANO.2011.2175942
stores a bit in the form of excess charge inside the oating body
of the cell transistor. The oating body charge acts almost like
an additional gate, resulting in a shift in the body potential from
its equilibrium value. In turn, the threshold voltage is changed
to an extent which depends on the magnitude of the oating
body charge and, therefore, the memory states can be read by
sensing and comparing the drain current of the cell transistor
with respect to that of a reference cell.
On the order hand, a silicon nanowire transistor (SNWT) of-
fers an appealing approach to scaling beyond CMOS devices
[10]. In general, silicon nanowires (SiNWs) can be achieved
using one of two distinct approaches: bottom-up and top-
down. Compared with the bottom-up synthesized SiNWs, the
top-down approach, in which bulk materials are reduced in size
to nanoscale patterns using advanced lithography tools, enables
the controlled assembly of the SiNWs into well-ordered arrays
at precise locations for the implementation of integrated elec-
tronic systems. To date, most of the previous studies on the
top-down fabricated SNWT have mainly focused on its logic
and nonvolatile memory applications [11][13]; however, there
have been few studies for the capacitor-less 1T-DRAM applica-
tions. In this paper, we present a capacitor-less 1T-DRAM cell
on SiO
2
/Si substrates using a SiNWas the channel material. The
SiNWs used in this study are derived from bulk Si wafers by
the top-down route that is fully compatible with the current Si-
based CMOS technology. Based on the insights into the oating
body effect of the PD SNWT, we experimentally conrm the
feasibility of using this PD SNWT for capacitor-less 1T-DRAM
applications.
II. DESIGN AND EXPERIMENTAL
Fig. 1 illustrates the fabrication steps employed to derive
single-crystalline SiNWs frombulk p-type (1 0 0) Si wafers with
a resistivity of 812 cm using a fully CMOS-compatible top-
down route, i.e., conventional photolithography combined with
anisotropic wet etching, thermal oxidation, and ion-implantation
doping. The Si substrate was etched anisotropically until the
desired trench depth was reached, with a oxide/nitride stack
dening the 400-nm-wide active Si lines. After the wafer was
dipped in 25 wt.% tetramethylammonium hydroxide [TMAH,
(CH
3
)
4
NOH)] solution [see Fig. 1(a)], thermal oxidation was
carried out in a wet ambient to reduce the size of the SiNWs
[see Fig. 1(b)]. Subsequently, the nitride lm was completely
stripped in hot phosphoric acid, and the patterned source/drain
regions of the SiNWs were doped to 110
20
cm
3
through a
1536-125X/$26.00 2011 IEEE
356 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 11, NO. 2, MARCH 2012
Fig. 1. Process ow and schematic representation for doped SiNW fabrication.
Fig. 2. SEM pictures of the SiNW after (a) crystallographic wet etching in
TMAH solution and (b) size reduction oxidation. In (b), chemical staining
was performed after the deposition of 150-nm-thick polysilicon in order to
distinguish the clear SiNW from the surrounding oxide layer. The scale bars are
100 nm.
masked ion implantation [see Fig. 1(c)]. Next, the wafer was
rstly annealed at 900

C for 60 min in nitrogen ambient, fol-
lowed by rapid thermal annealing (RTA) at 1000

C for 10 s
in order to activate the implanted dopants with uniform dif-
fusion and eliminate defects. After removing the surrounding
oxide, the single-crystalline SiNWs with degenerately doped
source/drain regions were formed [see Fig. 1(d)]. More detailed
process was well explained in our previous work [14], with
some modication in crystallographic wet etching of Si lines.
Fig. 2(a) shows the scanning electron microscopy (SEM) image
of the crystallographic wet etched Si line, with the correspond-
ing SiNW after size reduction oxidation shown in Fig. 2(b).
Note that, in Fig. 2(b), chemical staining using buffered oxide
etchant (BOE) solution was performed after the deposition of
150-nm-thick polysilicon in order to distinguish the clear SiNW
from the surrounding oxide layer. It can be seen that the SiNW
has an inverted triangular cross section with a width and height
of 150 nm. The dimensions of the SiNW channel with a low
doping concentration of 210
15
cm
3
are large enough to ob-
tain the volume of the oating body. In addition, the Si neck
connecting the SiNW to the Si substrate is sufciently narrow
for it to be easily transferred froma donor Si chip onto a receiver
substrate. A PD SNWT 1T-DRAM cell with a channel length of
0.7 m was constructed by transferring the as fabricated SiNWs
onto a SiO
2
/Si substrate. An oxynitride gate dielectric and Al
gate electrode were used. Fig. 3(a) and (b) shows the schematic
Fig. 3. (a) Schematic and (b) plane-view SEM image of the PD SNWT 1T-
DRAM cell on SiO
2
/Si substrates. The scale bar is 5 m.
and plane-viewSEMimage of the PDSNWT 1T-DRAMcell on
SiO
2
/Si substrates, respectively. Shown in Fig. 4 is a secondary-
ion mass spectroscopy (SIMS) depth prole of the oxynitride.
It is found that nitrogen piles up at the interface and the oxide
thickness is around 12 nm.
III. RESULTS AND DISCUSSION
We rst investigated the transistor characteristics of a PD
SNWT on SiO
2
/Si substrates. Fig. 5 shows the normalized I
DS
versus V
GS
transfer characteristics of the PD SNWT under the
normal operation with V
DS
values of 0.05 and 1.0 V. The drain
currents are normalized with respect to the perimeter of the
SiNW, where the effective channel width (W
e
) is measured to
LEE et al.: FLOATING BODY EFFECT IN PARTIALLY DEPLETED SILICON NANOWIRE TRANSISTORS 357
Fig. 4. SIMS depth proles of the oxynitride. It is found that nitrogen piles
up at the interface and the oxide thickness is around 12 nm.
Fig. 5. Normalized I
DS
versus V
GS
transfer curves of the PD SNWT under
the normal operation with V
DS
values of 0.05 and 1.0 V.
be about 300 nm from the SEM image of Fig. 2(b). The thresh-
old voltage (V
T
) and subthreshold swing (SS) are 0.25 V and
96 mV/dec, respectively, at V
DS
= 0.05 V. The drain-induced
barrier lowering (DIBL) is 0.22 V/V, which is fairly large,
probably due not only to the low doping concentration
(210
15
cm
3
) of the SiNW channel, but also to the large
dimensions (width and height of 150 nm) of the SiNW chan-
nel. Shown in Fig. 6 is the normalized I
DS
versus V
DS
output
characteristics of the PD SNWT with V
GS
as a parameter. The
kink points that imply the occurrence of the oating body ef-
fect are clearly found in these curves, indicating that the excess
holes generated by impact ionization are stored inside the oat-
ing body of the device. The result suggests that the PD SNWT
can be used as a capacitor-less 1T-DRAM cell.
Based on the insights into the oating body effect in the
PD SNWT, we next investigated the feasibility of using it for
capacitor-less 1T-DRAM applications. The operation principle
of the PD SNWT 1T-DRAM cell is shown in Fig. 7(a) and (b),
with the experimental results shown in Fig. 7(c). The source of
the PDSNWT 1T-DRAMcell is connected to the ground poten-
tial (GND), the drain to a bit line (BL), and the gate to a word
line (WL). To write 1 data into the PDSNWT 1T-DRAMcell,
the WL is biased to 1.5 Vand the BL is raised to 2.5 Vfor inject-
ing the excess holes into the oating body by impact ionization
[see Fig. 7(a)]. As excess holes accumulate in the oating body,
the body potential is steadily raised. Consequently, the decrease
in the threshold voltage leads to an increase in the BL current.
Fig. 6. Normalized I
DS
versus V
DS
output curves of the PDSNWT with V
GS
as a parameter.
On the other hand, to write 0 data into the PD SNWT 1T-
DRAM cell, the WL is xed at a bias of 1.5 V and the BL bias
is triggered to 3.5 V for sweeping out the stored holes from
the oating body by forward bias on the body-drain junction,
causing the body potential to decrease [see Fig. 7(b)]. The ex-
cess of ionized acceptors creates a negative charge, causing the
threshold voltage to increase and, consequently, the BL current
to decrease. The read operation is performed by sensing the
difference in the BL current between the 1 and 0 states in
the linear region so as not to disturb the cell data states by im-
pact ionization. Fig. 7(c) shows the normalized I
BL
versus V
WL
transfer characteristics of the PD SNWT 1T-DRAM cell with
V
BL
=0.1 V. Each of these curves corresponds to the 1 or 0
state. Note that the cell data between the 1 and 0 states can
be distinguished fromeach other by sensing the difference in the
read current at V
WL
= 1.5 V and V
BL
= 0.1 V. The differences
in the read current and threshold voltage between the two data
states, which are indices of the sensing margin, are measured to
be 0.71 A/m and 0.36 V, respectively.
For the PD SNWT to be used in practical capacitor-less 1T-
DRAM applications, its reliability characteristics should be
examined. Fig. 8(a) shows the read retention characteristics
measured at room temperature under the read conditions of
V
WL
= 1.5 V and V
BL
= 0.1 V. If we dene the read retention
time as the time it takes to close the sensing margin by 50%, a
nondestructive readout ensures the read retention time of about
90 ms. Although the 0 state is maintained, the 1 state is sig-
nicantly degraded, due to the recombination of the excess hole
charges, which is mainly caused by the junction leakage current
or by the lowering of the potential barrier. Moreover, because a
high electric eld is in effect during the write 1 operation due
to impact ionization, we evaluated the endurance characteristics
using the write 1 stress with V
WL
= 1.5 V and V
BL
= 2.5 V.
Fig. 8(b) shows that the threshold voltage shift is expected to be
about 0.41 V even after 10
7
s of the write 1 stress.
In order to verify that our top-down route providing a print-
able form of the inverted triangular SiNWs can be applied
on insulating plastic substrates for future exible electronics
358 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 11, NO. 2, MARCH 2012
Fig. 7. Schematic illustration for (a) write 1 and (b) write 0 operation of the PD SNWT 1T-DRAM cell. (c) Normalized I
BL
versus V
WL
transfer curves
with V
BL
= 0.1 V. Each of these curves corresponds to the 1 or 0 state.
Fig. 8. (a) Read retention characteristics under read condition of V
WL
=
1.5 V and V
BL
= 0.1 V. (b) V
T
shift as a function of write 1 stress time.
applications, a mechanically exible PD SNWT 1T-DRAM cell
on plastic substrates is in fabrication now.
IV. CONCLUSION
We have demonstrated the PD SNWT on SiO
2
/Si substrates
for potential capacitor-less 1T-DRAM application by use of a
fully CMOS-compatible SiNW as the channel material. Our
top-down route to the fabrication of the SiNWs provides greater
exibility in the design of the PD SNWT 1T-DRAM cell, al-
lowing for precise control over the dimension and impurity con-
centration of the SiNW channel by means of crystal orientation
dependent wet etching, size reduction oxidation, and ion im-
plantation doping. By virtue of a printable form of the inverted
triangular SiNWs with this top-down route, the PD SNWT 1T-
DRAM cell can be constructed on insulating plastic substrates
for future exible electronics applications.
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Authors photographs and biographies not available at the time of publication.