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Centro de Educao Profissional Irmo Mrio

Cristvo
Curso Tcnico em Mecatrnica
Disciplina de Eletrnica Digital

Apostila de Laboratrio de Eletrnica Digital


Verso 2.1 1 semestre 2013
Prof. Marcelo do C.C. Gaiotto.

Aluno(a): ________________________________________________
Turno: _______________

Turma______

Centro de Educao Profissional Irmo Mrio Cristvo Laboratrio de


Eletrnica Digital Prof. Marcelo Gaiotto

CI - Circuito Integrado Tecnologias


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Equivalncia Lgico/Eltrico
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CI - Circuito Integrado Invlucros, identificao


dos pinos e sequncia de contagem
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Centro de Educao Profissional Irmo Mrio Cristvo Laboratrio de


Eletrnica Digital Prof. Marcelo Gaiotto

Variveis - Equivalente Fsico Chaves e Botes


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PROBE Visualizao de sinais entradas e sadas


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Clculos:

Identificao dos Pinos do LED


3

Centro de Educao Profissional Irmo Mrio Cristvo Laboratrio de


Eletrnica Digital Prof. Marcelo Gaiotto

Passos para realizar os projetos de Laboratrio


forma mais rpida e eficiente
ATENO
Ler o roteiro de laboratrio da experincia que ser
realizada
1 Desenhe o smbolo da funo lgica que se deseja testar em um projeto prtico. Neste exemplo
ser criado um projeto de teste para funo lgica AND:

2 Procure o circuito integrado que implementa fisicamente esta funo lgica na lista apresentada
no roteiro da experincia, sejam esses TTL ou CMOS; - neste exemplo: 74LS08

3 Identifique quantas entradas sero utilizadas para criar este projeto; 2 entradas

4 Escolha uma das portas lgicas disponvel no circuito integrado e copie os nmeros equivalentes
s entradas e sadas da mesma, colocando-os bem prximos do smbolo e escreva o cdigo do
circuito integrado sobre o smbolo;

Centro de Educao Profissional Irmo Mrio Cristvo Laboratrio de


Eletrnica Digital Prof. Marcelo Gaiotto
5 Desenhe uma chave ou boto (quando especificado) para CADA VARIVEL;
LEMBE QUE CADA VARIVEL (chave) DEVE POSSUIR AS INFORMAES BSICAS
CONFORME O MODELO APRESENTADO

6 Conecte os sinais das variveis s entradas da porta lgica;

7 Desenhe um PROBE (resistor e LED) para cada entrada (variveis) e para cada sada utilizada e
coloque os pinos de alimentao do CI circuito integrado;

Alimentao: VCC: +5V : pino 14


GND: pino 7
5

Centro de Educao Profissional Irmo Mrio Cristvo Laboratrio de


Eletrnica Digital Prof. Marcelo Gaiotto
8 O projeto est pronto, agora para testar o seu funcionamento, utilize uma tabela verdade que
represente teoricamente o mesmo, manuseando as chaves do conjunto de chaves para cada
combinao da tabela verdade, e verifique se a resposta para cada linha foi igual.

Caso j tenha realizado estes passos, as probabilidades de sucesso sero muito grandes.
Um grande passo ser dado nos estudos aqui propostos, espero que o realizem com toda vontade e
afinco, pois o mundo da eletrnica fascinante!
Sejam bem vindos, boa sorte e sucesso a todos!
Professor Marcelo do C.C. Gaiotto

Centro de Educao Profissional Irmo Mrio Cristvo Laboratrio de


Eletrnica Digital Prof. Marcelo Gaiotto

Laboratrio 1 Teste de Portas Lgicas


Objetivos:

Aprender como interpretar os dados da especificao tcnica do fabricante;


Conhecer os equipamentos utilizados para efetuar as prticas;
Verificar o comportamento de cada porta lgica;
Comprovar as teorias de portas lgicas;
Iniciar o trabalho com o Protoboard;
Montagem limpa e exemplar (fiao curta e arrumada).

Tempo de Execuo: ____ Aulas


Incio: ____/___/_____ - Trmino: ____/___/_____

Desenvolvimento
Equipamentos e materiais necessrios para realizar a experincia:

1 CI 74LS00;
1 CI 74LS02;
1 CI 74LS04;
1 CI 74LS08;
1 CI 74LS32;
1 CI 74LS86;
3 leds;

3 resistores de 330R;
1 protoboard;
1 fonte de alimentao;
1 conjunto de chaves digitais;
Fios para conexo.

1) Realizar uma pesquisa sobre as famlias construtivas TTL Exemplo: LS, F, L, S....
apresentando suas caractersticas mais importantes. A pesquisa dever conter no mximo 10
linhas
e
dever
se
entregue
na
prxima
aula
de
laboratrio:
dia:
________/________/____________
2) Para cada circuito integrado da lista, identifique e anote:
Qual a tecnologia construtiva, quantas portas lgicas cada circuito integrado possui, qual
funo lgica que representa e quantas entradas cada uma possui?
EXEMPLO:
74LS08: circuito integrado TTL com 4 portas AND de 2 entradas
______________________________________________________________________________
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______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________

Centro de Educao Profissional Irmo Mrio Cristvo Laboratrio de


Eletrnica Digital Prof. Marcelo Gaiotto
3) Desenhe a disposio interna dos smbolos das funes lgicas implementadas por cada um
dos circuitos integrados da lista dentro dos invlucros a seguir, identificando-os com seu
cdigo e os nmeros dos pinos.

Centro de Educao Profissional Irmo Mrio Cristvo Laboratrio de


Eletrnica Digital Prof. Marcelo Gaiotto

4) Projete um circuito de teste para cada funo lgica vista na teoria, utilizando os seus
respectivos circuitos integrados, que se encontram na lista do roteiro;
5) Projete um circuito de teste para a identidade da funo lgica XOR, utilizando apenas
funes lgicas bsicas;
6) Se voc deixar um ou mais terminais de entrada em aberto (sem conexo com a chave de
entrada), qual a resposta na sada? Que concluso voc tira desta observao? TESTE ESTA
CONDIO, COM O PROJETO UTILIZANDO O CI 74LS08.

ATENO
1 NO SERO ACEITOS PEDIDOS DE VISTOS DE PROJETOS/CIRCUITOS SEM OS CLCULOS OU FALTANDO ITENS
DE PROJETO;
2 PARA EVITAR TRANSTORNOS E PERDA DE TEMPO, SEMPRE LEIA O ROTEIRO DA EXPERINCIA ANTES DE VIR
PARA O LABORATRIO.
3 - SE O ALUNO NO APRESENTAR OS PROJETOS DOS CIRCUITOS DE TESTE ANTES DA MONTAGEM, NO SER
VALIDADA A EXPERINCIA.
4 O ALUNO DEVE REALIZAR AS PESQUISAS E O DESENVOLVIMENTO DOS PROJETOS ANTES DE INICIAR O
LABORATRIO.

Dica e RESUMO para montagens: Com os projetos desenvolvidos e corretos siga estas
orientaes:
1 Coloque o(s) circuito(s) integrado(s) no protoboard de maneira a facilitar suas conexes;
2 Coloque o conjunto de chaves em uma posio favorvel e que facilite as suas ligaes;
3 Alimentar todos os circuitos integrados utilizados no projeto;
4 Alimentar o conjunto de chaves e ou botes variveis Sx ou PBx;
5 Inicie a montagem do projeto conectando as variveis aos pinos identificados no projeto;
6 Monte os conjuntos de visualizao Probes um para cada entrada (variveis) e para a sada
ou sadas utilizadas;
7 Para testar o funcionamento, utilize uma tabela verdade que represente teoricamente o projeto,
manuseando as chaves do conjunto de chaves para cada combinao da tabela verdade, e verifique
se a resposta foi verdadeira.
9

Centro de Educao Profissional Irmo Mrio Cristvo Laboratrio de


Eletrnica Digital Prof. Marcelo Gaiotto
Projeto - Circuito de teste para o CI: 74LS00

Visto Projeto: ___________

10

Centro de Educao Profissional Irmo Mrio Cristvo Laboratrio de


Eletrnica Digital Prof. Marcelo Gaiotto
Projeto - Circuito de teste para o CI: 74LS02

Visto Projeto: ___________

11

Centro de Educao Profissional Irmo Mrio Cristvo Laboratrio de


Eletrnica Digital Prof. Marcelo Gaiotto
Projeto - Circuito de teste para o CI: 74LS04

Visto Projeto: ___________

12

Centro de Educao Profissional Irmo Mrio Cristvo Laboratrio de


Eletrnica Digital Prof. Marcelo Gaiotto
Projeto - Circuito de teste para o CI: 74LS08

Alimentao: VCC: +5V : pino 14

GND: pino 7

13

Centro de Educao Profissional Irmo Mrio Cristvo Laboratrio de


Eletrnica Digital Prof. Marcelo Gaiotto
Projeto - Circuito de teste para o CI: 74LS32

Visto Projeto: ___________

14

Centro de Educao Profissional Irmo Mrio Cristvo Laboratrio de


Eletrnica Digital Prof. Marcelo Gaiotto
Projeto - Circuito de teste para o CI: 74LS86

Visto Projeto: ___________

15

Centro de Educao Profissional Irmo Mrio Cristvo Laboratrio de


Eletrnica Digital Prof. Marcelo Gaiotto
Projeto - Circuito de teste para a IDENTIDADE da XOR

Visto Projeto: ___________

16

Centro de Educao Profissional Irmo Mrio Cristvo Laboratrio de


Eletrnica Digital Prof. Marcelo Gaiotto

Laboratrio 2 Universalidade de Portas NAND e


NOR e Circuitos Habilitadores
Objetivos:

Aprender como interpretar os dados da especificao tcnica do fabricante;


Conhecer os equipamentos utilizados para efetuar as prticas;
Verificar o comportamento de cada porta lgica quando associadas em circuitos;
Comprovar a universalidade das portas lgicas;
Comprovar a necessidade e a utilizao de portas lgicas como habilitadores;
Praticar a montagem de circuitos mais complexos no Protoboard;
Montagem limpa e exemplar (fiao curta e arrumada).

Tempo de Execuo: ____ Aulas


Incio: ____/___/_____ - Trmino: ____/___/_____

Desenvolvimento
Equipamentos e materiais necessrios para realizar a experincia:

2 CI 74LS00;
2 CI 74LS02;
3 leds;
3 resistores de 330R;
1 protoboard;

1 fonte de alimentao;
1 conjunto de chaves digitais;
Fios para conexo.

1) Utilizando a universalidade de portas NAND, apresente o projeto de teste para uma funo
lgica INVERSORA;
2) Utilizando a universalidade de portas NAND, apresente o projeto de teste para uma funo
lgica AND;
3) Utilizando a universalidade de portas NAND, apresente o projeto de teste para uma funo
lgica OR;
4) Utilizando a universalidade de portas NOR, apresente o projeto de teste para uma funo
lgica INVERSORA;
5) Utilizando a universalidade de portas NOR, apresente o projeto de teste para uma funo
lgica OR;
6) Utilizando a universalidade de portas NOR, apresente o projeto de teste para uma funo
lgica AND;
7) Utilizando a universalidade de portas NAND ou NOR, apresente o projeto de teste para uma
funo lgica XOR;
8) Monte uma tabela verdade para cada circuito de teste realizando as combinaes possveis
nas chaves digitais de entrada, anotando o correspondente resultado da sada;
9) Escolha um circuito habilitador no livro, Eletrnica Digital Princpios e Aplicaes, do
autor Tocci (circuitos para habilitar/desabilitar) e apresente o projeto de teste;
10) Compare os resultados obtidos com os descritos nas aulas tericas. Anote as concluses.

ATENO
1 - NO SERO ACEITOS PEDIDOS DE VISTOS DE CIRCUITOS SEM OS CLCULOS E OU
FALTANDO ITENS DE PROJETO;
2 PARA EVITAR TRANSTORNOS E PERDA DE TEMPO, SEMPRE LEIA O ROTEIRO DA
EXPERINCIA ANTES DE VIR PARA O LABORATRIO.
3 - SE O ALUNO NO APRESENTAR OS PROJETOS DOS CIRCUITOS DE TESTE ANTES DA
MONTAGEM, NO SER VALIDADA A EXPERINCIA.

17

Centro de Educao Profissional Irmo Mrio Cristvo Laboratrio de


Eletrnica Digital Prof. Marcelo Gaiotto
Projeto: Funo lgica INVERSORA usando NAND

Visto Projeto: ___________

18

Centro de Educao Profissional Irmo Mrio Cristvo Laboratrio de


Eletrnica Digital Prof. Marcelo Gaiotto
Projeto: Funo lgica AND usando NAND

Visto Projeto: ___________

19

Centro de Educao Profissional Irmo Mrio Cristvo Laboratrio de


Eletrnica Digital Prof. Marcelo Gaiotto
Projeto: Funo lgica OR usando NAND

Visto Projeto: ___________

20

Centro de Educao Profissional Irmo Mrio Cristvo Laboratrio de


Eletrnica Digital Prof. Marcelo Gaiotto
Projeto: Funo lgica INVERSORA usando NOR

Visto Projeto: ___________

21

Centro de Educao Profissional Irmo Mrio Cristvo Laboratrio de


Eletrnica Digital Prof. Marcelo Gaiotto
Projeto: Funo lgica OR usando NOR

Visto Projeto: ___________

22

Centro de Educao Profissional Irmo Mrio Cristvo Laboratrio de


Eletrnica Digital Prof. Marcelo Gaiotto
Projeto: Funo lgica AND usando NOR

Visto Projeto: ___________

23

Centro de Educao Profissional Irmo Mrio Cristvo Laboratrio de


Eletrnica Digital Prof. Marcelo Gaiotto
Projeto: Funo lgica XOR usando somente NAND ou usando somente NOR
Visto Projeto: ___________

24

Centro de Educao Profissional Irmo Mrio Cristvo Laboratrio de


Eletrnica Digital Prof. Marcelo Gaiotto
Projeto: Habilitador

Visto Projeto: ___________

25

Centro de Educao Profissional Irmo Mrio Cristvo Laboratrio de


Eletrnica Digital Prof. Marcelo Gaiotto

Laboratrio 3 Automao Predial


Sistema de Bombeamento
Objetivos:

Aprender como interpretar os dados da especificao tcnica do fabricante;


Conhecer os equipamentos utilizados para efetuar as prticas;
Iniciar a interpretao e o desenvolvimento de projetos;
Conhecer e utilizar circuitos de tecnologia CMOS em projetos;
Desenvolver um Sensor de barreira ptica utilizando um LED de Transmissor (TX) e outro
Receptor (RX) de infravermelho.
Comprovar a utilizao dos Mtodos: Soma de Produtos, Produtos de Somas e Mapas
de Karnaugh.
Aplicar os conceitos de Universalidade de portas NAND e NOR;
Montagem limpa e exemplar (fiao curta e arrumada).

Tempo de Execuo: ____ Aulas


Incio: ____/___/_____ - Trmino: ____/___/_____

Desenvolvimento
Equipamentos e materiais necessrios:

Os componentes e equipamentos ficaro a critrio de cada equipe. TODOS OS CIRCUITOS


QUE FOREM UTILIZADOS DEVERO SER DE TECNOLOGIA

CMOS,

E SUA

12V;
Os alunos devero calcular o resistor do PROBE para que a corrente do LED no seja
inferior 7mA e NO ultrapasse o valor mximo de 10mA.

ALIMENTAO DEVER SER DE

1) Realizar uma pesquisa sobre: famlias construtivas CMOS (apresentando suas caractersticas
mais importantes), INFRAVERMELHO (comprimento de onda, aplicaes, etc).
A pesquisa dever conter no mximo 10 linhas para cada item, e dever se entregue na
prxima aula de laboratrio: dia: ________/________/____________
2) Projetar o circuito lgico de controle da casa de mquinas de um edifcio que realize o
acionamento de uma bomba e uma eletrovlvula para encher duas caixas dgua, uma no alto
do edifcio a partir de outra, como reservatrio, colocada no trreo. O circuito atravs da
informao de sensores, convenientemente dispostos nas caixas dgua, dever atuar na
bomba e na eletrovlvula ligada canalizao de entrada. O desenho abaixo apresenta o
esquema da situao.

Diagrama em blocos do sistema de controle


26

Centro de Educao Profissional Irmo Mrio Cristvo Laboratrio de


Eletrnica Digital Prof. Marcelo Gaiotto
1 - obs:Convencionar estados das variveis antes de iniciar o projeto, ligado 1, desligado 0. Facilita bastante!!!!
2 obs: Os sensores (A,B e C) devero ser montados na placa de pontes de terminal de cada equipe usando o circuito com
o LED Infravermelho transmissor e receptor, sendo que a ligao e o ponto de sada de sinal so mostrados na figura a seguir:

Figura do circuito do sensor Infravermelho por barreira ptica


Led Transmissor: normalmente azul claro, mas tambm pode ser encontrado transparente
e a forma de identificao dos seus terminais igual a dos LEDs comuns.
Corrente para o led Transmissor ITX = 15 25 mA;
Foto-receptor: normalmente transparente e seu invlucro mais comum o de um led
transparente;
3) Se voc deixar um ou mais terminais de entrada em aberto (sem conexo com a chave de
entrada), qual a resposta na sada? Que concluso voc tira desta observao? TESTE ESTA
CONDIO, COM O PROJETO UTILIZANDO O CICD4081

ATENO
1 NO SERO ACEITOS PEDIDOS DE VISTOS DE PROJETOS/CIRCUITOS SEM OS CLCULOS OU FALTANDO ITENS
DE PROJETO;
2 PARA EVITAR TRANSTORNOS E PERDA DE TEMPO, SEMPRE LEIA O ROTEIRO DA EXPERINCIA ANTES DE VIR
PARA O LABORATRIO.
3 - SE O ALUNO NO APRESENTAR OS PROJETOS DOS CIRCUITOS DE TESTE ANTES DA MONTAGEM, NO SER
VALIDADA A EXPERINCIA.
4 O ALUNO DEVE REALIZAR AS PESQUISAS E O DESENVOLVIMENTO DOS PROJETOS ANTES DE INICIAR O
LABORATRIO.

27

Centro de Educao Profissional Irmo Mrio Cristvo Laboratrio de


Eletrnica Digital Prof. Marcelo Gaiotto
Tabela verdade, Mtodos de Soma de Produtos, Produtos de Soma ou Mapas de Karnaugh do
Projeto da Bomba e Eletrovlvula

28

Centro de Educao Profissional Irmo Mrio Cristvo Laboratrio de


Eletrnica Digital Prof. Marcelo Gaiotto
Projeto dos Circuitos da Bomba e Eletrovlvula

Visto Projeto: ___________

29

Centro de Educao Profissional Irmo Mrio Cristvo Laboratrio de


Eletrnica Digital Prof. Marcelo Gaiotto

Laboratrio 4

Circuitos Decodificadores, Mux/Demux e


Drivers BCD 7 Segmentos
Objetivos:

Aprender como interpretar os dados da especificao tcnica do fabricante;


Conhecer os equipamentos utilizados para efetuar as prticas;
Melhorar a interpretao e o desenvolvimento de projetos;
Continuar a aplicao de circuitos integrados com tecnologia CMOS em projetos;
Comprovar a utilizao dos mapas de Karnaugh.
Comprovar o funcionamento de decodificadores e suas funes.
Comprovar o funcionamento e necessidade de multiplexadores e demultiplexadores;
Comprovar a utilizao de decodificadores e drivers de BCD para displays de 7
segmentos;
Montagem limpa e exemplar (fiao curta e arrumada).

Tempo de Execuo: ____ Aulas


Incio: ____/___/_____ - Trmino: ____/___/_____

Desenvolvimento

LEMBRE OS CIRCUITOS QUE FOREM DE TECNOLOGIA CMOS


SUA ALIMENTAO DEVER SER DE 12V. Neste caso devero
calcular o resistor do PROBE para que a corrente mxima do LED no
seja inferior 7mA e NO ultrapasse o valor mximo de 10mA.
Nos circuitos onde se est trabalhando com tecnologia TTL, a
alimentao dever ser de 5V, e o a corrente do PROBE dever ser de
15 mA, cabendo aos alunos o clculo dos resistores mesmos.
A corrente dos segmentos do display dever ser de 12 mA, cabendo
aos alunos o clculo dos resistores dos mesmos.

Equipamentos e materiais necessrios para realizar a experincia:

1 CI 4081;
1 CI 40106;
1 CI 74LS138;
1 CI 74LS151;
1 CD 4511 decodificador e
driver de BCD para display de7
Segmentos;
19 leds;

1 display de 7 segmentos
catodo comum;
19 resistores de 330R;
1 protoboard;
1 conjunto de chaves digitais;
1 fonte de alimentao.
Fios para conexo.

1) Realizar uma pesquisa sobre: Decodificadores, Multiplexadores, Demultiplexadores e Display


de 7 segmentos Anodo Comum e Catado Comum de como eles funcionam.
A pesquisa dever conter no mximo 10 linhas para cada item, e dever se entregue na
prxima aula de laboratrio: dia: ________/________/____________
2) Utilizando Circuitos Integrados de tecnologia CMOS, projete e implemente um decodificador
de 2 para 4. A apresentao das sadas dever ser realizada por intermdio de um PROBE.

Diagrama em bloco do decodificador de binrio para decimal.


30

Centro de Educao Profissional Irmo Mrio Cristvo Laboratrio de


Eletrnica Digital Prof. Marcelo Gaiotto
3) Como projeto apresentado, monte o circuito de teste para o CI CD 4511, monte a tabela
verdade e realize os teste de todas as funcionalidades dos sinais de controle.

Pinos do display de 7 segmentos.


4) Projete e implemente um sistema como o apresentado no diagrama a seguir, utilizando o CI
74LS151 e o CI 74 LS138 LEMBRE-SE QUE ESTES SO TTL; cuidado com as entradas de
seleo, respeite os sinais mais significativos.

Diagrama em blocos do sistema multiplexador e demultiplexador

ATENO
1 NO SERO ACEITOS PEDIDOS DE VISTOS DE PROJETOS/CIRCUITOS SEM OS CLCULOS OU FALTANDO ITENS
DE PROJETO;
2 PARA EVITAR TRANSTORNOS E PERDA DE TEMPO, SEMPRE LEIA O ROTEIRO DA EXPERINCIA ANTES DE VIR
PARA O LABORATRIO.
3 - SE O ALUNO NO APRESENTAR OS PROJETOS DOS CIRCUITOS DE TESTE ANTES DA MONTAGEM, NO SER
VALIDADA A EXPERINCIA.
4 O ALUNO DEVE REALIZAR AS PESQUISAS E O DESENVOLVIMENTO DOS PROJETOS ANTES DE INICIAR O
LABORATRIO.

31

Centro de Educao Profissional Irmo Mrio Cristvo Laboratrio de


Eletrnica Digital Prof. Marcelo Gaiotto
Tabela verdade e Mapas de Karnaugh do Circuito Decodificador

32

Centro de Educao Profissional Irmo Mrio Cristvo Laboratrio de


Eletrnica Digital Prof. Marcelo Gaiotto
Projeto do Circuito Decodificador

Visto Projeto: ___________

33

Centro de Educao Profissional Irmo Mrio Cristvo Laboratrio de


Eletrnica Digital Prof. Marcelo Gaiotto
Tabela verdade do CI CD4511 driver BCD 7 segmentos

34

Centro de Educao Profissional Irmo Mrio Cristvo Laboratrio de


Eletrnica Digital Prof. Marcelo Gaiotto
Projeto de teste do CI CD4511 Decodificador BCD para 7 segmentos

35

Centro de Educao Profissional Irmo Mrio Cristvo Laboratrio de


Eletrnica Digital Prof. Marcelo Gaiotto
Tabela verdade do Multiplexador e Demultiplexador

36

Centro de Educao Profissional Irmo Mrio Cristvo Laboratrio de


Eletrnica Digital Prof. Marcelo Gaiotto
Projeto do Multiplexador e Demultiplexador

37

Centro de Educao Profissional Irmo Mrio Cristvo Laboratrio de


Eletrnica Digital Prof. Marcelo Gaiotto

Laboratrio 5 Circuitos Flip-Flops e Buffers


Tristate
Objetivos:

Aprender como interpretar os dados da especificao tcnica do fabricante;


Conhecer os equipamentos utilizados para efetuar as prticas;
Iniciar a atividade com circuitos sequenciais;
Comprovar o funcionamento de BUFFER TRISTATE;
Comprovar o funcionamento dos FLIP-FLOPS.
Montagem limpa e exemplar (fiao curta e arrumada).

Tempo de Execuo: ____ Aulas


Incio: ____/___/_____ - Trmino: ____/___/_____

Desenvolvimento
Equipamentos e materiais necessrios:
Os componentes e equipamentos ficaro a critrio de cada equipe.
1. Realizar uma pesquisa sobre: Fan in e Fan out, Entradas Sncronas e Assncronas.
A pesquisa dever conter no mximo 10 linhas e dever se entregue na prxima aula de
laboratrio: dia: ________/________/____________
2. Para o circuito de teste: flip-flop RS utilizando portas tipo NAND, complete o projeto e
apresente a tabela verdade antes de test-lo;
3. Para o circuito de teste: flip-flop RS utilizando portas tipo NOR, complete o projeto e apresente
a tabela verdade antes de test-lo;
4. Complete o projeto de teste para o CI 74LS74 FLIP-FLOP D;
5. Complete o projeto de teste para o CI 74LS76 FLIP-FLOP JK;
6. Complete o projeto de teste para o CI 74LS244 OCTAL BUFFER TRISTATE;
7. Complete o projeto de teste para o CI 74LS373 OCTAL LATCH D com sada TRISTATE;

Questes:
1) Qual foi a principal dificuldade encontrada para realizar a experincia?
2) Qual a diferena dos flip-flops RS implementados com portas NAND em relao aos
implementados com portas NOR?
3) O valor da tabela verdade foi diferente do valor esperado? Justifique.
4) Para que serve o OE (ou OC dependendo do fabricante) do CI 74LS373?
5) Para que serve as entradas assncronas nos circuitos integrados 74LS74 e 74LS76?

ATENO
1 NO SERO ACEITOS PEDIDOS DE VISTOS DE PROJETOS/CIRCUITOS SEM OS CLCULOS OU FALTANDO ITENS
DE PROJETO;
2 PARA EVITAR TRANSTORNOS E PERDA DE TEMPO, SEMPRE LEIA O ROTEIRO DA EXPERINCIA ANTES DE VIR
PARA O LABORATRIO.
3 - SE O ALUNO NO APRESENTAR OS PROJETOS DOS CIRCUITOS DE TESTE ANTES DA MONTAGEM, NO SER
VALIDADA A EXPERINCIA.
4 O ALUNO DEVE REALIZAR AS PESQUISAS E O DESENVOLVIMENTO DOS PROJETOS ANTES DE INICIAR O
LABORATRIO.

38

Centro de Educao Profissional Irmo Mrio Cristvo Laboratrio de


Eletrnica Digital Prof. Marcelo Gaiotto
Projeto do Flip-Flop RS com NAND

Visto Projeto: ___________

39

Centro de Educao Profissional Irmo Mrio Cristvo Laboratrio de


Eletrnica Digital Prof. Marcelo Gaiotto
Projeto do Flip-Flop RS com NOR

Visto Projeto: ___________

40

Centro de Educao Profissional Irmo Mrio Cristvo Laboratrio de


Eletrnica Digital Prof. Marcelo Gaiotto
Projeto do FLIP- FLOP D com o CI 74LS74

Visto Projeto: ___________

41

Centro de Educao Profissional Irmo Mrio Cristvo Laboratrio de


Eletrnica Digital Prof. Marcelo Gaiotto
Projeto do FLIP- FLOP JK com o CI 74LS76

Visto Projeto: ___________

42

Centro de Educao Profissional Irmo Mrio Cristvo Laboratrio de


Eletrnica Digital Prof. Marcelo Gaiotto
Projeto do BUFFER TRISTATE com o CI 74LS244

Visto Projeto: ___________

Projeto do OCTAL LATCH D com sada TRISTATE CI 74LS373

Visto Projeto: ___________

43

Centro de Educao Profissional Irmo Mrio Cristvo Laboratrio de


Eletrnica Digital Prof. Marcelo Gaiotto

Laboratrio 6 Aplicaes de FLIP-FLOPS


Circuitos geradores de clock, divisores de frequncia, sequenciais,
contadores e monoastveis (temporizadores)
Objetivos:

Aprender como interpretar os dados da especificao tcnica do fabricante;


Conhecer os equipamentos utilizados para efetuar as prticas;
Comprovar o funcionamento dos flip-flops.
Comprovar o funcionamento dos contadores mdulo N
Comprovar a utilizao de circuitos temporizadores;
Montagem limpa e exemplar (fiao curta e arrumada).

Tempo de Execuo: ____ Aulas


Incio: ____/___/_____ - Trmino: ____/___/_____

Desenvolvimento
Equipamentos e materiais necessrios:

1 74LS14 TTL;
1 CD40106 CMOS
1 CD 4047 CMOS
1 CD 4017 CMOS
2 74LS90 TTL
2 CD4511 driver BCD para 7
segmentos
2 Displays de 7 segmentos catodo
comum

20 resistores de 330R;
1 Potencimetro de 10K
1 protoboard;
1 fonte de alimentao.
1 osciloscpio Digital + duas pontas
de prova;
Resistores diversos.

1. Projetar e implementar um circuito de teste para o circuito integrado CD4017, testando as


possibilidades de criar seqenciadores de 2, 5, 8 e 10 sadas, utilizando o gerador de clock
anterior para que o acionamento entre as trocas de sada, ou mudanas de sequncias sejam
em 3Hz. Obs.: Escolha um dos valores de capacitor (1nF, 10nF, 100nF, 10uF/50V)
disponveis em seu material, facilita os clculos.
2. Utilizando ainda o gerador de clock de 3Hz, montar um circuito contador de 0 99, utilizando
2 CI 74LS90 e os 2 drivers de BCD para 7 segmentos CD4511;
3. Projetar e implementar um circuito temporizador utilizando o CI 4047 para um tempo de
acionamento de 2 segundos. Em seguida altere projeto para operar de forma ajustvel para
um tempo de acionamento mnimo de 2 segundos e mximo de 30 segundos.

ATENO
1 NO SERO ACEITOS PEDIDOS DE VISTOS DE PROJETOS/CIRCUITOS SEM OS CLCULOS OU FALTANDO ITENS
DE PROJETO;
2 PARA EVITAR TRANSTORNOS E PERDA DE TEMPO, SEMPRE LEIA O ROTEIRO DA EXPERINCIA ANTES DE VIR
PARA O LABORATRIO.
3 - SE O ALUNO NO APRESENTAR OS PROJETOS DOS CIRCUITOS DE TESTE ANTES DA MONTAGEM, NO SER
VALIDADA A EXPERINCIA.
4 O ALUNO DEVE REALIZAR AS PESQUISAS E O DESENVOLVIMENTO DOS PROJETOS ANTES DE INICIAR O
LABORATRIO.

44

Centro de Educao Profissional Irmo Mrio Cristvo Laboratrio de


Eletrnica Digital Prof. Marcelo Gaiotto
Projeto 1: Sequenciador com o CD4017

Visto Projeto: ___________

Projeto 2: Contador de 0 99

Visto Projeto: ___________

45

Centro de Educao Profissional Irmo Mrio Cristvo Laboratrio de


Eletrnica Digital Prof. Marcelo Gaiotto
Projeto 3: Temporizador de 2 30 segundos com CD4047

Visto Projeto: ___________

46

Centro de Educao Profissional Irmo Mrio Cristvo Laboratrio de


Eletrnica Digital Prof. Marcelo Gaiotto

Material de apoio
Equipamentos: PROTOBOARD
Conexes eltricas internas da Matriz de contatos, PROTOBOARD.

Conjunto de Chaves digitais MODELO ANTIGO

47

Centro de Educao Profissional Irmo Mrio Cristvo Laboratrio de


Eletrnica Digital Prof. Marcelo Gaiotto
CONJUNTO DE CHAVES DIGITAIS COM 4 BOTES

SIMBOLOGIA DA CADA CHAVE DIGITAL


DIAGRAMA ELTRICO DOS BOTES da HEXKIT SWITCH

48

Centro de Educao Profissional Irmo Mrio Cristvo Laboratrio de


Eletrnica Digital Prof. Marcelo Gaiotto

Sadas Totem-Pole de circuitos integrados TTL


Atua normalmente como uma fornecedora de corrente, fornece os nveis Lgicos 1 e 0

Sadas Open Coletor


So recomendadas para acionamento de cargas em tenses diferentes das de controle TTL, e
somente fornece o nvel lgico 0.

49

Centro de Educao Profissional Irmo Mrio Cristvo Laboratrio de


Eletrnica Digital Prof. Marcelo Gaiotto

CD 4047
Multivibrador Astvel/Monoastavel Configurvel
Diagrama de blocos interno

Formula para clculo de freqncia:


Clculo para circuitos astveis tipo - rodando livre, gatilhos positivo e
negativo:
tA(10, 11) = 4.40 RC
tA (13) = 2.20 RC

Formas de onda do Astavel

50

Centro de Educao Profissional Irmo Mrio Cristvo Laboratrio de


Eletrnica Digital Prof. Marcelo Gaiotto

Clculo para circuitos monoastveis tipo redisparavel e gatilhos


positivo e negativo:
tM (10, 11) = 2.48 RC

Formas de onda do Monosatavel

Formas de onda do modo redisparvel


Configurao para Astvel gatilho positivo
Configurao para Astvel - Rodando livre

Configurao para Astvel gatilho negativo

Configurao para Monoastvel gatilho


positivo

Configurao para monoastvel gatilho


negativo

Configurao para monoastvel


redisparavel

51

Curso Tcnico em Mecatrnica Disciplina de Eletrnica Digital


Prof. Marcelo do C.C. Gaiotto
Folhas de exerccios de desenho de portas lgicas Para melhorara a fixao dos smbolos s
funes Lgicas, contorne-as refazendo os desenhos e escreva em baixo de cada uma seu
nome, e sua expresso algbrica Exemplo: AND (AB), OR (A+B), INVERSORA ( A ).

Centro de Educao Profissional Irmo Mrio Cristvo Laboratrio de


Eletrnica Digital Prof. Marcelo Gaiotto

53

Centro de Educao Profissional Irmo Mrio Cristvo Laboratrio de


Eletrnica Digital Prof. Marcelo Gaiotto

Lista de Exerccios Recomendados 1 semestre 2012


*** estes exerccios no so para entregar ***
Livro LOURENO. Antonio Carlos,
CRUZ. Eduardo C. Alves, FERREIRA.
Sabrina Rodero, JUNIOR. Salomo
Choueri Eletrnica Digital Circuitos
Digitais - Editora rica
2.2 pg 32
Livro CAPUANO,Francisco Gabriel
Exerccios de Eletrnica Digital
Editora rica
** Exerccios propostos
1.1 pg. 13;
1.2 pg. 13;
1.3 pg. 13 e pg. 14;
** Exerccios resolvidos
EX 2.1 pg. 17;
EX 2.2 pg. 18;
EX 2.3 pg. 19;
EX 2.4 pg. 20;
EX 2.5 pg. 20;
EX 2.8 pg. 24 com NAND e com
NOR;
EX 2.9 pg. 26;
** Exerccios propostos
EX 2.1 pg. 28;
EX 2.2 pg. 29;
EX 2.3 pg. 30;
EX 2.4 pg. 30;
EX 2.5 pg. 30;
EX 2.7 pg. 30;
EX 2.8 pg. 30;
EX 2.12 pg. 32;
EX 2.13 pg. 32;
EX 2.15 pg. 32;
EX 2.16 pg. 32;
** Exerccios resolvidos
EX 3.2 pg. 34;
EX 3.3 pg. 34;
EX 3.5 pg. 36;
EX 3.6 pg. 37;

** Exerccios propostos
EX 3.1 pg. 54 (a) e (b);
EX 3.2 pg. 54;
EX 3.3 pg. 54;
EX 3.4 pg. 54;
EX 3.5 pg. 54;
EX 3.6 pg. 54;
EX 3.7 pg. 54;
EX 3.9 pg. 54;
EX 3.17 pg. 59;
EX 3.18 pg. 59;
Livro IDOETA, Ivan Valeije.
CAPUANO, Francisco Gabriel
Elementos de Eletrnica Digital
37 Edio, Editora rica
** Exerccios propostos
1.6.1 pg. 36;
1.6.2 pg. 36;
1.6.3 pg. 37;
1.6.6 pg. 37;
1.6.7 pg. 37;
1.6.8 pg. 37;
1.6.9 pg. 38;
1.6.10 pg. 38;
1.6.11 pg. 38;
1.6.12 pg. 38;
1.6.13 pg. 38;
1.6.14 pg. 38;
1.6.15 pg. 38;
1.6.16 pg. 39;
** Exerccios resolvidos
2.3.1 pg. 52 55 do exerccio 1
ao 4;
2.4.1 pg. 56 58 do exerccio 1
ao 3;
2.5.1 pg. 61 65 do exerccio 1
ao 4;

54

Centro de Educao Profissional Irmo Mrio Cristvo Laboratrio de


Eletrnica Digital Prof. Marcelo Gaiotto

Livro RONALD J. TOCCI, NEAL S.


WIDMER.
Sistemas
Digitais:
Princpios e Aplicaes - Makrom
Books
EX 3.12 (a) e (b) pg. 59;
EX 3.14 pg. 59;
EX 3.16 (a) pg. 60;
EX 3.19 pg. 60;
EX 3.21 pg. 60;
EX 3.26 pg. 60;
Bibliografia de Eletrnica Digital
NATALE, Ferdinando. Eletrnica Industrial. So Paulo: rica, 1994.

IDOETA, Ivan V. Elementos de eletrnica digital. So Paulo: rica, 1994.

SILVA, Ricardo P. e. Eletrnica digital. Florianpolis: UFSC, 1995.


ERCEGOVAC, Milos D. Introduo aos sistemas digitais. Porto Alegre: Bookman, 2000.
ARAUJO,Celso de. Praticando eletrnica digital. So Paulo: rica, 1997.
MALVINO, Alber Paul. Aplicao de princpios digitais. So Paulo: McGraw-Hill, 1988.

RONALD J. TOCCI, NEAL S. WIDMER. Sistemas Digitais: Princpios e Aplicaes Makrom Books

LOURENO/ CRUZ/ FERREIRA/ JUNIOR/ ANTONIO C. DE,/ EDUARDO C. ALVES/


SABRINA R./ SALOMO C. - Circuitos Digitais - Estude e Use - rica

55

Centro de Educao Profissional Irmo Mrio Cristvo


Curso Tcnico em Mecatrnica
Disciplina de Eletrnica Digital

Relatrio de laboratrio

Laboratrio ___ - ______________________________


____/____/_______

Aluno:_________________________________________________
Turno:_________ Turma:____________

Laboratrio: ___ - __________________________


Lista de equipamentos e materiais necessrios:

Introduo terica:

Desenvolvimento

Escala Volts/DIV
Canal1: ____________Ponta de Prova: _____
Canal2: ____________Ponta de Prova: _____
Escala Time/DIV
TIME/DIV: _____________

Observaes

Escala Volts/DIV

Escala Volts/DIV

Canal1: ____________Ponta de Prova: _____

Canal1: ____________Ponta de Prova: _____

Canal2: ____________Ponta de Prova: _____

Canal2: ____________Ponta de Prova: _____

Escala Time/DIV

Escala Time/DIV

TIME/DIV: _____________

TIME/DIV: _____________

Observaes

Concluso:

Lista de referncias bibliogrficas utilizadas:

Nome:___________________________________ Turma:___ Turno:___


Questes - Pesquisas

SN54/74LS00
QUAD 2-INPUT NAND GATE
ESD > 3500 Volts

QUAD 2-INPUT NAND GATE


LOW POWER SCHOTTKY

VCC
14

13

12

11

10

J SUFFIX
CERAMIC
CASE 632-08
1

14

GND

N SUFFIX
PLASTIC
CASE 646-06

14
1

14
1

D SUFFIX
SOIC
CASE 751A-02

ORDERING INFORMATION
SN54LSXXJ
SN74LSXXN
SN74LSXXD

Ceramic
Plastic
SOIC

GUARANTEED OPERATING RANGES


Symbol

Parameter

Min

Typ

Max

Unit

VCC

Supply Voltage

54
74

4.5
4.75

5.0
5.0

5.5
5.25

TA

Operating Ambient Temperature Range

54
74

55
0

25
25

125
70

IOH

Output Current High

54, 74

0.4

mA

IOL

Output Current Low

54
74

4.0
8.0

mA

FAST AND LS TTL DATA


5-2

SN54/74LS00
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol
S b l

Min

Parameter
P

VIH

Input Clamp Diode Voltage

VOH

Input HIGH Current

IIL

Input LOW Current

IOS

Short Circuit Current (Note 1)

Guaranteed Input HIGH Voltage for


All Inputs
Guaranteed Input LOW Voltage for
p
g
All Inputs

VCC = MIN, IIN = 18 mA

Output LOW Voltage

IIH

Test C di i
T
Conditions

Output HIGH Voltage

VOL

2.0

Unit
U i
V

Input LOW Voltage

VIK

Max

Input HIGH Voltage

VIL

Typ

54

0.7

74

0.8
0.65

1.5

54

2.5

3.5

74

2.7

3.5

,
,
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table

54, 74

0.25

0.4

IOL = 4.0 mA

74

0.35

0.5

IOL = 8.0 mA

VCC = VCC MIN,


VIN = VIL or VIH
per Truth Table

20

VCC = MAX, VIN = 2.7 V

mA

VCC = MAX, VIN = 7.0 V

0.4

mA

VCC = MAX, VIN = 0.4 V

100

mA

VCC = MAX

Power Supply Current


Total, Output HIGH

1.6

mA

VCC = MAX

Total, Output LOW

ICC

0.1

4.4

20

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS (TA = 25C)


Limits
Symbol
S b l

Parameter
P

Min

Typ

Max

Unit
U i

Test C di i
T
Conditions
VCC = 5.0 V
CL = 15 pF

tPLH

Turn-Off Delay, Input to Output

9.0

15

ns

tPHL

Turn-On Delay, Input to Output

10

15

ns

FAST AND LS TTL DATA


5-3

SN54/74LS02
QUAD 2-INPUT NOR GATE

QUAD 2-INPUT NOR GATE


VCC
14

LOW POWER SCHOTTKY


13

12

11

10

J SUFFIX
CERAMIC
CASE 632-08

7
14

GND

N SUFFIX
PLASTIC
CASE 646-06

14
1

14
1

D SUFFIX
SOIC
CASE 751A-02

ORDERING INFORMATION
SN54LSXXJ
SN74LSXXN
SN74LSXXD

Ceramic
Plastic
SOIC

GUARANTEED OPERATING RANGES


Symbol

Parameter

Min

Typ

Max

Unit

VCC

Supply Voltage

54
74

4.5
4.75

5.0
5.0

5.5
5.25

TA

Operating Ambient Temperature Range

54
74

55
0

25
25

125
70

IOH

Output Current High

54, 74

0.4

mA

IOL

Output Current Low

54
74

4.0
8.0

mA

FAST AND LS TTL DATA


5-1

SN54/74LS02
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol
S b l

Min

Parameter
P

VIH

Input Clamp Diode Voltage

VOH

Input HIGH Current

IIL

Input LOW Current

IOS

Short Circuit Current (Note 1)

2.0

Guaranteed Input LOW Voltage for


p
g
All Inputs

VCC = MIN, IIN = 18 mA

Output LOW Voltage

IIH

Test C di i
T
Conditions
Guaranteed Input HIGH Voltage for
All Inputs

Output HIGH Voltage

VOL

Unit
U i
V

Input LOW Voltage

VIK

Max

Input HIGH Voltage

VIL

Typ

54

0.7

74

0.8
0.65

1.5

54

2.5

3.5

74

2.7

3.5

,
,
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table

54, 74

0.25

0.4

IOL = 4.0 mA

74

0.35

0.5

IOL = 8.0 mA

VCC = VCC MIN,


VIN = VIL or VIH
per Truth Table

20

VCC = MAX, VIN = 2.7 V

mA

VCC = MAX, VIN = 7.0 V

0.4

mA

VCC = MAX, VIN = 0.4 V

100

mA

VCC = MAX

Power Supply Current


Total, Output HIGH

3.2

mA

VCC = MAX

Total, Output LOW

ICC

0.1

5.4

20

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS (TA = 25C)


Limits
Symbol
S b l

Parameter
P

Min

Typ

Max

Unit
U i

Test C di i
T
Conditions
VCC = 5.0 V
CL = 15 pF

tPLH

Turn-Off Delay, Input to Output

10

15

ns

tPHL

Turn-On Delay, Input to Output

10

15

ns

FAST AND LS TTL DATA


5-2

SN54/74LS04
HEX INVERTER

HEX INVERTER
VCC
14

LOW POWER SCHOTTKY


13

12

11

10

J SUFFIX
CERAMIC
CASE 632-08

7
14

GND

N SUFFIX
PLASTIC
CASE 646-06

14
1

14
1

D SUFFIX
SOIC
CASE 751A-02

ORDERING INFORMATION
SN54LSXXJ
SN74LSXXN
SN74LSXXD

Ceramic
Plastic
SOIC

GUARANTEED OPERATING RANGES


Symbol

Parameter

Min

Typ

Max

Unit

VCC

Supply Voltage

54
74

4.5
4.75

5.0
5.0

5.5
5.25

TA

Operating Ambient Temperature Range

54
74

55
0

25
25

125
70

IOH

Output Current High

54, 74

0.4

mA

IOL

Output Current Low

54
74

4.0
8.0

mA

FAST AND LS TTL DATA


5-1

SN54/74LS04
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol
S b l

Min

Parameter
P

VIH

Input Clamp Diode Voltage

VOH

Input HIGH Current

IIL

Input LOW Current

IOS

Short Circuit Current (Note 1)

ICC

2.0

Power Supply Current


Total, Output HIGH
p
Total, Output LOW

Guaranteed Input LOW Voltage for


p
g
All Inputs

VCC = MIN, IIN = 18 mA

Output LOW Voltage

IIH

Test C di i
T
Conditions
Guaranteed Input HIGH Voltage for
All Inputs

Output HIGH Voltage

VOL

Unit
U i
V

Input LOW Voltage

VIK

Max

Input HIGH Voltage

VIL

Typ

54

0.7

74

0.8
0.65

1.5

54

2.5

3.5

74

2.7

3.5

,
,
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table

54, 74

0.25

0.4

IOL = 4.0 mA

74

0.35

0.5

IOL = 8.0 mA

VCC = VCC MIN,


VIN = VIL or VIH
per Truth Table

20

VCC = MAX, VIN = 2.7 V

mA

VCC = MAX, VIN = 7.0 V

0.4

mA

VCC = MAX, VIN = 0.4 V

100

mA

VCC = MAX

2.4

20

0.1

mA

VCC = MAX

6.6

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS (TA = 25C)


Limits
Symbol
S b l

Parameter
P

Min

Typ

Max

Unit
U i

Test C di i
T
Conditions
VCC = 5.0 V
CL = 15 pF

tPLH

Turn-Off Delay, Input to Output

9.0

15

ns

tPHL

Turn-On Delay, Input to Output

10

15

ns

FAST AND LS TTL DATA


5-2

DM74LS08
Quad 2-Input AND Gates
General Description
This device contains four independent gates each of which
performs the logic AND function.

Features
n Alternate Military/Aerospace device (54LS08) is
available. Contact a Fairchild Semiconductor Sales
Office/Distributor for specifications.

Connection Diagram
Dual-In-Line Package

DS006347-1

Order Number 54LS08DMQB, 54LS08FMQB, 54LS08LMQB, DM54LS08J, DM54LS08W, DM74LS08M or DM74LS08N


See NS Package Number E20A, J14A, M14A, N14A or W14B

Function Table
Y = AB
Inputs

Output

H = High Logic Level


L = Low Logic Level

1998 Fairchild Semiconductor Corporation

DS006347

www.fairchildsemi.com

DM74LS08 Quad 2-Input AND Gates

March 1998

Absolute Maximum Ratings (Note 1)


Supply Voltage
Input Voltage
Operating Free Air Temperature Range

DM54LS and 54LS


DM74LS
Storage Temperature Range

7V
7V

55C to +125C
0C to +70C
65C to +150C

Recommended Operating Conditions


Symbol

Parameter

DM54LS08

DM74LS08

Units

Min

Nom

Max

Min

Nom

Max

4.5

5.5

4.75

5.25

VCC

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

0.7

0.8

IOH

High Level Output Current

0.4

0.4

mA

IOL

Low Level Output Current

mA

TA

Free Air Operating Temperature

70

4
55

125

Note 1: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these
limits. The parametric values defined in the Electrical Characteristics table are not guaranteed at the absolute maximum ratings. The Recommended Operating
Conditions table will define the conditions for actual device operation.

Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol

Parameter

Conditions

Min

Typ

Max

Units

1.5

(Note 2)
VI

Input Clamp Voltage

VOH

High Level Output


Voltage

VOL

Low Level Output


Voltage
Input Current @ Max

II

VCC = Min, II = 18 mA
VCC = Min, IOH = Max,
VIH = Min

DM54

3.4

DM74

VCC = Min, IOL = Max,


VIL = Max
IOL = 4 mA, VCC = Min

2.5
2.7

3.4

DM54

0.25

DM74

0.35

0.4
0.5

DM74

0.25

0.4

VCC = Max, VI = 7V

0.1

V
mA

Input Voltage
IIH

High Level Input Current

IIL

Low Level Input Current

IOS

Short Circuit
Output Current

ICCH

Supply Current with

VCC = Max, VI = 2.7V


VCC = Max, VI = 0.4V
VCC = Max

20

0.36

mA
mA

DM54

20

100

DM74

(Note 3)
VCC = Max

20

100
2.4

4.8

mA

4.4

8.8

mA

Outputs High
ICCL

Supply Current with

VCC = Max

Outputs Low

Switching Characteristics
at VCC = 5V and TA = 25C (See Section 1 for Test Waveforms and Output Load)
RL = 2 k
Symbol

CL = 15 pF

Parameter

CL = 50 pF

Units

Min
tPLH

Propagation Delay Time

Max

Min

Max

13

18

ns

11

18

ns

Low to High Level Output


tPHL

Propagation Delay Time


High to Low Level Output

Note 2: All typicals are at VCC = 5V, TA = 25C.


Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second.

www.fairchildsemi.com

Revised March 2000

DM74LS14
Hex Inverter with Schmitt Trigger Inputs
General Description
This device contains six independent gates each of which
performs the logic INVERT function. Each input has hysteresis which increases the noise immunity and transforms a
slowly changing input signal to a fast changing, jitter free
output.

Ordering Code:
Order Number

Package Number

Package Description

DM74LS14M

M14A

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow

DM74LS14SJ

M14D

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

DM74LS14N

N14A

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code.

Connection Diagram

Function Table
Y=A
Input

Output

H = HIGH Logic Level


L = LOW Logic Level

2000 Fairchild Semiconductor Corporation

DS006353

www.fairchildsemi.com

DM74LS14 Hex Inverter with Schmitt Trigger Inputs

August 1986

DM74LS14

Absolute Maximum Ratings(Note 1)


Supply Voltage

Note 1: The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The Recommended Operating Conditions table will define the conditions
for actual device operation.

7V

Input Voltage

7V
0C to +70C

Operating Free Air Temperature Range

65C to +150C

Storage Temperature Range

Recommended Operating Conditions


Min

Nom

Max

VCC

Symbol
Supply Voltage

Parameter

4.75

5.25

Units
V

VT+

Positive-Going Input Threshold Voltage (Note 2)

1.4

1.6

1.9

VT

Negative-Going Input Threshold Voltage (Note 2)

0.5

0.8

HYS

Input Hysteresis (Note 2)

0.4

0.8

IOH

HIGH Level Output Current

0.4

mA

IOL

LOW Level Output Current

mA

TA

Free Air Operating Temperature

70

Note 2: VCC = 5V.

Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol

Parameter

Conditions

VI

Input Clamp Voltage


HIGH Level

VIL = Max

Max

LOW Level

3.4

VCC = Min, IOL = Max

Output Voltage

VOL

2.7

Units

1.5

VCC = Min, IOH = Max

Output Voltage

Typ
(Note 3)

VCC = Min, II = 18 mA

VOH

Min

VIH = Min

0.25

0.4

VCC = 5V, VI = VT+

0.14

mA

VCC = 5V, VI = VT

Input Current at

0.5

VCC = Min, IOL = 4 mA


IT+

0.35

0.18

mA

Positive-Going Threshold
IT

Input Current at
Negative-Going Threshold

II

Input Current @ Max Input Voltage

VCC = Max, VI = 7V

0.1

IIH

HIGH Level Input Current

VCC = Max, VI = 2.7V

20

IIL

LOW Level Input Current

VCC = Max, VI = 0.4V

0.4

mA

IOS

Short Circuit Output Current

VCC = Max (Note 4)

100

mA

ICCH

Supply Current with Outputs HIGH

VCC = Max

8.6

16

mA

ICCL

Supply Current with Outputs LOW

VCC = Max

12

21

mA

20

mA

Note 3: All typicals are at VCC = 5V, TA = 25C.


Note 4: Not more than one output should be shorted at a time, and the duration should not exceed one second.

Switching Characteristics
at VCC = 5V and TA = 25C
RL = 2 k
Symbol

CL = 15 pF

Parameter

CL = 50 pF

Units

Min
tPLH

Propagation Delay Time


HIGH-to-LOW Level Output

www.fairchildsemi.com

Max

22

25

ns

LOW-to-HIGH Level Output


tPHL

Min

Propagation Delay Time

Max

22

10

33

ns

Revised March 2000

DM74LS32
Quad 2-Input OR Gate
General Description
This device contains four independent gates each of which
performs the logic OR function.

Ordering Code:
Order Number

Package Number

Package Description

DM74LS32M

M14A

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow

DM74LS32SJ

M14D

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

DM74LS32N

N14A

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code.

Connection Diagram

Function Table
Y=A+B
Inputs

Output

Y
L

H = HIGH Logic Level


L = LOW Logic Level

2000 Fairchild Semiconductor Corporation

DS006361

www.fairchildsemi.com

DM74LS32 Quad 2-Input OR Gate

June 1986

DM74LS32

Absolute Maximum Ratings(Note 1)


Supply Voltage

Note 1: The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The Recommended Operating Conditions table will define the conditions
for actual device operation.

7V

Input Voltage

7V
0C to +70C

Operating Free Air Temperature Range

65C to +150C

Storage Temperature Range

Recommended Operating Conditions


Symbol

Parameter

Min

Nom

Max

4.75

5.25

Units

VCC

Supply Voltage

VIH

HIGH Level Input Voltage

VIL

LOW Level Input Voltage

0.8

IOH

HIGH Level Output Current

0.4

mA

IOL

LOW Level Output Current

mA

TA

Free Air Operating Temperature

70

Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol

Parameter

Conditions

VI

Input Clamp Voltage


HIGH Level

VIH = Min

Max

LOW Level

3.4

VCC = Min, IOL = Max

Output Voltage

VOL

2.7

Units

1.5

VCC = Min, IOH = Max

Output Voltage

Typ
(Note 2)

VCC = Min, II = 18 mA

VOH

Min

VIL = Max

0.35
0.25

IOL = 4 mA, VCC = Min

0.5
0.4

II

Input Current @ Max Input Voltage

VCC = Max, VI = 7V

0.1

IIH

HIGH Level Input Current

VCC = Max, VI = 2.7V

20

IIL

LOW Level Input Current

VCC = Max, VI = 0.4V

0.36

mA

IOS

Short Circuit Output Current

VCC = Max (Note 3)

100

mA

ICCH

Supply Current with Outputs HIGH

VCC = Max

3.1

6.2

mA

ICCL

Supply Current with Outputs LOW

VCC = Max

4.9

9.8

mA

20

mA

Note 2: All typicals are at VCC = 5V, TA = 25C.


Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second.

Switching Characteristics
at VCC = 5V and TA = 25C
RL = 2 k
Symbol

CL = 15 pF

Parameter

CL = 50 pF

Units

Min
tPLH
tPHL

Propagation Delay Time


HIGH-to-LOW Level Output

www.fairchildsemi.com

Max

11

15

ns

LOW-to-HIGH Level Output

Min

Propagation Delay Time

Max

11

15

ns

5474 DM5474 DM7474


Dual Positive-Edge-Triggered D Flip-Flops
with Preset Clear and Complementary Outputs
General Description
This device contains two independent positive-edge-triggered D flip-flops with complementary outputs The information on the D input is accepted by the flip-flops on the positive going edge of the clock pulse The triggering occurs at a
voltage level and is not directly related to the transition time
of the rising edge of the clock The data on the D input may
be changed while the clock is low or high without affecting
the outputs as long as the data setup and hold times are not

violated A low logic level on the preset or clear inputs will


set or reset the outputs regardless of the logic levels of the
other inputs

Features
Y

Alternate Military Aerospace device (5474) is available


Contact a National Semiconductor Sales Office Distributor for specifications

Connection Diagram
Dual-In-Line Package

TL F 6526 1

Order Number 5474DMQB 5474FMQB DM5474J DM5474W DM7474M or DM7474N


See NS Package Number J14A M14A N14A or W14B

Function Table
Inputs

Outputs

PR

CLR

CLK

L
H
L
H
H
H

H
L
L
H
H
H

X
X
X

X
X
X
H
L
X

H
L
H
H
L
Q0

L
H
H
L
H
Q0

u
u
L

H e High Logic Level


X e Either Low or High Logic Level
L e Low Logic Level
e Positive-going transition of the clock
e This configuration is nonstable that is it will not persist when either the preset and or clear
inputs return to their inactive (high) level
Q0 e The output logic level of Q before the indicated input conditions were established

C1995 National Semiconductor Corporation

TL F 6526

RRD-B30M105 Printed in U S A

5474 DM5474 DM7474 Dual Positive-Edge-Triggered D Flip-Flops


with Preset Clear and Complementary Outputs

June 1989

Absolute Maximum Ratings (Note)


Note The Absolute Maximum Ratings are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits The
parametric values defined in the Electrical Characteristics
table are not guaranteed at the absolute maximum ratings
The Recommended Operating Conditions table will define
the conditions for actual device operation

If Military Aerospace specified devices are required


please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage
7V
Input Voltage
5 5V
Operating Free Air Temperature Range
b 55 C to a 125 C
DM54 and 54
DM74
0 C to a 70 C
Storage Temperature Range

b 65 C to a 150 C

Recommended Operating Conditions


Symbol

DM5474

Parameter

DM7474

Units

Min

Nom

Max

Min

Nom

Max

45

55

4 75

5 25

VCC

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

IOH

High Level Output Current

IOL

Low Level Output Current

fCLK

Clock Frequency (Note 2)

tW

Pulse Width
(Note 2)

Clock High

30

30

Clock Low

37

37

Clear Low

30

30

V
V

08

08

b0 4

b0 4

mA

16

Preset Low

15

16

Input Setup Time (Notes 1

tH

Input Hold Time (Notes 1

TA

30

Free Air Operating Temperature

2)

MHz

ns

30

20u

2)

mA

15

20u

5u

tSU

Note 1 The symbol (

5u

b 55

125

ns
ns

70

u) indicates the rising edge of the clock pulse is used for reference

Note 2 TA e 25 C and VCC e 5V

Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol

Parameter

Conditions

VI

Input Clamp Voltage


High Level Output
Voltage

VOL

Low Level Output


Voltage

VCC e Min IOH e Max


VIL e Max VIH e Min
VCC e Min IOL e Max
VIH e Min VIL e Max

II

Input Current
Input Voltage

IIH

High Level Input


Current

Typ
(Note 3)

VCC e Min II e b12 mA

VOH

Max

Min

Units

b1 5

24

Max

34

02

04
1

VCC e Max VI e 5 5V
VCC e Max
VI e 2 4V

V
mA

40

Clock

80

Clear

120

Preset
IIL

Low Level Input


Current

40

VCC e Max
VI e 0 4V

b1 6

Clock

b3 2

(Note 6)

Clear

b3 2

Short Circuit
Output Current

VCC e Max
(Note 4)

DM54

b 20

b 55

DM74

b 18

b 55

Supply Current

VCC e Max (Note 5)

Preset
IOS
ICC

mA

b1 6

17

Note 3 All typicals are at VCC e 5V TA e 25 C


Note 4 Not more than one output should be shorted at a time
Note 5 With all outputs open ICC is measured with the Q and Q outputs high in turn At the time of measurement the clock is grounded
Note 6 Clear is tested with preset high and preset is tested with clear high

mA

30

mA
mA

SN54/74LS76A
DUAL JK FLIP-FLOP
WITH SET AND CLEAR
The SN54 / 74LS76A offers individual J, K, Clock Pulse, Direct Set and Direct Clear inputs. These dual flip-flops are designed so that when the clock
goes HIGH, the inputs are enabled and data will be accepted. The Logic Level
of the J and K inputs will perform according to the Truth Table as long as minimum set-up times are observed. Input data is transferred to the outputs on the
HIGH-to-LOW clock transitions.

DUAL JK FLIP-FLOP
WITH SET AND CLEAR
LOW POWER SCHOTTKY

J SUFFIX
CERAMIC
CASE 620-09

MODE SELECT TRUTH TABLE


INPUTS

OUTPUTS

16

OPERATING MODE
SD
Set
Reset (Clear)
*Undetermined
Toggle
Load 0 (Reset)
Load 1 (Set)
Hold

CD

L
H
L
H
H
H
H

H
L
L
H
H
H
H

X
X
X
h
l
h
l

X
X
X
h
h
l
l

H
L
H
q
L
H
q

Q
L
H
H
q
H
L
q

N SUFFIX
PLASTIC
CASE 648-08

16
1

*Both outputs will be HIGH while both SD and CD are LOW, but the output states are unpredictable
if SD and CD go HIGH simultaneously.
H,h = HIGH Voltage Level
L,l = LOW Voltage Level
X = Immaterial
l, h (q) = Lower case letters indicate the state of the referenced input (or output) one setup time prior
to the HIGH-to-LOW clock transition

D SUFFIX
SOIC
CASE 751B-03

16
1

ORDERING INFORMATION
SN54LSXXJ
SN74LSXXN
SN74LSXXD

Ceramic
Plastic
SOIC

LOGIC DIAGRAM
LOGIC SYMBOL
Q

SD
Q

CP

J C Q
D

SET (SD)
K

15

14

SD
Q

11

16
CLEAR (CD)

CP

J C Q
D

10

12

8
VCC = PIN 5
GND = PIN 13

CLOCK (CP)

FAST AND LS TTL DATA


5-1

SN54/74LS76A
GUARANTEED OPERATING RANGES
Symbol

Parameter

Min

Typ

Max

Unit

VCC

Supply Voltage

54
74

4.5
4.75

5.0
5.0

5.5
5.25

TA

Operating Ambient Temperature Range

54
74

55
0

25
25

125
70

IOH

Output Current High

54, 74

0.4

mA

IOL

Output Current Low

54
74

4.0
8.0

mA

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)


Limits
Symbol
S b l

Min

Parameter
P

VIH

Input Clamp Diode Voltage

VOH

Test C di i
T
Conditions

2.0

Guaranteed Input HIGH Voltage for


All Inputs
Guaranteed Input LOW Voltage for
p
g
All Inputs

VCC = MIN, IIN = 18 mA

Output HIGH Voltage

VOL

Unit
U i
V

Input LOW Voltage

VIK

Max

Input HIGH Voltage

VIL

Typ

Output LOW Voltage

54

0.7

74

0.8
0.65

1.5

54

2.5

3.5

74

2.7

3.5

VCC = MIN, IOH = MAX, VIN = VIH


,
,
or VIL per Truth Table
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table

54, 74

0.4

IOL = 4.0 mA

74

0.35

0.5

IOL = 8.0 mA

J, K
Clear
Clock
IIH

0.25

20
60
80

VCC = MAX, VIN = 2.7 V

J, K
Clear
Clock

0.1
0.3
0.4

mA

VCC = MAX, VIN = 7.0 V

0.4
0.8

mA

VCC = MAX, VIN = 0.4 V

100

mA

VCC = MAX

6.0

mA

VCC = MAX

Input HIGH Current

IIL

Input LOW Current

IOS

Short Circuit Current (Note 1)

ICC

J, K
Clear, Clock

Power Supply Current

20

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS (TA = 25C, VCC = 5.0 V)


Limits
Symbol
S b l

Parameter
P

fMAX

Maximum Clock Frequency

tPLH
tPHL

Min

Typ

30

Max

45

Unit
U i

Clock, Clear,
Clock Clear Set to Output

Test C di i
T
Conditions

MHz

15

20

ns

15

20

ns

Max

Unit
U i

VCC = 5.0 V
50
CL = 15 pF

AC SETUP REQUIREMENTS (TA = 25C)


Limits
Symbol
S b l

Parameter
P

Min

Typ

tW

Clock Pulse Width High

20

ns

tW

Clear Set Pulse Width

25

ns

ts

Setup Time

20

ns

th

Hold Time

ns

Test C di i
T
Conditions

FAST AND LS TTL DATA


5-2

VCC = 5 0 V
5.0

SN54/74LS86
QUAD 2-INPUT
EXCLUSIVE OR GATE
QUAD 2-INPUT
EXCLUSIVE OR GATE
LOW POWER SCHOTTKY
VCC
14

13

12

11

10

J SUFFIX
CERAMIC
CASE 632-08
14

7
GND

N SUFFIX
PLASTIC
CASE 646-06

14
1

TRUTH TABLE
IN

OUT

L
L
H
H

L
H
L
H

L
H
H
L

14
1

D SUFFIX
SOIC
CASE 751A-02

ORDERING INFORMATION
SN54LSXXJ
SN74LSXXN
SN74LSXXD

Ceramic
Plastic
SOIC

GUARANTEED OPERATING RANGES


Symbol

Parameter

Min

Typ

Max

Unit

VCC

Supply Voltage

54
74

4.5
4.75

5.0
5.0

5.5
5.25

TA

Operating Ambient Temperature Range

54
74

55
0

25
25

125
70

IOH

Output Current High

54, 74

0.4

mA

IOL

Output Current Low

54
74

4.0
8.0

mA

FAST AND LS TTL DATA


5-1

SN54/74LS86
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol
S b l

Min

Parameter
P

VIH

Input Clamp Diode Voltage

VOH

Input HIGH Current

IIL

Input LOW Current

IOS

Short Circuit Current (Note 1)

ICC

2.0

Power Supply Current

Guaranteed Input LOW Voltage for


p
g
All Inputs

VCC = MIN, IIN = 18 mA

Output LOW Voltage

IIH

Test C di i
T
Conditions
Guaranteed Input HIGH Voltage for
All Inputs

Output HIGH Voltage

VOL

Unit
U i
V

Input LOW Voltage

VIK

Max

Input HIGH Voltage

VIL

Typ

54

0.7

74

0.8
0.65

1.5

54

2.5

3.5

74

2.7

3.5

,
,
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table

54, 74

0.25

0.4

IOL = 4.0 mA

74

0.35

0.5

IOL = 8.0 mA

VCC = VCC MIN,


VIN = VIL or VIH
per Truth Table

40

VCC = MAX, VIN = 2.7 V

0.2

mA

VCC = MAX, VIN = 7.0 V

0.8

mA

VCC = MAX, VIN = 0.4 V

100

mA

VCC = MAX

10

mA

VCC = MAX

Typ

Max

Unit
U i

20

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS (TA = 25C)


Limits
Symbol
S b l

Parameter
P

Min

tPLH
tPHL

Propagation Delay,
Other Input LOW

12
10

23
17

ns

tPLH
tPHL

Propagation Delay,
Other Input HIGH

20
13

30
22

ns

Test C di i
T
Conditions

FAST AND LS TTL DATA


5-2

VCC = 5.0 V
CL = 15 pF

DM74LS90 Decade and Binary Counters

August 1986
Revised March 2000

DM74LS90
Decade and Binary Counters
General Description

Features

Each of these monolithic counters contains four masterslave flip-flops and additional gating to provide a divide-bytwo counter and a three-stage binary counter for which the
count cycle length is divide-by-five for the DM74LS90.

s Typical power dissipation 45 mW


s Count frequency 42 MHz

All of these counters have a gated zero reset and the


DM74LS90 also has gated set-to-nine inputs for use in
BCD nines complement applications.
To use their maximum count length (decade or four bit
binary), the B input is connected to the QA output. The
input count pulses are applied to input A and the outputs
are as described in the appropriate truth table. A symmetrical divide-by-ten count can be obtained from the
DM74LS90 counters by connecting the QD output to the A
input and applying the input count to the B input which
gives a divide-by-ten square wave at output QA.

Ordering Code:
Order Number

Package Number

Package Description

DM74LS90M

M14A

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow

DM74LS90N

N14A

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code.

Connection Diagram

Reset/Count Truth Table


Reset Inputs

Output

R0(1)

R9(2)

QD

QC

QB

QA

COUNT

COUNT

DS006381

R9(1)

2000 Fairchild Semiconductor Corporation

R0(2)

COUNT

COUNT

www.fairchildsemi.com

DM74LS90

Function Tables

Logic Diagram

BCD Count Sequence (Note 1)


Count

Output
QD

QC

QB

QA
L

Bi-Quinary (5-2) (Note 2)


Count

Output
QA

QD

QC

QB
L

H = HIGH Level
L = LOW Level
X = Dont Care
The J and K inputs shown without connection are for reference only and
are functionally at a high level.

Note 1: Output QA is connected to input B for BCD count.


Note 2: Output QD is connected to input A for bi-quinary count.
Note 3: Output QA is connected to input B.

www.fairchildsemi.com

Supply Voltage

7V

Input Voltage (Reset)

7V

Input Voltage (A or B)

Note 4: The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics table are not guaranteed at the absolute maximum ratings.
The Recommended Operating Conditions table will define the conditions
for actual device operation.

5.5V
0C to +70C

Operating Free Air Temperature Range

65C to +150C

Storage Temperature Range

Recommended Operating Conditions


Symbol

Parameter

Min

Nom

Max

Units

4.75

5.25

LOW Level Input Voltage

0.8

IOH

HIGH Level Output Current

0.4

mA

IOL

LOW Level Output Current

mA

fCLK

Clock Frequency (Note 5)

MHz

fCLK

Clock Frequency (Note 6)

VCC

Supply Voltage

VIH

HIGH Level Input Voltage

VIL

32

B to QB

16

A to QA

20

B to QB

10

15

50

Reset

ns

25

tW

Pulse Width (Note 6)

30

Reset

MHz

15

tW

Pulse Width (Note 5)

A to QA

25

tREL

Reset Release Time (Note 5)

25

tREL

Reset Release Time (Note 6)

35

TA

Free Air Operating Temperature

ns
ns

ns
C

70

Note 5: CL = 15 pF, RL = 2 k, TA = 25C and VCC = 5V.


Note 6: CL = 50 pF, RL = 2 k, TA = 25C and VCC = 5V.

Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol

Parameter

Conditions

VI

Input Clamp Voltage


HIGH Level

VIL = Max, VIH = Min

LOW Level

VCC = Min, IOL = Max

Output Voltage

VOL

2.7

VIL = Max, VIH = Min

(Note 8)

Max

Units

1.5

VCC = Min, IOH = Max

Output Voltage

Typ
(Note 7)

VCC = Min, II = 18 mA

VOH

Min

3.4

0.35

0.5

0.25

IOL = 4 mA, VCC = Min

0.4

VCC = Max, VI = 7V

Reset

0.1

VCC = Max

0.2

VI = 5.5V

0.4

VCC = Max, VI = 2.7V

Reset

20

40

IIH

Input Current @ Max


Input Voltage

II

80

HIGH Level
Input Current
LOW Level

Reset

VCC = Max, VI = 0.4V

Input Current
IOS

Short Circuit Output Current

VCC = Max (Note 9)

ICC

Supply Current

VCC = Max (Note 7)

2.4

mA

0.4

A
B

IIL

3.2
20

mA

100
9

mA

15

mA

Note 7: All typicals are at VCC = 5V, TA = 25C.

www.fairchildsemi.com

DM74LS90

Absolute Maximum Ratings(Note 4)

SN54/74LS138

1-OF-8 DECODER/
DEMULTIPLEXER
The LSTTL / MSI SN54 / 74LS138 is a high speed 1-of-8 Decoder /
Demultiplexer. This device is ideally suited for high speed bipolar memory
chip select address decoding. The multiple input enables allow parallel expansion to a 1-of-24 decoder using just three LS138 devices or to a 1-of-32
decoder using four LS138s and one inverter. The LS138 is fabricated with the
Schottky barrier diode process for high speed and is completely compatible
with all Motorola TTL families.

1-OF-8 DECODER /
DEMULTIPLEXER
LOW POWER SCHOTTKY

Demultiplexing Capability
Multiple Input Enable for Easy Expansion
Typical Power Dissipation of 32 mW
Active Low Mutually Exclusive Outputs
Input Clamp Diodes Limit High Speed Termination Effects

J SUFFIX
CERAMIC
CASE 620-09

CONNECTION DIAGRAM DIP (TOP VIEW)


VCC

O0

O1

O2

O3

O4

O5

16

15

14

13

12

11

10

16

O6
9

NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.

N SUFFIX
PLASTIC
CASE 648-08

16
1

1
A0

2
A1

3
A2

4
E1

5
E2

6
E3

7
O7

8
GND

PIN NAMES

HIGH
A0 A2
E1, E2
E3
O0 O7

LOW

0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.

Address Inputs
Enable (Active LOW) Inputs
Enable (Active HIGH) Input
Active LOW Outputs (Note b)

0.25 U.L.
0.25 U.L.
0.25 U.L.
5 (2.5) U.L.

NOTES:
a) 1 TTL Unit Load (U.L.) = 40 A HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
Temperature Ranges.

LOGIC DIAGRAM
A2
3

D SUFFIX
SOIC
CASE 751B-03

LOADING (Note a)

A1

A0

ORDERING INFORMATION
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD

Ceramic
Plastic
SOIC

LOGIC SYMBOL

E1 E2 E3

16

VCC = PIN 16
GND = PIN 8
= PIN NUMBERS

1 2 3

456
12 3

A0 A1 A2

O0 O1 O2 O3 O4 O5 O6 O7

15 14 13 12 11 10 9 7
VCC = PIN 16
GND = PIN 8
7

O7

10

O6

11

O5

12

O4

13

O3

14

O2

15

O1

O0

FAST AND LS TTL DATA


5-1

SN54/74LS138
FUNCTIONAL DESCRIPTION
The LS138 is a high speed 1-of-8 Decoder/Demultiplexer
fabricated with the low power Schottky barrier diode process.
The decoder accepts three binary weighted inputs (A0, A1, A2)
and when enabled provides eight mutually exclusive active
LOW Outputs (O0 O7). The LS138 features three Enable inputs, two active LOW (E1, E2) and one active HIGH (E3). All
outputs will be HIGH unless E1 and E2 are LOW and E3 is
HIGH. This multiple enable function allows easy parallel ex-

pansion of the device to a 1-of-32 (5 lines to 32 lines) decoder


with just four LS138s and one inverter. (See Figure a.)
The LS138 can be used as an 8-output demultiplexer by
using one of the active LOW Enable inputs as the data input
and the other Enable inputs as strobes. The Enable inputs
which are not used must be permanently tied to their appropriate active HIGH or active LOW state.

TRUTH TABLE
INPUTS

OUTPUTS

E1

E2

E3

A0

A1

A2

O0

O1

O2

O3

O4

O5

O6

O7

H
X
X
L
L
L
L
L
L
L
L

X
H
X
L
L
L
L
L
L
L
L

X
X
L
H
H
H
H
H
H
H
H

X
X
X
L
H
L
H
L
H
L
H

X
X
X
L
L
H
H
L
L
H
H

X
X
X
L
L
L
L
H
H
H
H

H
H
H
L
H
H
H
H
H
H
H

H
H
H
H
L
H
H
H
H
H
H

H
H
H
H
H
L
H
H
H
H
H

H
H
H
H
H
H
L
H
H
H
H

H
H
H
H
H
H
H
L
H
H
H

H
H
H
H
H
H
H
H
L
H
H

H
H
H
H
H
H
H
H
H
L
H

H
H
H
H
H
H
H
H
H
H
L

H = HIGH Voltage Level


L = LOW Voltage Level
X = Dont Care

A0
A1
A2
LS04
A3
A4

H
123
A0 A1 A2

123
A0 A1 A2

123
A0 A1 A2

123
A0 A1 A2

LS138

LS138

LS138

LS138

O0 O1 O2 O3 O4 O5 O6 O7

O0 O1 O2 O3 O4 O5 O6 O7

O0 O1 O2 O3 O4 O5 O6 O7

O0 O1 O2 O3 O4 O5 O6 O7

O0

O31

Figure a

FAST AND LS TTL DATA


5-2

SN54/74LS138
GUARANTEED OPERATING RANGES
Symbol

Parameter

Min

Typ

Max

Unit

VCC

Supply Voltage

54
74

4.5
4.75

5.0
5.0

5.5
5.25

TA

Operating Ambient Temperature Range

54
74

55
0

25
25

125
70

IOH

Output Current High

54, 74

0.4

mA

IOL

Output Current Low

54
74

4.0
8.0

mA

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)


Limits
Symbol
S b l

Parameter
P

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

VIK

Input Clamp Diode Voltage

VOH

Output HIGH Voltage


O
V l

VOL

Input LOW Current

IOS

Short Circuit Current (Note 1)

ICC

Unit
U i

Max

Test C di i
T
Conditions

Input HIGH Current

IIL

Typ

Power Supply Current

Guaranteed Input LOW Voltage for


p
g
All Inputs

2.0

Guaranteed Input HIGH Voltage for


All Inputs

VCC = MIN, IIN = 18 mA

Output LOW Voltage

IIH

Min

54

0.7

74

0.8
0.65

1.5

54

2.5
25

3.5
35

74

2.7

3.5

VCC = MIN, IOH = MAX, VIN = VIH


MIN,
MAX,
or VIL per Truth Table
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table

54, 74

0.25

0.4

IOL = 4.0 mA

74

0.35

0.5

IOL = 8.0 mA

20

VCC = MAX, VIN = 2.7 V

0.1

VCC = MAX, VIN = 7.0 V

mA

VCC = MAX, VIN = 0.4 V

100

mA

VCC = MAX

10

20

mA

0.4

mA

VCC = MAX

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS (TA = 25C)


Symbol
S b l

Levels of
Delay

Parameter
P

Limits
Min

Typ

Max

Unit
U i

tPLH
tPHL

Propagation Delay
Address to Output

2
2

13
27

20
41

ns

tPLH
tPHL

Propagation Delay
Address to Output

3
3

18
26

27
39

ns

tPLH
tPHL

Propagation Delay E1 or E2
Enable to Output

2
2

12
21

18
32

ns

tPLH
tPHL

Propagation Delay E3
Enable to Output

3
3

17
25

26
38

Test C di i
T
Conditions

ns

VCC = 5.0 V
50
CL = 15 pF

AC WAVEFORMS
VIN

1.3 V
tPHL

VOUT

VIN

1.3 V

1.3 V

tPLH

1.3 V
tPHL

VOUT

1.3 V

Figure 1

1.3 V
tPLH

1.3 V

1.3 V

Figure 2

FAST AND LS TTL DATA


5-3

Revised March 2000

DM74LS151
1-of-8 Line Data Selector/Multiplexer
General Description

Features

This data selector/multiplexer contains full on-chip decoding to select the desired data source. The DM74LS151
selects one-of-eight data sources. The DM74LS151 has a
strobe input which must be at a low logic level to enable
these devices. A high level at the strobe forces the W output HIGH, and the Y output LOW.

s Select one-of-eight data lines

The DM74LS151 features complementary W and Y outputs.

s Performs parallel-to-serial conversion


s Permits multiplexing from N lines to one line
s Also for use as Boolean function generator
s Typical average propagation delay time data input to
W output 12.5 ns
s Typical power dissipation 30 mW

Ordering Code:
Order Number

Package Number

Package Description

DM74LS151M

M16A

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

DM74LS151SJ

M16D

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

DM74LS151N

N16E

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code.

Connection Diagram

Truth Table
Inputs

Outputs

Select

Strobe

D0

D0

D1

D1

D2

D2

D3

D3

D4

D4

D5

D5

D6

D6

D7

D7

H = HIGH Level
L = LOW Level
X = Don't Care
D0, D1...D7 = the level of the respective D input

2000 Fairchild Semiconductor Corporation

DS006392

www.fairchildsemi.com

DM74LS151 1-of-8 Line Data Selector/Multiplexer

August 1986

DM74LS151

Logic Diagrams

See Address Buffers

Address Buffers

www.fairchildsemi.com

Supply Voltage

Note 1: The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The Recommended Operating Conditions table will define the conditions
for actual device operation.

7V

Input Voltage

7V
0C to +70C

Operating Free Air Temperature Range

65C to +150C

Storage Temperature Range

Recommended Operating Conditions


Symbol

Parameter

Min

Nom

Max

4.75

5.25

Units

VCC

Supply Voltage

VIH

HIGH Level Input Voltage

VIL

LOW Level Input Voltage

0.8

IOH

HIGH Level Output Current

0.4

mA

IOL

LOW Level Output Current

mA

TA

Free Air Operating Temperature

70

Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol

Parameter

Conditions

VI

Input Clamp Voltage


HIGH Level

VCC = Min, IOH = Max

Output Voltage

VIL = Max, VIH = Min

Typ
(Note 2)

VCC = Min, II = 18 mA

VOH

Min

LOW Level

1.5
2.7

VCC = Min, IOL = Max

Output Voltage

VOL

Max

VIL = Max, VIH = Min

3.4

V
V

0.35

0.5

0.25

IOL = 4 mA, VCC = Min

Units

0.4

II

Input Current @ Max Input Voltage

VCC = Max, VI = 7V

0.1

IIH

HIGH Level Input Current

VCC = Max, VI = 2.7V

20

IIL

LOW Level Input Current

VCC = Max, VI = 0.4V

0.4

mA

IOS

Short Circuit Output Current

VCC = Max (Note 3)

100

mA

ICC

Supply Current

VCC = Max (Note 4)

10

mA

20
6

mA

Note 2: All typicals are at VCC = 5V, TA = 25C.


Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 4: ICC is measured with all outputs OPEN, strobe and data select inputs at 4.5V, and all other inputs OPEN.

www.fairchildsemi.com

DM74LS151

Absolute Maximum Ratings(Note 1)

Revised March 2000

DM74LS244
Octal 3-STATE Buffer/Line Driver/Line Receiver
General Description

Features

These buffers/line drivers are designed to improve both the


performance and PC board density of 3-STATE buffers/
drivers employed as memory-address drivers, clock drivers, and bus-oriented transmitters/receivers. Featuring 400
mV of hysteresis at each low current PNP data line input,
they provide improved noise rejection and high fanout outputs and can be used to drive terminated lines down to
133.

s 3-STATE outputs drive bus lines directly


s PNP inputs reduce DC loading on bus lines
s Hysteresis at data inputs improves noise margins
s Typical IOL (sink current)

24 mA

s Typical IOH (source current) 15 mA


s Typical propagation delay times
Inverting

10.5 ns

Noninverting

12 ns

s Typical enable/disable time

18 ns

s Typical power dissipation (enabled)


Inverting

130 mW

Noninverting

135 mW

Ordering Code:
Order Number

Package Number

Package Description

DM74LS244WM

M20B

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

DM74LS244SJ

M20D

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

DM74LS244N

N20A

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code.

Connection Diagram

Function Table
Inputs

Output

Y
L

L = LOW Logic Level


H = HIGH Logic Level
X = Either LOW or HIGH Logic Level
Z = High Impedance

2000 Fairchild Semiconductor Corporation

DS008442

www.fairchildsemi.com

DM74LS244 Octal 3-STATE Buffer/Line Driver/Line Receiver

August 1986

DM74LS244

Absolute Maximum Ratings(Note 1)


Supply Voltage

Note 1: The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The Recommended Operating Conditions table will define the conditions
for actual device operation.

7V

Input Voltage

7V
0C to +70C

Operating Free Air Temperature Range

65C to +150C

Storage Temperature Range

Recommended Operating Conditions


Symbol

Parameter

Min

Nom

Max

Units

4.75

5.25

LOW Level Input Voltage

0.8

IOH

HIGH Level Output Current

15

mA

IOL

LOW Level Output Current

24

mA

TA

Free Air Operating Temperature

70

VCC

Supply Voltage

VIH

HIGH Level Input Voltage

VIL

Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol

Parameter

Min

Conditions

VI

Input Clamp Voltage

VCC = Min, II = 18 mA

HYS

Hysteresis (VT+ VT)

Typ

Max

(Note 2)

VCC = Min

1.5
0.2

Units
V

0.4

3.4

Data Inputs Only


VOH

HIGH Level Output Voltage

VCC = Min, VIH = Min

2.7

VIL = Max, IOH = 1 mA


VCC = Min, VIH = Min

2.4

VIL = Max, IOH = 3 mA


VCC = Min, VIH = Min

VIL = 0.5V, IOH = Max


LOW Level Output Voltage

VCC = Min

IOL = 12 mA

0.4

VIL = Max

VOL

IOL = Max

0.5

VO = 2.7V

20

VIH = Min

IOZL

Off-State Output Current,

VCC = Max

HIGH Level Voltage Applied

IOZH

VIL = Max

Off-State Output Current,

VIH = Min

VO = 0.4V

20

VCC = Max

VI = 7V

0.1

mA

20

LOW Level Voltage Applied


II

Input Current at Maximum


Input Voltage

IIH

HIGH Level Input Current

VCC = Max

VI = 2.7V

IIL

LOW Level Input Current

VCC = Max

V I = 0.4V

IOS

Short Circuit Output Current

VCC = Max (Note 3)

ICC

Supply Current

VCC = Max,

Outputs HIGH

13

23

Outputs Open

Outputs LOW

27

46

Outputs Disabled

32

54

Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second.

www.fairchildsemi.com

200

40

Note 2: All typicals are at VCC = 5V, TA = 25C.

0.5

225

mA
mA

SN54/74LS373
SN54/74LS374

OCTAL TRANSPARENT LATCH


WITH 3-STATE OUTPUTS;
OCTAL D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUT

OCTAL TRANSPARENT LATCH


WITH 3-STATE OUTPUTS;
OCTAL D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUT

The SN54 / 74LS373 consists of eight latches with 3-state outputs for bus
organized system applications. The flip-flops appear transparent to the data
(data changes asynchronously) when Latch Enable (LE) is HIGH. When LE is
LOW, the data that meets the setup times is latched. Data appears on the bus
when the Output Enable (OE) is LOW. When OE is HIGH the bus output is in
the high impedance state.
The SN54 / 74LS374 is a high-speed, low-power Octal D-type Flip-Flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. A buffered Clock (CP) and Output Enable (OE) is common
to all flip-flops. The SN54 / 74LS374 is manufactured using advanced Low
Power Schottky technology and is compatible with all Motorola TTL families.

LOW POWER SCHOTTKY

20
1

Eight Latches in a Single Package


3-State Outputs for Bus Interfacing
Hysteresis on Latch Enable
Edge-Triggered D-Type Inputs
Buffered Positive Edge-Triggered Clock
Hysteresis on Clock Input to Improve Noise Margin
Input Clamp Diodes Limit High Speed Termination Effects

PIN NAMES

J SUFFIX
CERAMIC
CASE 732-03

N SUFFIX
PLASTIC
CASE 738-03

20
1

DW SUFFIX
SOIC
CASE 751D-03

LOADING (Note a)
20

HIGH
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
65 (25) U.L.

Data Inputs
Latch Enable (Active HIGH) Input
Clock (Active HIGH going edge) Input
Output Enable (Active LOW) Input
Outputs (Note b)

D0 D7
LE
CP
OE
O0 O7

LOW
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
15 (7.5) U.L.

ORDERING INFORMATION
SN54LSXXXJ
Ceramic
SN74LSXXXN Plastic
SN74LSXXXDW SOIC

NOTES:
a) 1 TTL Units Load (U.L.) = 40 A HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 7.5 U.L. for Military (54) and 25 U.L. for Commercial
(74) Temperature Ranges. The Output HIGH drive factor is 25 U.L. for Military (54) and
65 U.L. for Commercial (74) Temperature Ranges.

CONNECTION DIAGRAM DIP (TOP VIEW)


SN54 / 74LS374

SN54 / 74LS373
D7

D6

O6

O5

D5

D4

O4

LE

20

19

18

17

16

15

14

13

12

11

1
OE

2
O0

3
D0

4
D1

5
O1

6
O2

7
D2

8
D3

9
O3

10
GND

VCC O7

VCC O7

D7

D6

O6

O5

D5

D4

O4

CP

20

NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.

19

18

17

16

15

14

13

12

11

1
OE

2
O0

3
D0

4
D1

5
O1

6
O2

7
D2

8
D3

9
O3

10
GND

FAST AND LS TTL DATA


5-1

SN54/74LS373 SN54/74LS374
TRUTH TABLE
LS374

LS373
Dn

LE

OE

On

Dn

Q0

LE

OE

On

Z*

Z*

H = HIGH Voltage Level


L = LOW Voltage Level
X = Immaterial
Z = High Impedance
* Note: Contents of flip-flops unaffected by the state of the Output Enable input (OE).

LOGIC DIAGRAMS
SN54LS / 74LS373

D0

D1

D
LATCH
ENABLE
LE
11

D2

D
Q
G

D3

D
Q
G

13

14

D4

D
Q
G

17

D5

D
Q
G

D6

D
Q
G

18

D
Q
G

VCC = PIN 20
GND = PIN 10
= PIN NUMBERS

D7
D
Q
G

Q
G

OE

O0
2

O1

O2

O3

O4

O5

12

O6

O7

16

15

19

SN54LS / 74LS374
3

D0

11

D1

D2

13

D3

14

D4

17

D5

18

D6

D7

CP
CP D
Q Q

CP D
Q Q

CP D
Q Q

CP D
Q Q

CP D
Q Q

CP D
Q Q

CP D
Q Q

CP D
Q Q

OE
1

O0

O1

O2
6

O3
9

O4
12

O5

O6

15

O7

16

19

GUARANTEED OPERATING RANGES


Symbol

Parameter

Min

Typ

Max

Unit

VCC

Supply Voltage

54
74

4.5
4.75

5.0
5.0

5.5
5.25

TA

Operating Ambient Temperature Range

54
74

55
0

25
25

125
70

IOH

Output Current High

54
74

1.0
2.6

mA

IOL

Output Current Low

54
74

12
24

mA

FAST AND LS TTL DATA


5-2

SN54/74LS373 SN54/74LS374
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol
S b l

Min

Parameter
P

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

VIK

Input Clamp Diode Voltage

VOH

Output HIGH Voltage

VOL

IOZL

Max

Unit
U i

Test C di i
T
Conditions

V
V

Guaranteed Input LOW Voltage for


p
g
All Inputs

2.0

Guaranteed Input HIGH Voltage for


All Inputs

VCC = MIN, IIN = 18 mA

Output LOW Voltage

IOZH

Typ

54

0.7

74

0.8
0.65

1.5

54

2.4

3.4

74

2.4

3.1

VCC = MIN, IOH = MAX, VIN = VIH


,
,
or VIL per Truth Table
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table

54, 74

0.25

0.4

IOL = 12 mA

74

0.35

0.5

IOL = 24 mA

Output Off Current HIGH

20

VCC = MAX, VOUT = 2.7 V

Output Off Current LOW

20

VCC = MAX, VOUT = 0.4 V

20

VCC = MAX, VIN = 2.7 V

0.1

mA

VCC = MAX, VIN = 7.0 V

IIH

Input HIGH Current

IIL

Input LOW Current

IOS

Short Circuit Current (Note 1)

ICC

Power Supply Current

0.4

mA

VCC = MAX, VIN = 0.4 V

130

mA

VCC = MAX

40

30

mA

VCC = MAX

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS (TA = 25C, VCC = 5.0 V)


Limits
LS373
Symbol
S b l

Parameter
P

Min

Typ

LS374
Max

Min

Typ

35

Unit
U i

Max

50

fMAX

Maximum Clock Frequency

tPLH
tPHL

Propagation Delay,
Data to Output

12
12

18
18

tPLH
tPHL

Clock or Enable
to Output

20
18

30
30

15
19

28
28

ns

tPZH
tPZL

Output Enable Time

15
25

28
36

20
21

28
28

ns

tPHZ
tPLZ

Output Disable Time

12
15

20
25

12
15

20
25

ns

Test C di i
T
Conditions

MHz
ns
CL = 45 pF,
pF
F
RL = 667

CL = 5.0 pF

AC SETUP REQUIREMENTS (TA = 25C, VCC = 5.0 V)


Limits
LS373
Symbol
S b l

Parameter
P

Min

LS374
Max

Min

Max

Unit
U i

tW

Clock Pulse Width

15

15

ns

ts

Setup Time

5.0

20

ns

th

Hold Time

20

ns

DEFINITION OF TERMS
SETUP TIME (ts) is defined as the minimum time required
for the correct logic level to be present at the logic input prior to
LE transition from HIGH-to-LOW in order to be recognized and
transferred to the outputs.

HOLD TIME (th) is defined as the minimum time following


the LE transition from HIGH-to-LOW that the logic level must
be maintained at the input in order to ensure continued
recognition.

FAST AND LS TTL DATA


5-3

Revised January 1999

CD4001BC/CD4011BC
Quad 2-Input NOR Buffered B Series Gate
Quad 2-Input NAND Buffered B Series Gate
General Description

Features

The CD4001BC and CD4011BC quad gates are monolithic


complementary MOS (CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. They have equal source and sink current
capabilities and conform to standard B series output drive.
The devices also have buffered outputs which improve
transfer characteristics by providing very high gain.

s Low power TTL:


Fan out of 2 driving 74L compatibility:

or 1 driving 74LS

s 5V10V15V parametric ratings


s Symmetrical output characteristics
s Maximum input leakage 1 A at 15V over full
temperature range

All inputs are protected against static discharge with diodes


to VDD and VSS.

Ordering Code:
Order Number

Package Number

Package Description

CD4001BCM

M14A

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow

CD4001BCSJ

M14D

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

CD4001BCN

N14A

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

CD4011BCM

M14A

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow

CD4011BCN

N14A

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code.

Connection Diagrams
Pin Assignments for DIP, SOIC and SOP
CD4001BC

Top View

1999 Fairchild Semiconductor Corporation

Pin Assignments for DIP and SOIC


CD4011BC

Top View

DS005939.prf

www.fairchildsemi.com

CD4001BC/CD4011BC Quad 2-Input NOR Buffered B Series Gate Quad 2-Input NAND Buffered B Series Gate

October 1987

CD4001BC/CD4011BC

Schematic Diagrams
CD4001BC

1/

of device shown

J=A+B
Logical 1 = HIGH
Logical 0 = LOW
All inputs protected by standard
CMOS protection circuit.

CD4011BC

/4 of device shown

J=AB
Logical 1 = HIGH
Logical 0 = LOW
All inputs protected by standard
CMOS protection circuit.

www.fairchildsemi.com

Recommended Operating
Conditions

0.5V to VDD +0.5V

Voltage at any Pin

Operating Range (VDD )

Power Dissipation (PD)


Dual-In-Line

700 mW

Small Outline

500 mW
65C to +150C

Storage Temperature (TS)


Lead Temperature (TL)
(Soldering, 10 seconds)

Note 2: All voltages measured with respect to VSS unless otherwise specified.

260C

DC Electrical Characteristics
Parameter

40C to +85C

CD4001BC, CD4011BC

Note 1: Absolute Maximum Ratings are those values beyond which the
safety of the device cannot be guaranteed. Except for Operating Temperature Range they are not meant to imply that the devices should be operated at these limits. The Electrical Characteristics tables provide conditions
for actual device operation.

0.5 VDC to +18 VDC

VDD Range

Symbol

3 VDC to 15 VDC

Operating Temperature Range

(Note 2)
40C

Conditions

Min

+25C

Max

Min

+85C

Typ

Max

Min

Max

Units

Quiescent Device

VDD = 5V, VIN = VDD or VSS

0.004

7.5

Current

VDD = 10V, VIN = VDD or VSS

0.005

15

VDD = 15V, VIN = VDD or VSS

IDD

0.006

30

0.05

0.05

0.05

0.05

0.05

0.05

0.05

0.05

0.05

LOW Level

VDD = 5V

Output Voltage

VOL

VDD = 10V

|IO| < 1 A

VDD = 15V
HIGH Level

VDD = 5V

Output Voltage

VOH

VDD = 10V

4.95

4.95

4.95

9.95

9.95

10

9.95

14.95

14.95

15

14.95

|IO| < 1 A

VDD = 15V

VDD = 5V, VO = 4.5V

Input Voltage

1.5

1.5

VDD = 10V, VO = 9.0V

LOW Level

1.5
3.0

3.0

3.0

VDD = 15V, VO = 13.5V

VIL

4.0

4.0

4.0

VDD = 5V, VO = 0.5V

3.5

3.5

3.5

VDD = 10V, VO = 1.0V

7.0

7.0

7.0

VDD = 15V, VO = 1.5V

11.0

11.0

11.0

LOW Level Output

VDD = 5V, VO = 0.4V

0.52

0.44

0.88

0.36

mA

Current

IOL

HIGH Level
Input Voltage

VIH

VDD = 10V, VO = 0.5V

1.3

1.1

2.25

0.9

mA
mA

(Note 3)

3.6

3.0

8.8

2.4

VDD = 5V, VO = 4.6V

0.52

0.44

0.88

0.36

mA

VDD = 10V, VO = 9.5V

1.3

1.1

2.25

0.9

mA

(Note 3)

VDD = 15V, VO = 13.5V

3.6

Input Current

VDD = 15V, VIN = 0V

0.30

105

0.30

1.0

VDD = 15V, VIN = 15V

IIN

VDD = 15V, VO = 1.5V

HIGH Level Output


Current

IOH

0.30

105

0.30

1.0

3.0

8.8

2.4

mA

Note 3: IOL and IOH are tested one output at a time.

AC Electrical Characteristics

(Note 4)

CD4001BC: TA = 25C, Input tr; tf = 20 ns. CL = 50 pF, RL = 200k. Typical temperature coefficient is 0.3%/C.
Symbol

120

250

ns

VDD = 10V

50

100

ns

35

70

ns

Propagation Delay Time,

VDD = 5V

110

250

ns

LOW-to-HIGH Level

VDD = 10V

50

100

ns

VDD = 15V

35

70

ns

Transition Time

VDD = 5V

90

200

ns

VDD = 10V

50

100

ns

VDD = 15V

tTHL, tTLH

Max

VDD = 5V
VDD = 15V

tPLH

Typ

Propagation Delay Time,


HIGH-to-LOW Level

tPHL

Parameter

Conditions

40

80

ns

7.5

pF

CIN

Average Input Capacitance

Any Input

CPD

Power Dissipation Capacity

Any Gate

14

Units

pF

Note 4: AC Parameters are guaranteed by DC correlated testing.

www.fairchildsemi.com

CD4001BC/CD4011BC

Absolute Maximum Ratings(Note 1)


(Note 2)

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

MC14001B

Quad 2-Input NOR Gate

B-Suffix Series CMOS Gates

MC14002B

The B Series logic gates are constructed with P and N channel


enhancement mode devices in a single monolithic structure (Complementary MOS). Their primary use is where low power dissipation and/or high
noise immunity is desired.
Supply Voltage Range = 3.0 Vdc to 18 Vdc
All Outputs Buffered
Capable of Driving Two Lowpower TTL Loads or One Lowpower
Schottky TTL Load Over the Rated Temperature Range.
Double Diode Protection on All Inputs Except: Triple Diode Protection
on MC14011B and MC14081B
PinforPin Replacements for Corresponding CD4000 Series B Suffix
Devices (Exceptions: MC14068B and MC14078B)

Dual 4-Input NOR Gate

MC14011B

Quad 2-Input NAND Gate

MC14012B

Dual 4-Input NAND Gate

MC14023B

Triple 3-Input NAND Gate

MC14025B

Triple 3-Input NOR Gate

MC14068B

L SUFFIX
CERAMIC
CASE 632

P SUFFIX
PLASTIC
CASE 646

8-Input NAND Gate

D SUFFIX
SOIC
CASE 751A

MC14071B

Quad 2-Input OR Gate

ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBD

Plastic
Ceramic
SOIC

TA = 55 to 125C for all packages.

MAXIMUM RATINGS* (Voltages Referenced to VSS)


Symbol
VDD

Parameter

DC Supply Voltage

Value

Unit

0.5 to + 18.0

Vin, Vout

Input or Output Voltage (DC or Transient)

0.5 to VDD + 0.5

lin, lout

Input or Output Current (DC or Transient),


per Pin

10

mA

PD

Power Dissipation, per Package

500

mW

Tstg

Storage Temperature

65 to + 150

_C

TL
Lead Temperature (8Second Soldering)
260
_C
* Maximum Ratings are those values beyond which damage to the device may occur.
Temperature Derating:
Plastic P and D/DW Packages: 7.0 mW/_C From 65_C To 125_C
Ceramic L Packages: 12 mW/_C From 100_C To 125_C

MC14072B

Dual 4-Input OR Gate

MC14073B

Triple 3-Input AND Gate

MC14075B

Triple 3-Input OR Gate

MC14078B

8-Input NOR Gate

MC14081B

Quad 2-Input AND Gate

MC14082B

Dual 4-Input AND Gate

This device contains protection circuitry to guard against damage


due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open.
REV 3
1/94

MOTOROLA CMOS LOGIC DATA


Motorola, Inc. 1995

MC14001B
7

LOGIC DIAGRAMS
NOR

NAND

OR

AND

MC14001B
Quad 2Input NOR Gate

MC14011B
Quad 2Input NAND Gate

MC14071B
Quad 2Input OR Gate

MC14081B
Quad 2Input AND Gate

1
2

1
2

1
2

5
6

5
6

5
6

5
6

8
9

10

8
9

10

8
9

10

8
9

10

12
13

2 INPUT

1
2

11

12
13

11

12
13

11

12
13

11

3 INPUT

MC14025B
Triple 3Input NOR Gate
1
2
8
3
4
5
11
12
13

10

4 INPUT

MC14002B
Dual 4Input NOR Gate
2
3
4
5
9
10
11
12

13
NC = 6, 8

MC14023B
Triple 3Input NAND Gate
1
2
8
3
4
5
11
12
13

8 INPUT

MC14001B
8

10

2
3
4
5
9
10
11
12

13
NC = 6, 8

1
2
8
3
4
5
11
12
13

10

MC14072B
Dual 4Input OR Gate
2
3
4
5
9
10
11
12

13
NC = 6, 8

MC14073B
Triple 3Input AND Gate
1
2
8
3
4
5
11
12
13

10

MC14082B
Dual 4Input AND Gate
2
3
4
5
9
10
11
12

13
NC = 6, 8

MC14068B
8Input NAND Gate

13

NC = 6, 8

MC14012B
Dual 4Input NAND Gate

MC14078B
8Input NOR Gate
2
3
4
5
9
10
11
12

MC14075B
Triple 3Input OR Gate

2
3
4
5
9
10
11
12

VDD = PIN 14
VSS = PIN 7
FOR ALL DEVICES
13

NC = 6, 8

MOTOROLA CMOS LOGIC DATA

PIN ASSIGNMENTS
MC14001B
Quad 2Input NOR Gate

MC14002B
Dual 4Input NOR Gate

IN 1A

14

VDD

OUTA

14

VDD

MC14011B
Quad 2Input NAND Gate

MC14012B
Dual 4Input NAND Gate

IN 1A

14

VDD

OUTA

14

VDD

IN 2A

13

IN 2D

IN 1A

13

OUTB

IN 2A

13

IN 2D

IN 1A

13

OUTB

OUTA

12

IN 1D

IN 2A

12

IN 4B

OUTA

12

IN 1D

IN 2A

12

IN 4B

OUTB

11

OUTD

IN 3A

11

IN 3B

OUTB

11

OUTD

IN 3A

11

IN 3B

IN 1B

10

OUTC

IN 4A

10

IN 2B

IN 1B

10

OUTC

IN 4A

10

IN 2B

IN 2B

IN 2C

NC

IN 1B

IN 2B

IN 2C

NC

IN 1B

VSS

IN 1C

VSS

NC

VSS

IN 1C

VSS

NC

MC14023B
Triple 3Input NAND Gate

MC14025B
Triple 3Input NOR Gate

MC14068B
8Input NAND Gate

MC14071B
Quad 2Input OR Gate
IN 1A

14

VDD

IN 1A

14

VDD

IN 1A

14

VDD

NC

14

VDD

IN 2A

13

IN 3C

IN 2A

13

IN 3C

IN 1

13

OUT

IN 2A

13

IN 2D

IN 1B

12

IN 2C

IN 1B

12

IN 2C

IN 2

12

IN 8

OUTA

12

IN 1D

IN 2B

11

IN 1C

IN 2B

11

IN 1C

IN 3

11

IN 7

OUTB

11

OUTD

IN 3B

10

OUTC

IN 3B

10

OUTC

IN 4

10

IN 6

IN 1B

10

OUTC

OUTB

OUTA

OUTB

OUTA

NC

IN 5

IN 2B

IN 2C

VSS

IN 3A

VSS

IN 3A

VSS

NC

VSS

IN 1C

MC14072B
Dual 4Input OR Gate

MC14073B
Triple 3Input AND Gate

MC14075B
Triple 3Input OR Gate

MC14078B
8Input NOR Gate

OUTA

14

VDD

IN 1A

14

VDD

IN 1A

14

VDD

NC

14

VDD

IN 1A

13

OUTB

IN 2A

13

IN 3C

IN 2A

13

IN 3C

IN 1

13

OUT

IN 2A

12

IN 4B

IN 1B

12

IN 2C

IN 1B

12

IN 2C

IN 2

12

IN 8

IN 3A

11

IN 3B

IN 2B

11

IN 1C

IN 2B

11

IN 1C

IN 3

11

IN 7

IN 4A

10

IN 2B

IN 3B

10

OUTC

IN 3B

10

OUTC

IN 4

10

IN 6

NC

IN 1B

OUTB

OUTA

OUTB

OUTA

NC

IN 5

VSS

NC

VSS

IN 3A

VSS

IN 3A

VSS

NC

MC14081B
Quad 2Input AND Gate

MC14082B
Dual 4Input AND Gate

IN 1A

14

VDD

OUTA

14

VDD

IN 2A

13

IN 2D

IN 1A

13

OUTB

OUTA

12

IN 1D

IN 2A

12

IN 4B

OUTB

11

OUTD

IN 3A

11

IN 3B

IN 1B

10

OUTC

IN 4A

10

IN 2B

IN 2B

IN 2C

NC

IN 1B

VSS

IN 1C

VSS

NC

MOTOROLA CMOS LOGIC DATA

NC = NO CONNECTION

MC14001B
9

MC14001B
10

MOTOROLA CMOS LOGIC DATA

IT(CL) = IT(50 pF) + (CL 50) Vfk


where: IT is in A (per package), CL in pF, V = (VDD VSS) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gates per
package.

To calculate total supply current at loads other than 50 pF:

** The formulas given are for the typical characteristics only at 25_C.

#Data labelled Typ is not to be used for design purposes but is intended as an indication of the ICs potential performance.
Total Supply Current**
(Dynamic plus Quiescent,
Per Gate, CL = 50 pF)

IT = (0.3 A/kHz) f + IDD/N


IT = (0.6 A/kHz) f + IDD/N
IT = (0.9 A/kHz) f + IDD/N

0 Level

VOL

5.0
10
15

0.05
0.05
0.05

0
0
0

0.05
0.05
0.05

0.05
0.05
0.05

Vdc

1 Level

VOH

5.0
10
15

4.95
9.95
14.95

4.95
9.95
14.95

5.0
10
15

4.95
9.95
14.95

Vdc

5.0
10
15

1.5
3.0
4.0

2.25
4.50
6.75

1.5
3.0
4.0

1.5
3.0
4.0

5.0
10
15

3.5
7.0
11

3.5
7.0
11

2.75
5.50
8.25

3.5
7.0
11

5.0
5.0
10
15

3.0
0.64
1.6
4.2

2.4
0.51
1.3
3.4

4.2
0.88
2.25
8.8

1.7
0.36
0.9
2.4

IOL

5.0
10
15

0.64
1.6
4.2

0.51
1.3
3.4

0.88
2.25
8.8

0.36
0.9
2.4

mAdc

Input Current

Iin

15

0.1

0.00001

0.1

1.0

Adc

Input Capacitance
(Vin = 0)

Cin

5.0

7.5

pF

Quiescent Current
(Per Package)

IDD

5.0
10
15

0.25
0.5
1.0

0.0005
0.0010
0.0015

0.25
0.5
1.0

7.5
15
30

Adc

IT

5.0
10
15

(VOL = 0.4 Vdc)


(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)

Output Drive Current


(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)

Sink

Source

IOH

(VO = 0.5 or 4.5 Vdc)


(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)

Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)

1 Level

VIH

Symbol

Adc

mAdc

VIL

Vin = 0 or VDD

Output Voltage
Vin = VDD or 0

Characteristic

Vdc
Vdc

VDD
Vdc

Min

Max

Min

Typ #

Max

Min

Max

Unit

55_C

25_C

125_C

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

Revised January 1999

CD40106BC
Hex Schmitt Trigger
General Description

Features

The CD40106BC Hex Schmitt Trigger is a monolithic complementary MOS (CMOS) integrated circuit constructed
with N and P-channel enhancement transistors. The positive and negative-going threshold voltages, VT+ and VT,
show low variation with respect to temperature (typ
0.0005V/C at VDD = 10V), and hysteresis, VT+ VT 0.2
VDD is guaranteed.

s Wide supply voltage range:

All inputs are protected from damage due to static discharge by diode clamps to VDD and VSS.

s High noise immunity:

3V to 15V

0.7 VDD (typ.)

s Low power TTL compatibility:


Fan out of 2 driving 74L or 1 driving 74LS
0.4 VDD (typ.),

s Hysteresis:

0.2 VDD guaranteed


s Equivalent to MM74C14
s Equivalent to MC14584B

Ordering Code:
Package Number

Package Description

CD40106BCM

Order Number

M14A

14-Lead Small Outline integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow Body

CD40106BCN

N14A

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code.

Connection Diagram

Schematic Diagram

Pin Assignments for DIP and SOIC

Top View

1999 Fairchild Semiconductor Corporation

DS005985.prf

www.fairchildsemi.com

CD40106BC Hex Schmitt Trigger

October 1987

CD40106BC

Absolute Maximum Ratings(Note 1)

Recommended Operating
Conditions (Note 2)

(Note 2)
0.5 to +18 VDC

DC Supply Voltage (VDD)


Input Voltage (VIN)

DC Supply Voltage (VDD)

0.5 to VDD +0.5 VDC


65C to +150C

Storage Temperature Range (TS)

500 mW

Lead Temperature (TL)


(Soldering, 10 seconds)

40C to +85C

Note 1: Absolute Maximum Ratings are those values beyond which the
safety of the device cannot be guaranteed. They are not meant to imply
that the devices should be operated at these limits. The table of Recommended Operating Conditions and Electrical Characteristics provides
conditions for actual device operation.

700 mW

Small Outline

0 to VDD VDC

Operating Temperature Range (TA)

Power Dissipation (PD)


Dual-In-Line

3 to 15 VDC

Input Voltage (VIN)

Note 2: VSS = 0V unless otherwise specified.

260C

DC Electrical Characteristics (Note 3)


Symbol

Parameter

40C

Conditions

Min

Max

+25C
Min

Typ

+85C
Max

Min

Max

Units

4.0

4.0

30

8.0

8.0

60

VDD = 15V

Quiescent Device Current

VDD = 5V
VDD = 10V

IDD

16.0

16.0

120

LOW Level Output

|IO| < 1 A

Voltage

VDD = 5V

0.05

0.05

0.05

VDD = 10V

0.05

0.05

0.05

VDD = 15V

VOL

0.05

0.05

0.05

HIGH Level Output

|IO| < 1 A

Voltage

VDD = 5V

4.95

4.95

4.95

VDD = 10V

9.95

9.95

10

0.95

VDD = 15V

VOH

14.95

14.95

15

14.95

0.7

1.4

Negative-Going Threshold

VDD = 5V, VO = 4.5V

Voltage

VT

1.4

4.0

1.4

2.1

6.0

2.1

Positive-Going Threshold

VDD = 5V, VO = 0.5V

3.0

4.3

VDD = 10V, VO = 1V

6.0

VDD = 15V, VO = 1.5V


Hysteresis (VT+ VT)

VDD = 5V

Voltage

2.0

0.7

3.2

4.0

5.0

6.0

3.0

3.6

8.6

6.0

9.0

12.9

1.0

3.6

VDD = 10V

2.0

VDD = 15V

3.0

LOW Level Output

VDD = 5V, VO = 0.4V

0.52

0.44

0.88

0.36

mA

Current (Note 3)

IOL

VDD = 10V, VO = 9V

Voltage
VH

2.0

VDD = 15V, VO = 13.5V


VT+

0.7

2.0

1.4

4.0

2.1

6.0

4.3

3.0

4.3

6.8

8.6

6.0

8.6

9.0

10.0

12.9

9.0

12.9

1.0

2.2

3.6

1.0

3.6

7.2

2.0

3.6

7.2

2.0

7.2

10.8

3.0

5.0

10.8

3.0

10.8

VDD = 10V, VO = 0.5V

1.3

1.1

2.25

0.9

mA
mA

VDD = 15V, VO = 1.5V

3.6

3.0

8.8

2.4

HIGH Level Output

VDD = 5V, VO = 4.6V

0.52

0.44

0.88

0.36

mA

Current (Note 3)

VDD = 10V, VO = 9.5V

1.3

1.1

2.25

0.9

mA

VDD = 15V, VO = 13.5V

IOH

3.6

Input Current

3.0

8.8

2.4

mA

VDD = 15V, VIN = 0V

0.30

105

0.30

1.0

VDD = 15V, VIN = 15V

IIN

0.30

105

0.30

1.0

Note 3: IOH and IOL are tested one output at a time.

www.fairchildsemi.com

TA = 25C, CL = 50 pF, RL = 200k, tr and tf = 20 ns, unless otherwise specified


Symbol

Max

VDD = 5V

220

400

ns

VDD = 10V

80

200

ns

VDD = 15V

70

160

ns

VDD = 5V

100

200

ns

VDD = 10V

tTHL or tTLH

Typ

Propagation Delay Time from


Input to Output

tPHL or tPLH

Parameter

50

100

ns

Transition Time

Conditions

Min

Units

VDD = 15V

40

80

ns

CIN

Average Input Capacitance

Any Input

7.5

pF

CPD

Power Dissipation Capacity

Any Gate (Note 5)

14

pF

Note 4: AC Parameters are guaranteed by DC correlated testing.


Note 5: CPD determines the no load ac power consumption of any CMOS device. For complete explanation see 74C Family Characteristics Application Note,
AN-90.

Switching Time Waveforms

tr = tf = 20 ns

Typical Applications
Low Power Oscillator

Note: The equations assume


t1 + t2 >> tPHL + tPLH

www.fairchildsemi.com

CD40106BC

AC Electrical Characteristics (Note 4)

CD40106BC

Typical Performance Characteristics


Guaranteed
Trip Point Range

Typical Transfer
Characteristics

Guaranteed

www.fairchildsemi.com

Revised January 1999

CD4017BC CD4022BC
Decade Counter/Divider with 10 Decoded Outputs
Divide-by-8 Counter/Divider with 8 Decoded Outputs
General Description

Features

The CD4017BC is a 5-stage divide-by-10 Johnson counter


with 10 decoded outputs and a carry out bit.

s Wide supply voltage range: 3.0V to 15V

The CD4022BC is a 4-stage divide-by-8 Johnson counter


with 8 decoded outputs and a carry-out bit.

s Low power Fan out of 2 driving 74L

These counters are cleared to their zero count by a logical


1 on their reset line. These counters are advanced on the
positive edge of the clock signal when the clock enable signal is in the logical 0 state.
The configuration of the CD4017BC and CD4022BC permits medium speed operation and assures a hazard free
counting sequence. The 10/8 decoded outputs are normally in the logical 0 state and go to the logical 1 state
only at their respective time slot. Each decoded output
remains high for 1 full clock cycle. The carry-out signal
completes a full cycle for every 10/8 clock input cycles and
is used as a ripple carry signal to any succeeding stages.

s High noise immunity:

0.45 VDD (typ.)

TTL compatibility: or 1 driving 74LS


s Medium speed operation: 5.0 MHz (typ.)
with 10V VDD
s Low power: 10 W (typ.)
s Fully static operation

Applications
Automotive
Instrumentation
Medical electronics
Alarm systems
Industrial electronics
Remote metering

Ordering Code:
Order Number

Package Number

Package Description

CD4017BCM

M16A

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

CD4017BCSJ

M16D

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

CD4017BCN

N16E

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

CD4022BCM

M16A

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

CD4022BCN

N16E

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code.

Connection Diagrams
Pin Assignments for DIP, SOIC and SOP
CD4017B

Pin Assignments for DIP and SOIC


CD4022B

Top View

Top View

1999 Fairchild Semiconductor Corporation

DS005950.prf

www.fairchildsemi.com

CD4017BC CD4022BC Decade Counter/Divider with 10 Decoded Outputs Divide-by-8 Counter/Divider with 8
Decoded Outputs

October 1987

CD4017BC CD4022BC

Logic Diagrams
CD4017B

Terminal No. 8 = GND


Terminal No. 16 = VDD

CD4022B

Terminal No. 16 = VDD


Terminal No. 8 = GND

www.fairchildsemi.com

Recommended Operating
Conditions (Note 2)

DC Supply Voltage (VDD )


Input Voltage (VIN)

0.5 VDC to +18 VDC

Input Voltage (VIN)

65C to +150C

Storage Temperature (TS)

500 mW

Lead Temperature (TL)


(Soldering, 10 seconds)

Symbol

Note 2: VSS = 0V unless otherwise specified.

260C

DC Electrical Characteristics
Parameter

40C to +85C

Note 1: Absolute Maximum Ratings are those values beyond which the
safety of the device cannot be guaranteed, they are not meant to imply that
the devices should be operated at these limits. The table of Recommended Operating Conditions and Electrical Characteristics provides
conditions for actual device operation.

700 mW

Small Outline

0 to VDD VDC

Operating Temperature Range (TA)

Power Dissipation (PD)


Dual-In-Line

+3 VDC to +15 VDC

DC Supply Voltage (VDD)

0.5 VDC to VDD +0.5 VDC

(Note 2)
40C

Conditions

Min

Max

+25
Min

+85C

Typ

Max

Min

Max

Units

Quiescent Device

VDD = 5V

20

0.5

20

150

Current

VDD = 10V

40

1.0

40

300

VDD = 15V

IDD

80

5.0

80

600

LOW Level

|IO| < 1.0 A

Output Voltage

VDD = 5V

0.05

0.05

0.05

VDD = 10V

0.05

0.05

0.05

VDD = 15V

VOL

0.05

0.05

0.05

HIGH Level

|IO| < 1.0 A

Output Voltage

VDD = 5V

4.95

4.95

4.95

VDD = 10V

9.95

9.95

10

9.95

VDD = 15V

VOH

14.95

14.95

15

14.95

LOW Level

|IO| < 1.0 A

Input Voltage

VDD = 5V, VO = 0.5V or 4.5V

1.5

1.5

1.5

VDD = 10V, VO = 1.0V or 9.0V

3.0

3.0

3.0

VDD = 15V, VO = 1.5V or 13.5V

VIL

4.0

4.0

4.0

HIGH Level

|IO| < 1.0 A

Input Voltage

VDD = 5V, VO = 0.5V or 4.5V

3.5

3.5

3.5

VDD = 10V, VO = 1.0V or 9.0V

7.0

7.0

7.0

VDD = 15V, VO = 1.5V or 13.5V

VIH

11.0

11.0

11.0

VDD = 5V, VO = 0.4V

0.52

0.44

0.88

0.36

mA

VDD = 10V, VO = 0.5V

1.3

1.1

2.25

0.9

mA

VDD = 15V, VO = 1.5V

3.6

3.0

8.8

2.4

mA

HIGH Level Output

VDD = 5V, VO = 4.6V

0.2

0.16

0.36

0.12

mA

Current (Note 3)

VDD = 10V, VO = 9.5V

0.5

0.4

0.9

0.3

mA

VDD = 15V, VO = 13.5V

IOH

LOW Level Output


Current (Note 3)

IOL

1.4

Input Current

1.2

3.5

1.0

mA

VDD = 15V, VIN = 0V

0.3

105

0.3

1.0

VDD = 15V, VIN = 15V

IIN

0.3

105

0.3

1.0

Note 3: IOL and IOH are tested one output at a time.

www.fairchildsemi.com

CD4017BC CD4022BC

Absolute Maximum Ratings(Note 1)


(Note 2)

CD4017BC CD4022BC

AC Electrical Characteristics

(Note 4)

TA= 25C, CL= 50 pF, RL= 200k, trCL and tfCL= 20 ns, unless otherwise specified
Symbol

Parameter

Conditions

Min

Typ

Max

Units

CLOCK OPERATION
VDD = 5V

800

ns

160

320

ns

VDD = 15V

130

250

ns

VDD = 5V

240

480

ns

85

170

ns

VDD = 15V

70

140

ns

VDD = 5V

500

1000

ns

VDD = 10V

200

400

ns

VDD = 15V

Carry Out Line

415

VDD = 10V

tPHL, tPLH Propagation Delay Time Carry Out Line

160

320

ns

VDD = 10V
Decode Out Lines

CL = 15 pF

tTLH, tTHL Transition Time Carry Out and Decode Out Lines
VDD = 5V

360

ns

100

180

ns

VDD = 15V

80

130

ns

VDD = 5V

100

200

ns

VDD = 10V

50

100

ns

VDD = 15V

tTHL

200

VDD = 10V

tTLH

40

80

ns

VDD = 5V

1.0

MHz

Respect to Carry

2.5

MHz

VDD = 15V

Maximum Clock Frequency

Measured with

VDD = 10V

fCL

Output Line

3.0

MHz

VDD = 5V

250

ns

45

90

ns

VDD = 15V

Minimum Clock Pulse Width

125

VDD = 10V

tWL, tWH

35

ns

20

15

VDD = 15V

Clock Rise and Fall Time

70

VDD = 5V
VDD = 10V

trCL, tfCL

VDD = 5V

CIN

240

ns

40

80

ns

VDD = 15V

32

65

ns

Minimum Clock Inhibit Data Setup Time

120

VDD = 10V

tSU

7.5

pF

Average Input Capacitance

Note 4: AC Parameters are guaranteed by DC correlated testing.

AC Electrical Characteristics

(Note 4)

TA = 25C, CL = 50 pF, RL = 200k, trCL and tfCL = 20 ns, unless otherwise specified
Symbol

Parameter

Conditions

Min

Typ

Max

Units

RESET OPERATION
tPHL, tPLH

Propagation Delay Time


415

800

ns

160

320

ns

VDD = 15V
Carry Out Line

VDD = 5V
VDD = 10V

Carry Out Line

130

250

ns

VDD = 5V

240

480

ns

85

170

ns

VDD = 10V

CL = 15 pF

VDD = 15V

70

140

ns

VDD = 5V

500

1000

ns

VDD = 10V

200

400

ns

VDD = 15V

160

320

ns

Minimum Reset

VDD = 5V

200

400

ns

Pulse Width

VDD = 10V

70

140

ns

Decode Out Lines

tW

VDD = 15V

55

110

ns

Minimum Reset

VDD = 5V

75

150

ns

Removal Time

VDD = 10V

30

60

ns

VDD = 15V

tREM

25

50

ns

www.fairchildsemi.com

CD4017BC CD4022BC

Timing Diagrams
CD4017B

CD4022B

www.fairchildsemi.com

Revised May 1999

CD4047BC
Low Power Monostable/Astable Multivibrator
s True and complemented buffered outputs

General Description
The CD4047B is capable of operating in either the
monostable or astable mode. It requires an external capacitor (between pins 1 and 3) and an external resistor
(between pins 2 and 3) to determine the output pulse width
in the monostable mode, and the output frequency in the
astable mode.
Astable operation is enabled by a high level on the astable
input or low level on the astable input. The output frequency (at 50% duty cycle) at Q and Q outputs is determined by the timing components. A frequency twice that of
Q is available at the Oscillator Output; a 50% duty cycle is
not guaranteed.
Monostable operation is obtained when the device is triggered by LOW-to-HIGH transition at + trigger input or
HIGH-to-LOW transition at trigger input. The device can
be retriggered by applying a simultaneous LOW-to-HIGH
transition to both the + trigger and retrigger inputs.
A high level on Reset input resets the outputs Q to LOW, Q
to HIGH.

s Only one external R and C required


MONOSTABLE MULTIVIBRATOR FEATURES
s Positive- or negative-edge trigger
s Output pulse width independent of trigger pulse duration
s Retriggerable option for pulse width expansion
s Long pulse widths possible using small RC components
by means of external counter provision
s Fast recovery time essentially independent of pulse
width
s Pulse-width accuracy
approaching 100%

maintained

at

duty

cycles

ASTABLE MULTIVIBRATOR FEATURES


s Free-running or gatable operating modes
s 50% duty cycle
s Oscillator output available
s Good astable frequency stability
typical= 2% + 0.03%/C @ 100 kHz

Features

frequency= 0.5% + 0.015%/C @ 10 kHz

s Wide supply voltage range:

3.0V to 15V

s High noise immunity: 0.45 VDD (typ.)


s Low power TTL compatibility: Fan out of 2 driving 74L
or 1 driving 74LS

deviation (circuits trimmed to frequency VDD = 10V


10%)

Applications
Frequency discriminators
Timing circuits

SPECIAL FEATURES
s Low power consumption: special CMOS oscillator
configuration

Time-delay applications

s Monostable (one-shot) or astable (free-running)


operation

Frequency multiplication

Envelope detection
Frequency division

Ordering Code:
Order Number

Package Number

Package Description

CD4047BCM

M14A

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow

CD4047BCN

N14A

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code.

1999 Fairchild Semiconductor Corporation

DS005969.prf

www.fairchildsemi.com

CD4047BC Low Power Monostable/Astable Multivibrator

October 1987

CD4047BC

Connection Diagram
Pin Assignments for SOIC and DIP

Top View

Function Table
Terminal Connections
To VDD

Function

Output Pulse

To VSS

From

Input Pulse
To

Typical Output
Period or
Pulse Width

Astable Multivibrator
Free-Running

4, 5, 6, 14

7, 8, 9, 12

10, 11, 13

tA(10, 11) = 4.40 RC

True Gating

4, 6, 14

7, 8, 9, 12

10, 11, 13

tA (13) = 2.20 RC

Complement Gating

6, 14

5, 7, 8, 9, 12

10, 11, 13

Positive-Edge Trigger

4, 14

5, 6, 7, 9, 12

10, 11

Negative-Edge Trigger

4, 8, 14

5, 7, 9, 12

10, 11

Retriggerable

4, 14

5, 6, 7, 9

8, 12

10, 11

Monostable Multivibrator

External Countdown (Note 1) 14

5, 6, 7, 8, 9, 12

Figure 1

Figure 1

Note 1: External resistor between terminals 2 and 3. External capacitor between terminals 1 and 3.

Typical Implementation of External Countdown Option

tEXT = (N 1) tA + (tM + tA/2)

FIGURE 1.

www.fairchildsemi.com

tM (10, 11) = 2.48 RC


Figure 1

CD4047BC

Block Diagram

Logic Diagram

*Special input protection circuit to permit larger input-voltage swings.

www.fairchildsemi.com

CD4047BC

Absolute Maximum Ratings(Note 2)

Recommended Operating
Conditions (Note 3)

(Note 3)
0.5V to +18VDC

DC Supply Voltage (VDD)


Input Voltage (VIN)

DC Supply Voltage (VDD)

0.5V to VDD +0.5VDC


65C to +150C

Storage Temperature Range (TS)

500 mW

Lead Temperature (TL)


(Soldering, 10 seconds)

40C to +85C

Note 2: Absolute Maximum Ratings are those values beyond which the
safety of the device cannot be guaranteed. They are not meant to imply
that the devices should be operated at these limits. The table of Recommended Operating Conditions and Electrical Characteristics provides
conditions for actual device operation.

700 mW

Small Outline

0 to VDD VDC

Operating Temperature Range (TA)

Power Dissipation (PD)


Dual-In-Line

3V to 15VDC

Input Voltage (VIN)

Note 3: VSS = 0V unless otherwise specified.

260C

DC Electrical Characteristics (Note 3)


Symbol

Parameter

40C

Conditions

Min

Max

25C
Min

Typ

85C
Max

Min

Max

Units

VOL

LOW Level Output Voltage

20

20

150

40

40

300

VDD = 15V

Quiescent Device Current

VDD = 5V
VDD = 10V

IDD

80

80

600

|IO| < 1 A
VDD = 5V

HIGH Level Output Voltage

0.05

0.05

0.05

0.05

0.05

VDD = 15V
VOH

0.05

VDD = 10V

0.05

0.05

0.05

|IO| < 1 A
VDD = 5V

4.95

4.95

4.95

VDD = 10V

9.95

9.95

10

9.95

VDD = 15V
LOW Level Input Voltage

14.95

14.95

15

14.95

VDD = 5V, VO = 0.5V or 4.5V

1.5

2.25

1.5

1.5

VDD = 10V, VO = 1V or 9V

VIL

3.0

4.5

3.0

3.0

6.75

4.0

4.0

VDD = 15V, VO = 1.5V or 13.5V


HIGH Level Input Voltage

4.0

VDD = 5V, VO = 0.5V or 4.5V

3.5

3.5

2.75

3.5

VDD = 10V, VO = 1V or 9V

VIH

7.0

7.0

5.5

7.0

VDD = 15V, VO = 1.5V or 13.5V


IOL

LOW Level Output Current

11.0

11.0

8.25

11.0

VDD = 5V, VO = 0.4V

0.52

0.44

0.88

0.36

mA
mA

HIGH Level Output Current


(Note 4)

1.3

1.1

2.25

0.9

3.6

3.0

8.8

2.4

mA

VDD = 5V, VO = 4.6V

0.52

0.44

0.88

0.36

mA

VDD = 10V, VO = 9.5V

1.3

1.1

2.25

0.9

mA

VDD = 15V, VO = 13.5V

IOH

VDD = 10V, VO = 0.5V


VDD = 15V, VO = 1.5V

(Note 4)

3.6

3.0

8.8

2.4

Input Current

mA

VDD = 15V, VIN = 0V

0.3

105

0.3

1.0

VDD = 15V, VIN = 15V

IIN

0.3

105

0.3

1.0

Note 4: IOH and IOL are tested one output at a time.

www.fairchildsemi.com

(Note 5)

Symbol

Typ

Max

Units

Propagation Delay Time Astable,

VDD = 5V

200

400

ns

Astable to Osc Out

VDD = 10V

100

200

ns

VDD = 15V

tPHL, tPLH

Parameter

Conditions

Min

80

160

ns

tWL, tWH

Minimum Input Pulse Duration

ns

300

600

ns

240

480

ns

VDD = 5V

300

600

ns

175

300

ns

150

250

ns

VDD = 5V

300

600

ns

125

250

ns

100

200

ns

VDD = 5V

100

200

ns

50

100

ns

VDD = 15V

Transition Time Q, Q, Osc Out

1200

VDD = 10V

tTHL, tTLH

700

VDD = 15V

Reset to Q, Q

ns

VDD = 5V

VDD = 10V

tPHL, tPLH

400

VDD = 15V

+ Trigger, Retrigger to Q

ns

200

VDD = 10V

tPHL, tPLH

ns

500

VDD = 15V

+ Trigger, Trigger to Q

900

250

VDD = 10V

tPHL, tPLH

550

VDD = 15V

Astable, Astable to Q, Q

VDD = 5V
VDD = 10V

tPHL, tPLH

40

80

ns

Any Input
VDD = 5V

500

1000

ns

VDD = 10V

200

400

ns

VDD = 15V

160

320

ns

VDD = 5V

15

VDD = 10V

VDD = 15V
CIN

+ Trigger, Retrigger, Rise and


Fall Time

tRCL, tFCL

7.5

pF

Average Input Capacitance

Any Input

Note 5: AC Parameters are guaranteed by DC correlated testing.

www.fairchildsemi.com

CD4047BC

AC Electrical Characteristics

TA = 25C, CL = 50 pF, RL = 200k, input tr = tf = 20 ns, unless otherwise specified.

CD4047BC

Typical Performance Characteristics


Typical Q, Q, Osc Out Period Accuracy vs
Supply Voltage (Astable Mode Operation)

f Q, Q
A

1000 kHz

B
C

Typical Q, Q, Pulse Width Accuracy vs


Supply Voltage Monostable Mode Operation

22k

100 kHz

22k
220k

1 kHz

220k

100 Hz

2.2M

7 s

22k

100 pF

60 s

220k

100 pF

550 s

220k

1000 pF

1000 pF

10 pF

1000 pF

5.5 ms

2.2M

1000 pF

Typical Q, Q and Osc Out Period Accuracy


vs Temperature Astable Mode Operation

f Q, Q
A

1000 kHz

B
C
D

Typical Q and Q Pulse Width Accuracy vs


Temperature Monostable Mode Operation

tM

2 s

22k

10 pF

7 s

22k

100 pF

60 s

220k

100 pF

550 s

220k

1000 pF

22k

10 pF

100 kHz

22k

100 pF

10 kHz

220k

100 pF

1 kHz

220k

1000 pF

www.fairchildsemi.com

22k

100 pF

2 s

100 pF

10 kHz

tM

10 pF

CD4047BC

Timing Diagrams
Astable Mode

Monostable Mode

Retrigger Mode

www.fairchildsemi.com

Revised January 1999

CD4511BC
BCD-to-7 Segment Latch/Decoder/Driver
General Description
The CD4511BC BCD-to-seven segment latch/decoder/
driver is constructed with complementary MOS (CMOS)
enhancement mode devices and NPN bipolar output drivers in a single monolithic structure. The circuit provides the
functions of a 4-bit storage latch, an 8421 BCD-to-seven
segment decoder, and an output drive capability. Lamp test
(LT), blanking (BI), and latch enable (LE) inputs are used to
test the display, to turn-off or pulse modulate the brightness
of the display, and to store a BCD code, respectively. It can
be used with seven-segment light emitting diodes (LED),
incandescent, fluorescent, gas discharge, or liquid crystal
readouts either directly or indirectly.

Applications include instrument (e.g., counter, DVM, etc.)


display driver, computer/calculator display driver, cockpit
display driver, and various clock, watch, and timer uses.

Features
s Low logic circuit power dissipation
s High current sourcing outputs (up to 25 mA)
s Latch storage of code
s Blanking input
s Lamp test provision
s Readout blanking on all illegal input combinations
s Lamp intensity modulation capability
s Time share (multiplexing) facility
s Equivalent to Motorola MC14511

Ordering Code:
Order Number

Package Number

Package Description

CD4511BCWM

M16B

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

CD4511BCN

N16E

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending suffix letter X to the ordering code.

Connection Diagrams

Segment Identification

Pin Assignments for SOIC and DIP

Top View

1999 Fairchild Semiconductor Corporation

DS005991.prf

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CD4511BC BCD-to-7 Segment Latch/Decoder/Driver

October 1987

CD4511BC

Truth Table
Inputs

Outputs

LE

BI

LT

Display

X = Dont Care
*Depends upon the BCD code applied during the 0 to 1 transition of LE.

Display

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DC Supply Voltage (VDD)


Input Voltage (VIN)
Storage Temperature Range (TS)

Recommended Operating
Conditions

0.5V to +18V
0.5V to VDD +0.5V

DC Supply Voltage (VDD)

Power Dissipation (PD)

3V to 15V

Input Voltage (VIN)

65C to +150C

0V to VDD

Operating Temperature Range (TA)

Dual-In-Line
Small Outline

40C to +85C

700 mW
500 mW

Lead Temperature (TL)

Note 1: Devices should not be connected with power on.

(Soldering, 10 seconds)

260C

DC Electrical Characteristics
Symbol

Parameter

40C

Conditions

Min

+25C

Max

Min

Typ

+85C
Max

Min

Max

Units

Quiescent

VDD = 5V

20

20

150

Supply Current

VDD = 10V

40

40

300

VDD = 15V

IDD

80

80

600

0.01

0.01

0.05

VDD = 10V

0.01

0.01

0.05

VDD = 15V

0.01

0.05

Output Voltage

VDD = 5V

4.1

4.1

4.57

4.1

Logical 1

VDD = 10V

9.1

9.1

9.58

9.1

Level

VDD = 15V

14.1

14.1

14.59

14.1

LOW Level

VDD = 5V, VOUT = 3.8V or 0.5V

Input Voltage

VIL

VDD = 5V

Level
VOH

Output Voltage
Logical 0

VOL

0.01

1.5

1.5

1.5

VDD = 10V, VOUT = 8.8V or 1.0V

3.0

3.0

3.0

VDD = 15V, VOUT = 13.8V or 1.5V

4.0

4.0

4.0

HIGH Level

VDD = 5V, VOUT = 0.5V or 3.8V

3.5

3.5

3.5

Input Voltage

VIH

VDD = 10V, VOUT = 1.0V or 8.8V

7.0

7.0

7.0

VDD = 15V, V OUT = 1.5V or 13.8V

11.0

11.0

11.0

Output

VDD = 5V, IOH = 0 mA

4.1

4.1

4.57

4.1

(Source) Drive

VDD = 5V, IOH = 5 mA

Voltage

VOH

VDD = 5V, IOH = 10 mA

3.3

2.5

9.1

4.24
3.6

3.6

2.8

2.8

3.75

9.1

9.1

9.58

8.75

8.75

4.12

9.17

VDD = 5V, IOH = 15 mA

3.94

VDD = 5V, IOH = 20 mA


VDD = 5V, IOH = 25 mA

3.54

VDD = 10V, IOH = 0 mA


VDD = 10V, IOH = 5 mA

9.26

VDD = 10V, IOH = 10 mA


VDD = 10V, I OH = 15 mA

V
8.45

7.8

9.04

VDD = 10V, IOH = 20 mA

8.1

8.1

14.1

14.1

8.9
14.59

VDD = 10V, IOH = 25 mA

8.75

VDD = 15V, IOH = 0 mA


VDD = 15V, I OH = 5 mA

V
14.1

13.45

14.27

VDD = 15V, IOH = 10 mA

13.75

13.75

13.1

13.1

14.18
13.95

VDD = 15V, IOH = 15 mA

14.07

VDD = 15V, IOH = 20 mA


VDD = 15V, I OH = 25 mA

V
12.8

0.36

mA

13.8

LOW Level

Output Current
IIN

Input Current

VDD = 5V, VOL = 0.4V

0.52

0.44

0.88

VDD = 10V, VOL = 0.5V

1.3

1.1

2.25

0.9

mA

VDD = 15V, VOL = 1.5V

IOL

3.6

3.0

8.8

2.4

mA

VDD = 15V, VIN = 0V

0.30

VDD = 15V, VIN = 15V

0.30

105 0.30

1.0

105

1.0

0.30

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CD4511BC

Absolute Maximum Ratings(Note 1)

CD4511BC

AC Electrical Characteristics

(Note 2)

TA = 25C and CL = 50 pF, typical temperature coefficient for all values of VDD = 0.3%/C
Typ

Max

Units

CIN

Symbol

Input Capacitance

VIN = 0

5.0

7.5

pF

tr

Output Rise Time

VDD = 5V

40

80

ns

(Figure 1a)

VDD = 10V

30

60

ns

VDD = 15V

25

50

ns

Output Fall Time

VDD = 5V

125

250

ns

(Figure 1a)

VDD = 10V

75

150

ns

VDD = 15V

65

130

ns

Turn-Off Delay Time

VDD = 5V

640

1280

ns

(Data) (Figure 1a)

VDD = 10V

250

500

ns

VDD = 15V

175

350

ns

Turn-On Delay Time

VDD = 5V

720

1440

ns

(Data) (Figure 1a)

VDD = 10V

290

580

ns

VDD = 15V

195

400

ns

Turn-Off Delay Time

VDD = 5V

320

640

ns

(Blank) (Figure 1a)

VDD = 10V

130

260

ns

VDD = 15V

100

200

ns

Turn-On Delay Time

VDD = 5V

485

970

ns

(Blank) (Figure 1a)

VDD = 10V

200

400

ns

VDD = 15V

160

320

ns

VDD = 5V

313

625

ns

tf

tPLH

tPHL

tPLH

tPHL

tPLH

Parameter

Turn-Off Delay Time

Conditions

Min

VDD = 10V

125

250

ns

VDD = 15V

90

180

ns

Turn-On Delay Time

VDD = 5V

313

625

ns

(Lamp Test) (Figure 1 a)

VDD = 10V

125

250

ns

VDD = 15V

90

180

ns

(Lamp Test) (Figure 1a)


tPHL

180

90

ns

VDD = 10V

76

38

ns

40

20

ns

Hold Time

VDD = 5V

90

ns

(Figure 1b)

VDD = 10V

38

ns

VDD = 15V

20

ns

Minimum Latch Enable

VDD = 5V

520

260

ns

Pulse Width (Figure 1 c)

VDD = 10V

220

110

ns

VDD = 15V

PWLE

VDD = 5V
VDD = 15V

tHOLD

Setup Time
(Figure 1b)

tSETUP

130

65

ns

Note 2: AC Parameters are guaranteed by DC correlated testing.

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CD4511BC

Switching Time Waveforms

FIGURE 1.

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CD4511BC

Typical Applications
Light Emitting Diode (LED) Readout

Gas Discharge Readout

Liquid Crystal (LC) Readout

Direct DC drive of LCs not recommended for life of LC readouts.

Fluorescent Readout

Incandescent Readout

**A filament pre-warm resistor is recommended to reduce filament thermal


shock and increase the effective cold resistance of the filament.

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