Sie sind auf Seite 1von 128

MSP430 MSP430

Architecture
Microcontroller characteristics
Integration: Able to implement a whole design onto a single
chip. chip.
Cost: Are usually low-cost devices (a few $ each);
Clock frequency: Compared with other devices
(microprocessors and DSPs), MCUs use a low clock frequency:
MCUs today run up to 100 MHz/100 MIPS (Million MCUs today run up to 100 MHz/100 MIPS (Million
Instructions Per Second).
Power consumption: Low power (battery operation); Power consumption: Low power (battery operation);
Bits: 4 bits (older devices) to 32 bits devices;
Memory: Limited available memory, usually less than 1 MByte;
Input/Output (I/O): Low to high (8 to 150) pin-out count
2
Input/Output (I/O): Low to high (8 to 150) pin out count.
MSP430 main characteristics (1/3)
Low power consumption:
0 1 A f RAM d t t ti 0.1 A for RAM data retention;
0.8 A for real-time clock mode operation;
250 A/MIPS during active operation. 250 A/MIPS during active operation.
Low operation voltage (from 1.8 V to 3.6 V);
< 1 s clock start-up;
< 50 nA port leakage;
Zero-power Brown-Out Reset (BOR).
3
MSP430 main characteristics (2/3)
On-chip analogue features:
10/12/16 bit A l t Di it l C t (ADC) 10/12/16-bit Analogue-to-Digital Converter (ADC);
12-bit dual Digital-to-Analogue Converter (DAC);
Comparator-gated timers; Comparator gated timers;
Operational Amplifiers (Op Amps);
Supply Voltage Supervisor (SVS).
16 bit RISC CPU:
Compact core design reduces power consumption and cost; Compact core design reduces power consumption and cost;
16-bit data bus;
27 core instructions; 27 core instructions;
7 addressing modes;
Extensive vectored-interrupt capability.
4
MSP430 main characteristics (3/3)
Flexibility:
Up to 256 kByte Flash; Up to 256 kByte Flash;
Up to 100 pins;
USART, I2C, Timers;
LCD driver;
Embedded emulation;
And many more peripherals modules And many more peripherals modules
Microcontroller performance:
Instruction processing on either bits, bytes or words
Reduced instructions set;
Compiler efficient; Compiler efficient;
Wide range of peripherals;
Flexible clock system.
5
MSP430 Architecture
Block diagram:
6
MSP430 architecture
MSP430X16X Architecture
I/O Port
ADC
ALU
DAC
Registers
Interrupts p
USARTx
TIMERs
DMA
HW Multiplier
Address Space
Mapped into a single, contiguous address space:
All i l di RAM Fl h/ROM i f ti All memory, including RAM, Flash/ROM, information
memory, special function registers (SFRs), and peripheral
registers.
Memory Map:
Memory Address Description Access
End: 0FFFFh
Start: 0FFE0h
Interrupt Vector Table
Word/Byte
End: 0FFDFh


Flash/ROM
0F800h
Word/Byte
0F800h
Start *:
01100h
y

010FFh
End *:
0107Fh Information Memory
Start: 01000h (Flash devices only)
Word/Byte
End: 0FFFh
Start: 0C00h
Boot Memory
(Flash devices only)
Word/Byte

09FFh
End *:
027Fh RAM
Start: 0200h
Word/Byte
End: 01FFh
Start: 0100h
16-bit Peripheral modules Word
End: 00FFh
Start: 0010h
8-bit Peripheral modules Byte
End: 000Fh
Start: 0000h
Special Function Registers Byte
9
Start: 0000h
Interrupt vector table
Mapped at the very end of memory space (upper 16
words of Flash/ROM): 0FFE0h - 0FFFEh (4xx devices);
Priority of the interrupt vector increases with the word
address.
10
Central Processing Unit (MSP430 CPU) (1/7)
RISC (Reduced Instructions Set Computing)
architecture:
Instructions are reduced to the basic ones (short set):
27 physical instructions;
24 emulated instructions. 24 emulated instructions.
This provides simpler and faster instruction decoding;
Interconnect by a using a common memory address bus
(MAB) and memory data bus (MDB) - Von Neumann
architecture: architecture:
Makes use of only one storage structure for data and
instructions sets.
The separation of the storage processing unit is implicit;
Instructions are treated as data (programmable)
11
Instructions are treated as data (programmable).
Central Processing Unit (MSP430 CPU) (2/7)
RISC (Reduced Instructions Set Computing) type
architecture: architecture:
Uses a 3-stage instruction pipeline containing:
Instruction decoding;
16 bit ALU 16 bit ALU;
4 dedicated-use registers;
12 working registers. g g
Address bus has 16 bit so it can address 65 kB (including
RAM + Flash + Registers); RAM + Flash + Registers);
Arithmetic Logic Unit (ALU):
Addition, subtraction, comparison and logical (AND, OR,
XOR) operations;
Operations can affect the overflow, zero, negative, and carry
12
p , , g , y
flags of the SR (Status Register).
Central Processing Unit (MSP430 CPU) (3/7)
Incorporates sixteen 16-bit registers:
4 registers (R0 R1 R2 and R3) have dedicated functions; 4 registers (R0, R1, R2 and R3) have dedicated functions;
12 register are working registers (R4 to R15) for general
use.
R0: Program Counter (PC):
Points to the next instruction to be read from memory and
executed by the CPU executed by the CPU.
R1: Stack Pointer (SP):
1st: stack can be used by user to store data for later use 1st: stack can be used by user to store data for later use
(instructions: store by PUSH, retrieve by POP);
2 d t k b d b b il f b ti 2nd: stack can be used by user or by compiler for subroutine
parameters (PUSH, POP in calling routine; addressed via offset
calculation on stack pointer (SP) in called subroutine);
13
Central Processing Unit (MSP430 CPU) (4/7)
R1: Stack Pointer (SP) (continued):
3 d d b b ti ll t t th t 3rd: used by subroutine calls to store the program counter
value for return at subroutine's end (RET);
4th: used by interrupt - system stores the actual PC value
first, then the actual status register content (on top of stack)
on return from interrupt (RETI) the system get the same on return from interrupt (RETI) the system get the same
status as just before the interrupt happened (as long as none
has changed the value on TOS) and the same program
counter value from stack counter value from stack.
14
Central Processing Unit (MSP430 CPU) (5/7)
R2: Status Register (SR):
St t t d t l bit Stores status and control bits;
System flags are changed automatically by the CPU;
Reserved bits are used to support the constant generator. Reserved bits are used to support the constant generator.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved for CG1 V SCG1 SCG0 OSCOFF CPUOFF GIE N Z C
Bit Description
8 V Overflow bit. V = 1 Result of an arithmetic operation overflows the signed-variable range.
7 SCG1 System clock generator 0. SCG1 = 1 DCO generator is turned off if not used for MCLK or SMCLK
6 SCG0 System clock generator 1. SCG0 = 1 FLL+ loop control is turned off
5 OSCOFF Oscillator Off. OSCOFF = 1 turns off LFXT1 when it is not used for MCLK or SMCLK
4 CPUOFF CPU off. CPUOFF = 1 disable CPU core.
3 GIE General interrupt enable. GIE = 1 enables maskable interrupts.
2 N Negative flag. N = 1 result of a byte or word operation is negative.
1 Z Zero flag. Z = 1 result of a byte or word operation is 0.
15
0 C Carry flag. C = 1 result of a byte or word operation produced a carry.
Central Processing Unit (MSP430 CPU) (6/7)
R2/R3: Constant Generator Registers (CG1/CG2):
Depending of the source-register addressing modes (As) Depending of the source-register addressing modes (As)
value, six constants can be generated without code word or
code memory access to retrieve them.
This is a very powerful feature which allows the
implementation of emulated instructions, for example,
instead of implement a co e inst ction fo an inc ement the instead of implement a core instruction for an increment the
constant generator is used.
Register As Constant Remarks
R2
00 R i t d
R2
00
-
Register mode
R2
01
(0)
Absolute mode
R2 10 00004h +4, bit processing
R2
11
00008h
+8 bit processing
R2
11
00008h
+8, bit processing
R3
00
00000h
0, word processing
R3 01 00001h +1
R3 10 00002h +2, bit processing
16 16
R3 11 0FFFFh -1, word processing
Central Processing Unit (MSP430 CPU) (7/7)
R4 - R15: GeneralPurpose
Registers: Registers:
These general-purpose registers are
adequate to store data registers,
address pointers or index values address pointers, or index values
and can be accessed with byte or
word instructions.
17 17
Central Processing Unit (MSP430X CPU) (1/9)
Main features of the MSP430X CPU architecture:
The MSP430X CPU extends the addressing capabilities of the The MSP430X CPU extends the addressing capabilities of the
MSP430 family beyond 64 kB to 1 MB;
To achieve this some changes have been made to the To achieve this, some changes have been made to the
addressing modes and two new types of instructions have
been added;
One instruction type allows access to the entire address
space, and the other is designed for address calculations;
The MSP430X CPU address bus has 20 bits, although the
data bus still has 16 bits. Memory accesses to 8-bit, 16-bit
and 20-bit data are supported;
Despite these changes, the MSP430X CPU remains
compatible with the MSP430 CPU, having a similar number
of egiste s
18
of registers.
Central Processing Unit (MSP430X CPU) (2/9)
Organization of the MSP430X CPU:
Although the MSP430X CPU structure is Although the MSP430X CPU structure is
similar to that of the MSP430 CPU, there
are some differences that will now be
highlighted;
With the exception of the status register
SR, all MSP430X registers are 20 bits;
The CPU can now process 20-bit or 16-
bit data.
19
Central Processing Unit (MSP430X CPU) (3/9)
The MSP430X CPU has 16 registers, some of which have
special use: special use:
R0 (PC) Program Counter: ( ) g
Has the same function as the MSP430 CPU, although now it
has 20 bits.
R1 (SP) Stack Pointer:
Has the same function as the MSP430 CPU, although now it Has the same function as the MSP430 CPU, although now it
has 20 bits.
( ) i R2 (SR) Status Register:
Has the same function as the MSP430 CPU, but it still has 16
bits.
20
bits.
Central Processing Unit (MSP430X CPU) (4/9)
R2 (SR) Status Register:
D i ti f th SR bit Description of the SR bits:
21
Central Processing Unit (MSP430X CPU) (5/9)
R2 (SR/CG1) and R3 (CG2) Constant Generators:
R i t R2 d R3 b d t t i diff t Registers R2 and R3 can be used to generate six different
constants commonly used in programming, without adding
an additional 16-bit word to the instruction;
The constants are fixed and are selected by the (As) bits of
the instruction (As) selects the addressing mode the instruction. (As) selects the addressing mode.
Values of constants
generated:
22
Central Processing Unit (MSP430X CPU) (6/9)
R2 (SR/CG1) and R3 (CG2) Constant Generators:
Whenever the operand is one of the six constants the Whenever the operand is one of the six constants, the
registers are selected automatically;
Therefore, when used in constant mode, registers R2 and R3
cannot be used as source registers cannot be used as source registers.
R4-R15 General-purpose registers:
Have the same function as in the MSP430 CPU, although
they now have 20 bits;
These registers can process 8-bit, 16-bit or 20-bit data;
If b t i itt t f th i t it t k bit 7 0 If a byte is written to one of these registers it takes bits 7:0,
the bits 19:8 are filled with zeroes. If a word is written to
one of these registers it takes bits 15:0, the bits 19:16 are
filled with zeroes
23
filled with zeroes.
Central Processing Unit (MSP430X CPU) (7/9)
R4-R15 General-purpose registers:
Handling byte data (8 bits) using the suffix B: Handling byte data (8 bits) using the suffix . B:
24
Central Processing Unit (MSP430X CPU) (8/9)
R4-R15 General-purpose registers:
Handling word data (16 bits) using the suffix W: Handling word data (16 bits) using the suffix . W:
25
Central Processing Unit (MSP430X CPU) (9/9)
R4-R15 General-purpose registers:
Manipulation of a 20 bit address using the suffix A: Manipulation of a 20-bit address using the suffix . A:
26
Instruction Format
There are three formats used to encode instructions
f i b th CPU for processing by the CPU core
Double operand
Single operand
Jumps
The instructions for double and single operands,
depend on the suffix used, (. W) word or (. B) byte
Th ffi ll d b t d t These suffixes allow word or byte data access
If the suffix is ignored, the instruction processes
word data by default word data by default
Source Addressing Modes
The MSP430 has four basic modes for the source
address:
Rs - Register
x(Rs) - Indexed Register ( ) g
@Rs - Register Indirect
@Rs+- Indirect Auto-increment @Rs+ Indirect Auto increment
In combination with registers R0-R3, three additional
source addressing modes are available: g
label - PC Relative, x(PC)
&label Absolute, x(SR) &label Absolute, x(SR)
#n Immediate, @PC+
Destination Addressing Modes
There are two basic modes for the destination
address:
Rd- Register
x(Rd) - Indexed Register ( ) g
In combination with registers R0/R2, two additional
destination addressing modes are available:
label - PC Relative, x(PC)
&label Absolute, x(SR) , ( )
Addressing modes
7 addressing modes for the source operand:
4 addressing modes for the destination operand:
Register mode; Indexed mode; Symbolic mode; Absolute eg ste ode; de ed ode; Sy bo c ode; bso ute
mode.
For the destination operand, two additional addressing
30
p , g
modes can be emulated.
Register Mode (Rn)
The most straightforward addressing mode and is
available for both source and destination available for both source and destination
Example:
mov.w r5,r6 ; move word from r5 to r6
The registers are specified in the instruction; no
further data is needed further data is needed
Also the fastest mode and does not require an
addition cycle addition cycle
Byte instructions use only the lower byte, but clear
the upper byte when writingg
Indexed Mode x(Rn)
The address is formed by adding a constant (index) to the y g ( )
contents of a CPU register
Example:
mo b 3( 5) 6 mo e b te f om mov.b 3(r5),r6 ; move byte from
; M(3
10
+r5) to r6
Indexed addressing can be used for source and/or Indexed addressing can be used for source and/or
destination
The index is located in the memory work following the
instruction and requires an additional memory cycle (If the instruction and requires an additional memory cycle (If the
index cannot be generated by the constant generator)
There is no restriction on the address for a byte, but words
must lie on even addresses
Symbolic Mode (PC Relative)
The address if formed by adding a constant (index) to the y g ( )
program counter (PC)
Example:
mo Cnt 6 mo e o d mov.w Cnt,r6 ; move word
; M(Cnt+PC) to r6
The PC relative index is calculated by the assembler The PC relative index is calculated by the assembler
Produces position-independent code, but rarely used in the
MSP430 because absolute addressing can reach all memory
addresses addresses
Note: this is NOT an appropriate mode of addressing when
referencing fixed locations in memory such as the special
function registers (SFRs)
Absolute Mode (&label)
The address is formed directly from a constant (index) and y ( )
specified by preceding a label with an ampersand (&)
Example:
mo &Cnt 6 mo e o d mov.w &Cnt,r6 ; move word
; Cnt to r6
Same as indexed mode with the base register value of 0 (by Same as indexed mode with the base register value of 0 (by
using the status register SR as the base register)
The absolute address is stored in the memory word following
the instruction and requires an additional cycle the instruction and requires an additional cycle
Note: this is the preferred mode of addressing when
referencing fixed locations in memory such as the special
function registers (SFRs)
Indirect Register Mode (@Rn)
The address of the operand is formed from the contents of p
the specified register
Example:
mo @ 5 6 mo e o d mov.w @r5,r6 ; move word
; M(r5) to r6
Only available for source operands Only available for source operands
Same as indexed mode with index equal to 0, but does not
require an additional instruction word
The value of the indirect register is unchanged
Indirect Autoincrement Mode (@Rn+)
The address of the operand is formed from the contents of p
the specified register and afterwards, the register is
automatically increment by 1 if a byte is fetched or by 2 if a
word is fetched
Example:
mov.w @r5+,r6 ; move word
; M(r5) to r6 ; M(r5) to r6
; increment r5 by 2
Only available for source operands. Only available for source operands.
Usually called post-increment addressing.
Note: All operations on the first address are fully completed before p y p
the second address is evaluated
Immediate Mode (#n)
The operand is an immediate value p
Example
mov.w #100,r6 ; 100 -> r6 mov.w #100,r6 ; 100 > r6
The immediate value is located in the memory word following
the instruction
Only available for source operands
The immediate mode of addressing is a special case of auto-
increment addressing that uses the program counter (PC) as increment addressing that uses the program counter (PC) as
the source register.
The PC is automatically incremented after the instruction is
fetched; hence points to the following word
Constant Generators
The following source register/addressing mode
combinations result in a commonly used constant operand
l value
Do not require an additional instruction word
Addressing Summary
Instruction set
27 core instructions;
24 emulated instructions;
The instruction set is orthogonal;
The core instructions have unique opcodes decoded by
the CPU, while the emulated ones need assemblers and
compilers for their mnemonics; compilers for their mnemonics;
There are three core-instruction formats:
Double operand;
Single operand;
Program flow control Jump
48
Program flow control - Jump.
Core Instructions
Total Instructions
The MSP430
You may not know how it works, but now you know the parts its made from!
Memory
ProgramCounter Status Register Memory Address Register
Memory
Destination Operand
Multiplexer
Memory
Mapped I/O
Source Operand
16 16 bit
Bus Driver
Port 1 Output
16 16-bit
Registers
Lots of Gates Instruction Register
Arithmetic Logic Unit
Condition Codes
Fetching an Instruction

PC

Device Systems and


Operating Modes Operating Modes
System Reset System Reset
System reset (1/5)
The MSP430 families make use of two independent reset
signals: signals:
Hardware reset signal - POR (Power On Reset);
Software reset signal PUC (Power Up Clear). g ( p )
Different events determine which one of the reset
signals is generated; signals is generated;
Sources that can generate a POR: Sources that can generate a POR:
Initial device power up;
Low signal at the reset pin (RST/NMI) when this is
f d d configured in reset mode;
Low signal at the supervisory voltage system (SVS) when
the register bit PORON is high. the register bit PORON is high.
System reset (2/5)
Sources that can generate a PUC:
A ti POR i l Active POR signal;
Watchdog timer (WDT) expired when it is configured in
supervision mode; p ;
Flash memory access control registers security key violation.
System reset (3/5)
Conditions:
Hardware reset signal (POR) is active then:
SR is reset; SR is reset;
PC is loaded with the address in location 0FFFEh;
Peripheral registers all enter their power up state.
Software reset signal (PUC) is active then:
SR is reset; SR is reset;
PC is loaded with either the reset vector (0FFFEh), or the
PUC source interrupt vector;
Only some peripheral registers are reset by PUC.
System reset (4/5)
All 2xx and 4xx MSP430 devices possess a reset circuit
by power source disturbance identified by Brown Out by power source disturbance identified by Brown Out
Reset (BOR);
This circuit is an enhanced POR system:
Includes a hysteresis circuit;
De ice sta s in eset mode ntil oltage is highe than the Device stays in reset mode until voltage is higher than the
upper threshold (VB_IT+):
BOR takes 2 msec to be inactive and allow the program p g
execution by CPU;
When voltage falls below the lower threshold (VB_IT-):
BOR circuit will generate a reset signal; BOR circuit will generate a reset signal;
Suspends processor operation until the voltage rises up
above the lower threshold inferior value.
System reset (5/5)
Brownout timing:
Device Systems and
Operating Modes Operating Modes
System Clocks System Clocks
System clocks (1/16)
Allows the CPU and peripherals to operate from different
clock sources; clock sources;
The system clocks depend on the device in the MSP430
family: family:
MSP430x2xx:
The Basic Clock Module+ (BCM+);
One or two oscillators (depending on the device);
Capable of working with external crystals or Capable of working with external crystals or
resonators;
Internal digitally controlled oscillator (DCO);
W ki f t 16 MH Working frequency to up 16 MHz;
Lower power consumption;
Lower internal oscillator start-up time. p
System clocks (2/16)
MSP430x2xx:
B i Cl k+ Basic Clock+:
System clocks (3/16)
MSP430x4xx:
F L k d L (FLL+) Frequency Locked Loop (FLL+):
One or two oscillators (depending on the device); One or two oscillators (depending on the device);
Capable of working with external crystals or
resonators;
Internal digitally controlled oscillator (DCO) adjusted Internal digitally controlled oscillator (DCO), adjusted
and controlled by hardware;
Synchronized to a high-frequency internal clock from
a low frequency external oscillator.
System clocks (4/16)
MSP430x4xx:
FLL+ FLL+:
System clocks (5/16)
The clock sources from these oscillators can be selected to
generate different clock signals: g g
Master clock (MCLK):
Generated by DCO (but can also be fed by the crystal
ill t ) oscillator);
Activate and stable in less than 6 sec;
Used by the CPU and high-speed peripherals.
Subsystem main clock (SMCLK):
Used as alternative clock source for peripherals.
Auxiliary clock (ACLK):
RTC self wake-up function from low power modes (32.768
kHz); kHz);
Always fed by the crystal oscillator.
Each clock can be internally divided by a factor of 1 2 4 or 8 Each clock can be internally divided by a factor of 1, 2, 4 or 8.
System clocks (6/16)
Low/High frequency oscillator (LFXT1):
Implemented in all MSP430 devices; Implemented in all MSP430 devices;
Used with either:
Low-frequency 32.768 kHz watch crystals (RTC);
Standard crystals, resonators, or external clock sources
in range 450 kHz to 8 MHz (16 MHz in 2xx family). g ( y)
The operating mode selection (one bit):
( 0) > LF clock; (=0) -> LF clock;
(=1) -> HF clock.
XTS: located at the BCSCTL1 register (2xx family);
XTS_FLL: located at the FLL_CTL0 register (4xx family).
System clocks (7/16)
Second crystal oscillator (XT2):
Sources of XT2CLK and its characteristics are identical to Sources of XT2CLK and its characteristics are identical to
LFXT1 in HF mode (range 450 kHz to 8 MHz, or 16 MHz in
the 2xx family);
Load capacitance for the high frequency crystal or p g q y y
resonator must be provided externally;
This oscillator can be disabled by the XT2OFF bit:
BCSCTL1 register in 2xx family; BCSCTL1 register in 2xx family;
FLL_CTL1 register in 4xx family (if XT2CLK is unused
for source the MCLK and SMCLK clock signals).
System clocks (8/16)
Digitally-controlled oscillator (DCO):
Integrated ring oscillator with RC-type characteristics; Integrated ring oscillator with RC type characteristics;
Provide a wide, software-controllable frequency range;
DCO frequency is synchronized to the FLL;
F eq enc mod lation method p o ided b FLL Frequency modulation method provided by FLL
functionality:
2xx family: 2xx family:
Does not have full FLL functionality;
The DCO generates an internal signal (DCOCLK):
Programmed internally or externally (DCOR bit); Programmed internally or externally (DCOR bit);
Controlled by a resistor connected to the R
OSC
and V
CC
pins.
System clocks (9/16)
2xx family:
The DCO control bits: The DCO control bits:
RSELx: f
DCO
range selection;
DCOx: f
DCO
defined by the RSEL bits. The step size y p
is defined by the parameter SDCO;
MODx: Modulation bits select how often
f
DCO
(RSEL DCO+1) is used within the period of 32 f
DCO
(RSEL, DCO+1) is used within the period of 32
DCOCLK cycles.
The frequency f
DCO
(RSEL, DCO) is used for the q y ( )
remaining cycles.
Specific frequency ranges and values vary by device: Specific frequency ranges and values vary by device:
( )
) 1 , ( ) , (
32
32
+
+

=
DCO RSEL DCO DCO RSEL DCO
avg
f MOD f MOD
f f
f
( )
) 1 , ( ) , (
32
+
+
DCO RSEL DCO DCO RSEL DCO
f MOD f MOD
System clocks (10/16)
2xx family:
Basic Clock Module+ (BCM+) registers configuration: Basic Clock Module+ (BCM+) registers configuration:
DCOCTL: DCO Control Register
7 6 5 4 3 2 1 0
DCOx MODx
Bit Description
7-5 DCOx Discrete DCO frequency selection step (depends on RSELx bits).
4-0 MODx Modulator selection.
System clocks (11/16)
2xx family:
B i Cl k M d l + (BCM+) i t fi ti Basic Clock Module+ (BCM+) registers configuration:
BCSCTL1: Basic Clock System Control Reg. 1
7 6 5 4 3 2 1 0
XT2OF XTS DIVAx RSELx
Bit Description
7 XT2OF XT2 oscillator fault:
XT2OF = 0 XT2 normal operation
XT2OF = 1 XT2 fault condition
6 XTS LFXT1 oscillator operating mode: 6 XTS LFXT1 oscillator operating mode:
XTS = 0 LF mode (low frequency)
XTS = 1 HF mode (high frequency)
5-4 DIVAx ACLK frequency divider: q y
DIVA1 DIVA0 = 0 0 /1
DIVA1 DIVA0 = 0 1 /2
DIVA1 DIVA0 = 1 0 /4
DIVA1 DIVA0 = 1 1 /8
3-0 RSELx Range select. Sixteen different frequency ranges are available.
System clocks (12/16)
2xx family:
B i Cl k M d l + (BCM+) i t fi ti Basic Clock Module+ (BCM+) registers configuration:
BCSCTL2: Basic Clock System Control Reg. 2
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
SELMx DIVMx SELS DIVSx DCOR
Bit Description
7-6 SELMx MCLK source: SELM1 SELM0 = 0 0 DCO 7 6 SELMx MCLK source: SELM1 SELM0 = 0 0 DCO
SELM1 SELM0 = 0 1 DCO
SELM1 SELM0 = 1 0 XT2
SELM1 SELM0 = 1 1 LFXT1
5-4 DIVMx MCLK frequency divider: DIVM1 DIVM0 = 0 0 /1
DIVM1 DIVM0 = 0 1 /2 DIVM1 DIVM0 = 0 1 /2
DIVM1 DIVM0 = 1 0 /4
DIVM1 DIVM0 = 1 1 /8
3 SELS SMCLK source: SELS = 0 DCO
SELS = 1 XT2
2-1 DIVSx SMCLK frequency divider: DIVS1 DIVS0 = 0 0 /1
DIVS1 DIVS0 = 0 1 /2
DIVS1 DIVS0 = 1 0 /4
DIVS1 DIVS0 = 1 1 /8
0 DCOR DCO resistor selector DCOR = 0 Internal resistor 0 DCOR DCO resistor selector DCOR 0 Internal resistor
DCOR = 1 External resistor
System clocks (13/16)
2xx family:
B i Cl k M d l + (BCM+) i t fi ti Basic Clock Module+ (BCM+) registers configuration:
BCSCTL3: Basic Clock System Control Reg. 3
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
XT2Sx LFXT1Sx XCAPx XT2OFF LFXT1OF
Bit Description
7-6 XT2Sx XT2 range select: XT2S1 XT2S0 = 0 0 0.4 1 MHz
XT2S1 XT2S0 = 0 1 1 3 MHz
XT2S1 XT2S0 = 1 0 3 16 MHz
XT2S1 XT2S0 = 1 1 0.4 16-MHz (Digital external)
5-4 LFXT1Sx Low-frequency clock select and LFXT1 range select: XTS=0: XTS=1:
LFXT1S1 LFXT1S0 = 0 0 32768 Hz 0.4 - 1-MHz
LFXT1S1 LFXT1S0 = 0 1 Reserved 1 - 3-MHz
LFXT1S1 LFXT1S0 = 1 0 VLOCLK 3 - 16-MHz
LFXT1S1 LFXT1S0 = 1 1 External 0.4 - 16-MHz
3-2 XCAPx Oscillator capacitor selection: XCAP1 XCAP0 = 0 0 ~1 pF
XCAP1 XCAP0 = 0 1 ~6 pF
XCAP1 XCAP0 = 1 0 ~10 pF
XCAP1 XCAP0 = 1 1 ~12.5 pF
1 XT2OFF XT2 oscillator fault: XT2OFF = 0 No fault condition
XT2OFF = 1 Fault condition
0 LFXT1OF LFXT1OF oscillator fault: LFXT1OF 0 No fault condition 0 LFXT1OF LFXT1OF oscillator fault: LFXT1OF = 0 No fault condition
LFXT1OF = 1 Fault condition
System clocks (14/16)
Internal clock signals:
In 2xx family clock system = the basic clock module+: In 2xx family clock system the basic clock module+:
Support for a 32768 Hz watch crystal oscillator;
Internal very-low-power low-frequency oscillator;
Internal digitally-controlled oscillator (DCO) stable <1 s Internal digitally-controlled oscillator (DCO) stable <1 s.
The BCM+ provides the following clock signals:
A ilia clock (ACLK) so ced eithe f om Auxiliary clock (ACLK), sourced either from:
32768 Hz watch crystal;
Internal oscillator LFXT1CLK in LF mode with an
internal load capacitance of 6 pF internal load capacitance of 6 pF.
Main clock (MCLK), the system clock used by the CPU;
Sub-Main clock (SMCLK), the sub-system clock used
by the peripheral modules.
System clocks (15/16)
Internal clock signals:
Both MCLK and SMCLK are sourced from DCOCLK at Both MCLK and SMCLK are sourced from DCOCLK at
~1.1 MHz but can be sourced up to 16 MHz;
2xx DCO calibration data (in flash info memory segment A). 2xx DCO calibration data (in flash info memory segment A).
DCO frequency Calibration register Size Address
1 MHz
CALBC1_1MHZ
CALBC0_1MHZ
Byte
Byte
010FFh
010FEh
8 MHz
CALBC1_8MHZ
CALBC0 8MHZ
Byte
Byte
010FDh
010FCh CALBC0_8MHZ Byte 010FCh
12 MHz
CALBC1_12MHZ
CALBC0_12MHZ
Byte
Byte
010FBh
010FAh
16 MH
CALBC1 16MHZ Byte 010F9h
16 MHz
CALBC1_16MHZ
CALBC0_16MHZ
Byte
Byte
010F9h
010F8h
System clocks (16/16)
Internal clock signals:
Electrical characteristics vary over the recommended supply Electrical characteristics vary over the recommended supply
voltage range of between 2.2 V and 3.6 V. Higher DCO
frequencies require higher supply voltages.
Typical characteristics in active mode supply current for the yp pp y
(2xx family):
Device Systems and
Operating Modes Operating Modes
Watchdog and Watchdog and
Supervisory Voltage System
Watchdog timer (WDT and WDT+) (1/4)
The 16-bit WDT module can be used in:
Supervision mode:
Ensure the correct working of the software application;
P f PUC Perform a PUC;
Generate an interrupt request after the counter
overflows overflows.
Interval timer:
Independent interval timer to perform a standard depe de t te a t e to pe o a sta da d
interrupt upon counter overflow periodically;
Upper counter (WDTCNT) is not directly accessible by
ft software;
Control and the interval time selecting WDTCTL register;
WDTCNT: clock signal ACLK or SMCLK (WDTSSEL bit).
Watchdog timer (WDT and WDT+) (2/4)
The WDT control is performed through the:
WDTCTL, Watchdog Timer Control Register, WDTCTL WDTCTL, Watchdog Timer Control Register, WDTCTL
Eight MSBs (WDTPW): Password function, read as
0x69h, write as 0x5Ah unless the user want to force a 0x69h, write as 0x5Ah unless the user want to force a
PUC from software.
15 8
Read with the value 0x69h, WDTPW write with the value 0x5Ah
Watchdog timer (WDT and WDT+) (3/4)
The WDT control is performed through the:
WDTCTL, Watchdog Timer Control Register, WDTCTL WDTCTL, Watchdog Timer Control Register, WDTCTL
Eight LSBs: WDT configuration
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
WDTHOLD WDTNMIES WDTNMI WDTTMSEL WDTCNTCL WDTSSEL WDTIS1 WDTIS0
Bit Description
7 WDTHOLD WDT hold when WDTHOLD = 1 Useful for energy economy 7 WDTHOLD WDT hold when WDTHOLD = 1. Useful for energy economy.
6 WDTNMIES Select the NMI interrupt edge when WDTNMI = 1 WDTNMIES = 0 NMI on rising edge
WDTNMIES = 1 NMI on falling edge
5 WDTNMI Select the RST/NMI pin function WDTNMI = 0 Reset function
WDTNMI = 1 NMI function WDTNMI 1 NMI function
4 WDTTMSEL Select the WDT mode: WDTTMSEL = 0 Supervision mode
WDTTMSEL = 1 Interval timer mode
3 WDTCNTCL WDT counter clear: WDTCNTCL = 0 No action
WDTCNTCL = 1 Counter initialization at 0x0000h
2 WDTSSEL Select the WDT clock signal: WDTSSEL = 0 SMCLK
WDTSSEL = 1 ACLK
1-0 WDTISx Select the WDT timer interval: WDTIS1 WDTIS0 = 0 0 Clock signal / 32768
WDTIS1 WDTIS0 = 0 1 Clock signal / 8192
WDTIS1 WDTIS0 = 1 0 Clock signal / 512
WDTIS1 WDTIS0 = 1 1 Clock signal / 64
Watchdog timer (WDT and WDT+) (4/4)
The WDT uses two bits in the Special Function Registers
(SFRs) for interrupt control: ( ) p
WDTIE: WDT interrupt enable (IE1.0):
Enables the WDTIFG interrupt for interval timer mode
when WDTIE=1.
WDTIFG: WDT interrupt flag (IFG1.0):
Supervision mode: Supervision mode:
WDTIFG sources a reset vector interrupt.
If WDTIFG=1, the WDT initiates the reset
condition (detectable reset source). condition (detectable reset source).
Interval mode:
WDTIFG set after the selected time interval and WDTIFG set after the selected time interval and
requests a WDT interval timer interrupt;
WDTIE and GIE bits set;
WDTIFG reset automatically (also can be reset by WDTIFG reset automatically (also can be reset by
software).
Supervisory Voltage System (SVS) (1/2)
Used to monitor:
AV
CC
supply voltage; AV
CC
supply voltage;
External voltage (located at the SVSIN input).
When AV
CC
or SVSIN drops below selected threshold:
Sets a flag generating an interrupt;
Generates a system reset (POR) Generates a system reset (POR).
Is disabled after a BOR to conserve current consumption;
SVS features:
Output of SVS comparator accessible by software; Output of SVS comparator accessible by software;
Low-voltage condition latched (accessible by software);
14 selectable threshold levels;
E t l h l t it t l lt External channel to monitor external voltage.
Supervisory Voltage System (SVS) (2/2)
SVS control performed by:
SVSCTL, SVS Control Register SVSCTL, SVS Control Register
7 6 5 4 3 2 1 0
VLDx PORON SVSON SVSOP SVSFG
Bit Description
7-4 VLDx Voltage level detect. VLD3 VLD2 VLD1 VLD0 = 0000 SVS is off
VLD3 VLD2 VLD1 VLD0 = 0001 1.9 V
3 2 0 00 0 2 VLD3 VLD2 VLD1 VLD0 = 0010 2.1 V
.
.
.
VLD3 VLD2 VLD1 VLD0 = 1101 3.5 V
VLD3 VLD2 VLD1 VLD0 = 1110 3.7 V
VLD3 VLD2 VLD1 VLD0 = 1111 SVSIN to 1.25V
3 PORON When PORON = 1 enables the SVSFG flag to cause a POR device reset
2 SVSON This bit reflects the status of SVS operation, being set (SVSON=1) when the SVS is on
1 SVSOP This bit reflects the output value of the SVS comparator:
SVSOP = 0 SVS comparator output is low
SVSOP = 1 SVS comparator output is high SVSOP 1 SVS comparator output is high
0 SVSFG When SVSFG=1 a low voltage condition occurs
Device Systems and
Operating Modes Operating Modes
I nterrupts I nterrupts
Interrupt management
Interrupts:
Are events applied to the application program that force a Are events applied to the application program that force a
detour in program flow;
C CPU b ti (ISR) Cause CPU subprogram execution (ISR);
When Interrupt Service Routine (ISR) ends, the program flow p ( ) , p g
returns to the previous state.
There are three classes of interrupts: There are three classes of interrupts:
Reset;
Interrupts not maskable by GIE;
Interrupts maskable by GIE.
84
Interrupt management
Execution of a program proceeds predictably, with Execution of a program proceeds predictably, with
interrupts being the exception
Interrupts are usually generated by hardware
Processor stops with it is doing,
Stores enough information to later resume, g ,
Executes an interrupt service routine (ISR),
Restores saved information, Restores saved information,
Resumes execution.
An interrupt is an asynchronous signal indicating the An interrupt is an asynchronous signal indicating the
need for attention
Interrupt management
A way to respond to an external event (i.e., flag being set)
without polling without polling
How it works:
H/W senses flag being set H/W senses flag being set
Automatically transfers control to s/w that services the interrupt
When done, H/W returns control to wherever it left off When done, H/W returns control to wherever it left off
Advantages:
Main Prog
ISR g
Transparent to user
cleaner code
:
:
:
:
C doesnt waste time polling
:
RETI
Interrupt Flags
Each interrupt has a flag that is raised (set) when the
interrupt occurs. interrupt occurs.
Each interrupt flag has a corresponding enable bit
setting this bit allows a hardware module to request
an interrupt.
Most interrupts are Most interrupts are
maskable, which means
they can only interrupt if
1) enabled and
2) the general interrupt
enable (GIE) bit is set in enable (GIE) bit is set in
the status register (SR).
GIE
Importance of the Status Register
Status Register (SR):
St t t d t l bit Stores status and control bits;
System flags are changed automatically by the CPU;
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved for CG1 V SCG1 SCG0 OSCOFF CPUOFF GIE N Z C
Bit Description
8 V Overflow bit. V = 1 Result of an arithmetic operation overflows the signed-variable range.
7 SCG1 System clock generator 0. SCG1 = 1 DCO generator is turned off if not used for MCLK or SMCLK
6 SCG0 System clock generator 1. SCG0 = 1 FLL+ loop control is turned off
5 OSCOFF Oscillator Off. OSCOFF = 1 turns off LFXT1 when it is not used for MCLK or SMCLK
4 CPUOFF CPU off. CPUOFF = 1 disable CPU core.
3 GIE General interrupt enable. GIE = 1 enables maskable interrupts.
2 N Negative flag. N = 1 result of a byte or word operation is negative.
1 Z Zero flag. Z = 1 result of a byte or word operation is 0.
0 C Carry flag. C = 1 result of a byte or word operation produced a carry.
88
Interrupt management
Interrupts preempt normal code execution
Interrupt code runs in the foreground Interrupt code runs in the foreground
Normal (e.g. main()) code runs in the background
Interrupts can be enabled and disabled p
Globally
Individually on a per-peripheral basis
Non Maskable Interrupt (NMI) Non-Maskable Interrupt (NMI)
The occurrence of each interrupt is unpredictable
When an interrupt occurs p
Where an interrupt occurs
Interrupts are associated with a variety of on-chip and off-
hi i h l chip peripherals.
Timers, Watchdog, D/A, Accelerometer
NMI, change-on-pin (Switch)
Interrupt management
Interrupts commonly used for
Urgent tasks w/higher priority than main code
Infrequent tasks to save polling overhead
Waking the CPU from sleep
Call to an operating system (software interrupt). p g y ( p )
Event-driven programming Event driven programming
The flow of the program is determined by eventsi.e.,
sensor outputs or user actions (mouse clicks, key presses)
or messages from other programs or threads.
The application has a main loop with event detection and
event handlers event handlers.
Interrupt management
The interrupts are used to:
Allow a CPU fast response to a specific event; Allow a CPU fast response to a specific event;
Avoiding continuous polling for rare events;
Minimal disruption to the processing of other tasks.
In GIE-maskable interrupts, if both peripheral interrupt In GIE maskable interrupts, if both peripheral interrupt
enable bit and GIE are set, when an interrupt is
requested, it calls the ISR;
The interrupt latency time:
At between the event beginning and the ISR execution;
Interrupt latency time starts with acceptance of IR and
counting until starting of first instruction of ISR.
91
g g
Interrupt management
During an interrupt event:
PC of the next instruction and the SR are pushed onto the PC of the next instruction and the SR are pushed onto the
stack;
Afterwards, the SR is cleared with exception of SCG0, along
with the appropriate interrupt, disabling interrupts (reset pp p p , g p (
the GIE flag);
Other ISRs will not be called.
The RETI instruction at the end of the ISR will return to
the original program flow, automatically popping the SR g p g y p pp g
and PC;
Ensure that:
The ISR processing time is less than the interrupts request
time interval;
To avoid stack overflow -> application program collapse.
Interrupt management
Types of interrupts (internal and external):
Reset; Reset;
Interrupts not maskable by GIE: (non)-maskable interrupts
(NMI);
Interrupts maskable by GIE. Interrupts maskable by GIE.
Interrupts priority (The nearer a module is to the
CPU/NMIRS, the higher the priority).
Interrupt management
Types of interrupts (internal and external):
Main differences between non-maskable and maskable
interrupts:
Non-maskable interrupts cannot be disabled by the GIE Non maskable interrupts cannot be disabled by the GIE
bit of the SR. Used for high priority events e.g.
emergency shutdown;
Maskable interrupts are recognized by the CPUs
interrupt control, so the GIE bit must be set. Can be
switched off by software.
The system reset interrupts (Oscillator/Flash and the Hard
) d h h k bl Reset) are treated as highest priority non-maskable
interrupts, with their own interrupt vectors.
Interrupt management
Types of interrupts (internal and external):
Non Maskable Interrupts: Non Maskable Interrupts:
Not masked by GIE;
Enabled by individual interrupt enable bits;
Depend on the event source:
NMIIE: Non-Maskable Interrupts Interrupt Enable:
RST/NMI is configured in NMI mode; RST/NMI is configured in NMI mode;
WDTNMIES bit generates an NMI;
The RST/NMI flag NMIIFG is also set.
ACCVIE: ACCess Violation to the flash memory
Interrupt Enable:
h fl h fl The flash ACCVIFG flag is set.
OFIE: Oscillator Fault Interrupt Enable:
This signal can be triggered by a PUC signal.
Interrupt management (example)
Types of interrupts (internal and external):
N M k bl I t t Non Maskable Interrupts:
Example: ACCVIE (2xx family).
ACCV=1 ACCVIFG=1 ACCV 1 ACCVIFG 1
ACCVIFG=1 and ACCVIE=1 (set by software) NMIRS=1
Interrupt management
Types of interrupts (internal and external):
(by GIE) Maskable Interrupts:
Peripherals with interrupt capability or the watchdog Peripherals with interrupt capability or the watchdog
timer overflow in interval timer mode;
Individual enable/disable flag, located in peripheral
registers or in the individual module;
Can be disabled by resetting the GIE bit in SR, either by
software or by hardware/interrupt software or by hardware/interrupt.
Interrupt Vectors
The CPU must know where to fetch the next The CPU must know where to fetch the next
instruction following an interrupt.
The address of an ISR is defined in an interrupt The address of an ISR is defined in an interrupt
vector.
The MSP430 uses vectored interrupts where each ISR The MSP430 uses vectored interrupts where each ISR
has its own vector stored in a vector table located at
the end of program memory.
Note: The vector table is at a fixed location (defined
by the processor data sheet), but the ISRs can be
located anywhere in memory located anywhere in memory.
Interrupt vector table
Mapped at the very end of memory space (upper 16
words of Flash/ROM): 0FFE0h - 0FFFEh (4xx devices);
Priority of the interrupt vector increases with the word
address.
99
Processing an Interrupt
1) Current instruction completed ) p
OR
2) MCLK started if CPU was off
3) Processor pushes program counter on stack
4) Processor pushes status register on stack
5) Interrupt w/highest priority is selected
6) Interrupt request flag cleared if single sourced
7) Status register is cleared 7) Status register is cleared
Disables further maskable interrupts (GIE cleared)
Terminates low-power mode Terminates low power mode
8) Processor fetches interrupt vector and stores it in the
program counter
9) User ISR must do the rest!
Interrupt Stack
Interrupt Service Routines
Look superficially like a subroutine.
However, unlike subroutines
ISRs can execute at unpredictable times.
Must carry out action and thoroughly clean up.
Must be concerned with shared variables.
Must return using reti rather than ret.
ISR must handle interrupt in such a way that the ISR must handle interrupt in such a way that the
interrupted code can be resumed without error
Copies of all registers used in the ISR must be saved
(preferably on the stack)
Interrupt Service Routines
Well-written ISRs: Well written ISRs:
Should be short and fast
Should affect the rest of the system as little as possible Should affect the rest of the system as little as possible
Require a balance between doing very little thereby
leaving the background code with lots of processing g g p g
and doing a lot and leaving the background code with
nothing to do
Applications that use interrupts should:
Disable interrupts as little as possible
Respond to interrupts as quickly as possible
Interrupt Service Routines
Interrupt-related runtime problems can be Interrupt related runtime problems can be
exceptionally hard to debug
Common interrupt-related errors include:
Failing to protect global variables g p g
Forgetting to actually include the ISR - no linker error!
Not testing or validating thoroughly Not testing or validating thoroughly
Stack overflow
Running out of CPU horsepower Running out of CPU horsepower
Interrupting critical code
T i t t t th il Trying to outsmart the compiler
Returning from ISR
MSP430 requires 6 clock cycles before the ISR q y
begins executing
The time between the interrupt request and the start of
the ISR is called latency the ISR is called latency
An ISR always finishes with the return from
interrupt instruction (reti) requiring 5 cycles interrupt instruction (reti) requiring 5 cycles
The SR is popped from the stack
Re-enables maskable interrupts
Restores previous low-power mode of operation
The PC is popped from the stack
Note: if waking up the processor with an ISR, the new g p p ,
power mode must be set in the stack saved SR
Interrupts in C
.
your code your code
.
Device Systems and
Operating Modes Operating Modes
Low Power Modes Low Power Modes
Low power operating modes (1/11)
One of the main features of the MSP430 families:
Low power consumption (about 1 mW/MIPS or less); Low power consumption (about 1 mW/MIPS or less);
Important in battery operated embedded systems.
Low power consumption is only accomplished:
Using low power operating modes design; Using low power operating modes design;
Depends on several factors such as:
Clock frequency;
Ambient temperature;
Supply voltage;
Peripheral selection;
Input/output usage;
Memory type; Memory type;
...
Low power operating modes (2/11)
Low power modes (LPM):
6 operating modes; 6 operating modes;
Configured by the SR bits: CPUOFF, OSCOFF, SCG1, SCG0.
Active mode (AM) - highest power consumption: Active mode (AM) - highest power consumption:
Configured by disabling the SR bits described above;
CPU is active;
All enabled clocks are active; All enabled clocks are active;
Current consumption: 250 A.
Software selection up to 5 LPM of operation;
Operation:
An interrupt event can wake up the CPU from any LPM;
Service the interrupt request;
Restore back to the LPM. Restore back to the LPM.
Low power operating modes (3/11)
Low power modes (LPM):
Example: Typical current consumption (41x family). Example: Typical current consumption (41x family).
Low power operating modes (4/11)
Low power modes (LPM):
Mode C ent SR bits config ation Clock signals Oscillato Mode Current SR bits configuration Clock signals Oscillator
~ [A] CPUOFF OSCOFF SCG1 SCG0 ACLK SMCLK MCLK DCO
DC
gen.
Low-power mode 0
35 1 0 0 0 1 1 0 1 1
(LPM0)
35 1 0 0 0 1 1 0 1 1
Low-power mode 1
(LPM1)
44 1 0 0 1 1 1 0 1 1*
Low-power mode 2
19 1 0 1 0 1 0 0 0 1
Low power mode 2
(LPM2)
19 1 0 1 0 1 0 0 0 1
Low-power mode 3
(LPM3)
0.8 1 0 1 1 1 0 0 0 0
Low power mode 4 Low-power mode 4
(LPM4)
0.1 1 1 1 1 0 0 0 0 0
*DCOs DC generator is enabled if it is used by peripherals.
Low power operating modes (5/11)
Low power modes (LPM) characteristics:
LPM0 to LPM3:
Periodic processing based on a timer interrupt;
LPM0: Both DCO source signal and DCOs DC gen.;
LPM0 and LPM1: Main difference between them is the
condition of enable/disable the DCOs DC generator; condition of enable/disable the DCO s DC generator;
LPM2: DCOs DC generator is active and DCO is
disabled;
LPM3: Only the ACLK is active (< 2 A).
LPM4: LPM4:
Externally generated interrupts;
No clocks are active and available for peripherals.
d d (0 ) Reduced current consumption (0.1 A).
Low power operating modes (6/11)
Program flow steps:
Enter Low-power mode:
Enable/disable CPUOFF, OSCOFF, SCG0, SCG1 bits in
SR; SR;
LPM is active after writing to SR;
CPU will suspend the program execution;
Disabled peripherals: Disabled peripherals:
Operating with any disabled clock;
Individual control register settings.
All I/O port pins and RAM/registers are unchanged;
Wake up is possible through any enabled interrupt.
Low power operating modes (7/11)
Program flow steps:
An enabled interrupt event wakes the MSP430;
Enter ISR: Enter ISR:
The operating mode is saved on the stack during ISR;
The PC and SR are stored on the stack;
Interrupt vector is moved to the PC; Interrupt vector is moved to the PC;
The CPUOFF, SCG1, and OSCOFF bits are automatically
reset, enabling normal CPU operation;
IFG flag cleared on single source flags IFG flag cleared on single source flags.
Returning from the ISR:
h l d f h k h The original SR is popped from the stack, restoring the
previous operating mode;
The SR bits stored in the stack are modified returning to
a different operating mode after RETI instruction a different operating mode after RETI instruction.
Low power operating modes (8/11)
Examples of applications development using the MSP430
with and without low power modes consideration: with and without low power modes consideration:
Example Without low power mode With low power mode
Toggling the bit 0 of port 1 (P1.0)
periodically
Endless loop
(100 % CPU load)
LPM0
Watchdog timer interrupt p y ( ) g p
UART to transmit the received
message at a 9600 baud rate
Polling UART receive
(100 % CPU load)
UART receive interrupt
(0.1 % CPU load)
Set/reset during a time interval,
periodically of the peripheral Endless loop Setup output unit periodically, of the peripheral
connected to the bit 2 of port 1
(P1.2)
Endless loop
(100 % CPU load)
Setup output unit
(Zero CPU load)
Power manage external devices like
O A
Putting the OPA Quiescent
( )
Shutdown the Op-Amp between data
acquisition
Op-Amp (Average current: 1 A)
acquisition
(Average current: 0.06 A)
Power manage internal devices like
Comparator A
Always active
(Average typical current: 35 A)
Disable Comparator A between data
acquisition
Using LPMs while the LED is switch
Respond to button-press interrupt in
P1.0 and toggle LED on P2.1
Endless loop
(100 % CPU load)
Using LPMs while the LED is switch
off:
LPM3: 1.4 A
LPM4: 0.3 A
Configure unused ports in output
direction
P1 interrupt service routine
Low power operating modes (9/11)
Rules of thumb for the configuration of LP applications:
Extended ultra-low power standby mode. Maximize LPM3;
Minimum active duty cycle; Minimum active duty cycle;
Performance on-demand;
Use interrupts to control program flow;
Replace software with on chip peripherals;
Manage the power of external devices;
Configure unused pins properly, setting them as outputs to
avoid floating gate current.
Low power operating modes (10/11)
Rules of thumb for LP applications configuration:
Low-power efficient coding techniques:
Optimize program flow; p p g ;
Use CPU registers for calculations and dedicated
variables;
Same code size for word or byte;
Use word operations whenever possible; p p
Use the optimizer to reduce code size and cycles;
Use local variable (CPU registers) instead of global Use local variable (CPU registers) instead of global
variables (RAM);
Use bit mask instead of bit fields;
Low power operating modes (11/11)
Rules of thumb for LP applications configuration:
Low-power efficient coding techniques:
Use unsigned data types where possible; g yp p ;
Use pointers to access structures and unions;
Use static const class to avoid run-time copying of Use static const class to avoid run-time copying of
structures, unions, and arrays;
Avoid modulo;
Avoid floating point operations;
Count down for loops; Count down for loops;
Use short ISRs.
Device Systems and
Operating Modes Operating Modes
Direct Memory Access ( DMA) Direct Memory Access ( DMA)
DMA capability (1/3)
The MSP430 has been designed for applications
requiring low power; q g p ;
When the application requires data-handling, the direct
memory access (DMA) capability included in some y ( ) p y
devices is useful:
5xxx; FG4xx(x); F261x; F16x(x) and F15x;
Among these: MSP430FG4618 (Experimenters board). g ( p )
DMA automatically handles data;
DMA does not require CPU intervention;
DMA helps reduce the power consumption (CPU remains DMA helps reduce the power consumption (CPU remains
sleeping).
120
DMA capability (2/3)
Concept of DMA: move functionality to peripherals:
P i h l l t th th CPU Peripherals use less current than the CPU;
Delegating control to peripherals allows the CPU to shut
down (saves power); ( p );
Intelligent peripherals are more capable, providing a
better opportunity for CPU shutoff;
DMA can be enabled fo epetiti e data handling inc easing DMA can be enabled for repetitive data handling, increasing
the throughput of peripheral modules;
Minimal software requirements and CPU cycles. q y
121
DMA capability (3/3)
The following TI Application Reports cover the use of the
DMA controller for different applications with the aim of DMA controller for different applications, with the aim of
lowering power consumption:
Streamlining the mixed-signal path with the signal-chain-
on-chip MSP430F169 <slyt078.pdf>
Interfacing the MSP430 with MMC/SD Flash Memory
Cards <slaa281b.pdf>
Digital FIR Filter Design Using the MSP430F16x
<slaa228 pdf> <slaa228.pdf>
Using the USCI I2C Master <slaa382.pdf>
122
DMA configuration and operation (1/6)
Block diagram:
123
DMA configuration and operation (2/6)
DMA controller features:
Three independent transfer channels; Three independent transfer channels;
Configurable (ROUNDROBIN bit) DMA channel priorities:
Default: DMA0DMA1DMA2;
DMA Transfer cycle time: DMA Transfer cycle time:
Requires only two MCLK clock cycles per transfer;
Each byte/word transfer requires:
2 MCLK cycles after synchronization;
1 MCKL cycle of wait time after transfer.
124
DMA configuration and operation (3/6)
DMA controller features:
Block sizes up to 65535 bytes or words; Block sizes up to 65535 bytes or words;
Configurable edge/level-triggered transfer (DMALEVEL bit). g g / gg ( )
Byte or word and mixed byte/word transfer capability:
B t t b t Byte-to-byte;
Word-to-word;
Byte-to-word (upper byte of the destination word is y ( pp y
cleared);
Word-to-byte (lower byte of the source word is
transferred). transferred).
125
DMA configuration and operation (4/6)
DMA controller features:
Four addressing modes for each DMA channel are independently Four addressing modes for each DMA channel are independently
configurable (DMASRCINCRx and DMADSTINCRx control bits):
Fixed address to fixed address;
Fixed address to block of addresses; Fixed address to block of addresses;
Block of addresses to fixed address;
Block of addresses to block of addresses.
126
DMA configuration and operation (5/6)
DMA controller features:
Six transfer modes (each channel is individually configurable Six transfer modes (each channel is individually configurable
by the DMADTx bits):
DMADTx Transfer mode Description DMAEN after DMADTx Transfer mode Description DMAEN after
transfer
000 Single transfer Each transfer requires a trigger 0
l bl k i f d
001 Block transfer
A complete block is transferred
with one trigger
0
010, 011 Burst-block transfer
CPU activity is interleaved with a
block transfer
0
block transfer
100
Repeated single
transfer
Each transfer requires a trigger 1
101
Repeated block
t f
A complete block is transferred
ith t i
1
transfer with one trigger
110, 111
Repeated burst-block
transfer
CPU activity is interleaved with a
block transfer
1

127

DMA configuration and operation (6/6)
DMA transfer example
DMA with flash memory:
Automatically moves data to the Flash memory;
Performs the data move data word/byte to the Flash;
The write timing control is done by the Flash controller;
Write transfers to the Flash memory succeed if the Flash Write transfers to the Flash memory succeed if the Flash
controller set-up is done before the DMA transfer and if
the Flash is not busy.
All DMA transfers:
Occur without CPU intervention;
Operate independently of any low-power modes;
Increase throughput of modules
128
Increase throughput of modules.