Nios II VGA Controller with DMA

User Guide
Introduction
The Nios II VGA Controller with DMA is an SOPC Builder component which can be
added to an SOPC Builder sstem to pro!ide VGA displa capabilit"
The controller is capable o# displain$ the #ollowin$ resolutions%
&'( ) '*(
*(( ) &((
+(,' ) -&*

All resolutions can be displaed in either +& or ,'.bit color" /esolution and color depth
settin$s are con#i$urable in the VGA Controller con#i$uration wi0ard in SOPC Builder"
The controller was desi$ned #or use with the 1ancelot dau$hter card2 a!ailable #rom
Microtroni)" The 1ancelot card #eatures a Te)as Instruments T3S*+4' !ideo di$ital to
analo$ con!erter 5DAC6 with a VGA output connector2 allowin$ displa to a VGA
monitor" Also on the card are two PS, connectors and a +7*8audio 9ac:" The 1ancelot
card attaches to the prototpe headers o# Nios II de!elopment boards allowin$ it to be
dri!en b ;PGA pins" The card is a!ailable #rom Microtroni) at%
http%77www"microtroni)"com7product<lancelot"html
Althou$h the VGA controller component was desi$ned #or use with the 1ancelot
dau$hter card2 it can be used with a Te)as Instruments T3S*+4' DAC soldered directl
to a board as well"
The VGA controller component also includes a 3A1 so#tware dri!er" =hen the VGA
controller is added to an SOPC Builder sstem2 the 3A1 dri!er is automaticall included
in an so#tware pro9ect which is built #or that sstem in Nios II ID>" The dri!er supports
all resolution modes and color depths without an code chan$es needed in the user?s
application code" The dri!er also automaticall handles bu##er swaps when the controller
is used in double.bu##ered mode"
Controller Architecture
The VGA controller is capable o# readin$ !ideo #rames directl #rom memor !ia DMA2
and dri!in$ the !ideo DAC directl without an processor inter!ention" Once the
controller is initiali0ed2 the onl time that processor inter!ention is needed is when ou
want to displa a new #rame bu##er at a di##erent address"
The VGA controller contains #i!e main lo$ic bloc:s%
Avalon slave port
Initiali0ation and control
Contains the control re$isters
Avalon read master
/eads !ideo data #rom memor 5DMA6
Dual clock FIFO
Trans#ers !ideo data between the sstem cloc: domain and the VGA cloc:
domain"
VGA signal sequencer
;ormats the !ideo data into the proper #ormat #or the T3S*+4' DAC"
Data Width Converter
Con!erts 4,.bit words o# data into +& or ,'.bit pi)els
See ;i$ure + #or a bloc: dia$ram o# the VGA Controller"
Figure 1 VGA Controller with DMA Block Diagram
Avalon Slave Port
The A!alon sla!e port is used to initiali0e2 con#i$ure and control the operation o# the
VGA controller b readin$ and writin$ ' 4,.bit control re$isters" The #ormat o# the
re$isters is as #ollows%
Offset Read!rite Function
()( /7= Sla!e Control /e$ister
()' /7= DMA Source /e$ister
()* /7= DMA Modulus /e$ister
()C / Current Source /e$ister
vga_clk_ext
sync_n
sync_t
blank_n
M1
M2
vsync
hsyn
c
R
G
B
FIFO
32-Bits
Data Width
Conerter
32!-"#! or
2$!
%i%o&rea
d
writ
e
use
d
VGA
'e(uencer
Aalon )ead
Master addres
s
wait_request
read_n
read_da
ta
sys_clk
Aalon
'lae
vga_clk_in
t
write_dat
a
Double registers
for eta!stability
"revention
*hreshold
+o,ic
okay to read okay to write
read_dat
a
read_n
write_n
Control
)e,isters
address
'lae Control )e,ister
4+""+ (
/eser!ed Start
Start . =hen this bit is set2 the VGA Controller be$ins readin$ !ideo data
#rom the DMA source address and sendin$ it to the !ideo DAC
/eser!ed. These bits are reser!ed #or #uture use"
DMA 'ource )e,ister
4+""(
Base address o# !ideo #rame to be displaed
This is the address where the be$innin$ o# the #rame to be displaed is located"
This re$ister must be written with a !alid !alue be#ore startin$ the controller" It
can also be re.written at an time with the address o# a new #rame bu##er" =hen
the controller #inishes displain$ the current #rame2 it will automaticall be$in
displain$ the new one"
DMA Modulus )e,ister
4+""(
Si0e in btes o# each #rame bu##er
The controller uses this re$ister to :now when it is #inished readin$ a #rame
bu##er" It must be written with a !alid !alue be#ore startin$ the controller"
Current 'ource )e,ister
4+""(
Base address o# #rame bu##er
This is a read onl re$ister that contains the base address o# the #rame bu##er
presentl bein$ read and sent to the !ideo DAC" So#tware ma want to read this
re$ister be#ore writin$ !ideo data in order to ma:e sure it is not writin$ to a #rame
bu##er which is in the middle o# bein$ displaed" =ritin$ to a #rame bu##er that is
currentl bein$ displaed can cause arti#acts and #lic:erin$ in the !ideo ima$e"
Avalon Read Master
The A!alon read master reads !ideo data #rom the address stored in the DMA Source
/e$ister" This bloc: is essentiall the DMA en$ine o# the VGA controller" The read
master reads data until it reaches the address stored in the DMA Modulus /e$ister2 then
reloads the !alue in DMA Source /e$ister and starts displain$ another #rame"
The read master will onl read data when there is room in the ;I;O to hold it2 and when
the controller has been enabled b the Start bit in the Sla!e Control re$ister"
The read master alwas reads 4,.bit words2 re$ardless o# the color depth o# the actual
!ideo data" This allows the data to be read more e##icientl2 consumin$ less bandwidth
5#ewer ccles6 o# the #rame bu##er memor2 which ma be hea!il used b the sstem"
The +& or ,'.bit pi)els are e)tracted #rom the 4,.bit data b another lo$ic bloc:2 the data
width con!erter"
Dual Clock FIFO
The dual cloc: ;I;O ser!es two purposes" ;irst2 it acts as the cloc:.domain brid$e
between the sstem cloc: and the VGA cloc:" Second2 it ser!es as the controller DMA?s
throttlin$ mechanism" =hen the ;I;O reaches a certain write threshold2 it si$nals the
DMA to stop writin$ data to it until the VGA se@uencer ma:es some room b emptin$
some data #rom the ;I;O and displain$ it"
Additionall2 i# the sstem suddenl becomes !er bus and access to the #rame bu##er
memor is temporaril restricted2 the ;I;O stores enou$h !ideo data #or the VGA
se@uencer to continue displain$ pi)els until the #rame bu##er memor can a$ain be read2
at which point the ;I;O is re#illed"
The depth o# the dual cloc: ;I;O is con#i$urable in the controller?s SOPC Builder
component wi0ard"
VGA Signal Sequencer
This bloc: ensures that the pi)el and control si$nals dri!in$ the e)ternal !ideo DAC
con#orm to the proper timin$ constraints" 3ori0ontal and Vertical snc si$nals are sent at
!arious inter!als2 dependin$ on which resolution mode the controller is displain$"
The VGA si$nal se@uencer also controls reads #rom the dual cloc: ;I;O"
Data Width Converter
Video data is alwas stored in the ;I;O as 4,.bit words" 3owe!er2 the !ideo DAC
re@uires ,' bit color inputs2 * bits each #or /ed2 Green2 and Blue" The data width
con!erter bloc: is responsible #or con!ertin$ the 4,.bit !ideo data read #rom the ;I;O
into ,'.bit pi)els"
The VGA controller supports 4 color depth #ormats2 +&.bit2 ,'.bit pac:ed2 and ,'.bit
unpac:ed" The data width con!erter can con!ert !ideo data #rom 4,.bit words to an o#
those depth #ormats"
"#-!it color
This is the simplest o# the color #ormats" >ach 4,.bit word read #rom the ;I;O contains
e)actl two pi)els" The width con!erter simpl reads the ;I;O once #or e!er two
pi)els2 then separates the pi)els b splittin$ the 4,.bit word in hal#" The +&.bit pi)el data
is then up.con!erted to the ,'.bit color that the !ideo DAC re@uires"
The ad!anta$es to this mode are that !ideo data can be read @uic:l b the DMA since it
can trans#er two pi)els per 4,.bit transaction" The disad!anta$e o# this mode is that onl
&A2A4& colors can be represented"
2$-!it un-ac.ed color
This #ormat is also #airl strai$ht #orward" >ach 4,.bit word read #rom the ;I;O contains
e)actl one ,'.bit pi)el2 and * unused bits" This means that #or each pi)el2 * bits o#
memor are wasted" In this mode2 the width con!erter reads one 4,.bit word #rom the
;I;O #or e!er pi)el2 then throws awa * bits"
The ad!anta$es o# this mode are that +&2---2,+& colors can be represented2 and pi)el.
writin$ routines in so#tware are simpler and #aster than the are in ,'.bit pac:ed mode"
The disad!anta$es o# this mode are that a bte o# memor is wasted #or e!er pi)el
displaed" In sstems with limited memor resources2 this could be a si$ni#icant issue"
2$-!it -ac.ed color
This is the most complicated color depth mode o# the three supported" >ach pi)el is
stored in three consecuti!e btes2 and all pi)els are stored conti$uousl in memor with
no wasted space between them" That means #or e!er three 4,.bit words that are read
#rom the ;I;O2 there e)ist #our pi)els" A $i!en 4,.bit word read #rom the ;I;O could
contain a #ull pi)el2 plus one bte #rom a nei$hborin$ pi)el2 or it could contain two btes
each #rom the two nei$hborin$ pi)els" ;urthermore2 pi)els can be spread across multiple
4,.bit words2 meanin$ the width con!erter must hold on to old data so it can reconstruct
pi)els #rom di##erent 4,.bit words" The width con!erter bloc: accomplishes this b a
se@uence o# multiple)in$ btes #rom current and past words read #rom the ;I;O" 1uc:il
the user does not ha!e to worr about an o# thisB the controller transparentl e)tracts the
correct pi)els #rom the data stream"
The ad!anta$es o# ,'.bit pac:ed mode are that +&2---2,+& colors can be represented2 and
less memor is needed per #rame than #or ,'.bit unpac:ed mode" The disad!anta$es are
that pi)el writin$ routines in so#tware can be complicated and slow since each pi)el must
be written as a series o# btes2 not one 4,.bit word transaction"
Resolution Modes
The VGA controller supports three resolution modes2 &'( ) '*(2 *(( ) &((2 and +(,' )
-&*" The resolution mode o# the controller is con#i$urable in the VGA controller?s SOPC
Builder component wi0ard"
The primar di##erences between these are the timin$ o# the snc and control si$nals2 and
the cloc: speed that must be pro!ided to the VGA si$nal se@uencer" The snc si$nal
timin$ is automaticall handled b the VGA controller2 but the user is responsible #or
pro!idin$ a cloc: o# the proper #re@uenc to the VGA controller"
A si$nal named C!$a<cl:8 e)ists at the top le!el o# the VGA controller" =hen a sstem
is $enerated in SOPC Builder2 this si$nal will appear at the sstem?s top le!el" Dou must
connect this si$nal to a cloc: o# the correct #re@uenc" A P11 can be used to pro!ide this
cloc:" The #ollowin$ table lists the cloc: #re@uencies needed #or the di##erent resolution
modes"
Resolution Mode Clock Fre"uenc# Re"uired $# VGA Controller
&'( ) '*( ,A M30
*(( ) &(( '( M30
+(,' ) -&* &A M30
Doule Fra!e "u##ers
The VGA controller and included dri!er both support usin$ double #rame bu##ers" This
allows the VGA controller to displa one #rame bu##er while the CPE constructs the ne)t
one" Double bu##erin$ pre!ents the #lic:erin$ caused b displain$ and writin$ to the
same #rame bu##er simultaneousl"
Usin, the VGA Controller in 'O/C Builder
The #ollowin$ topics relate to instantiatin$ and con#i$urin$ the VGA Controller in SOPC
Builder
SOPC "uilder Co!$onent Wi%ard
The VGA Controller SOPC Builder component wi0ard is where most o# the controller?s
options are set" The #ollowin$ options are con#i$urable in the VGA Controller SOPC
Builder component wi0ard%
Color Depth
+&.bit
,'.bit unpac:ed
,'.bit pac:ed
DMA Transaction Tpes
Ese Pipelined /eads
Ese Burstin$ /eads 5not et supported6
FIFO Depth
/epresented in 4,.bit words" Can be selected to be an e!en multiple o# ,
#rom +,* to &AA4&"
!esolution
&'( ) '*(
*(( ) &((
+(,' ) -&*
Frame "u##er
Sin$le ;rame Bu##er
Double ;rame Bu##er
;i$ure , shows the VGA Controller?s SOPC Builder component wi0ard
Figure % &he VGA Controller 'O(C Builder Com)onent !i*ard
Aritration share settings in an SOPC "uilder s&ste!
=hen usin$ the VGA Controller in an SOPC Builder sstem2 it is important that the read
master port is $i!en a lar$e arbitration share #or the memor5s6 holdin$ the #rame bu##ers"
This will help ensure that the VGA controller is ne!er $ets so star!ed #or memor
bandwidth that the ;I;O becomes empt" I# the ;I;O becomes empt2 the VGA
se@uencer will li:el lose snc and will be unable to reco!er unless the controller is reset
b disablin$ it2 then re.enablin$ it"
A--endi0 A1 +ancelot Nios II Deelo-2ent Board
/inouts
This table lists the pinouts #or the 1ancelot card on !arious Nios II De!elopment boards"
/)O*O "
+ancelot si,nal -roto" -ins "c23 2c34 2s#3&)O5'
B#$% 11&2' ()*_G1+ ()*_,1- ()*_G2
B#1% 11&2- ()*_.1/ ()*_,10 ()*_.1
B#2% 11&20 ()*_G1- ()*_,21 ()*_.2
B#1% 11&12 ()*_.12 ()*_32/ ()*_,+
B#+% 11&11 ()*_G1' ()*_,2+ ()*_,1
B#/% 11&11 ()*_.1- ()*_322 ()*_31
B#2% 11&12 ()*_.10 ()*_421 ()*_,1
B#'% 11&1/ ()*_.1' ()*_M21 ()*_32
G#$% 11&1 ()*_51- ()*_62/ ()*_51
G#1% 11&+ ()*_510 ()*_72+ ()*_52
G#2% 11&/ ()*_D1- ()*_721 ()*_D2
G#1% 11&2 ()*_D10 ()*_321 ()*_D1
G#+% 11&' ()*_D1' ()*_32$ ()*_61
G#/% 11&- ()*_D2$ ()*_72/ ()*_62
G#2% 11&0 ()*_61' ()*_722 ()*_61
G#'% 11&1$ ()*_71' ()*_*1- ()*_6+
M1 12&11 ()*_,1/ ()*_822 ()*_3/
M2 12&12 ()*_91- ()*_82/ ()*_32
R#$% 11&2/ ()*_G10 ()*_.22 ()*_G1
R#1% 11&21 ()*_G2$ ()*_.2/ ()*_3+
R#2% 11&21 ()*_G1/ ()*_32+ ()*_31
R#1% 11&1- ()*_G12 ()*_321 ()*_.+
R#+% 11&1' ()*_72$ ()*_.2+ ()*_.1
R#/% 11&12 ()*_710 ()*_.21 ()*_G+
R#2% 11&1/ ()*_71/ ()*_G22 ()*_G1
R#'% 11&1+ ()*_712 ()*_G2/ ()*_7+
blank_n 11&11 ()*_610 ()*_G2+ ()*_71
hsync 11&1' ()*_.2$ ()*_R1' ()*_,2
sync_n 11&12 ()*_61- ()*_G21 ()*_72
sync_t 11&11 ()*_71- ()*_(1- ()*_71
vsync 11&10 ()*_312 ()*_(1' ()*_:2
vga_clk 11&11 ()*_721 ()*_,2
audio_right 12&' ()*_.1+ ()*_R10 ()*_G2
audio_left 12&/ ()*_310 ()*_41' ()*_M1
/)O*O 2
+ancelot si,nal -roto2 -ins "c23 2c34 2'#3&)O5'
B#$% 12&2' ()*_412 ()*_;B2$ ()*_;;+
B#1% 12&2- ()*_411 ()*_;52$ ()*_;B1
B#2% 12&20 ()*_912 ()*_;72$ ()*_;B+
B#1% 12&12 ()*_9- ()*_;D10 ()*_;51
B#+% 12&11 ()*_<12 ()*_;62$ ()*_;52
B#/% 12&11 ()*_<- ()*_;510 ()*_;D1
B#2% 12&12 ()*_80 ()*_;;1- ()*_<'
B#'% 12&1/ ()*_=0 ()*_;;1' ()*_;D2
G#$% 12&1 ()*_41/ ()*_;62+ ()*_42
G#1% 12&+ ()*_91/ ()*_421 ()*_42
G#2% 12&/ ()*_<1/ ()*_822 ()*_=1
G#1% 12&2 ()*_=1/ ()*_;721 ()*_=2
G#+% 12&' ()*_81/ ()*_;621 ()*_81
G#/% 12&- ()*_81+ ()*_;522 ()*_82
G#2% 12&0 ()*_=1+ ()*_;B21 ()*_91
G#'% 12&1$ ()*_<1+ ()*_;D21 ()*_92
M1 1/&11 ()*_811 ()*_<12 ()*_<12
M2 1/&12 ()*_=11 ()*_;51' ()*_;D11
R#$% 12&2/ ()*_=12 ()*_;621 ()*_;;1
R#1% 12&21 ()*_812 ()*_;721 ()*_<+
R#2% 12&21 ()*_411 ()*_=1- ()*_<1
R#1% 12&1- ()*_R11 ()*_=1' ()*_9+
R#+% 12&1' ()*_<11 ()*_910 ()*_91
R#/% 12&12 ()*_911 ()*_81- ()*_;B2
R#2% 12&1/ ()*_=11 ()*_;622 ()*_;B1
R#'% 12&1+ ()*_811 ()*_;722 ()*_;;2
blank_n 12&11 ()*_R1+ ()*_;D21 ()*_;;1
hsync 12&1' ()*_40 ()*_91' ()*_90
sync_n 12&12 ()*_41+ ()*_;521 ()*_<2
sync_t 12&11 ()*_91+ ()*_;D22 ()*_<1
vsync 12&10 ()*_R0 ()*_81' ()*_91$
vga_clk 1'&11 ()*_:- ()*_72$ ()*_,'
audio_right 1/&' ()*_=1$ ()*_;610 ()*_812
audio_left 1/&/ ()*_90 ()*_;51- ()*_<0