In the Name Of God

Custom Implementation
of DSP Systems
(Winter 2013)
Assignment 5 - Digital FIR Filter
Implementation Using Xilinx ISE

Description 5-1-
In this assignment, you will get familiar with FIR filter
structures and Xilinx ISE Core Generator and DSP48A1 slice in
Spartan6 FPGAs. Nowadays, FPGAs have special function
blocks to implement signal processing systems as DSP
functions and you should be able to use them for your goals.
Details 5-2-
Equation (1) shows the basic equation for a single-
channel FIR filter. Fig. 1 shows conventional tapped delay line
implementation of FIR filters [1]:
(1)

1
0
) ( ) ( ) (
N k
k
k n x k h n y

Fig. 1: Conventional Tapped Delay Line FIR Filter [1].

Due Date: April 06, 2013
Teacher Assistant:
Siamack Beig Mohammadi
siamackbm@yahoo.com
Silicon Intelligent Laboratory
SILab



Digital FIR Filter Implementation Using Xilinx ISE
2
First of all, look at customized FIR filter structures for FPGAs in [1-2] and shortly
compare and report their architectures with respect to their features.
Then look at DSP48A1 user guide [2] and analyze its architecture and find and report
the features you need to configure. Also, explain how to configure the slice to do your
desired function.
Now, you should be able to show how to map a filter structure to one or more
DSP48A1 slices to have a FIR filter. In this assignment you will configure DSP48A1
slice using Xilinx ISE Core Generator.
Step 1: In this step FIR filter will be designed by MATLAB and implemented entirely
using Xilinx ISE Core Generator. Follow these steps:
a. Using MATLAB filter design and analysis tool (FDATool) achieve FIR filter
coefficients according to low-pass filter specifications in Assignment 3. Quantize
the filter coefficients with 16 bits and best-precision fractional length. Export
quantized coefficients to a file.
b. In order to import the coefficients youll need a .coe file with the format described
in [4]. Change the exported file to match this format.
c. Create a project in Xilinx ISE and use FIR compiler in IP cores from Xilinx Core
Generator following this path: Digital Signal Processing -> Filters -> FIR Compiler.
Import the coefficients and choose non-symmetric structure. You can observe the
frequency response of filter with FIR compiler tool according to your coefficients.
Set sample period equal to clock cycle.
d. Repeat the previous step again and choose symmetric structure. Note that
Transpose Multiply Accumulate architecture doesnt support symmetric
structure. Use Systolic Multiply Accumulate structure for both structures.
e. Please note that you should configure filter options such as word length,
coefficient width, and according to your FIR filter design in MATLAB. In the
Implementation Details tab, observe the cycle latency which shows the delay
between first input to the filter and first valid output. Report and compare
estimated resource usage and cycle latency in symmetric and non-symmetric
implementations. Can you describe how clock latency is calculated? For input and
coefficient buffers (memory), FIR compiler gives you a few options such as
distributed buffers or a block of memory. It is important to know that a circular
buffer is a suitable option for FIR implementation.
Step 2: In this step you should instantiate just one DSP48A1 slice (in IP cores from
Core Generator follow this path: Basic Elements -> DSP48 Macro) to build previous
filter with your own design (symmetric structure). For this single-MAC structure,
youll need to add a coefficient ROM, a circular data buffer (RAM), and a controller in
Verilog to do the filtering operation (Hint: use pre-adder in DSP48A1). Fig. 2 shows
corresponding top-level block diagram (with the exception of pre-adder which is not
included in DSP48 slice but youll use it in DSP48A1).

Digital FIR Filter Implementation Using Xilinx ISE
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Fig. 2: Symmetric Single-MAC FIR Filter [1].
Follow steps below:
a. Create a new project and add DSP48A1 slice using Core Generator. Report applied
settings. Which instruction have you set for this macro?
b. For the memory elements use Block Memory (in IP cores from Core Generator
follow this path: Memories & Storage Elements -> RAMs & ROMs -> Block Memory
Generator). For the coefficients create a single port ROM module and initialize it
with your coefficients. Remember to change the exported coefficients file
according to the format specified in [5] and remove half of them (due to
symmetry). Select and report proper memory width and depth.
c. Select dual port RAM structure for the data RAM module with read-first property.
Note that circular operation of data RAM is achieved via control unit and proper
selection of read addresses. Select and report proper memory width and depth.
d. Create a Verilog module for the control unit. It should control reset, read/write
address, and write enable signals for your IP cores. Sample code for a smaller
block will be provided.
e. Create a top-level Verilog module and instantiate previous modules to build the
complete structure of FIR filter. View HDL Instantiation Template in the Design
tab under Design Utilities would be useful.
Step 3: Using your controller in previous step, write a Verilog description for
Multiply-Accumulation (MAC) unit and use it to do the same operation of previous
step (symmetric structure). Synthesize the description and with schematic viewer
observe the mapping result and compare observation with previous step (Select top-
level module -> Synthesize -> View Technology Schematic). Refer to [6,7] for help on
Verilog hardware description language or just google it.
Step 4: Now the filters will be tested. Follow these steps:
a. Develop input file in text format with MATLAB. A .wav file with high-frequency
noise components will be given. Sampling rate and dynamic range are already set
to proper values for this file. You can do quantization with MATLAB fixed-point
numeric object. Apply 16-bit quantization to inputs. Check these codes:

Digital FIR Filter Implementation Using Xilinx ISE
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b. Filter quantized input data (with filter function) and extract expected output
text file. Use output bit-widths set in Xilinx ISE for output qantization. Remember
to use 16-bit quantized coefficients for filtering.
c. Develop a self-checking testbench able to read input samples from a text file,
apply them to an instance of implemented structure, and compare the output with
expected output read from a text file. You can consider cycle delay by adding
initial zero values in expected output file. Your testbench should be changed a bit
for single-MAC structure. Sample code will be provided.
d. The testbench must create a text file which includes the simulation outputs.
Import this file to MATLAB and plot output spectrum. You can use script below to
import text file to MATLAB (apply any change needed):

Test all the different structures youve developed. Show output data waveform along
with expected value for one sample (Just for one of the simulations).Note that only
input signal and coefficients have been quantized in MATLAB and additions and
multiplications are done perfectly. Justify why we would expect exact match between
MATLAB and ISE simulation outputs? (Hint: check internal bit-width of DSP48A1
module)
Report Inclusion 5-3-
Write your observations in your report and explain all steps you did in your experiment,
expected comparisons and explanations. Report all the described and requested steps,
any setting you change for IP cores, and answer all questions. Also append your
testbench and m-files developed in MATLAB and clearly explain the final results and
your experiences.
Use reference standard format to write your reports.


Digital FIR Filter Implementation Using Xilinx ISE
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References 5-4-
[1] Xilins, XtremeDSP for Virtex-4 FPGAs User Guide, May 15, 2008.
[2] Xilinx, Spartan-6 FPGA DSP48A1 Slice User Guide, August 13, 2009.
[3] Xilinx, ISE Core Generator User Guide, 2010.
[4] LogiCORE IP FIR Compiler v5.0, Product Specification/ auth. Xilinx. - [s.l.]: Xilinx
Inc., 2011-DS534.
[5] LogiCORE IP Block Memory Generator v4.2, Product Specification / auth. Xilinx. -
[s.l.]: Xilinx Inc., 2010 -DS512.
[6] Wikipedia: The Free Encyclopedia, Verilog, [Retrieved: March 10, 2013],
Available: http://en.wikipedia.org/wiki/Verilog
[7] D. K. Tala, Asic-World: Online knowledge source for hardware designers, 2013.
Available: http://www.asic-world.com/verilog/index.html.



Good Luck
Happy Norouz!
Monday, March 11, 2013