Simple CMOS OPAMPS PDF

Lecture 440 Simple MOSFET Op Amps (12/10/01) Page 440-1
ECE 4430 - Analog Integrated Circuits and Systems P.E. Allen - 2001
LECTURE 440 SIMPLE MOSFET OP AMPS
(READING: Text-Sec. 6.4 and 6.8)
INTRODUCTION
The objective of this presentation is:
1.) Illustrate the analysis of MOS op amps
2.) Prepare for the design of MOS op amps
Outline
Simple Op Amps
Two-stage
Folded-cascode
Summary
SIMPLE TWO-STAGE OP AMPS
Two-Stage CMOS Op Amp
Circuit:
DC Conditions:
I
5
= I
bias
, I
1
= I
2
= 0.5I
5
= 0.5I
bias
,
I
7
= I
6
= nI
Bias
V
icm
(max) = V
DD
- V
SG3
+ V
T1
V
icm
(min) = V
SS
+V
DS5
(sat) + V
GS1
V
out
(max) = V
DD
- V
SD6
(sat)
V
out
(min) = V
SS
+ V
DS7
(sat)
Notice that the output stage is class A
I
sink
= I
7
and I
source
=
K
N
W
6
2L
6
(V
DD
-V
SS
-V
T
)
2
- I
7
I
Bias
Fig. 440-01
-
+
v
in
M1 M2
M3 M4
M5
M6
M7
v
out
V
DD
V
SS
C
L
-
+
V
SG6
-
+
V
SG4
I
4
I
5
I
7
I
6
I
3
I
42
I
1
M8
DC Balance Conditions for the Two-Stage Op Amp
For best performance, keep all transistors in
saturation.
M4 is the only transistor that cannot be forced into
saturation by internal connections or external
voltages.
Therefore, we develop conditions to force M4 to be
in saturation.
1.) First assume that V
SG4
= V
SG6
. This will
cause proper mirroring in the M3-M4 mirror.
Also, the gate and drain of M4 are at the same
potential so that M4 is guaranteed to be in
saturation.
2.) Let S
i

W
i
L
i
, if V
SG4
= V
SG6
, then I
6
=
_ S
6
S
4
I
4
3.) However, I
7
=
_ S
7
S
5
I
5
=
_ S
7
S
5

,
_ 2I
4

4.) For balance, I
6
must equal I
7

S
6
S
4
=
2S
7
S
5
which is called the balance conditions
5.) So if the balance conditions are satisfied, then V
DG4
= 0 and M4 is saturated.
-
+
v
in
M1 M2
M3 M4
M5
M6
M7
v
out
V
DD
V
SS
V
Bias
+
-
C
c
C
L
-
+
V
SG6
-
+
V
SG4
I
4
I
5
I
7
I
6
Fig. 440-02
Small-Signal Performance of the Two-Stage CMOS Op Amp
I
Bias
Fig. 440-03
-
+
v
in
M1 M2
M3 M4
M5
M6
M7
v
out
V
DD
V
SS
C
L
-
+
V
SG6
-
+
V
SG4
I
4
I
5
I
7
I
6
I
3
I
42
I
1
M8
x1 x1 xn
-g
m1
v
in
2
C
M
1
g
m3
g
m4
v
1
g
m1
v
in
2
C
1
r
ds2
||r
ds4
g
m6
v
2
r
ds6
||r
ds7
C
L
v
1 v
2
C
c
+
-
v
out
r
ds1
||r
ds3
g
m1
v
in
r
ds2
||r
ds4
g
m6
v
2
r
ds6
||r
ds7
C
II
v
2
C
c
+
-
v
out C
I
+
-
v
in
g
m3
> g
ds2
+g
ds4
g
m3
C
M
> GB
C
c
Small-Signal Performance of the Two-Stage CMOS Op Amp
Summary of the small signal performance:
Midband performance-
A
o
= g
mI
g
mII
R
I
R
II
g
m1
g
m6
(r
ds2
||r
ds4
)(r
ds6
||r
ds7
), R
out
= r
ds6
||r
ds7
, R
in
=
Roots-
Zero =
g
mII
C
c
=
g
m6
C
c
Poles at p
1

-1
g
mII
R
I
R
II
C
c
=
-(g
ds2
+g
ds4
)(g
ds6
+g
ds7
)
g
m6
C
c
and p
2

-g
mII
C
II

-g
m6
C
L
Assume that g
m1
= 100S, g
m6
= 1mS, r
ds2
= r
ds4
= 2M r
ds6
= r
ds7
= 0.5M, C
c
= 5pF
and C
L
= 10pF:
A
o
= (100S)(1M)(1000S)(0.25M) = 25,000V/V, R
in
= , R
out
= 250k
Zero = 1000S/5pF = 2x10
8
rads/sec or 31.83MHz,
p
1
=
-1
(1mS)(1M)(0.25M)(5pF)
= -800 rads/sec or 127.3Hz,
GB = 3.178MHz
and p
2
= (-1000S/10pF) = 10
8
rads/sec or 15.915MHz
Fig. 440-04
-10
8
2x10
8
-8x10
2
j

Slew Rate of a Two-Stage CMOS Op Amp
Remember that slew rate occurs when currents flowing in a capacitor become limited and
is given as
I
lim
= C
dv
C
dt
where v
C
is the voltage across the capacitor C.
-
+
v
in
>>0
M1 M2
M3 M4
M5
M6
M7
v
out
V
DD
V
SS
V
Bias
+
-
C
c
C
L
I
5
Assume a
virtural
ground
I
7
I
6 I
5
I
CL
Positive Slew Rate
-
+
v
in
<<0
M1 M2
M3 M4
M5
M6
M7
v
out
V
DD
V
SS
V
Bias
+
-
C
c
C
L
I
5
Assume a
virtural
ground
I
7
I
6
=0
I
5 I
CL
Negative Slew Rate Fig. 440-05
SR
+
= min
]
1
1
1 I
5
C
c
,
I
6
-I
5
-I
7
C
L
=
I
5
C
c
because I
6
>>I
5
SR
-
=

min
]
1
1
1 I
5
C
c
,
I
7
-I
5
C
L
=
I
5
C
c
if I
7
>>I
5
.
Therefore, if C
L
is not too large and if I
7
is significantly greater than I
5
, then the slew rate
of the two-stage op amp should be,
SR =
I
5
C
c

Folded Cascode, CMOS Op Amp
Circuit:
Comments:
The bias currents, I
4
and I
5
, should
be designed so that I
6
and I
7
never
become zero (i.e. I
5
=I
6
=1.5I
3
)
This amplifier is nearly balanced
(would be exactly if R
A
was equal
to R
B
)
Self compensating
Poor noise performance, the gain occurs at the output so all intermediate transistors
contribute to the noise along with the input transistors. (Some first stage gain can be
achieved if R
A
and R
B
are greater than g
m1
or g
m2
.
R
B
-
+
v
in
M1 M2
M4 M5
M6
M11
v
out
V
DD
V
SS
V
Bias
+
-
C
L
R
2
M7
M8 M9
M10
M3
Fig. 440-06
I
3
I
4
I
5
I
6
I
7
I
1
I
2
R
1
M13
M14
M12
R
A
A
B
Small-Signal Analysis of the Folded Cascode Op Amp
Model:
Recalling what we
learned about the
resistance looking into
the source of the
cascode transistor;
R
A
=
r
ds6
+R
2
+(1/g
m10
)
1 + g
m6
r
gs6

1
g
m6
and R
B
=
r
ds7
+ R
II
1 + g
m7
r
ds7

R
II
g
m7
r
ds7
where R
II
g
m9
r
ds9
r
ds11
The small-signal voltage transfer function can be found as follows. The current i
10
is
written as
i
10
=
-g
m1
(r
ds1
||r
ds4
)v
in
2[R
A
+ (r
ds1
||r
ds4
)]

-g
m1
v
in
2

and the current i
7
can be expressed as
i
7
=
g
m2
(r
ds2
||r
ds5
)v
in
2
]
1
1
1 R
II
g
m7
r
ds7
+ (r
ds2
||r
ds5
)
=
g
m2
v
in
2
_
1 +
R
II
(g
ds2
+g
ds5
)
g
m7
r
ds7
=
g
m2
v
in
2(1+k)
where k =
R
II
(g
ds2
+g
ds4
)
g
m7
r
ds7
The output voltage, v
out
, is equal to the sum of i
7
and i
10
flowing through R
out
. Thus,
v
out
v
in
=
_
g
m1
2
+
g
m2
2(1+k)
R
out
=
_ 2+k
2+2k
g
mI
R
out
g
m1
v
in
2
r
ds1
r
ds4
r
ds6
g
m6
v
gs6
R
2
+
R
A
g
m2
v
in
2
r
ds2
r
ds5
r
ds7
g
m7
v
gs7
R
II
R
B
i
10
i
10
+
-
v
gs7
+
-
v
gs6
Fig. 440-07
+
-
v
out
i
7
1
g
m10
Frequency Response of the Folded Cascode Op Amp
The frequency response of the folded cascode op amp is determined primarily by the
output pole which is given as
p
out
=
-1
R
out
C
out

where C
out
is all the capacitance connected from the output of the op amp to ground.
All other poles must be greater than GB = g
m1
/C
out
. The approximate expressions for
each pole is
1.) Pole at node A: p
A
-1/R
A
C
A
2.) Pole at node B: p
B
-1/R
B
C
B
3.) Pole at drain of M6: p
6

-1
(R
2
+1/g
m10
)C
6

4.) Pole at source of M8: p
8
-g
m8
/C
8
5.) Pole at source of M9: p
9
-g
m9
/C
9
6.) Pole at gate of M10: p
10
-g
m10
/C
10
where the approximate expressions are found by the reciprocal product of the resistance
and parasitic capacitance seen to ground from a given node. One might feel that because
R
B
is approximately r
ds
that this pole might be too small. However, at frequencies where
this pole has influence, C
out
, causes R
out
to be much smaller making p
B
also non-dominant.
Example 1 - Folded Cascode, CMOS Op Amp
Assume that all g
mN
= g
mP
= 100S, r
dsN
= 2M, r
dsP
= 1M, and C
L
= 10pF. Find all
of the small-signal performance values for the folded-cascode op amp.
R
II
= 0.4G, R
A
= 10k, and R
B
= 4M k =
0.4x10
9
(0.3x10
-6
)
100
= 1.2
v
out
v
in
=
_ 2+1.2
2+2.2
(100)(57.143) = 4,354V/V
R
out
= R
II
||[g
m7
r
ds7
(r
ds5
||r
ds2
)] = 400M||[(100)(0.667M)] = 57.143M
|p
out
|

=
1
R
out
C
out
=
1
57.143M10pF
= 1,750 rads/sec. 278Hz GB = 1.21MHz
Comments on the Folded Cascode, CMOS Op Amp:
Good PSRR
Good ICMR
Self compensated
Can cascade an output stage to get extremely high gain with lower output resistance
(use Miller compensation in this case)
Need first stage gain for good noise performance
Widely used in telecommunication circuits where large dynamic range is required
SUMMARY
Two stage op amp gives reasonably robust performance as an on-chip op amp
DC balance conditions insure proper mirroring and all transistors in saturation
Slew rate of the two-stage op amp is I
5
/C
c
Folded cascode op amp offers wider input common voltage range
Folded cascode op amp is a self-compensated op amp because of the dominant pole at
the output

Simple CMOS OPAMPS PDF

Hochgeladen von

Dokumentinformationen

Originaltitel

Copyright

Verfügbare Formate

Dieses Dokument teilen

Dokument teilen oder einbetten

Freigabeoptionen

Stufen Sie dieses Dokument als nützlich ein?

Sind diese Inhalte unangemessen?

Copyright:

Verfügbare Formate

Simple CMOS OPAMPS PDF

Hochgeladen von

Copyright:

Verfügbare Formate

Lecture 440 Simple MOSFET Op Amps (12/10/01) Page 440-1

Lecture 440 Simple MOSFET Op Amps (12/10/01) Page 440-6

Das könnte Ihnen auch gefallen