Sie sind auf Seite 1von 58

EI332-LINEAR & DIGITAL INTEGRATED CIRCUITS

UNIT 1
FABRICATION OF INTEGRATED CIRCUITS
1.What is an integrated circuit?
The integrated circuit or IC is a miniature , low cost electronic circuit consisting of active and
passive components that are irreparably joined together on a single crystal chip of silicon.
.!ist the advantages of IC over discrete component circuit.
"iniature and hence increased e#uipment density.
Cost reduction due to batch processing
Increased system reliability due to the elimination of soldered joints.
Improved functional performance
"atched devices
Increased operating speeds
$eduction in power consumption.
%.&roadly classify IC's.
(igital ICs
!inear ICs
).*how the classification of ICs.
Integrated circuits
"onolithic circuits +ybrid circuits
&ipolar ,nipolar
-.n junction (ielectric "/*01T 201T
isolation isolation
3.What is a monolithic circuit?
It means a circuit fabricated from a single stone or a single crystal.

4.What are the ) distinct layers if IC?
!ayer no.15r )66 m7, is a -.type silicon substrate upon which the IC is fabricated.
!ayer no.5r 3.3 m7, is a thin n.type material grown as a single crystal e8tensin of the substrate
using epita8ial deposition techni#ues.9ll active and passive components are fabricated within this
layer using selective diffusion of impurities.
!ayer no.%56.6. m7, is a very thin *io

layer for preventing diffusion of
impurities wherever not
re#uired using photo lithographic techni#ue.
!ayer no.)5r 1 m7, is an aluminium layer used for obtaining interconnection
between components.
:.What are the basic processes used to fabricate ICs using planar technology?
o *ilicon wafer5substrate7preparation
o 1pita8ial growth
o /8idation
o -hotolithography
o (iffusion
o Ion implantation
o Isolation techni#ue
o "etalli;ation
o 9ssembly processing and pac<aging
=.!ist out the steps used in the preparation of si.wafers.
Crystal growth and doping
Ingot trimming and grinding
Ingot slicing
Wafer polishing and etching
Wafer cleaning
>.Write the basic chemical reaction used for the epita8ial growth of pure silicon.
The basic chemical reaction used for the epita8ial growth of pure silicon is
the hydrogen
reduction of silicon tetrachloride.

166
o
c
*iCl
)
? +

*i ? )+Cl
16.What are the important properties of *io

?
*io

has the property of preventing the diffusion of almost all impurities through it.It
serves very important purposes.
*io is an e8tremely hard protective coating and unaffected by almost all reagents e8cept by
+Cl.Thus it stands against any contamination.
&y selective etching of *io

,diffusion of impurities through carefully defined windows in the
*io

can be accomplished to fabricate various components.
11.Why is the o8idation process called the thermal o8idation?
&ecause high temperature is used to grow the o8ide layer.
1.What are the process involved in photolithography?
-hotographic mas<
-hoto etching
1%.What is the main purpose of photoetching?
,sed for the removal of *io

from desired regions so that the desired impurities can be


diffused.
1).@ame the technologies used for the fabricators or ICs
"onolithic technology
+ybrid technology
13.18plain the word A1pita8yB.
It means arranging atoms in single crystal fashion upon a single crystal substrate,so that the
resulting layer is an e8tension of the substrate crystal structure.
14.18plain the process of o8idation.
The silicon wafers are stac<ed up in a #u#rt; boat and then inserted into
#uart; furnace
tube.The *i.wafers are raised to a high temperature in the range of >36 to 1136
o
C and at the same
time,e8posed to a gas containing /

or +

/ or both.The chemical reaction is


*i ? +

6 *i/

? +

1:.What are the advantages of ion implantation techni#ue?


It is performed at low temperature.Therefore previously diffused regions have a
lesser tendency for lateral spreading.
In diffusion process ,temperature has to be controlled over a large area inside the
oven,whereas in ion implantation techni#ue,accelerating potential and the beam
content are dielectrically controlled from outside.
1=.!ist any isolation techni#ues.
-.n junction isolation
(ielectric isolation
1>.Write short notes on dielectric isolation.
In dielectric isolation, a layer of solid dielectric such as silicon di o8ide or
ruby
completely surrounds each component, thereby producing isolation ,both electrical and
physical.This isolation dielectric layer is thic< enough so that its associated capacitance is
negligible.9lso,it is possible to fabricate both p.n.p and n.p.n transistor within the same silicon
substrate.
6."ention the use of dielectric isolation
,sed for fabricating professional grade ICs re#uired for speciali;ed
applications
vi;.aerospace and military,where higher cost is justified by superior performance.
1.What is metalli;ation?
The process to produce a thin metal film layer that will serve to ma<e interconnection of the
various components on the chip.
.What are the main advantages of using aluminium for metalli;ation?
o It is relatively a good conductor
o It is easy to deposit aluminium films using vacuum deposition.
o 9luminium ma<es good mechanical bonds with silicon.
o 9luminium forms low resistance,non.rectifying contact with p.type silicon and the
heavily doped n.type silicon.
%.@ame the % different pac<age configurations.
T 6.3 glass metal pac<age
Ceramic flat pac<age
(ual in line5ceramic or plastic type7
).What are the various steps involved in the fabrication of a typical circuit?
Wafer preparation
1pita8ial growth
/8idation
Isolation diffusion
&ase diffusion
1mitter diffusion
9luminium metalli;ation
3.What are the various devices which constitute a monolithic circuit?
Transistors
(iodes
$esistors
Capacitors
Inductors
4.What is the main structural difference that ma<es integrated transistor poorer than discrete
transistor?
The structural difference ma<es an integrated transistor poorer than discrete transistor in
waysC
Collector contact being at the top increases the collector current path thereby
increasing the collector series resistance and non.Dce5sat7of the device.
In the integrated transistor ,additional parasitic capacitance appears between collector
and substrate as substrate is held at negative potential.
:.18plain why buried layer is used?
The higher collector series resistance of an integrated transistor can be easily
reduced by a
process <nown as A buried layerB.In this, heavily doped n? region is sandwiched between the
n.type epita8ial collector and p.type substrate. This buried n? region provides a low resistivity
current path from the active collector region5n type layer7 to the collector constant5n? contact
layer7.In effect, the n? layer shunts the n.layer of the collector region w.r.t the flow of the
current thus effectively reducing the collector resistance.
=.What are the different ways of integrating p.n.p transistors?
Dertical or substrate p.n.p
!ateral p.n.p
Triple diffused p.n.p
>.Write shot notes on vertical p.n.p transistors.
The p.type substrate itself is used as p.collectors n.epita8ial layer for the base and the ne8t
p.diffusion5base in n.p.n structure7as the emitter region. This type of p.n.p transistor has the
limitation that collector has to be held at the most negative potential in the circuit
for
providing good isolation.
%6.What is a triple diffused p.n.p transistor?
If to a standard n.p.n transistor, an e8tra p.type diffusion is added after the n.diffusion, it is
#uite possible to obtain a p.n.p transistor and is <nown as triple diffused p.n.p transistors.
%1.Why is n.p.n transistor preferred in integrated circuits over p.n.p transistor?
9 vertical p.n.p transistor has the disadvantage that its collector has to be held at a
fi8ed negative voltage.
!ateral p.n.p transistor has inferior characteristic as the base width is usually larger
controlled by lateral diffusion of p.type impurities and photolithographic limitations during mas<
ma<ing and alignment.
The diffusion coefficient of the collector impurities should be as small as possible to
avoid the movement of the collector impurities should be as small as possible to avoid the
movement of the collector function.*ince n.type impurities have smaller diffusion constant than
p.type impurities,then n.type collector moves very little while p.type moves appreciably.This
ma<es the n.p.n transistor superior in performance with relatively easier process control.
%.What are the different methods available for fabrication of integrated resistors?
o (iffused resistor
o 1pita8ial resistor
o -inched resistor
o Thin film resistor
%%."ention the advantages of thin film resistors over the diffused resistors.
Thin film resistors have lesser and smaller parasitic components and
hence their high fre#uency behaviour is better.
The values of thin film resistors can be easily adjusted after
fabrication by cutting a part of the resistor with a laser beam.
Thin film resistors have low temperature coefficient thereby ma<ing
them more stable.
%).What are the common methods for obtaining integrated capacitors?
2unction capacitor
"/* and thin film capacitor
%3.18plain the process of 201T fabrication.
The basic process used are the same as in &2T fabrication.The epita8ial layer
which formed
the collector of the &2T is used as the n.channel of the 201T.The p? gate is formed in the n.
channel by the process of diffusion or ion implantation.The n? regions have been formed under
the drain and source contact regions to provide good ohmic contact.
%4.What are silicon gate "/* transistors?
-olycrystallane silicon when doped with phosphorous is conductive and is
used as the gate
electrode instead of aluminium.This reduces D
T
to about 1 to D.*uch device are called silicon
gate "/* transistors.
%:.Compare thic< and thin film technologies.
Thic< film ICs are made by the process of screen printing,usually sil<
screening techni#ue,
whereas the materials used to ma<e thin film are generally deposited onto substrates in a vacuum
chamber. @evertheless, thic< film technology produces cheap and rugged resistors ,capacitors and
conducting patterns the processing e#uipment for thic< film circuit is relatively ine8pensive and
easy to use.Thin film technology provides greater precision in manufacturing but is more costly
than thic< film technology.
%=.What are the various methods used for deposition of thin film?
o Dacuum evaporation
o *puttering
o Eas plating
o 1lectro plating
o 1lectroless plating
o *il< screening
%>.What are the types of plating techni#ue?
1lectro plating
1lectroless plating
)6.!ist out some basic thic< film processes.
*creen printing
Ceramic firing
)1.What is an ohmic contact?
9luminium used for ma<ing interconnection is a p.type impurity in
silicon.The formation of
rectifying p.n junction is avoided by ma<ing n? diffusions in the n. regions where contact is to
be made using aluminium.*uch contacts are called ohmic contacts.
)."ention the advantages of polysilicon gate "/*01T over aluminium gate.
It lowers D
T
It reduces capacitances due to self.aligning property.
)%.18plain why inductors are difficult to fabricate in ICs.
&ecause IC devices are dimensional.IC inductors can be made in the form
of flat metallic
thin film spirals by successive deposition of conduction patterns. Dery small value of inductance
of the order of nano.henry with low #uality factor can be obtained. 0or any reasonable
inductance value, a % dimensional coil structure is needed to obtain a large number of turns.
)).+ow the use of inductor are avoided?
&y simulating the circuits using $C active networ<s.
)3.What are the advantages of "&15"olecular &eam 1pita8y7 over CD(5Chemical Dapour
(eposition7
!ow Temperature processing Fminimises autodoping and out
diffusion
-recise control of doping
Complicated doping profiles can be generated
9 wider choice of dopants can be used.
)4.What is $eactive plasma etching
The term reactive plasma is meant to describe a discharge in which
ioni;ation and fragment of gases ta<es place and produce chemically active
species.*uch plasmas are reactive both in the gas phase and solid surfaces
e8posed to them.When these interactions are used to form volatile products
so that material is etched from surfaces that are not mas<ed by lithographic
patterns,this techni#ue is <nown as reactive plasma etching
):.What are the reactive plasma etching techni#ues.
-lasma etchers and &arrel $eactors
$eactive Ion 1tching
$eactive Ion &eam 1tching
"icro wave plasma etching
)=.(efine throughput of the process
@umber of wafers etched per unit time
)>.(efine diffusion in a solid
It can be defined as atomic movement of diffusant in the crystal lattice by
Dacancies or self interstitials.
36.(efine diffusion by a vacancy
9 host atom ac#uires sufficient energy to leave the lattice site ,becoming a self
interstitial atom and creating a vacancy.When a neighbouring atom moves to
this vacancy site it is diffusion by vacancy
31.(efine double vacancy or divacancy
To produce impurity atom movement rather than oscillating between the two
lattice sites by e8changing positions with a vacancy ,the vacancy has to
diffuse away from the site that the impurity atom has just occupied or the
impurity atom has to move to a second vacancy that is at the nearest of
neighbouring of original vacancy.This is double vacancy or divacancy
3.What is interstitial diffusion mechanism.
9n interstitial atom moving from one place to another without occupying a
lattice site is
interstitial diffusion mechanism.
3%.What are the techni#ues used to study the diffusion of 9s and *b in *i/
*I"*.*econdary Ion "ass *pectrometry
$I&*.$utherford &ac< *puttering
3).(efine *puttering.
It is the ejection of material from a surface caused by bombardment
by energetic ions such as 9r? and Ge ? .
UNIT II
LINEAR INTEGRATED CIRCUITS
1.What is an op.amp?
It is a special type of amplifier that, by proper selection of its e8ternal components could be
configured for a variety of operations such as amplification, addition, subtraction and
integration.
.The basic building bloc< of an op.amp is differential a!lifier.
%.(efine input offset voltage.
It is the voltage that must be applied between the input terminals of the op.amp to nullify the output
voltage.
).(efine slew rate.
It is defined as the ma8imum rate of change of output caused by
a step input voltage.
3.What is C"$$ 5Common "ode $ejection $atio7 and write its e8pression?
The relative sensitivity of an op.amp to a difference signal as compared to
common mode signal is called C"$$ and gives the figure of merit - for the
differential amplifier, where pH9dI
I9cI
Common "ode $ejection $atio H (ifferential gain
Common mode gain
4."ention the various stages in an op.amp.
The first stages are differential amplifiers, third stage is buffer and level translator and the last stage
is the output device.
:.If f
6
is the pea< fre#uency of the op.amp,'9' is its open loop gain.'&' is the
feedbac< factor
then what is the bandwidth of the amplifier with feedbac<?
&andwidth H f
6
51?9&7
=.Why are 01T op.amps better than &2T op.amps?
&ecause 01T op.amps has high input resistance, high slow rate
and low input offset
current.
>.What is compensated op.amp?
/p.amp which is internally compensated with the compensating networ< is designed in the
circuit to control the gain and phase shift of the op.amp.
16.(efine unity gain bandwidth of an op.amp.
The fre#uency at which the gain is e#ual to one is called unity
gain bandwidth.
11.When does the op.amp behaves as a switch?
When op.amp is operating in open loop mode it acts as a switch.
Consider signals D1 and D applied at both inverting and non.inverting
terminal respectively. *ince the gain of the op.amp is infinite, the output D
6
is
either at its positive saturation voltage5?D
sat
7 or negative saturation voltage 5.
D
sat
7 as D
1
J D

or D

F D
1
respectively. Therefore amplifier acts as a switch.
1.(erive the e8pression of closed loop gain of an inverting amplifier.
Writing the nodal e#uation at node Ka'
D
a
F D
i
? D
a
. D
6
H 6
$
1
$
f
where D
a
is the voltage at node Ka'.*ince node Ka' is at virtual ground D
a
H6
9
C!
H D
6
H .$
f

D
i
$
i

1%.What is an inverting amplifier?
9 signal is applied to the inverting input terminal.The output voltage is
feedbac< to the inverting input terminal through $
f
.$
1
networ<.The output
signal is the amplifier form of input signal with a phase shift of 1=6
6
.*uch a
circuit is called an inverting amplifier.
1).What is a non.inverting amplifier?
If the signal is applied to the non.inverting input terminal and the output
is feedbac<, the circuit amplifies without inverting the input signal. *uch a
circuit is called a non.inverting amplifier.
13. What is linear op.amp circuit?
9n op.amp circuit which has the output signal with the same shape as the
input signal is called linear op.amp circuit. 9t no time during the cycle,does the
op.amp goes into saturation.
14.!ist out some linear op.amp circuit.
Inverting amplifier
@on.inverting amplifier
(ifferential amplifier
Instrumentation amplifiers
Current boosters
Controlled current sources
9utomatic gain control circuits.
1:. What is non.linear op.amp circuit?
9n op.amp circuit which has the output signal with the different shape
from the input signal is called non.linear op.amp circuit.(uring a part of input
cycle, the op.amp saturates.
1=. !ist out some non.linear op.amp circuit.
Comparators
Wave shapers
1>.+ow is the gain stabili;ed by negative feedbac<?
@egative feedbac< is used mainly to stabili;e the overall voltage gain.If
the open loop voltage gain 9/! increases for any reason,the output voltage will
increase and feeds bac< more voltage to the inverting input.Ths opposing
feedbac< voltage reduces D.Therefore , eventhough it has increased, D has
decreased and the final output increases much less than it would be without the
negative feedbac<.
6.What is a voltage follower?
The circuit in which the output voltage follows the input voltage both in
magnitude and phase is called as the voltage follower circuit.
1.What is a differentiator?
9 differentiator is an op.amp circuit which differentiates the input signal ie
the output waveform is the derivative of the input waveform.
.What are the main drawbac<s of ideal differentiator?
9t high fre#uency,a differentiators may become unstable and brea< into
oscillation.
The input impedence ie51LMC17 decreases with increase in
fre#uency,thereby ma<ing the circuit sensitive to high fre#uency noise.
%.What are the steps to be followed while designing a good differentiator?
Choose fa e#ual to highest fre#uency of the input signal.
9ssume a practical value of C15N1O07and then calculate $f.
Choose fbH16fa5*ay7.@ow calculate the values of $1 and C1 so
that
$1C1 H $fCf.
).What are the main applications of differentiator?
It is used in wave shaping circuits to detect the fre#uency in an input
signal.
It is also used as rate of change detector in modulations.
3.What is an integrator circuit? +ow is it obtained?
9n op.amp circuit which produces an output signal which is an integral
of input signal is called as integrator circuit. It is obtained by simply
interchanging resistor and capacitor of differentiator circuit.
4. What are the main drawbac<s of ideal integrator circuit?
9t low fre#uencies such as dc5 M P 6 7 the gain becomes infinite.
When the op.amp saturates ie the capacitor is fully charged it behaves li<e
an open circuit.
:.Why is the practical integrator circuit called lossy integrator?
The gain of an integrator at a low fre#uency 5 dc7 can be limited to avoid
the saturation problem.If the feedbac< capacitor is shunted by a resistance $
f
The parallel combination of $
f
and C
f
behaves li<e parallel capacitor,which
dissipates power unli<e an ideal capacitor.0or this reason,this circuit is called as
lossy integrator.
=.Why is an amplifier also called an error amplifier?
9n amplifier also called an error amplifier in control theory , which
accepts the signal G
d
and yields the output signal.
G
6
Ha.Gd
where a is the forward gain of the amplifier is called the open.loop gain of the
circuit.
>.What is precision diode?
When the input signal D
i
J D
r
L 9
/!
then the output D
/9
,the output of op.amp
e8ceeds D
r
and the diode ( conducts.
When the input signals D
i
is less or negative than the D
r
L 9
/!
, the diode ( is
off and no current is delivered to the load $
!
e8cept for small bias current of
the op.amp and the reverse saturation current of the diode.This circuit is
called precision diode capable of rectifying input signals of order of mD.
%6.Eive the output voltage when Di is positive and negative in a precision diode.
When D
i
is positive,diode (
1
conducts causing D
6
to negative by one diode
drop
5D
r
H6.4v7.+ence,diode (

is reverse biased.The output voltage D
6
is ;ero.
When D
i
is negative ie D
i
N 6, diode (

conducts (
1
is off.The negative
input D
i
forces the op.amp circuit D
/@
positive and causes (

to
conduct./utput D
6
becomes positive.
%1. What are the main drawbac<s of basic log op.amp circuit?
The main drawbac<s of log op.amp circuit is that,the emitter saturation
current I
s
varies from transistor to transistor and with temperature.Thus a stable
reference D
ref
cannot be obtained.
%.To implement analog multipliers" l#$arit%i& a!lifier' and antil#$arit%i&
a!lifier'
are re#uired.
%%.What are function generators?
0unction generators are circuits, which are used to provide the basic
waveform with minimum number of e8ternal components.
%).(CO )(#lta$e C#ntr#lled O'&illat#r* is the heart of function generator.
%3.!ist out the normally available function generator.
IC! =6%= waveform generator
G$ F 64 function generator
%4.What is a comparator?
It is a circuit, which compares a signal voltage applied at one
input of an op.amp with
output QD
sat
5 H D
CC
7.
%:.What are the types of comparators?
@on.inverting comparator
Inverting comparator
%=.!ist out the applications of comparator.
Rero crossing detector
Window detector
Time mar<er generator
-hase meter
%>. What are the main drawbac<s of ;ero crossing detector?
The ouput D
6
may not switch #uic<ly from one saturation voltage to the
other.
&ecause of the noise at the op.amps input terminals the output fluctuates,
detecting ;ero reference crossing for noise voltage as well as D
in
.
)6.18plain the principle of operation of a phase detector.
In phase detector ,both the input voltage are converted into spi<es and the
time interval between the pulse spi<es of one input and that of the other is
measured.The time interval is proportional to the phase difference./ne can
measure phase angles from 6
6
to %46
6
with such a circuit.
)1.What is *chmitt trigger?
It is an inverting comparator with positive feedbac<.This circuit convert an
irregular shaped waveform to a s#uare wave or pulse.This circuit is called as
s#uaring circuit.
). What is hysteresis width?
It is the difference between the upper threshold voltage5D
,T
7 and lower
threshold voltage5D
!T
7.
D
+
H D
,T
. D
!T
H $

D
sat
$
1
? $

)%.What are the important characteristics of comparator?


*peed of operation
9ccuracy
Compatibility of output
)).What are the types of multivibrators?
"onostable multivibrator
9stable multivibrator
)3.In astable multivibrator,both the states are +,a'i-'ta-le.
)4./#n#'ta-le ,lti0i-rat#r )#ne '%#t ,lti0i-rat#r* has one stable state and
the other is
#uasi stable state.
):.Why is the monostable multivibrator circuit called time delay circuit and gating
circuit?
&ecause it generates a fast transition at a predetermined time T after the
application of input trigger.
It is called as a gating circuit because it generates rectangular waveform
at a definite time and could be used as gate parts of a system.

)=.What is a triangular wave generator?
It is obtained by integrating a s#uare wave obtained by an
astable multivibrator.
)>.What is the main function of 333 timer?
It is a higher stable device for generating accurate time delay or
oscillation.
36."ention few applications of 333 timer.
/scillator
-ulse generator
$amp and s#uare wave generator
"onoshot multivibrator
&urglar alarm
31.What should be the voltage levels that should be provided at pin) and pin of
an IC333 monostable multivibrator?
0or reset to be effective,at input voltage at reset pin5pin)7should be less than
6.)D.Whenever the input at pin is larger than 1L% D
CC
the output is high.
3. What is the function served by each of the bloc< listed in timer IC?5a7,pper
transistor
5b7(ischarge transistor?
i. 9s the upper comparator gets L%DCC from the
potential divider and the lower
comparator 1L%DCC and also they aid in determining the time interval.
ii. When the output is high,6 is saturated and acts as a short circuit, shorting
the
e8ternal capacitor to ground.
3%. What is a filter circuit?
It is often a fre#uency selective circuit that passes a specified band of
fre#uencies and attenuates signals of fre#uencies outside this band.
3).What is a counter timer?
9 timer connected in oscillator configuration and the output of the timer
connected to the counter is <nown as counter timer.It can produce time delay
ranging from microseconds to days.
33."ention the application of the monostable mode of operation of 333IC.
"issing pulse detector
!inear ramp generator
0re#uency divider
-ulse width modulation
34.IC111 tier is linear type IC.
3:.18plain the function of reset in IC 333.
The reset input provides a mechanism to reset the flipflop in a manner which
overrides the effect of any instruction coming to 00 from low comparator.This
overriding reset is effective when the reset input is less than about 6.)D.
3=.What is the time constant of 333 monostable circuit?
TH1.1 $C
where T is the time during which 333 circuit is on.
3>.+ow can you turn off the output before the time constant in a monostable
multivibrator
circuit?
When a negative going reset pulse is applied to the reset terminal during
the timing cycle,transistor S

goes off S
1
becomes on and the e8ternal timing
capacitor C is discharged.
46.18plain the principle of operation of the missing pulse detector monostable
circuit.
Whenever the input trigger is low,the emitter diode of the transistor is
forward biased.The capacitor C gets clamped to few tenths of a volt 56.:D7.The
ouput of the timer goes +IE+.The circuit is designed so that the time period of
the monostable circuit is slightly greater 51L% longer7 than that of the triggering
pulse.*o, as long as the triggering pulse train <eeps coming at pin , the output
remains +IE+.+owever if a pulse misses , the trigger input is high and
transistor S is cut.off.The 333 timer enters into normal state of monostable
operation.
41.What are the main applications of the missing pulse detector monostable
circuit?
,sed to detect missing heart beat.
,sed for speed control and measurement.
4.What is the main function of voltage regulator?
Is to provide a stable dc voltage for processing other electronic
circuits.
4%.What are the different types of voltage regulators?
0i8ed output voltage regulator5positive or negative7
9djustable output voltage regulator5positive or negative7
*witching regulators
*pecial regulators
4).What are switching regulators?
$egulators which operates the transistor as a high fre#uency onLoff switch,so
that the power transistor does not conduct current continuously is called
switching regulators.
43.What is a voltage regulator?
It is an electronic circuit that provides a stable dc voltage independent of the
load current,temperature and ac line voltage variations.
44. What are the ) main parts of voltage regulators?
$eference voltage circuit
1rror amplifier
*eries pole transistor
0eedbac< networ<
4:.(efine !ine regulation.
It is defined as the percentage change in the output voltage for a change
in the input voltage.It is usually e8pressed in millivolts.
4=.(efine !oad regulation.
It is defined as the change in output voltage for the change in input current.It
is usually e8pressed in millivolts or as the percentage of D
o
.
4>.What are the main advantages of voltage regulator?
*hort circuit protection
/uput voltage5positive or negative7can be varied.
:6.What are the limitations of :% regulators?
@o built in thermal protection
It has no short circuit current limits.
:1.What is current limiting ability?
It refers to the ability of a regulator to prevent the load current from
increasing above a preset value.
:.+ow is the IC:% protected from short circuits5due to more load demand7?
To protect the current from short circuits which may arrive due to the
demand of more current by the load,an e8ternal resistor $
*C
is connected
between the terminals C
!
and C
*
.C
!
is also connected to the output terminal D
/
and C
*
terminal to the load.
:%.What is the main advantage of current feedbac< method?
Current method limits the short circuit current and get allow
higher currents to the load.
:).+ow is current boosted in an IC regulator?
The current is boosted by adding a boost transistor S
1
that comes from
unregulated (C supply.The output current from D
/
terminal drives the base of
the pass transistor S
1
.This base current gets multiple8ed by the beta of the pass
transistor, so that :% has to provide only base current.
*o, I
load
H Tpasstransistor

U I
o
5:%7
:3.What are the basic drawbac<s of series regulators?
The input step down transformer used is bul<y and most e8pensive
component.
*ince it operates at low line fre#uency,larger values of filter capacitors are
re#uired.
1fficiency is less.
"ore power is dissipiated in the series pass transistor,which is always in the
active region.
:4.+ow is dissipated in the series pass transistor,which is always in the active
region?
In a switched mode regulator,the pass transistor is used as a Acontrolled
switchB and is operated at either cut.off or saturated state.+ence the power
transmitted across the pass device ie. In discrete pulses rather than a steady
current flow.*ince,the pass device is operated as a low impedance switch higher
efficiency is achieved.

::.The efficiency of the switched mode power supply is in the range of 23-435
:=.The output level is controlled by varying the !,l'e 6idt% of the switching
waveform.
:>.Why are series regulators called as series voltage regulators?
*ince the transistors conduct in the active or linear region,these
regulators are called linear regulators or series regulators or voltage regulators.
=6.What is an oscillator?
It is basically a feedbac< circuit where,a fraction D
0
of the output voltage D
/
of an
amplifier is feedbac< to the input.
=1.What are the conditions to be satisfied for sustained oscillation?
The magnitude condition I9
D
I H 1
9
D
H 6
o
or %46
o
=.Classify sine wave oscillators based on the range of fre#uency.
$C /scillators for audio fre#uency
!C oscillators for radio fre#uency.
=%.Why there is no phase shift provided in the feedbac< networ< in Wein.&ridge oscillator?
In Wein.bridge oscillator, the feedbac< signal is connected to the 5?7 input terminal so that,
the op.amp is wor<ing as a non.inverting amplifier.Therefore the feedbac< networ< need not
provide any phase shift.
=3.18plain the principle of operation of practical Wein.&ridge oscillator.
In practical Wein &ridge oscillator,resistor $
)
is initially adjusted to give a gain,so
that oscillations start.The output signal grows in amplitude,until the voltage across $
%
approaches
the cut.in voltage of the diode.9s the diode begins to turn on,the effective feedbac< resistance $
f
decreases because the diode is in parallel with the resistance $
%
.This will reduce the gain of the
amplifier which inturn lowers the output amplitude.+ence sustained oscillation can be
obtained.0urther if the output signal falls,the diodes would bedgin to turn.off,thereby increasing
$
f
which inturn increasing gain.
=4.What is an electric filter?
It is often a fre#uency selective circuit that passes a specified band of fre#uencies and
bloc<s or attenuates signals of fre#uencies outside this band.
=:.Classify filters.
9nalog or digital
-assive or active
9udio5907 or radio fre#uency5$07.
==.What are the advantages of active filters?
Gain and frequency adjustment flexibility:*ince the op.amp is capable of
providing a gain,the input signal is not attenuated.The active filter is easier to tune or
adjust.
No loading problem:&ecause of the high input resistance and low output
resistance of the op.amp,the active filter does not cause loading of the source or load.
Cost:Typically active filters are more economical.This is because of the
variety of cheaper op.amps and the absence of inductors.
=>.What are the basic elements of filters?
1ach filter consists of op.amp as an active element and resistors and capacitors as passive
elements.
>6.Why is the &utterworth filter called flat.flat filter?
The main characteristic of &utterworth filter is that,it has flat passband as well as stop
band.*o &utterworth filter is called flat.flat filter.
>1.What are the steps involved in designing a low pass filter?
Choose a value of high cut.off fre#uency f
+
.
*elect a value of C less than or e#ual to 1 0
Calculate the value of $ using $ H 1
f
+
C
0inally select values of $
1
and $
f
dependent on the desired pass band gain9
0
using,
9
f
H 1?5$
f
L$
1
7.
>.What is fre#uency scaling?
The procedure used to convert an original cut.off fre#uency f
+
to a new cut.off fre#uency f
+
is called fre#uency scaling.
>%.What are the steps involved in designing second order low pass filter?
Choose a value of high cut.off fre#uency f
+
.
*et $H$%H$ and CHc%HC and choose a value of C less than or e#ual to 1 0.
Calculate the value of $ using $ H 1
f
+
C
$
0
should be e#ual to 6.3=4$
1
.+ence choose a value of $
1
166 and calculate the
value of $
f
.
>).The roll.off rate in the stop band of second order.low pass filter is t6i&e.
>3.What is a band pass filter?
9 filter that allows the signal to pass through it, between the cut off fre#uencies f+ and f!
and attenuates all other fre#uencies outside this pass.band is called as a band pass filter.
>4.What are the types of band pass filters?
Wide band pass filter,which has its figure of merit S,less than 16.
@arrow band pass filter,which has its figure of merit S,greater than 16.
>:.What are the uni#ue features of narrow band.pass filter?
It has feedbac< paths, hence the name multiple feedbac< filter.
The op.amp is used in the inverting mode.
>=. What is the total time period of 9stable multivibrator.
Total time period is given as
TH T1 H $C ln 1?T
1. T
where T H $
$1?$
>>. Write the e8pression for pulse width monostable multivibrator.
-ulse Width TH $C ln 51? D
(
L Dsat7
1. T
where T H $
$1?$
166.(esign the Wein bridge oscillator with fo H >43+;
!et CH 6.63V 0
fo H 1
8 %.1)8 $8C

$ H 1
6.63816
F4
8 >43
$ H %.% <ilo ohms
9v H 1? 5$fL$17 H %,
!et $1H 1 <ilo ohms
$f H $1 H 81< H ) <ilo ohms
5 use a 36 < -/T7
UNIT III
DIGITAL INTEGRATED CIRCUITS
. What is the main feature of C"/*.
The main feature of C"/* is that both n.channel and -.channel is fabricated on the
same
substrate.
%. What is integration density?
It is the measure of the amount of logic placed on the silicon chip.
). Write down the procedure for designing the transistor circuitry for C"/* logic
circuit.
Construct the logic diagram using basic 9/I or /9I structuring deeper nesting such
as /9/I and 9/9I is allowed. (eeper nesting /9/I and 9/9I is allowed.
,se the gate n01T relations to construct the n01T logic circuit between the output
and ground.
To obtain the topology of the p01T array,start with the original logic diagram and
push the bubble bac< toward the input using the (e"organs rules.Continue the bac<ward
pushing until every input is bubbled.The p01T circuitry between the output and D
((
is then
obtained.
3. What is a latch?
It is a device that can receive and hold an input bit.
4. What is a bistable circuit?
9 bistable circuit is one that can store 5or hold7 either a logic 6 or a logic 1 indefinitely 5or
atleast as long as power is applied7.
:. What is ring oscillator circuit?
9 closed loop with an odd number of inverter is called as ring oscillator as the signal at any
point oscillates in time.
=. What is register?
9 register is a general term that describes a group of circuits that are used to store a word
or a group of flipflops.
>. What is a register file?
It is a collection of word.si;e storage registers.
16. 18plain the half adder circuit.
9 half adder circuit has ; inputs58 and y7 and outputs5 the sum * and the carry out C7.The
outputs are given by the e#uation
* H 8 y
CH8.y
11. Write the verilog behavourial description of half adder circuit.
"odule half adder5sum, c.out,8,y7W
Input 8,yW
/utput sum,c.outW
9ssign5c.out,sum7H8 ?yW
1nd module.
1. Write the high level D+(! description of full adder circuit.
"odule full adder5sum, c.out,a,b,c.in7W
Input a,b,c.inW
/utput sum,c.outW
9ssign5c.out,sum7Ha?b?c.inW
1nd module.
1%. What are the % operational modes of *$9"?
They are hold, write and read.When the cell is in hold state, the value of the bit is stored in
the cell for future use. (uring a write operation ,a logic 6 or 1 is fed to the cell for
storage.The value of the stored bit is transmitted to the outside world during a read operation.
1). What is static noise margin?
It is the separation between the curves along a )3
6
slope in the drawing and has unit of
volts.
13. +ow is butterfly plot obtained?
It is obtained by forcing an input on one of the internal nodes and plotting the response on
the other side,then performing the same operation to the other side.
14. +ow are *$9" arrays obtained?
They are created by replicating the basic storage cell and adding the necessary peripheral
circuitry.
1:. 9 1=X= *$9" chip holds 1=< =bit words for a total of 1"b of total storage.What
should be the
width of address word to select every =.bit word location.
"Hlog

51=Y7H1: to select every =.bit word location.


1=. What is a floating gate?
9 reprogrammable $/" array is built using special 01Ts that use a pair of stac<ed
poly gates.The top most gate constitutes the usual gate terminal of the
transistor.+owever,another poly gate layer is sandwiched in between the top poly and
silicon substrates.It is not electrically connected to any part of the transistor or au8illary
circuitry and is therefore called as electrically floating gate.
1>. What is gate array?
It is used to describe an entire class of devices.It refers to a user programmable chip that
can be logically configured.
6. What is logic array?
It is a structural unit that can be AprogrammedB to provide various functions and system
tas<s.
1. Consider a ($9" cell with C
s
H36p0 and a bit line capacitance of C
bit
H=C
s
.9ssuming
a ma8imum
voltage of D
*
HD
ma8
H.3D on the storage capacitor.0ind the final voltage during the logic read
operation.
0inal voltage during logic read operation is
D
f
H51L>75.37 H := mD
. What is fan.in.
The number of inputs to a logic gate is called the fan.in50I7.
%. What are n01T pass transistors?
-ass transistors are single 01Ts that pass the signal between the drain and source
terminals of a fi8ed power supply value.
). 1lectric isolation is achieved in gate arrays using &,t #ff tran'i't#r'.
3. 18plain $9".
$9" has the basic unit called binary cell.The binary cell can store either 1 or 6
indefinitely,as long as the power is /@.(ata can be written into $9" as read out from
$9".The previously stored data can be erased and new data can be written into $9".+ence
it is called as read write memory.When power supply is switched /00,all the binary cells
gets erased.
4. What are the different types of $9"?
o @/*$9"s5@itride metal /8ide *emiconductor $9"s7
o C"/*5Complementary metal o8ide semiconductor $9"s7
o *chott<y TT! $9"s
o 1C! $9"s.
:. What are the types of array in $9"?
!inear array
Coincident array
=. What is the procedure followed to store a new word in memory?
9pply the binary address of the desired word to the address lines.
9pply the data bits that must be stored in memory to the data input lines.
9ctivate the write input. The memory unit will then ta<e the bits from the
Input data lines and store them in the word specified by the address line.
>. What is the procedure followed to ta<e a word out of memory?
9pply the binary address of the desired word to the address lines.
9ctivate the read input.The memory unit will then ta<e the bits from the word
that has been selected by the address and apply them to the data output
lines.
%6. What is memory enable or chip select?
It is a control input which is used to enable the particular memory chip in a multichip
implementation of a large memory.When the memory enable is inactive ,the memory chip is
not selected and no operation is performed. .When the memory enable input is active ,the
readLwrite determines the operation to be performed.
%1. What is access and cycle time?
The access time of the memory is the time re#uired to select a word and read it.The cycle
time of a memory is the time re#uired to complete a write operation.
%. +ow does the read write input determines the type of operation?
If read write is 1,the memory performs a read operation symboli;ed by the statement,
(ataout "emZ9ddress[W
If read write is 6,the memory performs a write operation symboli;ed by the statement,
"emZ9ddress[ (ataInW
%%. 18plain *$9".
It is an operating mode.It consista of internal latches that stores the binary
information.The stored information remains valid as long as power is applied to the unit.It is
easier to use and has shorter read and write cycles.
%). 18plain ($9".
It is an operating mode,which stores the binary information in the form of electric charges on
capacitors.The capacitors are provided in inside the chip by "/* transistors.The stored charge on
the capacitors tend to discharge with time and the capacitors must be periodically recharged by
refreshing the dynamic memory. $efreshing is done by cycling through the words every few
milliseconds to restore the decaying charge.
%3. (ifferentiate volatile and non volatile memory.
%4.
%3.What is the use of .dimensional decoding?Eive an e8ample.
,sed to arrange the memory cells in an array in the form of a s#uare.
0or e8ampleC
9 decoder with Y inputs and
<
outputs re#uires
<
9@( gates with Y inputs
per
gate.The total number of gates and number of inputs per gate can be reduced by employing two
decoders in a dimensional selection scheme.It will result in two <L F input decoders instead of
one <.input decoder./ne decoder performs the row selection and other the column selection.
%:. What are the types of semiconductor memories?
$9" and $/".
%=. What is meant by a non.destructive readout?
1ach memory location contains one byte of data.When a byte is read from the memory,it
is not destroyed,but remains in the memory.This process of AcopyingB the contents of a
memory location without destroying the contents is called non.destructive readout.
Dolatile memory
@on volatile memory
They are memory units which lose
stored information when power is
turned /00.
It retains stored information when
power is turned /00.
18ampleC*$9" and ($9". 18ampleC"agnetic dis< and $/".
%>. !ist out the advantage and disadvantage of dynamic $9" cell.
Ad0anta$e7
This type of cell is very simple thus allowing very large memory arrays to be
constructed on a chip at a lower cost per bit than in static memories.
Di'ad0anta$e7
The storage capacitor cannot hold its charge over an e8tended period of time and will
lose the stored data bits unless its charge is refreshed periodically.This process o f refreshing
re#uires additional memory circuitry and complicates the operation of the dynamic $9".
%>.What is a ripple counter.
9 ripple counter is a counter that uses type T 0lip flops to
perform a counting
function where each T lead is connected to output of previous stage.
)6.(efine a decoder.
9 decoder is a device that ta<es a binary word and energi;es a
particular line
based upon contents of that word.
)1.18plain half adder
+ere two one bit words are added ,resulting in two bits of data,a
sum bit and a
carry bit.
). 18plain full adder
0ull adder is a device capable of adding three binary bits
,resulting in a sum and
carry.
)%. (efine memory address and capacity.
The location of a unit of data in the memory array is its
address.The capacity of a
memory is the total number of data units that can be stored.
)).What is data bus and address bus.
(ata units go into memory during a write operation and come out of
memory during a read operation on a set of lines called the data bus.
0or a readLwrite operation,an address is selected by placing a binary
code representing the desired address on a set of lines called the address bus.
)3.What is the main purpose of address burst feature.
It allows the memory to read or write upto ) locations using a single
address.
)4.What are the types of ($9"
0ast -age "ode 50-"7 ($9", the 18tended (ata /utput51(/7
($9",the &urst 18tended (ata /utput5&1(/7 ($9" and synchronous
($9".
UNIT I(
(LSI INTEGRATED CIRCUITS
1.(raw the circuit symbol of n"/* depletion "/*01T.
(rain
Eate
*ource
.What is diffusion mas< or thin o8ide mas<?
"as< 1. pattern *io

to e8pose the silicon surface in areas where paths in the


diffusion layer or source, drain or gate areas of transistors are re#uired. (eposits thin o8ide
overall.
%.Write short notes on fabrication of n"/*.
-rocessing ta<es place on a p.doped silicon crystal wafer on which is
grown a thic< layer if *io
.
"as< 1. pattern *io

to e8pose the silicon surface in areas where


paths in the diffusion layer or source,drain or gate areas of transistors are
re#uired.(eposits thin o8ide overall.
"as< . -attern the ion implementation within the thino8 where the
depletion mode devices are to be produced.self aligning.
"as< %.(eposit polysilicon overall51.3 m thic< typically7,then
pattern using
"as< %.,sing the same mas<, remove thin o8ide where it is not covered by
polysilicon.
(iffuse n
?
regions into areas where thin o8ide has been removed.
Transistor drain and sources are thus self.aligning w.r.t the gate structures.
"as< ).Erow thic< o8ide over all and then etch for contact outs.
"as< 3.(eposits metal and pattern with mas< 3.
"as< 4.would be re#uired by the over glassing process step.
).What are the different approaches to C"/* fabrication?
o -.well process
o @.well process
o The twin tub process
o The silicon.on.insulator processes.
3. What are the % main steps of p.well process?
"as<ing
(iffusion
-atterning
4.*how the main steps in a typical n.well process.
:.18plain the twin tub process.
In this process, a substrate of high resistivity n.type material is started and
then n.well and p.well regions are created. Through this process it is possible to preserve
the performance of n.transistors without compressing the p
.
transistors. (oping control is
more readily achieved some rela8ation in manufacturing tolerances results. This is
particularly important as far as latch.up is concerned.
=.Compare C"/* and bipolar technologies.
C"/* technology &ipolar technology
1.!ow static power dissipation. +igh power dissipation.
.+igh input impedance.5low drive
current7.
!ow input impedance.5high drive
current7.
%.+igh pac<ing density. !ow pac<ing density.
).+igh delay sensitivity to load. !ow delay sensitivity to load.
0ormation of n.well regions
(efine n"/* and -"/* active areas
0ield and gate o8idation 5thino87
0orm and pattern polysilicon
-
?
diffusion
@
?
diffusion
Contact cells
(eposit and pattern metalli;ation
/ver glass with cuts for bonding pads
>.!ist out the steps behind the fabrication process of single poly gate metal C"/*.
0orm n. well
(elineate active areas
Channel stop
Threshold D
T
adjustment
(elineate polygate areas
0orm n
?
active areas
0orm p
?
active areas
(efine contacts
(elineate the metal areas.
16.E--ea a'8in$ is one of the methods of mas< ma<ing.
11.What are the advantages of 1.beam mas<s?
Tighter layer to layer registration
*maller feature si;es.
1.What are the different approaches to the design of 1.beam machines?
$aster scanning
Dector scanning
1%.What is cross tal<?
Whenever an interconnect line is placed in close pro8imity to any other interconnect
line, the conductors are coupled by a parasitic capacitance. -ulsing a voltage on one of
the lines induces stray signals on all lines that are coupled to it. This phenomenon is
called cross tal<.
1).(raw the general overview of design hierarchy.
*ystem specifications
9bstract high level model D+(!,verilog +(!
!ogic synthesis
Circuit design
-hysical design
"anufacturing
0inished D!*I chip
13.18plain the term reliability.
It is concerned with projecting the lifetime of a component once it is placed
into
operation.It is defined as the probability that an item will perform a re#uired function
under
stated conditions for a stated period of time.
14.What are the % major regions of bathtub curve.
Infant mortalities are the failures that occur after a very short period of time ie early
in the system. These tend to arise from manufacturing defect that manifest themselves
after a few hours of operation. The central portion of the curve represents random failures
during normal operation, while wear.out describe the end of life.
1:.What is a vector?
It is an array of binary inputs that are applied to the device.under.test5(,T7
or
the chip under test.
1=.What is the main purpose of performing functional testing?
,sed to determine whether a chip is good or bad by forcing the circuit to perform
various functions and chec<ing the response.
1>.18plain the short.circuited 01T.
9 short.circuited 01T is one that always conducts the drain source current
with
an applied drain source voltage D
(*
.The gate has no control over the operation.
6.What is fault dominance?
When sa1 fault occur at both the input and the output of an 9nd gate. The
output overrides the input fault, so that anything to the left of the gate may be ignored.
This is called fault dominance.
1.What is path sensiti;ation?
When the gate to be tested is embedded on a larger logic networ<, we can use
the e8isting circuitry to create a specific path from the location of the fault to an
observable output point.This techni#ue is called path sensiti;ation.
.What is path propogation?
The process of creating the path is called propagation.
%.What are the steps involved in path sensiti;ation?
0orward drive
&ac<ward trace.
).What is infant mortalities?
Infant mortalities are failures that occur after a very short period of time5ie7 early in
the life of the system. These tend to arise from manufacturing defects that manifests
themselves after a few hours of operation.
3.Consider a small chip that has about ,66,666 01Ts. What is the 0IT value needed to
achieve an average reliability of no more than 1 transistor failure over 1 year?
9ssuming =:46 hours per year,we see that the 01Ts represent a total of
5,66,6667 X 5=:467H1.:3 X 16
>
device hours L years.To find the 0ITs needed to obtain 1
failure per year we write
58L16
>
751.:3 X 16
>
7 H 1 where 8 is the 0IT value.
*olving gives 8H6.4: 0ITs as the re#uired rate.
4.Eive the e8pression for mean time to failure5"TT07.
It is given by,
"TT0 H T H 1
@ G
av
:.+ow is the average failure rate590$7obtained?
90$ between times t

J t
1
is obtained by the ratio of the failure rate to the
duration of the timing interval. 9ssuming t

H T and t
1
H 6 for simplicity gives,
90$5t7H 1
T
=.What is the main drawbac< of path sensiti;ation?
/ne drawbac< of path sensiti;ation is that the process of generating test
vectors
may become long and involved.
>.What is !ocal /8idation.
/8idation can be made selective by depositing and patterning *i
%
@
)
before /8idation
,which allows the o8ide to form only wherever *i
%
@
)
is removed ,since *i
%
@
)
bloc<s the
o8idation.This is called !ocal /8idation.
%6.+ow is the minimum feature si;e determined
"inimum feature si;e determined by the ability to reproduce feature routinely i.e
how
accurately the feature can be transferred to *ilicon during pattern transfer process.
%1.What are @esting Tolerances.
(istances re#uired to AnestB the features of one level with respect to features on a
previous level is called @esting Tolerances.
%.What is the purpose of chan stop region.
It serves the isolation between two transistors in the same IC chip.
%%.Eive the principle of operation of an n"/* transistor.
It operates by causing a negative charge to move from source to drain in response to a
positive charge on the gate.
%).Eive the two modes of operation of @"/* transistors.
i7 1nhancement mode
ii7 (epletion "ode
%3.What is threshold adjust implant.
If boron implant is done in fabrication process to adjust the threshold
voltage of a
particular transistor ,then it is threshold adjust implant.
%4.What is the purpose of -.Elass
-.Elass5-hospho.*ilicate Elass 7 serves important purposes.
i7 It reduces viscosity and at low temperatures ,glass will flow to
smooth the surface topography.
ii7 -rotects from mobile ion5@a7 contamination.
%:. What is Abirds bea< encroachmentB
Erowth of field o8ide layer causes o8ide to penetrate under mas<ing
nitride layer.This causes space between transistors to grow during
o8idation.This o8ide growth under nitride layer is called Abirds bea<
encroachmentB
%=.(efine -unch.through
If channel doping is too high ,a reduction in carrier mobility occurs at
the surface
and if too low,drain electric field will punch through to source .This is
-unch.through
and it indicates source and drain are nearly touching. /ne techni#ue to
reduce punch.
through is to implant boron deep into channel region to raise substrate
doping without
changing surface concentration.
%>.What is hot electron problem.
This arises when device dimensions are reduced ,but supply voltage is
held
constant,and results in increase in electric field generated in *ilicon.Thus
electrons gain
sufficient energy and gets injected into gate o8ide.@ow charging of gate
oside occurs
which raises D
T
. /ne approach to minimise this is to reduce electric field
at drain
region.
)6.What is p.tub5p.well7 process.
This process involves p.type dopant into n.substrate at a concentration
that is high
enough to compensate n.substrate and tto have good control over
desired p.type
doping.
)6.What is n.tub5n.well7 process.
n.tub is formed in a p.type substrate.n.channel device is formed by p.
type substrate.
)1.What is Trench Isolation
Trench Isolation is etching a narrow deep groove in *ilicon and then
filling it with
o8ide or polysilicon.It is used to decouple bipolar transistors.
).+ow was the base width determined in &ipolar IC Technology.
It is determined by difference between two impurity diffusion profiles
and this
technology is used for high speed appWcations.
)%.(efine Eummel @umber.
Total integrated charge in active base is called Eummel @umber.as
Eummel number decreases,gain of transistor increases.
)).What is Integrated Injection logic.5I

! logic7
Integrated Injection logic.5I

! logic7 also called merged transistor


logic5"T!7. 9nd
allows close pac<ing of transistors.!ogic element consists of a pnp
transistor connected
to a series of npn transistors.Collector of pnp and base of npn are
electrically connected
and share a common p.type.npn transistors share a common emitter.
)3.What is Class 166 environment
1nvironment having a ma8imum of 166 particles per cubic foot with
particles larger
than 6.3 micro meter.
)4.What is the purpose of automatically generated wafer map.
This shows misalignment distances and direction of misalignment
between levels in
a C"/* process.
):.Eive the e8pression for failure rate.
\N 1 0ailure
16
3
devices 8 :6 hours
\N 1) 0IT ,where 1 0IT H 1 0ailure ,nit H 1 0ailure
16
>
(evice.+our
)=. (efine the term A*oft errorB
It refers to random failure not related to physically defective
device.These errors are
reduced by coating IC with a material of low density of radio active
contamination.
)>.(efine $ents $ule.
@umber of signal terminals or pac<age IL/'s re#uired for logic
devices can be
estimated using an empirical relationship <nown as $ents $ule.
@umber IL/ H ] 5Eate Count7
T
36.What are two die bonding methods and wire bonding methods.
(ie bonding methods are
i7 +ard *olders51utectic7
ii7 -olymers 5 1po8ies ^ -olymides7
Wire bonding methods are
i7 Thermosonic ^ Themo compression ball and wedge
using 9u wire
ii7 ,ltrasonic wedge.wedge using 9u F9l wires.
31.Eive the advantage of C"/* technology.
-ower consumed by the device is very less.This is due to the fact
that ,the logic element
draws significant power only during transitions from one state to another.
3.What are the future trends for devices.
Trends are towards
i7 *elf aligned structures
ii7 Three dimensional devices
3%.What are the different types of pac<ages
i7 *I- 5*ingle FIn. !ine -ac<age7
ii7 (I-5 (ual.In.!ine -ac<age7
iii7 -E95-in Erid 9rray -ac<age7
iv7 &E95&all Erid 9rray -ac<age7
v7 !CC 5 !eadless Chip Carrier7
vi7 -!CC 5 -lastic !eadless Chip Carrier7
3).What are the pac<age fabrication technologies
i7 Ceramic -ac<age Technology
ii7 -lastic "oulding Technology
iii7 Elass *ealed $efractory Technology
33.(efine 9vailability.
It is the probability that an item will operate when needed ,or the
average fraction of
time that a system is e8pected to be in operating condition.
34.What are the typical failures that occur in semiconductor devices.
i7 *urface charge accumulation
ii7 (ielectric brea<down
iii7 1lectromigration
iv7 Corrosion
v7 "aterial 0atigue
vi7 Contact degradation
3:.What is meant by thermal and electrical burn.in.
The burn.in test is used to accelerate the fault growth rate so that the
devices which
are prone to infant mortality are identified easily.The burn.in process
involves <eeping
the devices in a temperature cycling oven in the supplies feeding to
them.
UNIT (
S9ECIAL A99LICATION IC'
1.What is the use of sample and hold circuit?
It samples an input signal and holds onto its last sampled value,until the input is
sampled again.
."ention few applications of sample and hold circuit.
9nalog to digital systems
-ulse code modulation systems.
%.What is sample period?
The time during which voltage across the capacitor is e#ual to input voltage is called
sample
period.
).What is hold period?
The time period T
+
during which the voltage across the capacitor is hold constant is
called time
period.
3.!ist out some of the commercially available sample and hold ICs.
o+arris semiconductor +9)6
o@ational semiconductor such as !01>=,!0%>%.
4.To obtain close appro8imation of the input waveform, the fre#uency of the sample and hold
circuit
,'t -e 'i$nifi&antl: %i$%er than that of the input.
:. What is 9nalog to (igital59L(7Converter?
9 circuit which converts the analog signal to digital signal is called analog to digital
converter.
=.When is (L9 converter used?
9 digital to analog converter is used when a binary output from a digital system must
be converted
to some e#uivalent analog voltage or current.
>.!ist out some applications of the 9L( and (L9 converters.
(igital audio recording and playbac<
Computers
"usic and video synthesis
-ulse code modulation and transmission
(ata ac#uisition
(igital multimeter
(irect digital control
(igital signal processing
"icroprocessor based instrumentation
16.!ist out the various resistive (9C techni#ues available.
Weighted resistor (9C
$.$ ladder
Inverted $.$ ladder
11.What is the resolution for a (9C?
The resolution of the converter is the smallest change in voltage,which may be
produced at the
output of the convertor.
1.What are the broad classification of 9(Cs
(irect type 9(Cs
Integrating type 9(Cs
1%.!ist out the direct type 9(Cs.
0lash5comparator7type converter
Counter type converter
Trac<ing or servo converter
*uccessive appro8imation type converter
1).!ist out some integrating type converters.
Charge balancing 9(C
(ual slope 9(C
13. What is integrating type converter?
9n 9(C converter that performs conversion in an indirect manner by first changing
the analog
input signal to a linear function of time or fre#uency and then to a digital code is <nown as
integrating type converter.
14.Where are the successive appro8imation type 9(Cs used?
,sed in applications such as data loggers and instumentation where
conversion speed is
important.
1:.The input stage of any data ac#uisition system will be 'a!le and %#ld &ir&,it.
1=.S,&&e''i0e a!!r#;iati#n type of 9(C has least conversion time.
1>.@ame the various types of electronic switches used in (9C.
*ingle pole double throw
Totem pole "/*01T switch
C"/* inverter switch
6.What is the main disadvantage of flash type 9L( converter?
The main disadvantage of flash type 9L( converter is that, the number of comparators
re#uired
almost doubles for each added bit. 0or egC9 bit 9(C re#uires % comparators, % bit
9(C needs : comparators.
1.What are the total number of cloc< pulses re#uired for =. bit *uccessive appro8imation 9L(
converter?
= cloc< pulses.
.18plain the principle of operation of *uccessive appro8imation 9(C.
The circuit consists of a *uccessive appro8imation register5*9$7, to find the
re#uired value of each bit by trial and error with the arrival of *T9$T command,*9$ sets the
"*& bit to 1.The output is converted into an anolog signal and it is compared with input
signal.The ouput is low or high.This process continues until all bits are chec<ed.
%.What are the main advantages of integrating type 9(Cs?
(o not re#uire a *L+ circuit at the input.
It is possible to transmit fre#uency even in noisy environment or in an isolated form.
).Eive the e8pression for output voltage D
a
of dual slope converters.
D
a
H 5D
$
75@7
5
n
7
where,
D
a
.J analog output voltage5Da7
D
$
.Jreference voltage
@.J digital count @.
3.(efine absolute accuracy.
It is the ma8imum deviation between actual converter output and ideal
converter output.
4.(efine relative accuracy.
It is the ma8imum deviation between actual converter output and ideal
converter
output,after gain and offset errors have been removed.
:.What is monotonic (9C?
9 monotonic (9C is one whose analog output increases for an increase in
digital input.
=.What is settling time?
It is the time ta<en for the output to settle within a specified band 51L7 !*&
of it*
0inal value following a code change at the input.

>.!ist out some 9L( converters.
9( :36 L9( :3%6
9( :31 L 9( :3%1
9(C 6=66 L 6=61 L6=6
%6. !ist out some (L9 converters.
(9C 6=66L6=61L6=6
(9C 6=%6L6=%1L6=%
(9C 166L161
(9C 16=L16>L116
%1.What is the main function of C*?
The input must be in its active low state for $( or W$ inputs to have any
effect.With C* high, the digital outputs are in the +i.R state,and no conversions can ta<e place.
%.(escribe the function of W$ and $( inputs.
$(5$ead7.This input is used to enable the digital output buffers.With
C*H$(H!/W,the digit output pins will have logic levels representing the results of the last 9L(
conversion.The micro computer can then read 5fetch7this digital data values over line system data
bus.
W$5Write7.9 !/W pulse is applied to this input to signal the start of a new
conversion.This is actually start conversion input.It is called a W$IT1 input because in a typical
application the microcomputer generate a W$IT1 pulse5similar to one used for routing to
memory7that drives this input.
%%.What is the function of the I@T$ output?
This output signal will go +IE+ at the start of a conversion and will return
!/W to signal the end of conversion.This is actually an end.of.conversion output signal,but it is
called I@T1$$,-T because in typical situation it is sent to microprocessors interrupt input to get
the microprocessors attention and let is <nown that the 9(C's data are ready to be read.
%).What is the purpose of D
I@
5.17?
In 9(C6=6),the input signal is varying over a range of 6.3 to %.3D.Inorder to
ma<e full use to the =.bit resolution,the 9L( must be matched to the analog signal
specifications.In this case, the full scale range is %.6D.+owever it is offset from ground by
6.3D.The offset 6.3D is applied to the negative input D
I@
5.17 establishing this as the 6 value
reference.
%3.What is step si;e or resolution?
The si;e or magnitude of each pin is the analog e#uivalent weight of the least
magnitude bit.This is called step si;e.
%4.What are analog signals?
-hysical variables that we want to measure,such as
temperature,pressure,humidity,distance,velocity
and so on,are continuously variable #uantities.9 transducer can be used to translate these
#uantities into
an electrical signal of voltage or current that fluctuates in proportion to the physical
variable.These
continuously variable voltage or current signal are called analog signals.
%:.What is ac#uisition time?
It is the amount of time the switch would have to remain closed.
%=.The ADC3<3< can multiple8 = different analog inputs into one 9(C.
9ART-B
UNIT-I
1.18plain in detail ,about photolithography, ion implantation and epita8ial
growth in IC
fabrication.
$efer -age @o.> in T1.
.18plain various methods of fabricating transistors in monolithic Integrated
circuit.
$efer -age @o.1 in T1.
%.0abricate a typical circuit using IC fabrication steps.
$efer -age @o.14 in T1.
). 18plain various methods of fabricating resistors in monolithic Integrated
circuit.
$efer -age @o.= in T1.
3.&riefly e8plain about crystal growing techni#ues.
$efer -age @o.3 in T1.
UNIT-II
4. (raw ^ 18plain the operation of a s#uare wave generator and obtain an
e8pression for its
fre#uency.
$efer -age @o.% in T1.
:.18plain with circuit and waveform the use of IC 333 as an monostable
multivibrator.
$efer -age @o. %4 in T1.
=. (raw the circuit of a Wien &ridge /scillator using /p.9mp and derive an
e8pression for
fre#uency of an oscillator.
$efer -age @o. )) in T1.
>. With the schematic of a simplest reali;ation of Doltage Controlled
triangularL*#uare Wave
/scillator and e8plain its waveform too.
$efer -age @o.%41 in T1.
16. 18plain in brief, with necessary diagrams, the astable mode of operation
of a 333 timer IC.
$efer -age @o.%)1 in T1.
11.(iscuss about monolithic voltage regulator IC !":%.*how connections
to supply
output voltage from to :D.
$efer -age @o.33 in T1.
1. (raw ^ 18plain the operation of a triangular wave generator and obtain
an e8pression for
its fre#uency.
$efer -age @o.%> in T1.
1%.&riefly e8plain about Instrumentatation amplifier with neat s<etches.
$efer -age @o.1)= in T1.
,@IT.III
1). (raw the circuit of C"/* @/$ gate.
$efer Class @otes.
13.(esign a synchronous decade counter using 2Y 0lipflops.
$efer -age @o.%4: in $1.
14.(esign a circuit which will go through the following se#uence using 2Y
0lipflops in T. 00
mode 1,%,:,4,1,_ If initial state of se#uence counter is ),chec< the
circuit you have
designed.
$efer Class @otes.
1:. If f1 H 9.&.C and f H 9?&?C .$eali;e the logic using C"/*
$efer Class @otes.
1=.(iscuss in brief about *tatic $9"s.
$efer -age @o. in $%.
1>.(iscuss in brief about (ynamic $9"s.
$efer -age @o. in $%.
,@IT.1D
6. 18plain in detail about any C"/* process with clear s<etches.
$efer -age @o.)=% in $.
1.Write in brief about *i Wafer preparation schemes.
$efer -age @o.3=3 in $.
. *how the flow diagram of major steps in bipolar IC fabrication
technology.18plain with
suitable figures.
$efer -age @o.)>> in $.
%.In brief discuss about re#uirement of design for D!*I ^ 0ailure
mechanisms and $ates in
semiconductor devices.
$efer -age @o. 43 in $.
).18plain in detail about @"/* IC technology.
$efer -age @o.): in $.
3.&riefly e8plain about the pac<aging of D!*I devices.
$efer -age @o.3>3 in $.
UNIT-(
4. 18plain in detail ,about $.$ ladder (9C and Inverted $.$ ladder
(9C.
$efer -age @o.%=: in T1.
:.18plain in detail about dual slope 9(C .
$efer -age @o.)6 in T1.
=.Write short notes on
i7 *witched Capacitor 0ilters
ii7 0unction Eenerators
$efer -age @o. )6> ^)>4 in T.
>. 18plain in brief about *uccessive 9ppro8imation 9(C.
$efer -age @o.)66 in T1.
%6. 18plain in brief about 0lash type 9(C.
$efer -age @o.%>3 in T1.
TE=T BOO>S7
1. (.$oy Choudhury, *hail 2ain ,A !inear Integrated CircuitsB@ew 9ge
International
-ublishers, @ew (elhi .
.$ama<ant 9.Eaya<wad , A /p.9mps and !inear ICsB.
REFERENCE BOO>S7
1. (.9.Eodse, 9.-.Eodse, A(igital *ystemsB ,Technical -ublications.
. *.".*;e ,AD!*I Technology B "c.Eraw +ill International 1ditions.
%. (igital 0undamentals by 0loyd.