Highly Robust Finfet Based Wide Fan-In Dynamic

OR Gate With Dynamic Threshold Voltage Control

Vikas Mahor and Manisha Pattanaik
VLSI Design Lab, ABV-Indian Institute of Information Technology and Management, Morena Link Road, Gwalior- 474010,
Madhya Pradesh, India
vikas@iiitm.ac.in, manishapattanaik@iiitm.ac.in

AbstractWide Fan-in dynamic OR gate has always been an
integral part of high speed microprocessors. But dynamic logic
gate suffers from low noise immunity. A weak PMOS keeper was
introduced to increase the noise immunity. Keeper technique acts
as a compensatory mechanism for charge loss due to leakage
current and maintains high noise immunity while allowing
leakage current through dynamic gate. A large size keeper is used
for wide fan-in dynamic OR gate which allows large leakage
current through the dynamic gate. This large leakage current
unnecessarily results in large power dissipation which can be a
critical factor for the microprocessors used in portable battery
operated devices. Recently double gate Finfet has been reported to
reduce leakage current effectively through it using threshold
voltage control through back gate biasing technique. In this paper
a new Finfet based wide fan-in dynamic OR gate has been
proposed with reduced leakage and high noise immunity. This
work reports a maximum leakage power reduction up to 70%
while maintaining high noise immunity as compared to basic
dynamic OR gate.
Keywords- Dynamic logic; Noise immunity; Finfet
I. INTRODUCTION
A highly noise immune leakage tolerant Finfet based wide
fan-in dynamic OR gate is proposed, which results in large
leakage power reduction and hence maintaining a high noise
immunity. Wide fan-in dynamic OR gate has always been a
suitable choice for the register file structure of any modern
high speed microprocessor. A large size keeper transistor used
in wide fan-in dynamic OR gate for increasing noise immunity
results in high leakage power. An effort has been made in this
work to reduce the dependability of wide fan-in dynamic OR
gate on keeper transistor for maintaining high noise immunity
while reducing leakage power dissipation. To achieve this
independent gate operated Finfet design has been used.
In this section firstly the importance of wide fan-in dynamic
OR gate is discussed and then the issues with the wide fan-in
dynamic OR gate are explained. Later in the section a brief
introduction to the independent gate Finfet device has been
given. Finally a brief review of some recently proposed Finfet
based wide fan-in dynamic OR gates is given.
A. Importance of wide fan-in OR gate in Register file
architecture
High speed microprocessors are used in almost all the smart
devices being used today such as iPhone, iPod, and mobile
phones [1]. Register files are integral part of such processors.
The register files are used almost in each clock cycle, as in
order to execute each instruction data should be read or written










(a) (b)













(c)

Figure.1. (a) Block diagram of a simplified register file, (b) read port
implemented using 4 x 1 multiplexer (MUX) [1] and (c) CMOS wide fan-in
dynamic OR gate
to the register file. Therefore register files forms an important
module in high speed microprocessors.
Fig. 1(a) shows the block diagram of such a register file
consisting of static RAM register, a read and a write port.
These ports are implemented using multiplexer and
demultiplexer whose implementation is shown in Fig. 1(b).
Fig. 1(b) illustrates a simple 4x1 multiplexer with 4 input lines.
Note that actual microprocessor would be consisting of 16 or
32 bit register file and hence would need 16 or 32 bit input OR
gate. Therefore, wide fan-in OR gate forms an important
structure in a high speed microprocessor. But designing a
highly robust wide fan-in dynamic OR gate is a difficult task in
sub 100nm regime [1]. High noise immunity and high
contention current are two major factors which make designing
the wide OR gate a challenging task.
B. Issues with wide fan-in dynamic OR gate
Due to low switching threshold of dynamic gates, it suffers
from low noise immunity [2]. When the dynamic gate is used
in high frequency circuits fabricated on highly dense chips,
then due to capacitive coupling of signals in the circuit
A


probability of noise affecting the input of dynamic gate
increases.
Wide fan-in dynamic OR gate shown in Fig. 1(c) suffers
from high leakage when all the inputs to the pull down
transistors are 0. This reduces the charge on dynamic node
and further reduces to noise immunity. To maintain the charge
at the dynamic node a feedback PMOS keeper transistor is
employed as shown in figure. This keeper increases the noise
immunity of the gate but at the cost of allowing leakage current
to pass through the dynamic gate. A typical Wide fan-in
dynamic OR gate with 32 or 64 inputs employs a large keeper
resulting in large leakage power dissipation through the
dynamic gate. Moreover the large size keeper causes large
contention between pull down network and keeper transistor
resulting in high power dissipation and large delay [1]. Trade-
off between delay and noise immunity is shown in Fig. 2, the
figure illustrates that an appropriate value of keeper to PDN
transistor width ratio (KPR) has to be selected to maintain high
noise immunity (UGN) for an acceptable amount of delay.
Unity Gain Noise (UGN) [8] is a noise metric used in this work
to measure the noise immunity, UGN is the maximum amount
of DC noise voltage available at all the inputs of PDN to cause
an equal amount of DC noise available at the output.











Figure 2. Delay and UNG of a wide fan-in dynamic OR gate versus keeper to
pull down transistor width ratio.
In the recent past authors have proposed many variants of
the wide fan-in dynamic OR gate [3], [4]. All designs are
capable of reducing contention and maintaining a high noise
immunity but at the cost of high leakage power.
C. Introduction to Finfet
Recently Finfet device has been reported to reduce the
leakage current using back gate bias. In this work a Finfet
based wide fan-in OR gate has been designed which is capable
of reducing the leakage power and maintaining high noise
immunity.
Fig. 3 shows a double gate Finfet device and its symbol.
Finfet devices are projected as the most likely substitute of the
conventional CMOS device due to its unique feature of
reduced short channel effects with scaling. Finfet can be used
in two different modes Shorted Gate (SG) mode (when the
front and back gate are tied together) and Independent Gate
(IG) mode (when the front and back gate are biased
independently). Apart from short channel effect reduction, the
threshold voltage of a Finfet can also be modulated
dynamically in the IG mode using back gate biasing technique







Figure 3. SG and IG mode Finfet device structure and symbol
[5]. In IG mode two different channels are formed beneath
each gate-oxide. Both the channels are capacitively coupled
with each other and hence voltage variation at one gate affects
the threshold voltage at the other gate. Suitable variation in the
back gate bias voltage V
gb
can be used to modulate the
threshold voltage of a Finfet. Work in [6] mathematically
explains the relation between back gate bias voltage (V
gb
),
front channel threshold voltage (V
thf0
) and back channel
threshold voltage (V
thb
). However an approximate relation for
threshold voltage modulation of Finfet using back gate biasing
can be taken from [6] as:







The ability of Finfet to modulate the threshold voltage
dynamically, actually allows the Finfet to be used for leakage
reduction. To illustrate leakage reduction capability of Finfet, an
N-Finfet is operated in the IG Mode as shown in Fig. 4. The
front gate voltage V
FG
is kept at 0 volt to ensure an OFF device
(leaking device). The back gate voltage V
GB
is swept from 0v to
-0.3v. The supply voltage is also varied from 0v to 1v. The
leakage current of N-Finfet is plotted against the supply


















Figure 4. Leakage current reduction with threshold voltage modulation in an
IG-Finfet

(1)

voltage (V
DD
) and the back gate bias voltage (V
gb
).
This result shows that how an IG Finfet can be used to
reduce leakage. This property of Finfet is utilized in this work
to make a low leakage high noise immune wide fan-in dynamic
OR gate.
D. Previous Works
Fig 5(a) shows a basic SG-Finfet based wide fan-in
dynamic OR gate. This design has an advantage over the
CMOS dynamic design that the short channel effects has been
reduced considerably, resulting in a reliable design. However
the design suffers from low noise immunity and large
contention.
Schematic shown in Fig 5(b) is IG-Finfet based wide fan-in
dynamic OR gate [3]. This design uses a single transistor as a
precharge device as well as a keeper. This reduces the
capacitive load on the dynamic node and hence reduces the
switching power dissipation. But still this design suffers from
high contention due large sized keeper.
Schematic in Fig 5(c) shows a high performance IG-Finfet
based wide fan-in OR gate design [4]. This design uses a
delayed clock to delay the input to the keeper and hence the
keeper remains OFF during initial period of evaluation phase.
This results in reduction of contention current and switching
delay but at the cost of reduced noise immunity during the
initial period of evaluation phase.
A common problem that can be observed with above three
designs is that the noise immunity of the designs is completely
depended on keeper size. Keeper maintains an appropriate
level of noise immunity while allowing large leakage to flow
through the PDN. In all designs on increasing the keeper size
noise immunity increases but at the cost of increased leakage
current.


(a)


(b)

(c)
Figure 5. (a) Basic SG-Finfet wide fan-in dynamic OR gate (b) High speed IG-
Finfet dynamic OR gate [3] (c) High speed IG-Finfet dynamic OR gate [4]
II. PROPOSED DESIGN
The proposed design aims at reducing the unwanted
leakage current for wide fan-in OR gate, along with achieving
high noise tolerance. In this section design, analysis and
operation of the proposed technique is described.
A. Design and Analysis:
The schematic of proposed wide fan-in dynamic OR gate is
shown in Fig. 6. In this design five Finfet transistors (N33
N36 and P3) has been added as compared to conventional
Finfet based dynamic OR gate. Transistor N33 has been
connected between the discharging path of pull-down network


















Figure 6. Proposed Finfet based wide fan-in dynamic OR gate

and footer transistor (N35). IG-Finfet N33 has been utilized
here to reduce the leakage through the PDN by the varying the
threshold voltage of N33 dynamically using the back gate bias
voltage V
N
. The circuit formed by SG-Finfets P3 and N36
connects back gate bias V
N
either to supply voltage V
DD
or to
the voltage source V
LOW
depending on the voltage at the
dynamic node V
X
. Voltage V
LOW
can be made available on chip
using many standard negative charge pumps discussed in [9].
Finfet N34 helps transistor N33 to discharge the dynamic node
faster when required.
To select an appropriate value of V
LOW
the tradeoff
between increase in delay and reduction in leakage is
considered here. The Leakage-Delay tradeoff for Finfet logic
circuits is explained in [7]. The switching delay and the amount
of leakage can be obtained by simulating the proposed design
on HSPICE using 32nm predictive technology model (PTM).
On simulating the design the leakage through the PDN (when
all inputs are 0) and delay of the circuit during worst case
delay condition (when any one input is 1) is noted down by
varying the supply voltage V
LOW
. The result is summarized in
Table 1.
From Fig. 4 it is clear that to obtain a maximum leakage
reduction through a Finfet, the back gate bias voltage should be
as low as possible. From Table I it can be observed that
although we are able to reduce leakage by reducing the voltage

TABLE I. LEAKAGE AND SWITCHING DELAY WITH RESPECT
TO VLOW
Low Voltage
Supply (VLOW)
Leakage Per Cycle (A) Switching
Delay (ps)
0 0.381 32.864
-0.1 0.311 33.021
-0.2 0.286 34.29
-0.3 0.193 36.88
-0.4 0.12 41.22
-0.5 0.081 44.15


V
LOW
but we need to pay the cost in terms of increasing
switching delay. However an appropriate value of V
LOW
(-0.3v)

can be selected by observing that there is not much increase in
the delay from V
LOW
0v to -0.3v and there is sudden increase in
delay from V
LOW
-0.3v onwards.
B. Operation of the Proposed Design:
Similar to conventional dynamic design the proposed
design has two phases of operation precharge phase and the
evaluation phase. During the precharge phase clock is high and
dynamic node is charged to V
DD
. During this period there will
be a high amount of leakage from the OFF PDN in a basic
Finfet Domino (Fig. 5(a)). However in the proposed design on
sensing a high VDD at dynamic node V
X
, the transistor N36
provides a back gate bias of -0.3v to the back gates of transistor
N33 and N34. This results in reduction of leakage in the
precharge phase as can be observed from the waveforms in
Fig.5. During the evaluation phase the clock is low and the
PDN is evaluated. However as explained in section I-B two
conditions during the evaluation phase are important, the worst
case delay (Named as Discharge condition) and the Leakage
condition. Both the conditions are explained as:
1) Leakage condition: In this condition the PDN is OFF and
leaking through the footer transistor in a basic Finfet
Domino (Fig.). In the proposed design as observed from Fig
4 and Fig 5, on sensing high V
DD
at the dynamic node the
transistor N36 keeps V
LOW
(-0.3v) connected to the back
gates of transistors N33 and N34 ensuring high threshold
voltages of both transistors and hence reducing leakage. In
the leakage condition high Vt OFF transistor N33 is stacked
with the OFF PDN transistors. Therefore both dynamic
threshold voltage and transistor stacking method has been
used for leakage reduction.
2) Discharge Condition: In this condition any one of the input
is ON and hence results in a worst case delay condition.
When the circuit switches from precharge phase to the
evaluation phase (Discharge condition) then the back gate
bias VN is still at VLOW, keeping transistor N33 as High
Vt and OFF. As observed from Fig. 6 and Fig. 7 during the
initial period of evaluation phase, voltage at the footer node
VFOOT increase to a high voltage. The high voltage at
VFOOT turns on the high Vt transistor N33, and dynamic
node V
X
slowly discharges. For a particular voltage at
dynamic node V
X
the transistor N36 becomes OFF and
transistor P3 becomes ON connecting High V
DD
to the back
gates of N33 and N34. Transistors N33 becomes low Vt and
Transistor N34 becomes ON ensuring fast discharge of
dynamic node. During initial period of evaluation phase
transistors N33 and N34 are still OFF and hence reducing the
chances of high contention current flowing from the keeper
towards the PDN.

III. SIMULATION RESULTS
To study the relative performance of the proposed design
with other recently proposed Finfet based wide fan-in dynamic
OR gate, the design in [3] and [4](Fig. 5(b),(c)) are simulated
along with the basic SG-Finfet wide fan-in dynamic OR
gate(Fig. 5(a)). All the designs are simulated on HSPICE using
the 32nm Finfet Predictive Technology Model (PTM).










Figure 7. Voltage variation at node Vx, VFOOT, VN and VOUT in the circuit
during precharge and evaluation phase.
The three voltage levels used for simulation are 1v as V
DD
, -
0.3v as V
LOW
and 0v as Ground reference at 72
o
c temperature.
Table II compares the UGN, Power dissipation, Delay and
Maximum operating frequency of the various designs with
proposed design. With leakage reduction, the average leakage
power per cycle has been reduced by 70 % as compared to
basic Finfet based domino design. As a result of this the UGN
of the proposed design has been increased by more than 50 %
as compared to basic domino without much degradation in the
speed of the proposed design. Switching delay () has been
calculated during the worst case delay condition. Maximum
frequency of operation is calculated as 1/2, keeping more than
50% duration of the evaluation phase reserved for settlement of
signals. Due to reduction in contention current (as discussed in
section II(A)), the switching delay of the proposed design has
been reduced as compared to the basic domino. This can be
observed from the table II, where the switching delay of the
proposed design reduces by 36 % as compared to basic domino
design. As discussed in section I(B), for a wide-fan in OR gate
we need to maintain a tradeoff between UGN and delay by

TABLE II. UGN, POWER DISSIPATION, DELAY AND OPERATING FREQUENCY COMPARISON AT KPR = 1

using an appropriate value of Keeper to Pull-down transistor
width ratio (KPR). This dependence of UGN on KPR has been
removed in the proposed design. In the proposed design high
noise immunity (high UGN) is achieved by controlling the
leakage through the PDN instead of depending on the keeper
size. This makes the UGN of proposed design almost
independent keeper size as opposed to other designs where the
UGN completely depends on the keeper size. The above
discussion can be verified with the simulation result in Fig. 8.
As discussed in section II(B) the contention current in the
proposed design has been reduced due to a non-existing path
from keeper to the ground during initial period of evaluation
phase. This can be verified from Fig. 9, which illustrates a 70%
reduction in peak value of contention current as compared to
basic Finfet based domino design.

IV. CONCLUSION
A novel Finfet based wide fan-in dynamic OR gate is
proposed, which is capable of increasing noise immunity by
reducing leakage current and making noise immunity
independent of the keeper size. For reducing leakage proposed
design makes use of dynamic threshold voltage control
mechanism through back gate biasing in an IG-Finfet.
Proposed design is capable of reducing leakage power by 85 %
as compared to standard Finfet based domino. Since high noise
immunity is achieved by reducing leakage, therefore a small
sized keeper is sufficient for maintaining required noise
margin. With low leakage, the proposed design is capable of
achieving high UGN, which is 50%, 48% and 55% higher than
the standard Finfet based domino, Finfet domino in [3] and [4]
respectively. A small size keeper used in the design results in
lower contention and hence less delay. With low contention,
the proposed design is capable of reducing delay and achieving
high speed. The delay is reduced by 36% as compared to
standard Finfet based domino. To illustrate the reduction in
contention between PDN and keeper, the current through
keeper is measured. The peak value of this contention current
is 70% lower than the peak value of contention current in
standard Finfet domino.

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Figure 8. UNG and delay comparison with respect to the keeper to pull down
transistor width ratio (KPR).

Figure 9. Contention current through the keeper during evaluation phase
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UGN
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(GHz)
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Cycle(W)
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