Verilog Reduction of a Voting Machine Verilog

Instructions
EE 1010 Introduction to ECE Digital Module, Part 2

Introduction: As mentioned last week, there are many powerful tools to implement
digital designs with. This can either be done on a gate by gate level like we did last week
or with devices known as Complex Programmable Logic Devices (CPLDs). You will be
introduced to CPLDs in the EE/COSC 2390 digital class, so we will not be using them
here. To implement a design using a CPLD, we use a synthesis tool designed for that
chip. The package we will use is Xilinx ISE version 6.3. Even though we will not
implement our voting machine design using a CPLD, we can use the Xilinx software to
create a Boolean equation for our machine and even show us the gate implementation of
it.

Procedure:

1) Begin by copying the project to a personal storage area such as the c:\temp
directory or your netuser (U: drive) space (if you have set up your EE
account). The project is located under K:\Pierre\ee1010\vote_machine2006.
Be sure to copy the entire folder, not just part of it.

2) Once you have copied the project somewhere you can modify it, open up the
Xilinx software. Do this by double clicking the Project Navigator icon on the
desktop or go to Start ->All Programs ->Xilinx ISE 6 ->Project Navigator

3) Once the Xilinx ISE software opens, go to File ->Open Project and browse to
where your project is stored. Under the vote_machine folder, there should be
a file named vote_machine.npl. This is the file we want to open.

4) Once the file opens, in the upper left there should be a Sources in Project
tree. Double click on the second vote_machine listing to open it.

5) You may want to expand the editing window so you can see most of the
project in one sitting. This simple C looking code is actually written in the
Hardware Descriptive Language (HDL) Verilog. Near the bottom of the
module you should see case({A,B,C,D}) followed by the entry 4b0000:
PASS=0; This entry is the first entry of your truth table when all of the votes
are negative. The A, B, C, and D terms represent the individual voters of the
corporation with A being Mr. Quine, B being Mrs. Karnaugh, C being Mr.
Boole, and D being Ms. McCluskey. The next case shown is when all votes
are positive and the motion passes. Use this outline to fill in the remaining
truth table items (HINT: there should be 16 of them total). If you need to
draw up a separate truth table and then fill in the Verilog code, feel free to do
so.

6) After typing in the truth table using the same format, save the project. The
best way to do this is to click the multiple disk icon (Save All) on the toolbar
at the top. This saves any of the open project files.

7) Once the project is saved, in the middle left hand side of the window, there
should be the Processes for Source: vote_machine tree diagram. Double
click on the Implement Design entry. A message should appear in the
bottom message window stating Started process Synthesize. If a message
pops up asking if you want to reload a file, click Yes. Wait a few seconds
until Release 6.3.03i CPLD HTML Report Processor G.38 is displayed. If
an Internet Explorer script error pops up, simply click No on it. If any other
errors pop up, check your truth table syntax or call one of the instructors over.

8) The design is now optimized and reduced so we can implement it digitally.
The Xilinx software should automatically open the CLPD Reports summary
window. If it does not, first click the plus next to Implement Design to
expand the tree. Find Fit under the tree and expand it as well. Under Fit,
there is an option called Fitter Report. Double click this option to open the
fitter report in the editing window.

9) The fitter report tells you how the design was fit into a particular CPLD, how
pins are used, and other useful information. However, the only thing we are
interested in is the reduced Boolean equation. On the left hand navigation
pane, click Equations. At the bottom of this pane, there should be the
option Equation Display Style. Change this to VHDL. It should display
something along the lines of assign PASS =(X AND Y) OR (C AND D)
only it will only use A,B,C, and D since those were our inputs. This is the
equation we will create using the gate chips like we did last week. Write the
equation down for reference.

10) Ask the instructor or teaching assistant to verify your equation. If it is correct,
you will be given a schematic representation. Use this schematic to layout
your gates and label the pins for the 74LS08 2 input AND gates and 4075 3
input OR gate.

11) Even though we will not implement the reduced equation using the Xilinx
chip, it is useful to see how the software implemented your design in the
95000 series CPLD. Click Pin List on the left hand navigation pane. The
assignment of each of the Xilinx chips 84 pins is visible now. If we were to
actually program the CPLD using the Xilinx software, this information would
tell us how to connect our switches, LED, and power to the final design.