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A NEW CONCEPT OF MULTILEVEL STATCOM BASED ON

CASCADE TOPOLOGY

Emil KOT, Grzegorz BENYSEK Ryszard STRZELECKI


University of Zielona Góra Gdynia Maritime University
Zielona Góra (Poland) Gdynia (Poland)

Abstract - Paper presents one way for power STATCOM acts as a sinusoidal, with fundamental
quality conditioning. This way means parallel frequency, voltage source, therefore described con-
connection of the STATCOM circuits with the ditioner makes possible to get:
network, therefore it is possible to “isolate” load i) sinusoidal source current;
from source and vice versa. Described condi- ii) reactive power compensation;
tioner makes possible to get: i) sinusoidal source iii) load voltage stabilization;
current; ii) reactive power compensation; iii) load iv) balanced source in conditions of the unbal-
voltage stabilization; iv) balanced source in con- anced load.
ditions of the unbalanced load. As STATCOM, Because STATCOM has to “produce” sinusoidal
the four level cascade based VSI has been used. voltage, multilevel Voltage Source Inverters (VSI)
To confirm results of the theoretical analysis are the perfect solution in this case [10]-[11]. Onto
some experimental results were presented. Addi- needs of the STATCOM, four-level cascade based
tional, control algorithm, to shape six-step output VSI inverter was developed [12].
voltage is proposed.

This work was supoorted by Polish Committee for 2. MULTI-LEVEL VSI


Scientific Research under Grant Nr 4T10A 037 25
pt.„Energoelektroniczne układy elastycznego ste- It is possible to notice more and more publications
rowania przepływem mocy w rozproszonych syste- concerning modernization and development, one of
mach zasilających prądu przemiennego” the basic directions in building DC/AC converters,
which there are multi-level voltage inverters, formu-
lating step voltages using few supply sources both iso-
1. INTRODUCTION lated as sectioned. Absence in such inverters trans-
formers takes off limitations in output voltage fre-
In professional literature [1]-[5] there are de- quency control in range of low frequencies. In result it
scribed many different ways to “isolate” sources is possible to distinguish three basic solution direc-
from disturbances introduced by the nonlinear loads tions of multi-level voltage inverters topologies:
and vice versa. For example to compensate reactive - multi-level voltage inverters with levelling di-
and higher harmonics currents, produced by the odes (DC- Diode Clamped);
nonlinear loads, STATCOM (STATic COMpensa- - multi-level voltage inverters with levelling ca-
tor) can be used [4]-[9]. In those systems (independ- pacitors (CC- Capacitor Clamped);
ent with control algorithm) there is need to extract, - multi-level voltage inverters as Isolated Series
from measured load or source currents (it depends if H-Bridges (ISHB), also called multi-level cas-
control algorithm is in open or closed loop), com- cade inverters;
pensating components, therefore the filtration qual- On the base of above been mentioned structures, it is
ity is as good as well it is possible to extract com- possible to create group of the new inverter topolo-
pensating components and shape them. gies as connection of the standard three-phase in-
Paper presents a one way of power quality im- verters with one-phase bridge inverters.
provement. In presented solution, power quality im- All above mentioned structures makes possible ob-
provement is possible to get if parallel connected tainment quasi-sinusoidal output voltages, in result
a) of what, it is possible to reduce or even to resign
from applying additional filtering arrangements. It is
a huge advantage mainly in refer to use of them in
drive and telecommunication, etc. Besides those in-
verters can be built on higher voltages than conven-
tional (with two voltage steps), what in case of de-
vices working, e.g. in industrial average voltage sys-
tems can lessen whole arrangement about fitting
transformer. Multi-level VSI are created among oth-
ers to improve output voltage wave shape. Because
b) multi-level voltage (reminds more sinusoidal) it con-
tains less higher harmonics, also extorted load cur-
rent is more sinusoidal (Fig.1a,b).

2.1. Proposed topology multi-level VSI

Fig.2 presents proposed inverter, which is a se-


ries connection of one-phase transistor bridges with
three-phase voltage inverter. Proposed inverter can
work both in three- as well as four-line nets in last
Fig.1. Phase-to-phase output voltage and its spec- case supply source on inverter input contains divider
trum: a) standard VSI inverter; b) cascade topol- from two capacitors, creating zero point.
ogy multi-level VSI(without PWM).

STATCOM
Udc1 T5 T5' T5'' VSI 2L
C/2
C

N C/2
T6 T6' T6''
VSI 3L1
L1 Udc2 T1 T2

C
T3 T4 VSI 3L2
L2 T1' T2'
C
Udc2

T3' T4' VSI 3L3


L3 T1'' T2''
C
Udc2

T3'' T4''

L1 UL1-2 L2 L3

T1 L
UL1

R
Load
N

Fig.2. Cascade topology based multi-level voltage inverter (experimental circuit)

Basic blocks of this type of inverter there are age values were accepted Udc2 and Udc1. All three
conventional three-phase inverter (T5-T6; T5’-T6’; one-phase bridges with unipolar modulation are
T5’’-T6’’), as well as tree one-phase bridges (T1- shaping three-step output voltage (VSI 3L), mean-
T4), (T1’-T4’), (T1’’-T4’’) from which every one is while three-phase bridge with bipolar modulation
connected in series with half-bridge of the three- shapes two-step phase voltage (UVSI 2L). Fig.3 pre-
phase inverter. Individual modules require isolated sents formation of the phase-to-phase output voltage
supply source. During registration even supply volt- UL1-2. It is a sum of voltages on one-phase of the in-
which is sum of output voltages first (VSI 2L) and
second (VSI 3L1) inverter with bipolar and unipolar
modulations and in result of this it is for-even-level
quasi-sinusoidal curve (when Udc1=Udc2).

Triangular signal

Sine waveform
UVSI 3L1

UVSI 2L
Fig.3. Voltage curves presenting phase-to-phase vol-
tage construction (from above: Ref2 – two step UL1
inverter phase-to-phase output voltage VSI 2L,
Ch2- three-level inverter output voltage VSI
3L2, Ch4 three-level inverter output voltage VSI
3L1, Ch1 – cascade multi-level inverter phase- Fig.5. Inverter bridges voltages summation to show
to-phase output voltage UL1-2) formulation of the four-level phase voltage

verter and phase-to-phase voltage of the three-phase 2.3. Experimental model


inverter (UL1-2=UVSI 3L2-UVSI 2L-UVSI 3L1). Number of
levels in the phase-to-phase output voltage, in three Experimental investigations (Fig.6 - Fig.9) were
line net, carries out N=2n-1, where: n- number of made with the following parameters: Udc1=Udc2=
levels in phase voltage for four line net. In this case 50V; load resistance R=20Ω and inductance
7-step output voltage in cascade topology based in- L=2mH. Analog PWM follow-up modulator with
verter is generated. 12kHz frequency was applied.

2.2. Control algorithm

In system presented in Fig.4. difference signal VSI 3L1 VSI 3L2 VSI 3L3
between current reference value iZ and real value iL
is given to proportional-integrating (PI) regulator.
Exit signal of this regulator is compared with three
triangular signals with frequencies of the commutat- VSI 2L
ing switches and with even amplitudes. Triangular
signals are shifted in relation to itself with amplitude PWM follow-
value as it is in Fig. 5. Result of comparison is given up modulator
to the comparator, which forms steering impulses
with modulated widths. Arrangements possess con-
stant switching frequency. Fig.6. Experimental model view of the multi-level
cascade topology inverter.
GNP
Udc

regulator PI
+
iz
+ FN
+
iL

Q Q Q
komparator T3 T5 T2
/Q /Q /Q ,u L
T1 T6 T4

Fig.4. Arrangement for load current course forma-


tion with constant switching frequency

Fig.5 presents inverter output voltage for one phase, Fig.7. Reference signal and load current, RL load.
cies. Triangular signals are shifted in relation to it-
self with value of amplitude how it shows Fig.11.a).
Principle of operation of the control algorithm is
similar how in Fig.4, with this that additionally on
exit of comparator logical arrangement was applied.

GNP GNP
Udc
Udc
regulator PI -
- +
iz - +
- +
- +
iL +
FN
Q Q Q Q Q

komparator /Q /Q /Q /Q /Q

Fig.8. Phase voltages of the cascade four-level VSI. uklad


logiczny

a) T1 T2 T3 T4 T5 T6

uL

Fig.10. Modified control algorithm of the proposed


multilevel VSI, where it is possible to shape six-
level phase output voltage .
a) Triangular signal

Sine waveform

b)

T1
b)
T2
T3
T4
T5
T6

c) UVSI 3L1
Fig.9. Phase-to-phase voltages of the proposed four-
level VSI a) with PWM, b) without PWM. UVSI

2.4. Extension of control algorithm UL1(4L)

So far there was considered multi-level cascade


topology inverter, in which supply voltage values on
UL1(5L)
individual inverter bridges were even Udc1=Udc2. d)
Then phase output voltage was sum of voltages on
one-phase bridge and half-bridge of the three-phase
UL1(6L)
inverter (Fig.5). Founding, that Udc1 ¹Udc2 as well as
applying control algorithm, which both makes pos-
sible summation as well as subtraction of voltage
values, it is possible on four level inverter topology Fig. 11. Voltage time base wave shapes presenting
to shape six-level phase voltage. phase voltage level formulation for proposed to-
Proposed diagram of the modified control algorithm pology: a) signal representing PWM; b) control
presents Fig.10. Modulation in this control algorithm signals (for one branch); c) voltages summation
was made on five comparators where there was and 4-level voltage UL1(4L) for Udc1=Udc2; d) 5-
compared sinusoidal modulating signal with five tri- level voltage UL1(5L) for Udc1=2Udc2 and 6-level
angular signals with even amplitudes and frequen- voltage UL1(6L) for Udc1=4Udc2.
Fig.12. shows voltage vectors in one-phase inverter parameters presented in Tab.1, was developed. Dur-
bridge and in one leg of the cascade inverter, which ing investigations DC link voltages were even
illustrate formation of levels in output voltage. From UDC1 =UDC2=UDC3=UDC4 and on output of the cascade
analysis of voltage vectors it results, that at mainte- based four level VSI a couple choke was imple-
nance of condition Udc1=Udc2, proposed topology mented.
VSI shapes 4 level phase voltage (Fig.11c; Fig.12b),
Tabl.1. Investigated system parameters
at maintenance of condition Udc1=2Udc2; five-level
(Fig.11d, Fig.12c), meanwhile at Udc1=4Udc2 – six- STATCOM
level (Fig.11d, Fig.12d). Source voltage 80 [V]
4 level 4 level
DC link voltage 70 [V]
a) b) Udc2 Couple choke LS 5.4 [mH]
Udc2 DC link capacitance C 2200 [mF]
3 level Udc2 3 level
Udc1 switching frequency 10 [kHz]
Udc1
2 level 2 level
Udc2 Udc1 Fig.(13-17) present experimental waveforms, during
Udc2 steady state operation of the STATCOM VPQC, for
1 level Udc2 1 level
two different load types, linear (resistive-inductive
6 level load) and non-linear (six pulse rectifier with resis-
Udc2 tive-inductive load).
c) d) 5 level
5 level Udc2
Fig.13 illustrates investigated conditioner’s behav-
Udc2 4 level
4 level
iour in situation of linear R-L load, R=20 [W] , L=72
Udc1 Udc1
Udc2 3 level [mH]. It is seen from this figure that multilevel
Udc1 3 level
Udc2 2 level Udc2
STATCOM has meaningful influence on the source
2 level current, distortions, in which, mostly come as result
Udc2 1 level Udc2 1 level of the distorted supply voltage ( Fig.14).

Fig.12. Voltage vectors presenting phase vol-tage a)


level formulation for cascade topology from
Fig.2: a) with 4levels for standard control from
Fig. 4 and condition Udc1=Udc2; b) with 4 levels
for modified control from Fig.10 and condition
Udc1=Udc2; c) with 5 levels for modified control
from Fig.10 and condition Udc1=2×Udc2; d) with
6 levels for modified control from Fig.10 and
condition Udc1=4×Udc2

In proposed method of voltages formation with 4, 5,


b)
6 levels, in cascade topology inverter with supply
condition Udc1 ≠Udc2 there are voltage "stresses” on
switches. Analysing one branch of the cascade in-
verter’s, for case from Fig.11b) voltages on transis-
tors of the inverter VSI 3L1 are two times larger
than on transistors of the three-phase inverter’s VSI
2L; what leads to larger commutation losses. For
case from Fig.11c) voltages on transistors are the
same, meanwhile for case from Fig.11d) larger volt-
age stresses are n transistors of the one-phase in-
verter VSI 3L1 o. In this of case losses of the VSI Fig.13. Symmetrical RL load: a) load; b) source (Ch-
3L1 inverter, are larger than those of the three-phase 1: source voltage (phase L1); Ch-2, Ch3, Ch4 –
bridge inverter’s. load/source currents in three phases.

Above figure illustrates also the reactive power


3. RESULTS IMPLEMENTATION PROPOSED compensation capability. Fig.15. demonstrates con-
VSI FOR STATCOM ditioner’s possibility for balancing the unbalanced
loads in conditions of balanced source. Fig.16. dem-
To verify results of the theoretical investigations onstrates the filtering capabilities of the multilevel
a down scale multilevel VSI hardware model, with STATCOM. As one can see from those figures, the
load current contains a large amount of harmonics a)
due to the six pulse rectifier with resistive-inductive
load, however the source current is almost sinusoi-
dal, see Fig.16. and Tab.2.
As it was told earlier, in the paper, STATCOM, with
described control algorithm, is “sensitive” on supply
voltage variations (sags, dips), one can see from
Fig.16. that those variations have impact on nature
of the source current, in our case, because of source
voltage magnitude is over it’s nominal value, be-
comes more inductive. Additionally Tab.2 presents b)
the THD coefficients in characteristic points of the
investigated STATCOM and Fig.17 [13] demon-
strates, in conditions of the non-linear load, four
level cascade based VSC’s DC link voltages.

c)

Fig.14. From above: Ch3 source voltage; Ch4 - mul-


tilevel VSI output voltage; Ch2=Ch3-Ch4 .

a) Fig.16. Non-linear load, source voltage magnitude


over it’s nominal value (3%): a) P2=0.8 [kW];
b), c) P2=1.2 [kW]. Ch-1: multilevel VSI output
voltage; Ch-2: source current; Ch3- source volt-
age; Ch4- load current.

b)

Fig.17. DC link voltages. From above: R-1: UDC1; R-


2:UDC2; R-3: UDC3; R-4: UDC4.

Tabl.2. THD Coefficients


THD [%]
Fig.15. Linear no symmetrical RL load: a) load side; I1 U1 IL Uc
b) source side (Ch-2, Ch3, Ch4 – load/source Non-linear 0.8 [kW] 3,3 3,3 25,3 2,9
currents in three phases) load 1.2 [kW] 2,6 3,5 24,2 3,7
4. CONCLUSIONS zasilające w energetyce”, Kozienice, marzec 2004,
pp.26.1-26.13.
Paper presents three phase STATCOM based on 9. R. Strzelecki, G. Benysek, A. Noculak: Wykorzysta-
the four level cascade VSI, which permits to fulfill nie urządzeń energoelektronicznych w systemie elek-
various tasks. To verify properties of the proposed troenergetycznym. Przegląd Elektrotechniczny, Nr.2,
conditioner’s a down scale hardware model was de- 2003, p.41-49.
veloped. On the base of experimental investigations 10. S. Bum-Seok, L. Yo-Han, H. Dong-Seok, T. Lipo.: A
one can say that: new multilevel inverter topology with hybrid ap-
- conditioner can free from higher harmonics proach, EPE Conference, Lausanne, 1999.
source current, even in situation of strongly de- 11. J. Song-Manguelle, S. Mariethoz, M. Veenstra and A.
formed load current; Rufer: A Generalized Design Principle of a Uniform
- conditioner stabilizes load voltage in situation of Step Asymmetrical Multilevel Converter For High
source voltage magnitude variations; Power Conversion, EPE Conference, Gratz, 2001.
- conditioner possess the reactive power compen- 12. G. Benysek, E.Kot, A. Baranowski.: Comparative
sation capability; analysis of the parallel active filters on base of the
- conditioner possess the capability of balancing multilevel inverters. EDPE Conference, Dubrovnik,
Croatia, pp.38-43, 2000.
the unbalanced loads in conditions of balanced
source; 13. R. Strzelecki, G. Benysek, J. Rusiński, E. Kot.:
- load voltage stabilization in conditions of the Analysis of DC Link Capacitor Voltage Balance in
Multilevel Active Power Filters, EPE’01-Graz.
source voltage magnitude variations leads to the
input reactive power growth;
- to avoid problem of the source voltage shape in- Prof. Ryszard Strzelecki
was born in 1955 in Bydgoszcz, Poland. He received the
fluence on the filtration quality, control algorithm
M.Sc. and Ph.D degree from Technical University in
has to be equipped with low pass filter to check Kiev. He received his D.Sc. degrees from Institute of
source voltage harmonics. Electrodynamics Academy Since of Ukraine. Presently,
he is Full Professor of the Gdynia Maritime University.
His areas of interest include power electronics circuits,
5. REFERENCES electric power quality and power flow controller
Mailing address: Ryszard Strzelecki
1. Ghosh A., Ledwich G: Power Quality Enhancement Gdynia Maritime University, Depart. Of Ship Automation
Using Custom Power Devices. Kluwer Academic Pu- 81 Morska Str, 65-246 Gdynia, POLAND
blishers, Boston, 2002. phone:(+48 58) 6901204, fax:(+48 58) 69-01-445
2. H. Fujita, Y. Watanabe, H. Akagi: Control and e-mail: rstrzele@am.gdynia.pl
analysis of a unified power flow controller, IEEE
Trans. Power Electronics, 14, 6, 1999, pp.1021-1027. Dr. Grzegorz Benysek
3. F. Peng, H. Akagi, H. Nabae: Compensation charac- was born in 1968 in Kramsko (district Zielona Góra), Po-
teristics of the combined system of shunt passive and land. He received M.Sc. and Ph.D. degrees from the
series active filters, IEEE Trans. on Industry Applica- Technical University of Zielona Góra. At present he is
tions, 1993, Vol.29, No.1, pp.144-15. Researcher in the University of Zielona Góra. His fields
of interest is in power electronics and distributed genera-
4. R. Strzelecki, H. Supronowicz: Power factor in AC tion.
supply systems and improvements methods, Publish-
ing house of the Technical University of Warszawa, Mailing address: Grzegorz Benysek
Warszawa 2000. Univ. of Zielona Góra, Institute of Elec. Engineering
5. R. Strzelecki, J. Rusiński, G. Benysek: Voltage 50 Podgórna Str., 65-246 Zielona Góra, POLAND
source power quality conditioner, Electromagnetic phone:(+48 68) 3282417, fax:(+48 68) 3254615
phenomena in Nonlinear Circuits - EPNC 2002, XVII e-mail: G.Benysek@iee.uz.zgora.pl
Symposium. Leuven, Belgia, 2002, pp. 179-182.
MSc. Emil Kot
6. N.G. Hingorani, L. Gyugi: Understanding FACTS. was born in 1974 in Bytom Odrzański, Poland. He re-
Concepts and Technology of Flexible AC Transmis- ceived M.Sc. degrees from the Technical University of
sion Systems. IEEE Press, New York, 2000 Zielona Góra. At present he is Researcher in the Univer-
7. C. Schauder: STATCOM for Compensation of Large sity of Zielona Góra. His fields of interest is in power
Electric Arc Furnace Installations: Proceedings of electronics, in particular multilevel converters.
the IEEE PES Summer Power Meeting, Edmonton,
Alberta, July 1999, pp. 1109-1112. Mailing address: Emil Kot
University of Zielona Góra, Institute of Elec. Engineering
8. R. Strzelecki, G. Benysek: Układy STATCOM i ich 50 Podgórna Str., 65-246 Zielona Góra, POLAND
rola w systemie elektroenergetycznym. Międzynaro- phone:(+48 68) 3282538, fax:(+48 68) 3254615
dowa Konf. Nauk-Tech. „Nowoczesne urządzenia
e-mail: E.Kot@iee.uz.zgora.pl

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