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Abstract
Low power consuming nano devices have been a dominant issue from the very inception of nano device research. The improved
e-beam lithography technique has been the blessings to the device engineers and many novel technologies were invented
including the Single Electron Transistor technology during post CMOS era. It showed enormous scope in dealing scaling limits
of CMOS technology but the detailed research revealed is fragility like room temperature operation, low gain and background
charges. Simultaneously Scientists came up with the idea to cope up with this problem by hybridizing CMOS-SET. Their efforts
paid off by successful implementation of this logic. Here our attempt was to employ the same technology for complex
architecture; thus the Moore and Mealy model was chosen. To confirm the acceptability of the proposed model it was simulated
in T-Spice simulation software and the results were of good trade-off.

Keywords: Hybrid CMOS-SET based Moore and Mealy model, e-beam lithography, tunnel junction, Coulomb Island.

1. INTRODUCTION
The 2003 edition of the International Technology Roadmap for Semiconductors predicts that in 15 years ultra-thin body
(UTB) CMOS transistors will reach gate lengths of 10 nm [1] based on Dennards theory of scaling [2]. Researchers
have predicted further that todays device speed has enhanced by four orders of magnitude from the earlier device speed
[3]. To the contrary, device down scaling by no means is a never-ending process. The limitations of CMOS scaling are
(i) minimum allowable channel length, (ii) random doping placement effect, (iii) depletion depth and junction depth,
(iv) minimum gate oxide thickness, (v) minimum supply voltage, etc. causes the limitations in physical laws and the
application laws of the CMOS technology. Furthermore, the limitations caused by (i) photolithography process, (ii)
integration process, (iii) low dielectric and super conductors and (iv) fabrication methods play a major role in the
manufacturing limits of CMOS technology. Empirical study on scaling limits of CMOS technology has been revealed
in many research publications so far [4 - 8]. Owing to such limiting factors, the size of the device will not cross the 22
nm mark even with latest e-beam lithography technique [9 - 14].
Scientists gave emphasis to the search for substitute technologies in post CMOS era. This search received a major
research boom for the last two decades and also produced several new technologies. Amid the new invented
technologies, Single Electron Device (SED), Carbon Nanotubes, Rapid Single Flux Quantum (RSFQ), Resonant
Tunneling Diodes (RTD), and Magnetic Spin devices [15-20] are quite impressive. Researches in Quantum Electronics
and Single Electronics are mostly accepted to replace the present CMOS technology in realizing much smaller devices.
Furthermore the quantum effect is a key function in designing future ultra small electronic device architectures. Despite
these facts, quantum effects is poised with some intrinsic limitations like (i) material and process related limitation, (ii)
power limitation, (iii) wiring limitation, (iv) quantum mechanical limitation and (v) system architecture limitation.
These shortcomings of the quantum effects categorically diminish the idea to incorporate quantum effects for VLSI in
the post CMOS era. This increases the opportunity for SED to be adapted in future technology to meet the required
increase in density and performance as well as the decrease in power dissipation [21-25].
Single electron transistors are often discussed as elements of nanometer scale electronic circuits because they can detect
the motion of individual electrons and hence can be made very small [26, 27]. But, SETs have high output impedance
and are sensitive to random background charges. This makes it unlikely that SETs would ever replace FETs in
applications where large voltage gain or low output impedance is necessary [28, 29]. The real problems preventing the
use of SETs in most applications are the (i) low gain, (ii) the high output impedance and (iii) the background charges.
Because of these limitations of SETs, it now seems that it has to go under extensive research before commercially
designing a SET based dense integrated circuits using the existing technology. Scientists even fear that ample
substitution of CMOS by SET is ambiguous. To overcome these difficulties scientists have explored a novel concept of
Hybrid CMOS-SET'; they adapted this approach of combining CMOS-SET to transport new functionalities of electron
which leads to better device manufacturing. Such incorporation smooths the pathway in device research to change
CMOS to SET in present context. The notion of hybrid CMOS-SET architectures although is in elementary stage but
Analytical Modeling of Hybrid CMOS-SET
Based Moore and Mealy Logical Circuit

Jayanta Gope
1
, Bikash Gupta
2
and Rupesh Anand
3


1
Professor, ECE Dept. Camellia School of Engineering and Technology, Kolkata, India
2& 3
Student, ECE Dept. Camellia School of Engineering and Technology, Kolkata, India
IPASJ International Journal of Computer Science(IIJCS)
Web Site: http://www.ipasj.org/IIJCS/IIJCS.htm
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empirical studies have been initiated both in industry and academia. Consequently, Toshiba demonstrated the
performance of a hybrid MOS-SET inverter [30] which ushered new possibility of hybridization in low power VLSI
design. Here we confine ourselves to study this novel hybrid CMOS-SET technology by designing Moore and Mealy
model in order to exploit the unmatched merits of this maneuver.

2. SET IN BRIEF
The device, much similar to FETs comprises of three terminals: both the outside terminal of each tunnel junction, and a
gate terminal, which is capacitively coupled to the node connecting the two tunnel junctions. The simple SET circuit
formation exhibits single electron charging effects in the single electron box. The tunnel junction attaches a metal
granule in one side of the surface where the electrons can liberally tunnel in and tunnel out. The most interesting
Coulomb interaction process of the single charge controls the correlated electron tunneling. [31] Regarding fabrication
the size and capacitance C of the tunnel junction is made small enough to make the tunneling of only one electron so
that it can generate a noticeable change e/C of the voltage across the junction. Moreover, a single electron can pile up
one bit of information, thereby reducing the power consumption. Thus SET made Single electron devices manipulate
individual electrons and ultimately utilize them in the form of the electron devices. Empirical results showed how the
momentum power product of SET is forecasted to lie close to the quantum limit set by the Heisenbergs uncertainty
principle. Thus the processing speed of such device is likely to match with the electronic speed. Similarly, delicate
sensitivity is about five orders of degree heightened than conventional solid-state CMOS transistors [32].

2.1 Tunneling of Electrons
Tunneling junction, a crucial characteristic of SET posses an innumerable number of applications in modern
technological era. The Fig.1 exemplifies the quantum justification of tunneling flanked by two metal plates of the
tunnel junctions. The electrons are held in between the metal plates by a potential wall, just like a box of finite height.
The electrons are hoarded up in thick or close spaced energy points because the box is incredibly spacious [33].


Figure 1 Tunneling phenomena through two metal plates of the tunnel junctions

The Pauli Exclusion Principle as stated is that all levels from the lowest energy state up to the Fermi level are filled at
T=0K. A few potential electrons are exited to higher levels with the rise in temperature from 0K. The work function is
referred to the variation in energy levels amid the Fermi level of the uncharged junction and the peak of the barrier
level. Thus by computing the Work function (W) and the voltage (V
s
) across the tunnel junction the barrier
transmission coefficient is calculated. The number of available states and the barrier transmission coefficient in group
function as a Conductance (G
t
) in a circuit where a tunnel junction is excited by a voltage source (U
s
); thus it resembles
that i=G
t
U
s.
The modus operandi of SET is that during operational activities the electron tunnels from the first point of a tunnel
junction to the end point of the tunnel junction and thereby changes the charge distribution of the respective circuit. For
uninterrupted tunneling the tunnel resistances (R
T
) and the fundamental resistance (R
q
) resides in a correlation
governed by the equation, R
T
>R
q
= h/e2= 25.818 K. Hence Coulomb Energy (E
C
) is needed to charge an island with
an electron E
C
=e
2
/(2C)>KT. Here C is the overall capacitance of an island and K is the constant term known as
Boltzmans constant (K=1.3810
-34
J/K). Once the Coulomb energy surpasses the available thermal energy, the
available energy supplied by voltage source starts to control the movement of electrons. [34] Thus the two tunnel
junctions build Coulomb Island where the electrons can only tunnel from one side of the insulators.
The capacitor simply acts as a cause to set the electric charge on the Coulomb Island. The tunneling current
significantly boosts the gate voltage to rise up to e/2C. Fig.2 elucidates the tunneling operations of electrons. The
simplistic way to understand this is that if an electron approach towards A and pulse
n-1
>5mV is applied, then the
electron can tunnel through junctions (J1 and J3) to C or E subject to the Coulomb energy [E
c
=e
2
/(2C)] +applied
energy has to be greater than the potential height of the barrier energy of junction(s) J1 (or J3).
IPASJ International Journal of Computer Science(IIJCS)
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Figure 2 Basic operation of tunneling of electrons in the tunnel junction

3. HYBRID CMOS-SET CO-INTEGRATION
Scientific publications revealed that in the coming decades, CMOS has to share its present dominance with SETs in
next generation ICs [35] although CMOS and SETs are relatively converse in nature. SET is a low-power consuming
device [36,37] having higher speed and robustness along with high integration density like advanced new
functionalities while CMOS posses benefits like voltage gain, which can compensate exactly for SETs intrinsic
drawbacks. Therefore, combining and hybridizing of SET and CMOS is likely to usher new functionalities [38,39] in
next generation device technology.

3.1 Analytical view of Hybrid CMOS-SET
To exploit SET to function as a switch is done by pushing the SET into the Coulomb blockade state i.e., the OFF
condition or by permitting it to conduct current i.e., the ON condition; thereafter it is likely to mimic MOSFET logic
architecture to develop a hybrid CMOS-SET logic family. The fundamental strategy is that it is formed by a PMOS
transistor as the load resistance of an SET. Significance here in this technology is that in the gates, the PMOS
transistor has the SET as its load. Thus some design rules has to be implied before practical hybrid CMOS-SET circuit
design. While the novel structures resemble CMOS inverter, but there are two basic differences, i.e., (i) the Pull Up
transistor is an SET and (ii) the V
DD
is defined by the SET device parameters. A SET-MOS quaternary transmission
gate [40] is highly accredited and mostly cited in reputed journals. Researchers at Delft University in Netherlands
proposed a SPICE simulation package for SET circuit [41] using the Orthodox theory. Following Fig.3 are some basic
logic gates made up of Hybrid CMOS-SET structures.


Figure 3 Fundamental hybrid CMOS-SET logic gates
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4. DESIGN AND ANALYSIS OF HYBRID CMOS-SET BASED MOORE AND MEALY MODEL

Figure 4 Hybrid CMOS-SET based Moore Model


Figure 5 Hybrid CMOS-SET based Mealy Model

All simulations were based on SPICE model which allows including the conventional MOS devices with SETs. More
conveniently, the logic operations of the circuits were first tested by simulation using T-Spice simulation software. The
MIB compact model for SET device and BSIM4.6.1 model for CMOS are to be incorporated for detailed empirical
results in near future; and due to limitation in time and space this could not be included in this presentation.
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Results Obtained
The present work explored the implementation of hybrid CMOS-SET logic gates based complex Moore and Mealy
model for next generation single electronics logic gates. The proposed models perform the logic operation correctly.
The power consumptions & propagation delays are quite less in hybrid CMOS-SET technology compared to CMOS
technology. Table 4.1 denotes the estimated values of power consumption of the logic gates in these two circuits. The
output voltage gain is likely to be about 4.8 as found from the slope of the transitional region. Employing a uniform
interval of clock pulse both the models is efficient enough to conduct a predetermined sequence of states. The present
projected conception of hybrid CMOS-SET architecture shows greater trade-off between CMOS and SET.

Table 4.1 POWER DISSIPATION OF SET-MOS HYBRID CIRCUITS
Circuit
type
Power
Supply
No. of
CMOS
No. of
SET
Power
Consumption
AND Gate 0.01V 3 3 1.02E-09 W
OR Gate 0.01V 3 3 1.02E-09 W
D Flip-flop 0.01V 9 9 4.12E-09 W
5. CONCLUSION
The design and simulation of hybrid CMOS-SET sequential circuits are attempted successfully and the results are
presented here categorically to unearth the underlying possibilities of perfect co-integration of CMOS-SET. The most
remarkable feature is that the SET and CMOS are placed in series and thereby the hybridization achieved improves the
gain of the models while the propagation delay is lessened to some extent. Based on the hybrid CMOS-SET logic gates,
the models are designed and implemented. The T-Spice simulation results of the proposed models are quite satisfactory
thereby the feasibility of using the proposed hybrid circuits in future low power ultra-dense VLSI/ULSI circuits is
firmly grounded. One most admiring aspect of such co-integration is that the hybrid CMOS-SET design can be
obtained at room temperature so that the fragility of SETs are controlled and further the model can exhibit their full
functionalities. Other remarkable consequences are that when the operating temperature lays near to sub ambient
regime the switching speed, mobility and power dissipation shows improved performance. Thus, the novelty and
robustness of the proposed model along with its merits like low power consumption draws the attention of both
academia and industry.

Acknowledgement
I, Jayanta Gope, along with my other co-authors hereby acknowledge the technological and financial aid provided by
Camellia School of Engineering and Technology under the direction of the Honble Director of this esteemed institute
Prof. (Dr.) A. S. Chaudhury. I sincerely thank him for his benevolent and inspiring notion in developing such research.

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AUTHORS

Prof. Jayanta Gope, B.E., PhD (Engg.), has completed his PhD in Nanotechnology from Jadavpur
University and is presently associated with Camellia School of Engineering and Technology. His field of
interest includes Nano device modeling, Single Electronic devices, Spintronic Devices, Hybrid CMOS-SET.
He has already published several international research articles in this category.

Mr. Bikash Gupta is a final year student of B.Tech in Electronics and Communication Engineering Department of
Camellia School of Engineering and Technology, West Bengal, India.


Mr. Rupesh Anand is a final year student of B.Tech in Electronics and Communication Engineering Department of
Camellia School of Engineering and Technology, West Bengal, India.