IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO.

11, NOVEMBER 2011 4049

Explicit Drain-Current Model of Graphene
Field-Effect Transistors Targeting Analog
and Radio-Frequency Applications
David Jimnez and Oana Moldovan
AbstractWe present a compact physics-based model of the
currentvoltage characteristics of graphene eld-effect transis-
tors, of especial interest for analog and RF applications where
band-gap engineering of graphene could be not needed. The phys-
ical framework is a eld-effect model and drift-diffusion carrier
transport. Explicit closed-form expressions have been derived for
the drain current continuously covering all operation regions. The
model has been benchmarked with measured prototype devices,
demonstrating accuracy and predictive behavior. Finally, we show
an example of projection of the intrinsic gain as a gure of merit
commonly used in RF/analog applications.
Index TermsAnalog, eld-effect transistor (FET), graphene,
modeling, radio frequency (RF).
G
RAPHENE has emerged as a candidate material for fu-
ture nanoelectronic devices. It exhibits very high mobility
(10
5
cm
2
/V s) and saturation velocity (10
8
cm/s), to-
gether with a promising ability to scale to short gate lengths
and high speeds by virtue of its thinness. The main concern
is the absence of a gap, therefore limiting the usefulness in
digital applications. Several approaches have appeared in the
last years to open a gap. For instance, graphene nanoribbons,
bilayer graphene, or strained graphene have been suggested.
However, graphene could still be very useful in analog and
radio-frequency (RF) applications where high ON/OFF current
ratios are not required [1]. In small signal ampliers, for
instance, the transistor is operated in the ON-state and small
RF signals that are to be amplied are superimposed onto the
DC gatesource voltage. Instead, what is needed to push the
limits of many analog/RF gures of merit (FoM), for instance,
the cutoff frequency or the intrinsic gain, is an operation region
where high transconductance, together with a small output
conductance, is accomplished. These conditions are realized
for state-of-the-art graphene eld-effect transistors (GFETs).
Specically, for large-area GFETs, the output characteristic
Manuscript received March 28, 2011; revised June 24, 2011 and July 26,
2011; accepted July 27, 2011. Date of publication September 15, 2011; date
of current version October 21, 2011. This work was supported in part by Min-
isterio de Ciencia e Innovacin under contracts FR2009-0020 and TEC2009-
09350, and the Department dUniversitats, Recerca i Societat de la Informaci
of the Generalitat de Catalunya under contract 2009SGR783. The review of this
paper was arranged by Editor M. A. Reed.
The authors are with the Departament dEnginyeria Electrnica, Escola
dEnginyeria, Universitat Autnoma de Barcelona, 08193 Bellaterra, Spain
(e-mail: david.jimenez@uab.es).
Color versions of one or more of the gures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identier 10.1109/TED.2011.2163517
Fig. 1. Cross section of the dual-gate GFET. It consists of a large-area
graphene channel on the top of an insulator layer, playing the role of back-gate
dielectric, grown on a heavily doped Si wafer acting as backgate. The source
and drain electrodes are contacting the graphene channel from the top and are
assumed to be ohmic. The source is grounded and considered the reference
potential in the device. The electrostatic modulation of the carrier concentration
in graphene is achieved via a top-gate stack consisting of the gate dielectric and
the gate.
shows a weak saturation that could be exploited for analog/RF
applications. Using this technology, cutoff frequencies in the
terahertz range are envisioned. Cutoff frequencies in the range
of hundreds of gigahertz have been demonstrated using nonop-
timized technologies [2], [3].
At this stage of development of GFET technology, model-
ing of the currentvoltage IV characteristics is important for
device design optimization, projection of performances, and
exploration of analog/RF circuits providing new or improved
functionalities. Here, we present a compact physics-based
model of the IV characteristics of GFETs where explicit
closed-form expressions have been derived for the drain cur-
rent. The framework is a eld-effect model and drift-diffusion
carrier transport, which is accurate to explain the electrical
behavior of GFETs [4], [5]. The compact model has been
benchmarked with measured IV characteristics of prototype
devices, demonstrating accuracy, and predictive behavior.
In the following, we focus on GFET with the cross section
depicted in Fig. 1. The electrostatics of this device can be un-
derstood using the equivalent capacitive circuit from [5]. There,
C
t
and C
b
are the top and bottom oxide capacitance, and C
q
represents the quantum capacitance of the graphene. Potential
V
c
represents the voltage drop across C
q
, where C
q
= k|V
c
|
under condition qV
c
k
B
T, with k = (2q
2
/)(q/(v
F
)
2
),
0018-9383/$26.00 2011 IEEE
4050 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO. 11, NOVEMBER 2011
and v
F
(= 10
6
m/s) is the Fermi velocity [6]. Potential V (x)
is the voltage drop in the graphene channel, which is zero
at the source end at x = 0 and equal to drainsource voltage
V
ds
at the drain end at x = L. Applying circuit laws to the
equivalent capacitive circuit and noting that the overall net
mobile sheet charge density in the graphene channel, dened as
Q
c
= q(p n), is equal to (1/2)C
q
V
c
, the following relation
is obtained:
V
c
(x) = (V
gs
V
gs0
V (x))
C
t
C
t
+C
b
+
1
2
C
q
+ (V
bs
V
bs0
V (x))
C
b
C
t
+C
b
+
1
2
C
q
(1)
where V
gs
V
gs0
and V
bs
V
bs0
are the top and back-
gatesource voltage overdrive, respectively. These quantities
comprise work-function differences between the gates and
the graphene channel, eventual charged interface states at the
graphene/oxide interfaces, and possible doping of the graphene.
To model the drain current, a drift-diffusion carrier transport
is assumed under form I
ds
= qW
c
(x)v(x), where W is the
gate width,
c
(x) = |Q
c
|/q is the free carrier sheet density
in the channel at position x, and v(x) is the carrier drift
velocity. Using a soft-saturation model, consistent with Monte
Carlo simulations [7], v(x) can be expressed as v = E/(1 +
|E|/v
sat
), where E is the electric eld, is the carrier low-
eld mobility, and v
sat
is the saturation velocity. The latter
is concentration dependent and given by v
sat
= /

c
[4].
Applying E = dV(x)/dx, combining the above expressions
for v and v
sat
, and integrating the resulting equation over the
device length, the drain current becomes
I
ds
=
qW
_
V
ds
0

c
dV
L +

_
V
ds
0
1
v
sat
dV

. (2)
The denominator represents an effective length (L
e
) to take
into account the saturation velocity effect. In order to get an
explicit expression for I
ds
, the integrals in (2) are solved using
V
c
as the integration variable and consistently expressing
c
and
v
sat
as a function of V
c
, i.e.,
I
ds
=
qW
_
V
cd
V
cs

c
(V
c
)
dV
dV
c
dV
c
L +

_
V
cd
V
cs
1
v
sat
(V
c
)
dV
dV
c
dV
c

(3)
where V
c
is obtained from (1) and can be written as (4), shown
at the bottom of this page.
The positive (negative) sign applies whenever (V
gs
V
gs0

V )C
t
+ (V
bs
V
bs0
V )C
b
> 0(< 0). The channel poten-
tial at source V
cs
is determined as V
c
(V = 0). Similarly,
the channel potential at drain V
cd
is determined as V
c
(V =
V
ds
). Moreover, (1) provides relation (dV/dV
c
) = (1 +
(kV
c
sgn(V
c
)/C
t
+C
b
)), where sgn refers to the sign function.
On the other hand, the charge sheet density can be written as

c
(V
c
) = kV
2
c
/(2q) +
0
. Extra term
0
added to
c
accounts
for the carrier density induced by impurities [8]. Inserting
these expressions into (3), the following explicit drain current
expression can be nally obtained:
I
ds
=
W
L
e
_
q
0
V
ds

k
6
_
V
3
cd
V
3
cs
_

k
2
8(C
t
+C
b
)
_
sgn(V
cd
)V
4
cd
sgn(V
cs
)V
4
cs
_
_
L
e
=L +

V
c
2

kV
2
c
2
q
+
0

0
log
_
2
__
k
2q
_
kV
2
c
2q
+
0
+
kV
c
2q
__
2
_
k
2q
sgn(V
c
)
2q
3(C
t
+C
b
)

_
_
kV
2
c
2q
+
0
_3
2

3
2
0
__
V
cd
V
cs

. (5)
To reproduce the experimental IV characteristics, account-
ing for the voltage drop at the S/D contacts is necessary. This
quantity must be removed from external V
ds_ext
in order to get
internal V
ds
. This is done by solving equation V
ds
= V
ds_ext

I
ds
(V
ds
)(R
s
+R
d
), noting that I
ds
is a function of V
ds
, as
given by (5).
To test the model, we have benchmarked the resulting IV
characteristics with experimental results extracted from devices
in [4] and [9]. The rst device under test has L = 1 m,
W = 2.1 m, top dielectric is HfO
2
of 15 nm, and permittivity
is 16, and the bottom dielectric is silicon oxide of 285 nm
[4]. The back-gate voltage was 40 V. The at-band voltages
V
gs0
and V
bs0
were tuned to 1.45 and 2.7 V, respectively. These
values were selected to locate the Dirac point according to the
experiment. It is worth noting that a ratio (C
t
//C
q
)/C
b
46
was estimated measuring the top-gate Dirac point at different
back-gate voltage. To capture this ratio, responsible of the gate
efciency, an effective top dielectric thickness of 26 nm was
used, yielding a better t with the experiments. A low-eld
mobility of 1200 cm
2
/V s for both electrons and holes, S/D
resistance of 800 , and phonon effective energy 55 meV
were considered. These values are consistent with the extracted
values. Sheet carrier density
0
= 10
11
cm
2
was selected for
the nal ne tuning.
Now we consider the output characteristics (see Fig. 2). To
t the experiment, phonon energy 15 meV was used
for V
gs
V
gs0
0. This is justied because the phonon ef-
fective energy overestimates the actual value for high sheet
V
c
=
(C
t
+C
b
) +
_
(C
t
+C
b
)
2
2k [(V
gs
V
gs0
V )C
t
+ (V
bs
V
bs0
V )C
b
]
k
(4)
JIMNEZ AND MOLDOVAN: DC MODEL OF GFET TARGETING ANALOG AND RF APPLICATIONS 4051
Fig. 2. Output characteristics obtained from the (solid lines) analytical model
compared with experimental results from (symbols) [4]. (Inset) Quantum
capacitance voltage drop as a function of the external sourcedrain voltage for
different gate voltage overdrive.
carrier densities [10]. Due to the gapless channel, the output
characteristics present a saturation-like behavior that includes
a second linear region. The crossover between the rst and
second linear regions could be understood, observing V
c
as a
function of V
ds_ext
(see the inset). Here, V
cd
and V
cs
are both
negative for small values of V
ds_ext
, meaning that the chan-
nel is entirely p-type. Increasing V
ds_ext
, at some point, V
cd
becomes positive, and the channel switches to n-type near the
drain end.
The second examined device is a top-gate device using a
different fabrication technology with L = 10 m, W = 5 m,
and HfO
2
as a dielectric with thickness of 40 nm [9]. The at-
band voltage was V
gs0
= 0.85 V according to the experiment.
A low-eld mobility of 7500 cm
2
/V s for both electrons and
holes, S/D resistance of 300 , and 100 meV were
considered. Sheet carrier density
0
= 3 10
11
cm
2
was used
for the nal tuning.
The resulting IV characteristics are shown in Fig. 3. We
have extended the simulated voltage range beyond the experi-
ment range to show the predictive behavior of the model. The
transfer characteristics exhibit an ambipolar behavior domi-
nated by holes (electrons) for V
gs
V
gs0
< V
gs,D
(> V
gs,D
)
where V
gs,D
(Dirac gate voltage) is given by V
gs,D
= V
gs0
+
V
ds
/2. The output characteristics behave similar as the rst
examined device. Once again, the comparison between the
model and the experiment further demonstrates the model
accuracy.
Next, we will give an example on how to use our
currentvoltage DC model to project an important FoM used
in RF/analog applications, namely, the intrinsic gain (G =
g
m
/g
ds
), which is dened as the ratio of the transconduc-
tance (g
m
= (I
ds
/V
gs
)) and the output conductance (g
ds
=
(I
ds
/V
ds
)). Both g
m
and g
ds
are small-signal quantities
directly derived from the DC model. Fig. 4(a) shows pro-
Fig. 3. (a) Transfer and (b) output characteristics obtained from the (solid
lines) compact model compared with experimental results from (symbols) [9].
jection of these quantities together with G, for the transistor
topology from [9], as a function of V
ds
(internal) for a xed
V
gs
= 0.75 V. Remarkably, when the transistor is operated at
the beginning of saturation region V
ds,pod
= V
gs
V
gs0
=
1.6 V, g
m
is maximum, whereas g
ds
is minimum, yielding
optimal G(= 15). This particular value V
ds,pod
sets the pin-
choff point exactly at x = L, indicating the crossover between
a p-type channel and a mixed p-type/n-type ambipolar channel.
As a peculiar characteristic of GFETs, different from what it
is observed in conventional silicon FETs, there exists a region
of negative g
m
(and G) for V
ds
< V
ds,D
= 2V
ds,pod
(=
3.2 V), where V
ds,D
could be named as Dirac drain voltage.
At this particular voltage, one half of the channel behaves as an
n-type and the other as a p-type. Negative g
m
is a consequence
of the crossing IV
ds
characteristics. It seems undesirable
for normal operation of the transistor to work in this region,
although it cannot be ruled out that any practical application
could be found. Finally, Fig. 4(b) shows how the intrinsic gain
for the same transistor could be tailored by expanding the range
of applied gate and drain voltage. For example, intrinsic gains
as large as G 100 could be obtained operating the transistor at
V
gs
= 1.75 V and V
ds
2.6 V.
4052 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO. 11, NOVEMBER 2011
Fig. 4. (a) Intrinsic gain, transconductance, and output conductance as a
function of the drain voltage. The channel is shown to be ambipolar, or p-type,
depending on the drain voltage. (b) Intrinsic gain as a function of the drain
voltage for different gate voltage to show how this FoM can be tailored by
properly selecting the bias point.
In conclusion, we have presented an explicit and compact
drain current model for large-area GFETs based on a eld-
effect model and drift-diffusion carrier transport, of especial
interest as a tool for design of analog/RF applications based on
graphene transistor technologies. We have illustrated howto use
the currentvoltage DC model to nd an important FoM used
in RF/analog applications, namely, the intrinsic gain. Discus-
sions of other FoM such as the cutoff frequency can be found
in [5].
REFERENCES
[1] F. Schwierz, Graphene transistors, Nat. Nanotechnol., vol. 5, pp. 487
496, 2010.
[2] Y.-M. Lin, C. Dimitrakopoulos, K. A. Jenkins, D. B. Farmer, H.-Y. Chiu,
A. Grill, and P. Avouris, 100-GHz transistors from wafer-scale epitaxial
graphene, Science, vol. 327, no. 5966, p. 662, Feb. 2010.
[3] L. Liao, Y.-C. Lin, M. Bao, R. Cheng, J. Bai, Y. Liu, Y. Qu, K. L. Wang,
Y. Huan, andX. Duan, High-speedgraphene transistors witha self-aligned
nanowire gate, Nature, vol. 467, no. 7313, pp. 305308, Sep. 2010.
[4] I. Meric, M. Y. Han, A. F. Young, B. Ozyilmaz, P. Kim, and K. Shepard,
Current saturation in zero-bandgap, top-gated graphene eld-effect tran-
sistors, Nat. Nanotechnol., vol. 3, no. 11, pp. 654659, 2008.
[5] S. Thiele, J. A. Schaefer, and F. Schwierz, Modeling of graphene metal
oxidesemiconductor eld-effect transistors with gapless large-area
graphene channels, J. Appl. Phys., vol. 107, no. 9, p. 094505, May 2010.
[6] T. Fang, A. Konar, H. Xing, and D. Jena, Carrier statistics and quantum
capacitance of graphene sheets and ribbons, Appl. Phys. Lett., vol. 91,
no. 9, p. 092109, Aug. 2007.
[7] J. Chauhan and J. Guo, High-eld transport and velocity saturation in
graphene, Appl. Phys. Lett., vol. 95, no. 2, p. 023120, Jul. 2009.
[8] J. Xia, F. Cheng, J. Li, and N. Tao, Measurement of the quantum ca-
pacitance of graphene, Nat. Nanotechnol., vol. 4, no. 8, pp. 505509,
Aug. 2009.
[9] J. Kedzierski, P.-L. Hsu, A. Reina, J. Kong, P. Healey, P. Wyatt, and
C. Keast, Graphene-on-insulator transistors made using C on Ni
chemical-vapor deposition, IEEE Electron Device Lett., vol. 30, no. 7,
pp. 745747, Jul. 2009.
[10] I. Meric, C. R. Dean, A. F. Young, J. Hone, P. Kim, and K. Shepard,
Graphene eld-effect transistors based on boron nitride gate dielectrics,
in IEDM Tech. Dig., 2010, pp. 556559.
David Jimnez received the Ph.D. degree in elec-
tronics engineering from the Universitat Autnoma
de Barcelona, Barcelona, Spain, in 2000.
Since 2004, he has been an Associate Profes-
sor with the Departament dEnginyeria Electrnica,
Universitat Autnoma de Barcelona. He was a Vis-
iting Researcher with the Universidad Autnoma
de Madrid, Madrid, Spain, in 2002; the Universitat
Rovira i Virgili, Tarragona, Spain, in 2003; Tokyo
Institute of Technology, Tokyo, Japan, in 2009; the
Universidad de Granada, Granada, Spain, in 2010;
and the cole Polytechnique Fdrale de Lausanne, Lausanne, Switzerland, in
2010. His research activity is focused on compact modeling of nanoscale tran-
sistors, including multiple-gate metaloxidesemiconductor eld-effect transis-
tors, silicon nanowire transistors, and carbon-based transistors. More recently,
his activities have expanded toward the research of new transistor architectures
based on materials that exhibit negative capacitance and memristance.
Oana Moldovan was born in Cluj-Napoca,
Romania, in 1980. She received the B.S. degree
in electronics and telecommunications engineering
from the Technical University of Cluj-Napoca,
Cluj-Napoca, in 2004 and the Ph.D. degree in
the Universitat Rovira i Virgili, Tarragona, Spain,
in 2008, with her doctoral research being on the
compact modeling of multiple-gate metaloxide
semiconductor eld-effect transistors, particularly
of the small-signal elements.
In 2006, she was a Visiting Graduate Student with
CINVESTAV, Mexico City, for two months. In 2007, she was a Visiting
Graduate Student for three months with the Microwave Laboratory, Universit
Catholique de Louvain, Louvain-la-Neuve, Belgium. Since 2009, she has been
a Juan de la Cierva Researcher with the Universitat Autnoma de Barcelona,
Barcelona, Spain, working in compact modeling of graphene transistors.