ECE 301 Digital Electronics

Counters
(Lecture #20)
The slides included herein were taken from the materials accompanying
Fundamentals of Logic Design, 6
th
Edition, by Roth and Kinney,
and were used with permission from Cengage Learning.
Spring 2011 ECE 301 - Digital Electronics 2
Counters

A counter is a sequential circuit (aka. finite

state machine) that cycles through a fixed
sequence of states.

The state of the counter is stored in Flip-Flops.

An n-bit counter

has n Flip-Flops

can cycle through at most 2

n
states.
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Counters
00
10
01 11
010 110
000 001 111
011 100 101
2-bit Counter
3-bit Counter
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Counters
2-bit Counter
3-bit Counter
00
01
10
using only 3 states
using only 5 states
010
101 011
000
110
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Binary Counters

An n-bit binary counter is a counter that cycles

through all 2
n
states in ascending (or
descending) order.
010 110
000 001 111
011 100 101
3-bit Binary Counter
Cycles through all 8 states
in ascending order
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Binary Counters: Design
1.Draw a state graph that specifies the desired
sequence of the counter.
2.Construct a state table from the state graph.

One Flip-Flop for each bit in the state.

3.Derive a K-map from the state table for each
Flip-Flop input.

Select the type of Flip-Flop to be used.

4.Determine the input equation(s) for each
Flip-Flop.
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Binary Counters: Design
Example: State Table (using D FF)
Present State Next State FF Inputs
C B A C
+
B
+
A
+
D
C
D
B
D
A
0 0 0 0 0 1
0 0 1 0 1 0
0 1 0 0 1 1
0 1 1 1 0 0
1 0 0 1 0 1
1 0 1 1 1 0
1 1 0 1 1 1
1 1 1 0 0 0
Q
+
= D
Characteristic
Equation:
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Binary Counters: Design
Example: K-maps (for D FF inputs)
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Binary Counters: Design
Example: Circuit Diagram (using D FF)
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Binary Counters: Design
Example: State Table (using T FF)
Q
+
= T xor Q
Characteristic
Equation:
Present State Next State FF Inputs
C B A C
+
B
+
A
+
T
C
T
B
T
A
0 0 0 0 0 1
0 0 1 0 1 0
0 1 0 0 1 1
0 1 1 1 0 0
1 0 0 1 0 1
1 0 1 1 1 0
1 1 0 1 1 1
1 1 1 0 0 0
Excitation Table:
Q Q
+
T
0 0 0
0 1 1
1 0 1
1 1 0
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Binary Counters: Design
Example: K-maps (for T FF inputs)
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Binary Counters: Design
Example: Circuit Diagram (using T FF)
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Binary Up-Down Counters
What constraints must be placed on the U and D control signals?
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Binary Up-Down Counters
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Loadable Counter with Enable
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Counters: Design
1.Draw a state graph that specifies the desired
sequence of the counter.
2.Construct a state table from the state graph.

One Flip-Flop for each bit in the state.

3.Derive a K-map from the state table for each
Flip-Flop input.

Select the type of Flip-Flop to be used.

4.Determine the input equation(s) for each
Flip-Flop.
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Counters: Design
Example:
Design the following counter using D Flip-Flops.
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Counters: Design
Example: State Table (using D FF)
Present State Next State FF Inputs
C B A C
+
B
+
A
+
D
C
D
B
D
A
0 0 0 1 0 0
0 0 1 x x x
0 1 0 0 1 1
0 1 1 0 0 0
1 0 0 1 1 1
1 0 1 x x x
1 1 0 x x x
1 1 1 0 1 0
D = Q
+
Excitation
Equation:
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Counters: Design
Example: K-maps (for D FF inputs)
D
C
D
B
D
A
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Counters: Design
Example: Circuit Diagram (using D FF)
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Counters: Design
Example:
Design the following counter using T Flip-Flops.
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Counters: Design
Example: State Table (using T FF)
Present State Next State FF Inputs
C B A C
+
B
+
A
+
T
C
T
B
T
A
0 0 0 1 0 0
0 0 1 x x x
0 1 0 0 1 1
0 1 1 0 0 0
1 0 0 1 1 1
1 0 1 x x x
1 1 0 x x x
1 1 1 0 1 0
T = Q xor Q
+
Excitation
Equation:
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Counters: Design
Example: K-maps (for T FF inputs)
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Counters: Design
Example: K-maps (for T FF inputs)
We could derive T
C
, T
B
, and T
A
directly from the state table,
but it is often more convenient to plot next-state maps
showing C
+
, B
+
, and A
+
as functions of C, B, and A, and then
derive T
C
, T
B
, and T
A
from these maps.
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Counters: Design
Example: Circuit Diagram (using T FF)
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Counters: Design
Example: Next States (for T FF inputs)
Although the original state table for the counter is not
completely specified, the next states of states 001, 101,
and 110 have been specified in the process of
completing the circuit design
110 101
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Counters: Design
Example:
Design the following counter using JK Flip-Flops.
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Counters: Design
Example: Using JK Flip-Flops
Excitation Table:
Q Q
+
J K
0 0 0 x
0 1 1 x
1 0 x 1
1 1 x 0
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Counters: Design
Example: State Table (using JK FF)
Present State Next State FF Inputs
C B A C
+
B
+
A
+
J
C
K
C
J
B
K
B
J
A
K
A
0 0 0 1 0 0
0 0 1 x x x
0 1 0 0 1 1
0 1 1 0 0 0
1 0 0 1 1 1
1 0 1 x x x
1 1 0 x x x
1 1 1 0 1 0
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Counters: Design
Example: K-maps (for JK FF inputs)
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Counters: Design
Example: Circuit Diagram (using JK FF)
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Questions?