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Copyright University of Colorado, 2005
Architecture of the PIC18F452
Architecture of the PIC18F452
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Copyright University of Colorado, 2005
Comments
Questions?
New students
Must attend ITLL orientation to receive computer account
and after hours access
Sign-up for orientation at the ITLL front desk
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Overview
PIC18F452 block diagram
PIC18F452 Pin out
Ports and resources
QwikFlash board schematic
PIC18F451 memory management
Numbering systems
Decimal, binary, octal and hexadecimal
RAM layout
Special function registers
Addressing modes
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PIC18Fx52
PIC18Fx52
block
diagram
RAM
1536
EEPROM
256
FLASH
32K
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PIC 18F452 Pin diagram
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The PIC18F452
The PIC18F452 has 5 ports (A-E)
Each port has 3 associated 8-bit registers
TRISx.bit defines the direction of bit in port x
TRISx.bit = 0 sets port x bit to be output
TRISx.bit =1 sets port x bit to be input
PORTx.bit is used to read the value of bit on port x
LATx.bit is used to set the value of bit on port x
A register is a reserved memory location in RAM
For example TRISA is at memory location 0xF92
If the value of TRISA = 00101101 then
TRISA.0 =1 so port A pin 0 (RA0) is an input (pin #2)
TRISA.1 = 0 so port A pin 1 (RA1) is an output (pin #3)
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The PORTS
Port A 7 bit wide bidirectional port
Resources: Timer0, Low voltage detect, ADC
Port B 8 bit wide bidirectional port with weak pull-up resistors
Resources: Interrupts, alt CCP2
Port C 8 bit wide bidirectional port
Resources: Timers 1-3, capture compare, SPI, I2C, UART
Port D 8 bit wide bidirectional port
Resources: Parallel slave port data
Port E 3 bit wide bidirectional port
Resources: Parallel slave port control
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PORT A
Digital I/O, OSC2, clock output RA6, OCS2, CLK0 14 6
Digital I/O, analog input 4, slave select
input (synchronous serial port), low
voltage detect
RA5, AN4, SS,
LVDIN
7 5
Digital I/O (open drain), timer0 clock in RA4, TOCKI 6 4
Digital I/O, analog input 3, analog Vref + RA3, AN3, VREF+ 5 3
Digital I/O, analog input 2, analog Vref - RA2, AN2, VREF- 4 2
Digital I/O, analog input 1 RA1, AN1 3 1
Digital I/O, analog input 0 RA0, AN0 2 0
Function Name Pin # Bit #
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PORT B
Digital I/O, IOC, serial programming data RB7, PGD 40 7
Digital I/O, IOC, serial programming clock RB6, PGC 39 6
Digital I/O, IOC, low voltage ICSP programming RB5
1
, PGM 38 5
Digital I/O, IOC RB4 37 4
Digital I/O, capture 2 input, compare 2 output,
pulse width modulation with CCP2MX bit
disabled
RB3, CCP2 36 3
Digital I/O, external interrupt 2 RB2, INT2 35 2
Digital I/O, external interrupt 1 RB1, INT1 34 1
Digital I/O, external interrupt 0 RB0, INT0 33 0
Function Name Pin # Bit #
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PORT C
Digital I/O, USART asynchronous RX,
USART synchronous data
RC7, TX, DT 26 7
Digital I/O, USART asynchronous TX,
USART synchronous clock
RC6, TX, CK 25 6
Digital I/O, SPI data output RC5, SDO 24 5
Digital I/O, SPI data input or I
2
C data I/O RC4, SDI, SDA 23 4
Digital I/O, synchronous serial clock for
I
2
C and SPI
RC3, SCK, SCL 18 3
Digital I/O, capture 1 in, compare 2 out,
pulse width modulator out
RC2, CCP1 17 2
Digital I/O, timer1 oscillator in, capture 2
in, compare 2 out, pulse width modulator
out with CCP2MX bit enabled
RC1, T1OSI, CCP2 16 1
Digital I/O, timer1 oscillator out, timer1
clock in
RC0, T1OSO,
T1CKI
15 0
Function Name Pin # Bit #
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PORT D
Digital I/O, parallel slave port bit 7 RC6, PSP7 30 7
Digital I/O, parallel slave port bit 6 RC6, PSP6 29 6
Digital I/O, parallel slave port bit 5 RD5, PSP5 28 5
Digital I/O, parallel slave port bit 4 RD4, PSP4 27 4
Digital I/O, parallel slave port bit 3 RD3, PSP3 22 3
Digital I/O, parallel slave port bit 2 RD2, PSP2 21 2
Digital I/O, parallel slave port bit 1 RD1, PSP1 20 1
Digital I/O, parallel slave port bit 0 RD0, PSP0 19 0
Function Name Pin # Bit #
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PORT E
Digital I/O, analog input 7,
parallel slave port chip select
RE2, AN7, CS 10 2
Digital I/O, analog input 6,
parallel slave port write
RE1, AN6, WR 9 1
Digital I/O, analog input 5,
parallel slave port read
RE0, AN5, RD 8 0
Function Name Pin # Bit #
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Resources
Timer0
8 or 16 bit timer
8 bit prescaler
Internal or external clock
Interrupt on overflow
Timer1
16 bit time or counter
Internal or external clock
Interrupt on overflow
Timer2
8 bit timer
8 bit period register (PR2)
Prescaler
Postscaler
Intrrupt on TMR2=PR2
Timer3
16 bit timer or counter
CCP1 & CCP2
16 bit capture/compare
Pulse width modulation (PWM)
10 bit resolution
Analog to digital converter (ADC)
10 bit resolution
8 channels multiplex to a single
ADC
Serial interfacing
I2C, SPI, UART
Interrupts
Timer, UART, SPI, I2C, ADC,
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PIC
Qwikflash
board
RS-232
LCD w/
Nibble interface
Pushbutton switch (RD3)
Rotary pulse generator
(RD1,0)
Red LEDs
Temperature sensor (AN0)
Potentiometer (AN4)
SPI DAC
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PIC Architecture
Harvard architecture
Separate program and data
bus
Supports pipelining
Fetch next instruction while
executing current instruction
Operand address bus
12 bits wide
2^12 = 4096
Data bus
8 bits wide
Program address bus
15 bits wide
2^15 = 32768
Instruction bus
16 bits wide
Program
Memory
CPU
Operand
Memory
(SFR &
RAM)
15 bits
8 bits 16 bits
12 bits
Program
Address
Data
Operand
Address
Instruction
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Number systems I
Basic numbering systems
Base X (X digits)
number ABC = A*X^2 + B*X^1 + C*X^0
N
th
place represents X^n
Decimal system
Base 10 (10 digits, 0-9)
Number 467 = 4*100 + 6*10 + 7*1
Binary system
Base 2 (2 digits, 0 &1, ON & OFF, TRUE & FALSE)
Number 1101 = 1*2^3 + 1*2^2 + 0*2^1 + 1*2^0 = 8 + 4 + 0 + 1 = 13
10
Octal system
Base 8 (8 digits, 0-7)
Number 467 = 4*8^2 + 6*8^1 + 7*8^0 = 4*64 + 6*8 + 7 = 311
10
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Number systems II
Hexadecimal system
Base 16 (17 digits, 0-9 & A-F)
Number 467 = 4*16^2 + 6*16^1 + 7*16^0 = 4*256 + 6*16 + 7 = 1127
10
Relationship between number systems
1 octal digit = 3 binary digits
111= 7
1 hexadecimal digit = 4 binary digits
1111 = F
Notation
Number are assumed to be in decimal unless otherwise specified
0x76 or H76 refers to a hexadecimal number
O76 refers to an octal number
B01001100 refers to a binary number
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Relationship between numbers
F 17 1111 15
E 16 1110 14
D 15 1101 13
C 14 1100 12
B 13 1011 11
A 12 1010 10
9 11 1001 9
8 10 1000 8
7 7 0111 7
6 6 0110 6
5 5 0101 5
4 4 0100 4
3 3 0011 3
2 2 0010 2
1 1 0001 1
0 0 0000 0
Hexadecimal Octal Binary Decimal
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Binary numbering language
Bit a binary digit (0 or 1)
Nibble or nybble a group of 4 bits. Corresponds to a single
hexadecimal digit
Byte a group of 8 bits. It can be represented by two hexadecimal
digits.
Word - a group of 16 bits
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RAM layout
12 bit address space
2^12 = 4096 bytes
Only 1536 +128 are used
RAM divided into 16 banks
each 256 bytes large
PIC18F452 uses 6 banks for
general purpose registers
(GPR) and 128 bits for special
functions registers (SFR).
The SFR are located at the top
of ram
Addresses 0xF80 to 0xFFF
The lowest 128 bits of RAM
are called access RAM
Addresses 0x000 to 0x080
GPR
GPR
GPR
GPR
GPR
UNUSED
Access RAM
SFR
0x000
0x100
0x200
0x300
0x400
0x500
0x600
0xF00
0xF80
0xFFF
0x080
Bank 0
Bank 3
Bank 4
Bank 5
Bank 1
Bank 2
Bank 15
GPR
Banks 6-14 and the lower
half of bank 15 are unused
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Special Function Registers
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PIC Addressing modes
Literal addressing
For moving constant values
Eg: movlw0x23 move the literal value 23 (hex) into the working register
Direct Addressing
For moving variables (eg: movwf COUNT move the value of the working into
variable COUNT.
Access bank direct (0x000 to 0x07F)
Bank direct (0xB00 to 0xB7F)
Requires correctly initializing Bank Select Register (BSR)
Indirect Addressing
Variable pointers
Useful for numbers larger than one byte
Utilizes registers
FSR0, FSR1, FSR2 (FSRx, x=0,1,2)
INDEFx, POSTDECx, POSTINCx, PREINCx, PLUSWx, where x=0,1,2 and
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Homework
LAB WEDNESDAY 31-AUG-05
ITLL Electronics shop (2-3pm)
Build your board
Read
Lab handout
Peatman Chapter 4
Peartman Appendix A1
LAB FRIDAY 02-SEP-05
ITLL Electronics shop (2-4pm)