SPI

1
Serial Peripheral Interface
Some registers parameters are only for 55800
SPI
2
SPI Features
I
Master/Slave
- Supports up to 15 external devices
I
Supports SPI modes 0 1 2 ! "
- #ll com$inations of cloc% p&ase and polarity
I
Programma$le'
- 8 to 1( $it )ata *engt&
- )elays $et+een c&ip selects
- )elays $et+een consecutive transfers
- )elays $et+een cloc% and data per c&ip select
I
Selecta$le Mode ,ault )etection
I
,ixed or -aria$le perip&eral selection
I
Perip&eral )ata .ontroller /P).0
- .&ained 1uffer support
I
*ocal *oop $ac% in Master mode
SPI
"
SPI Block Diagram
PM.
)I-
SPI Interface
M.2
M.2/"2
P).
#P1
PI3
SP.2
MIS3
M3SI
4P.S0/4SS
4P.S1
4P.S2
4P.S"
SPI Interrupt
#P1 1ridge
#S1
SPI
5
Dependencies
I
PM. &as to $e programmed 1
st
for SPI to +or%
I
PI3 .ontroller &as to $e programmed for t&e pins to $e&ave as
intended
I
SPI Perip&eral Inputs 6see7 t&e state of t&e pad8
I
,or example'
- 9se t&e SPI as a transmitter only8
- Program t&e PI3 controller pins for SP.2 and M3SI to $e outputs8
- Program t&e PI3 controller pin for MIS3 to $e a :PI38
; <&e SPI perip&eral=s internal MIS3 input +ill see t&e state of t&e :PI38
I
1e careful of 4P.S0/4SS/:PI3 pin
- If you only &ave 1 external SPI devices t&en tec&nically you can don=t need
an external c&ip select8
- >o+ever if t&e SPI sees a 0 on 4SS PI3 line a Mode ,ault can $e generated8
SPI
5
Master Mode Clock Generation
I
S.1? is 0 on reset8 0 leads to un-predicta$le results8
- Set to somet&ing ot&er t&an 0 $efore 1
st
transfer
- @ac& .&ip Select can &ave its o+n $aud rate
; ,)I- is t&e same for all c&ip selects
M.2/"2 1
0
M.2
,)I-
1aud ?ate :enerator SP.2
SPIA.S?088"
S.1?
15 8
SP.2 BM.2//4 C S.1?0
B1 to 255
SPIAM?
"
0
1
1
"2
,)I- 4
SPI .*3.2
SPI
(
SPI Control Register SPI_CR
I
SPI@4 B 1 B SPI @4#1*@
I
SPI)IS B 1 B SPI )IS#1*@
- .urrent transfer completes
- #ll pins are inputs
I
*#S<C,@?
- 1 B 4P.S rises as soon as last $it transferred out of S&ift register occurs
I
SD?S< B 1 B ?@S@< B soft+are controlled &ard+are reset
- Driting a Eero to t&is register &as no effect
I
SD?S< ! *#S<C,@? cleared $y &ard+are
SPI)IS SPI@4
1 0
SD?S<
F
*#S<C,@?
25
1ot& B 1 SPI B )isa$led
SPI
F
Master Mode Shift Register
I
<C@MP<G
- Set after any programma$le delay
- M.2 can $e turned off in PM. at t&is time
I
3-?@S
- 4o data loaded into ?) +&en B 1
- ?ead SPIAS? to clear
I
<)?@
- .leared +&en SPIA<)? +ritten
- 9sed to trigger P). transfer
I
?)?,
- .leared +&en SPIA?)? read
S&ift ?egister M3SI
SPIA.S?088"
.P3*
0
MIS3
*S1
MS1
4.P>#
1
1I<S
5 F
?)
0 15
SPIA?)?
?)?, 3-?@S
0 "
<)
0 15
SPIA<)?
<)?@
1
SPIAS?
SPI .*3.2
0000 B8
0001 BH
1 B3verrun 1 B?) ,ull 1 B<) @mpty
1 BS&ift ?egister
! <) @mpty
<C@MP<G
H
SPI
8
Mode Fault
I
Mode ,ault occurs +&en t&e SPI is a master and anot&er master &as
asserted 4P.S0/4SS lo+8
- 4P.S0/4SS is normally configured as an open drain
- #dd an external pull-up to 4P.S0/4SS to prevent spurious mode faults
I
@na$led $y default
I
SPI perip&eral gets disa$led +&en fault occurs
18 ?ead SPIAS? to clear M3), $it
28 ?e-ena$le SPI perip&eral t&roug& SPIAM? SPI@4 $it
4P.S0
MS<?
SPIAM?
M3),)IS
M3),
5
0
SPIAM?
2
SPIAS?
1 B,ault
0 B@na$le
SPI
H
Data Transfer Delas
I
<&ree delays can $e programmed
- )elay 1et+een .&ip Selects /D!"BCS0
; )elays assertion from one c&ip select to anot&er
; Same delay for all c&ip selects
- )elay 1efore SP.2 /D!"BS#
; SP.2 is delayed after t&e c&ip select assertion
; Programma$le for eac& c&ip select
- )elay 1et+een .onsecutive <ransfers /D!"BCT#
; Programma$le for eac& c&ip select
SPI
10
Transfer Delas
I
)elay 1et+een .&ip Selects /D!"BCS0
- 9se to accommodate SPI devices +it& long float times
- )elay B I of M.2 periods if ,)I- B 0 or I of M.2 periods J "2 if ,)I- B 1
- If )*G1.S K ( its set to ( to guarantee a minimum delay
; 3r ( J "2 M.2 periods if ,)I- B 1
4P.S0
4P.S1
SP.2
D!"BCS )*G1S )*G1.< )*G1.<
SPI
11
Transfer Delas
I
)elay 1efore SP.2 /D!"BS0
- )efines delay from 4P.S valid to 1
st
valid SP.2 transition
- If )*G1S B 0 t&e delay B L t&e SP.2 period
- )elay B I of M.2 periods if ,)I- B 0 or I of M.2 periods J "2 if ,)I- B 1
4P.S0
4P.S1
SP.2
)*G1.S D!"BS )*G1.< )*G1.<
SPI
12
Transfer Delas
I
)elay 1et+een .onsecutive <ransfers /D!"BCT#
- )efines delay $et+een 2 consecutive transfers +it&out removing t&e c&ip
select
- )elay is al+ays inserted after eac& transfer and $efore removing t&e c&ip
select if needed
- If )*G1.< B 0 t&en no delay
- )elay B ///"2 x 4 x )*G1.<0 / M.20 M // 4 x S.1? 0 / /2 x M.200
; 4 B 1 if ,)I- B 0 else 4 B "2
4P.S0
4P.S1
SP.2
)*G1.S )*G1S D!"BCT D!"BCT
SPI
1"
Peripheral Selection
I
,ixed' PS $it in SPIAM? B 0
- SPI manages data flo+ +it& only one external SPI device at a time
- P). uses optimal 8 or 1( $it data to transfer data N memory efficient
- P.S field in SPIAM? used to select device on t&e $us
I
-aria$le' PS $it in SPIAM? B 1
- SPI manages data flo+ +it& more t&an one external SPI device8
- 9sing t&e P). data is transferred in "2 $it mode8
; "2 $it S?#M locations are encoded to select t&e appropriate external device
automatically8
; 4ot as memory efficient $ut allo+s for multiple SPI device communication
+it&out processor intervention
- P.S field in SPIA.S?088" select external devices on t&e SPI $us
I
SPI still manages t&e programma$le data lengt& of 8 to 1( $its in
eit&er mode8
SPI
15
Peripheral Chip Select Decoding
I
P.S)@. $it in SPIAM? B 0
- .&ip selects 4P.S0 N 4P.S" are directly connected to SPI devices
- P.S field in SPI_MR maps directly to 4P.S0 to 4P.S"
; 1 of 5 encoding
I
P.S)@. $it in SPIAM? B 1
- .&ip selects 4P.S0 N 4P.S" are connected to a 5 to 1( decoder
- P.S field in SPI_TDR is $inary encoded8
- SPIA.S?0 controls external SPI devices 0-" SPIA.S?1 controls O
I
Pins 4P.S0 N 4P.S" at a logic 1 indicates no device selected
- P.S value of 1111 is reserved for no transfers +&en P.S)@. B 1 or 0
- 15 external devices can $e controlled +&en P.S)@. B 1
- 5 external devices can $e controlled +&en P.S)@. B 0
SPI
15
Peripheral Chip Select Decoding
PCSD$C % &
SPI 0 SPI 1 SPI "
SP.2
M3SI
MIS3
0 1 1 1
P.S <)
1H 1( 15 0
SPIAM?
4P.S0
4P.S1
4P.S2
4P.S"
S>I,<
?@:IS<@?
M3SI
SPIA<)?
SPI
1(
Peripheral Chip Select Decoding
PCSD$C % '
SPI 0 SPI 1 SPI F
SP.2
M3SI
MIS3
0 1 1 1
P.S <)
1H 1(15 0
SPIA<)?
4P.S0
4P.S1
4P.S2
4P.S"
5 to 1(
)@.3)@?
S>I,<
?@:IS<@?
M3SI
0
1
F
15
SPI
1F
(aria)le Peripheral Mode
SPI )@-I.@
)#<#
"2 1I< S?#M M@M3?G
#))?@SS
1101 <)
1H 1(15 0
C
2" 20
*#S<C,@?
25
C
"1 25
1101 <)
1H 1(15 0
C
2" 20
*#S<C,@?
25
C
"1 25
1101 <)
1H 1(15 0
C
2" 20
*#S<C,@?
25
C
"1 25
1101 <)
1H 1(15 0
C
2" 20
*#S<C,@?
25
C
"1 25
0x100
0x108
0x10.
0x105
0111 <)
1H 1(15 0
C
2" 20
*#S<C,@?
25
C
"1 25
0111 <)
1H 1(15 0
C
2" 20
*#S<C,@?
25
C
"1 25
0111 <)
1H 1(15 0
C
2" 20
*#S<C,@?
25
C
"1 25
0111 <)
1H 1(15 0
C
2" 20
*#S<C,@?
25
C
"1 25
0x110
0x118
0x11.
0x115
0111 <)
1H 1(15 0
C
2" 20
*#S<C,@?
25
C
"1 25
0x120
P.S
!*ST+F$R % ', Current -PCS pin de.asserts as soon as the data transfer has occurred
SPI
18
Fi/ed0(aria)le 1 Chip Select Summar
I
,ixed
- .ommunication managed +it& one perip&eral at a time $y t&e processor
- .&ip Selects controlled $y SPIAM?
- Memory efficient processor in-efficient
I
-aria$le
- >ig&ly automated communication +it& up to 15 devices +it& no processor
intervention
- .&ip Selects controlled $y SPIA<)? every +rite to SPIA<)? can select a
different SPI device
- Processor efficient memory in-efficient
I
.&ip Select )ecoding
- 1 of 5 @ncoding
; 1it 0 of P.S field &as priority
N P.S B 0000 B 4P.S0 B 0 4P.S 1-" B 1
N P.S B 0101 B 4P.S1 B 0 4P.S 02" B 1
- 1inary @ncoding
; 1111 not allo+ed
SPI
1H
(aria)le Peripheral Mode
I
.an you use -aria$le Perip&eral Mode +it& only 5 external SPI
devicesP
- Ges
; .&ip Select decoding &as to $e done $y user=s SD8
; P.S in SPIA.S?088" maps directly to 4P.S pins
; Soft+are can create $us contention8
SPI
20
Sla2e Mode
I
Slave mode c&aracteristics defined $y SPIA.S?0
I
?)?, in SPIAS? rises on transfer from S&ift ?egister to ?ead )ata
?egister
I
If ?)?, is already &ig& transfer is a$orted 3-?@S $it is set
I
D&en a transfer starts data s&ifted out is +&at=s present in t&e s&ift
register
SP.2
4SS
SPI)IS
MS<?
SPI@4
SPI .*3.2
SPI
21
SPI Peripheral Data Controller
I
)M# from memory to perip&eral and vice versa
- .an $e external memory on @1I for t&ose parts t&at &ave an @1I
I
1 Master .loc% .ycle needed for memory to perip&eral transfer
I
2 Master .loc% .ycles needed for perip&eral to memory transfer
I
,or eac& c&annel
- "2 $it memory pointer /incremented $y $yte &alf-+ord or +ord0
- 1( $it transfer count /decrements0
- "2 $it next memory pointer /incremented $y $yte &alf-+ord or +ord0
- 1( $it next transfer count /decrements0
I
?egisters
- ?eceive Pointer ?egister /?P?0 and <ransmit Pointer ?egister /<P?0
- ?eceive .ounter ?egister /?.?0 and <ransmit .ounter ?egister /<.?0
- ?eceive 4ext Pointer ?egister /?4P?0 and <ransmit 4ext Pointer ?egister
/<4P?0
- ?eceive 4ext .ounter ?egister /?4.?0 and <ransmit 4ext .ounter ?egister
/<4.?0
SPI
22
SPI PDC Chaining Buffers
I
<ransmit .&annel @xample
- D&en SPIA<.? B 0
; .ontents of SPIA<4P? are loaded into SPIA <P?
; .ontents of SPIA <4.? are loaded into SPIA <.?
; SPIA <4.? is set to 0
; ,lags are updated accordingly
SPI
2"
SPI PDC Flags
I
@4)?C is set +&en ?.? B 0
I
?C19,, is set +&en ?.? B 0 ! ?4.? B 0
I
@4)<C is set +&en <.? B 0
I
<C19,@ is set +&en <.? B 0 ! <4.? B 0
I
>o+ do you program t&e P). to exceed 1"10F0 transfersP
- Program SPI Including Interrupt
- *oad 0x,,,, into $ot& ?.? ! ?4.?
- *oad memory pointers ?P? ! ?4P?
- @na$le P). c&annel
- D&en @4)?C -Q 1
; Interrupt gets generated
; .&ec% ?4.? B 0
; *oad ?4.? +it& anot&er value
; *oad ?4P? +it& t&e next address
SPI
25
SPI PDC Control 1 Status
I
.ontrol
- @na$le
; Driting a 1 to t&e 6@47 $it ena$les t&e c&annel if t&e 6)IS7 $it is not set
- )isa$le
; Driting a 1 to t&e 6)IS7 $it disa$les t&e c&annel
I
Status
- 1 B transfers for t&at c&annel are ena$led
H
?C<)IS ?C<@4
1
0
<C<)IS <C<@4
8
SPIAP<.?
H
?C<@4
0
<C<@4
8
SPIAP<S?
SPI
25
SPI PDC Register !ocations
I
.ontrol registers start at perip&eral address offset $y 0x100
- 0x100 ' SPIA?P? ' SPI ?eceive Pointer ?egister ?ead/Drite
- 0x105 ' SPIA?.? ' SPI ?eceive .ounter ?egister ?ead/Drite
- 0x108 ' SPIA<P? ' SPI <ransmit Pointer ?egister ?ead/Drite
- 0x10. ' SPIA<.? ' SPI <ransmit .ounter ?egister ?ead/Drite
- 0x110 ' SPIA?4P? ' SPI ?eceive 4ext Pointer ?egister ?ead/Drite
- 0x115 ' SPIA?4.? ' SPI ?eceive 4ext .ounter ?egister ?ead/Drite
- 0x118 ' SPIA<4P? ' SPI <ransmit 4ext Pointer ?egister ?ead/Drite
- 0x11. ' SPIA<4.? ' SPI <ransmit 4ext .ounter ?egister ?ead/Drite
- 0x120 ' SPIAP<.? ' SPI P). <ransfer .ontrol ?egister Drite-only
- 0x125 ' SPIAP<S? ' SPI P). <ransfer Status ?egister ?ead-only
I
SPI control registers for S#MFS start at address 0 x ,,,@ 0000
I
SPI P). control registers start at address 0 x ,,,@ 0100
SPI
2(
SPI Interrupts
I
SPI Interrupt @na$le ?egister SPIAI@? /Drite 3nly0
0 B 4o effect
1 B @na$le
I
SPI Interrupt )isa$le ?egister SPIAI)? /Drite 3nly0
0 B 4o effect
1 B )isa$le
I
SPI Interrupt Mas% ?egister SPIAIM? /?ead 3nly0
0 B 4ot ena$led
1 B @na$led
<)?@ ?)?,
1 0
M3),
2
3-?@S
"
@4)<C @4)?C
5 5
?C19,,
(
<C19,@
F
4SS?
8
<C@MP<G
H
SPIAI@? SPIAI)? SPIAIM?
SPI
2F
SPI Interrupts
I
?eceive )ata ?egister ,ull
I
<ransmit )ata ?egister @mpty
I
Mode ,ault @rror
I
3verrun @rror
I
@nd of ?eceive 1uffer
I
@nd of <ransmit 1uffer
I
?eceive 1uffer ,ull
I
<ransmit 1uffer @mpty
I
4SS ?ising
I
<ransmit ?egisters @mpty
1 interrupt line goes to t&e #I.
?ead SPIAS? to determine +&ic& interrupt occurred
P). ?elated
<)?@ ?)?,
1 0
M3),
2
3-?@S
"
@4)<C @4)?C
5 5
?C19,,
(
<C19,@
F
4SS?
8
<C@MP<G
H
SPI
28
SPI Status Register SPI_SR
I
?eceive )ata ?egister ,ull
I
<ransmit )ata ?egister @mpty
I
Mode ,ault @rror
I
3verrun @rror
I
@nd of ?eceive 1uffer
I
@nd of <ransmit 1uffer
I
?eceive 1uffer ,ull
I
<ransmit 1uffer @mpty
I
4SS ?ising
I
<ransmit ?egisters @mpty
I
SPI @na$le Status
10
P). ?elated
<)?@ ?)?,
1 0
M3),
2
3-?@S
"
@4)<C @4)?C
5 5
?C19,,
(
<C19,@
F
4SS?
8
<C@MP<G
H
SPI
2H
SPI Summar
I
>ig& Speed8 55 M$/s for S#MFS devices
I
Separate $aud rate generation on eac& c&ip select
I
.an control up to 15 external SPI devices
I
Programma$le data lengt& of 8 to 1( $its
I
>ig&ly flexi$le automated )M# support
- Put t&e processor to sleep +&ile transferring data
I
Programma$le delays on c&ip selects to accommodate various $us
timing from different SPI I. manufacturers
I
@rror c&ec%ing
- *ocal *oop 1ac%
- Mode ,ault )etection