Wide Area Differential Protection System

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3-24-2006
Wide Area Diferential Protection System
Jie Tang
Florida State University
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Tang, Jie, "Wide Area Diferential Protection System" (2006). Electronic Teses, Treatises and Dissertations. Paper 1717.

THE FLORIDA STATE UNIVERSITY

FAMU-FSU OF COLLEGE OF ENGINEERING

WIDE AREA DIFFERENTIAL PROTECTION SYSTEM

By

JIE TANG

A Dissertation Submitted to the
Department of Mechanical Engineering
in partial fulfillment of the
requirements for the degree of
Doctor of Philosophy

Degree Awarded:
Summer Semester, 2006

Copyright 2006
Jie Tang

The members of the Committee approve the Dissertation of Jie Tang defended on March
24, 2006.

__________________________
Peter G. McLaren
Professor Co-Directing Dissertation

__________________________
Dave Cartes
Professor Co-Directing Dissertation

__________________________
Jim Zheng
Outside Committee Member

_________________________
Juan Ordonez
Committee Member

__________________________
Jie Chang
Committee Member

__________________________
Chiang Shih
Committee Member

Approved:

_____________________________________________
Chiang Shih, Chair, Department of Mechanical Engineering

________________________________
C.J. Chen, Dean, College of Engineering

The Office of Graduate Studies has verified and approved the above named committee
members.
ii

Are you staying home today?
Yes, mam.
iii

ACKNOWLEDGEMENTS
I wish to thank Professor Peter G. McLaren for his introductions on the dissertation; the
members of the examination committee for their involvement and effort in the examination
process; Dr.Woodruff and Mike Sloderbeck for their assistances in the RTDS; Dr. Cartes and Dr.
Baldwin for their encouragement in the very first years of my graduate studies; MSU for the use
of their relays and assistance with the hardware in the loop system in Chapter 4.

iv

TABLE OF CONTENTS
LIST OF TABLES.......................................................................................................................VII
LIST OF FIGURES ................................................................................................................... VIII
LIST OF FIGURES ................................................................................................................... VIII
LIST OF SYMBOLS & TERMS................................................................................................... X
ABSTRACT.................................................................................................................................. XI
CHAPTER 1 ................................................................................................................................... 1
INTRODUCTION.......................................................................................................................... 1
1.1 BACKGROUND........................................................................................................................ 1
1.2 THE RESEARCH PROJECT ....................................................................................................... 6
1.3 CONTRIBUTIONS OF THE DISSERTATION............................................................................... 10
1.4 ORGANIZATIONS OF THE DISSERTATION.............................................................................. 10
CHAPTER 2 ................................................................................................................................. 12
DIFFERENTIAL PROTECTION ................................................................................................ 12
2.1 INTRODUCTION .................................................................................................................... 12
2.2 TYPES OF DIFFERENTIAL PROTECTION................................................................................. 13
2.3 ADVANCES IN DIGITAL DIFFERENTIAL RELAYING TECHNIQUE............................................ 19
2.4 COMMUNICATION ISSUES..................................................................................................... 23
CHAPTER 3 ................................................................................................................................. 26
SYMMETRICAL COMPONENTS FAULT CHARACTESTICS ANALYSIS FOR
UNGROUNDED POWER SYSTEMS ........................................................................................ 26
3.1 INTRODUCTION .................................................................................................................... 26
3.2 UNGROUNDED POWER SYSTEM MODEL............................................................................... 27
3.3 NOMINAL CURRENT QUANTITIES......................................................................................... 31
3.4 CHARACTERISTICS ANALYSIS FOR SINGLE-PHASE-GROUND FAULTS.................................. 32
3.5 CHARACTERISTICS ANALYSIS FOR PHASE TO PHASE TYPES OF FAULTS .............................. 53
3.6 VERIFICATION OF CHARACTERISTIC FORMULAE.................................................................. 61
3.7 DIFFERENTIAL TYPE OF FAULT DETECTION......................................................................... 85
CHAPTER 4 ................................................................................................................................. 87
WIDE AREA DIFFERENTIAL PROTECTION SYSTEM........................................................ 87
4.1 INTRODUCTION .................................................................................................................... 87
4.2 DIFFERENTIAL RING PRINCIPLE ........................................................................................... 89
4.3 WIDE AREA DIFFERENTIAL PROTECTION............................................................................. 97
4.4 WADP EXPERIMENTAL SYSTEM....................................................................................... 102
4.5 CASE STUDIES AND RESULTS............................................................................................. 107
v

CHAPTER 5 ............................................................................................................................... 117
FUZZY DIFFERENTIAL ALARM SYSTEM.......................................................................... 117
5.1 INTRODUCTION .................................................................................................................. 117
5.2 FUNDAMENTALS ON FUZZY INFERENCE SYSTEM............................................................... 119
5.3 DIFFERENTIAL FAULT CLASSIFIER FACTORS ..................................................................... 125
5.4 FUZZY CLASSIFICATION RULES ......................................................................................... 130
5.5 FUZZY DIFFERENTIAL ALARM SYSTEM.............................................................................. 135
CHAPTER 6 ............................................................................................................................... 142
CONCLUSIONS AND FUTURE RESEARCH ........................................................................ 142
APPENDIX A............................................................................................................................. 146
APPENDIX B............................................................................................................................. 148
APPENDIX C............................................................................................................................. 151
REFERENCES ........................................................................................................................... 171
BIOGRAPHICAL SKETCH ...................................................................................................... 177

vi

LIST OF TABLES
TABLE 3. 1 LABEL AND THEIR DESCRIPTIONS.......................................................................... 29
TABLE 3. 2 CHARACTERISTIC EQUATIONS FOR PHASE-A-TO-GROUND FAULT AT SELECTED
POSITIONS.............................................................................................................. 52
TABLE 3. 3 CHARACTERISTIC EQUATIONS FOR PHASE-B/C-TO-GROUND FAULT AT SELECTED
POSITIONS.............................................................................................................. 54
TABLE 3. 4 DIFFERENTIAL CURRENTS FOR PHASE B-C FAULT................................................ 60
TABLE 3. 5 SIMULATION PARAMETERS .................................................................................... 64
TABLE 4. 1 PROTECTION RESULTS FOR CASE 2...................................................................... 114
TABLE 4. 2 TEST SCENARIOS AND RESULTS ASSOCIATED WITH LOSS OF CT4 DATA............. 115
TABLE 5. 1 CHOICES OF DIFFERENTIAL MAGNITUDE FACTORS.............................................. 125
TABLE 5. 2 CHOICE OF DIFFERENTIAL ANGLE FACTORS (IN DEGREE).................................... 127
TABLE 5. 3 DIFFERENTIAL FAULT CLASSIFIER FACTORS ....................................................... 129
TABLE 5. 4 FAULT TYPE CODING........................................................................................... 134
TABLE 5. 5 FUZZY VARIABLE REPRESENTING FAULT TYPE................................................... 135
TABLE C. 1 OUTMOST RING CT SELECTION TABLE ............................................................... 161
TABLE C. 2 SIGNAL ON TERMINAL BLOCKS............................................................................ 164
TABLE C. 4 SEL RELAY DIGITAL OUTPUT STATE.................................................................. 166
TABLE C. 5 LOGIC RELATION BETWEEN RELAY, DOPTO CARD AND CIRCUIT BREAKER ..... 168
TABLE C. 6 OPERATION STATUS OF CIRCUIT BREAKER TRIP CIRCUIT.................................... 176
vii

LIST OF FIGURES
FIGURE 1. 1 DUPLICATION OF RELAYS AND CTS........................................................................ 2
FIGURE 1. 2 CB2 BREAKER FAILURE PROTECTION ..................................................................... 3
FIGURE 1. 3 REMOTE BACKUP PROTECTION................................................................................ 4
FIGURE 1. 4 TIME GRADED OC SCHEME..................................................................................... 4
FIGURE 1. 5 ZONE DISTANCE SCHEME ........................................................................................ 5
FIGURE 1. 6 FAULT IMPEDANCE TRAJECTORIES FOR AB-G FAULTS ........................................... 8
FIGURE 1. 7 PHASE A CURRENTS MEASURED BY C1 OVER-CURRENT RELAY ............................ 9
FIGURE 2. 1 THE PRINCIPLE OF OVER-CURRENT DIFFERENTIAL PROTECTION............................. 14
FIGURE 2. 2 EXTERNAL FAULT WITH CT2 SATURATION........................................................... 14
FIGURE 2. 3 HIGH IMPEDANCE DIFFERENTIAL PROTECTION...................................................... 15
FIGURE 2. 4 BIAS PERCENTAGE DIFFERENTIAL PROTECTION .................................................... 17
FIGURE 2. 5 WIDE AREA COMMUNICATION NETWORK FOR WADP SYSTEM............................ 25
FIGURE 3. 1 AN UNGROUNDED SHIP TYPE OF POWER SYSTEM MODEL..................................... 28
FIGURE 3. 2 SEQUENCE NETWORK FOR THE UNGROUNDED SYSTEM MODEL ............................ 30
FIGURE 3. 3 SEQUENCE NETWORKS AND INTERCONNECTIONS FOR A PHASE-A-TO-GROUND
FAULT.................................................................................................................... 34
FIGURE 3. 4 REDUCED SEQUENCE CIRCUIT ............................................................................... 35
FIGURE 3. 5 VOLTAGE PATTERNS FOR A SOLID PHASE-A-TO GROUND FAULT......................... 38
FAULT AT F2.......................................................................................................... 45
FAULT AT F3.......................................................................................................... 49
FAULT AT F4/5....................................................................................................... 51
FIGURE 3. 9 SEQUENCE NETWORKS AND INTERCONNECTIONS OF PHASE B-C FAULT............... 56
FIGURE 3. 10 SEQUENCE NETWORK AND ITS INTERCONNECTIONS FOR PHASE B-C-GROUND
FAULT.................................................................................................................... 62
FIGURE 3. 11 SEQUENCE NETWORK FOR THREE-PHASE FAULT............................................... 63
FIGURE 3. 12 NOMINAL LINE TO GROUND VOLTAGES ............................................................ 65
FIGURE 3. 13 NOMINAL CURRENTS MEASURED BY SENSORS S AND R................................... 65
FIGURE 3. 14 NOMINAL DIFFERENTIAL CURRENTS ................................................................. 66
FIGURE 3. 15 VOLTAGES DURING A PHASE A GROUND SOLID FAULT ................................. 67
FIGURE 3. 16 VOLTAGE PHASOR DIAGRAM (RMS)................................................................. 68
FIGURE 3. 17 VOLTAGES FOR PHASE B-GROUND FAULT......................................................... 68
FIGURE 3. 19 VOLTAGES FOR PHASE C-GROUND FAULT......................................................... 69
FIGURE 3. 21 VOLTAGE PHASOR DIAGRAM FOR HIGH IMPEDANCE......................................... 70
FIGURE 3. 22 PHASE DIFFERENTIAL CURRENTS FOR A PHASE A GROUND SOLID FAULT ..... 71
FIGURE 3. 23 PHASE DIFFERENTIAL CURRENTS FOR A PHASE B GROUND SOLID FAULT ..... 73
FIGURE 3. 24 PHASE DIFFERENTIAL CURRENTS FOR A PHASE C GROUND SOLID FAULT ..... 74
viii

FIGURE 3. 25 PHASE DIFFERENTIAL CURRENT PHASOR DIAGRAM.......................................... 76
FIGURE 3. 26 SEQUENCE DIFFERENTIAL CURRENTS PHASOR DIAGRAM.................................. 79
FIGURE 3. 27 PHASE DIFFERENTIAL CURRENT PHASOR DIAGRAM.......................................... 83
FIGURE 3. 28 SEQUENCE DIFFERENTIAL CURRENT PHASOR DIAGRAM ................................... 85
FIGURE 4. 1 DIFFERENTIAL RINGS............................................................................................. 90
FIGURE 4. 2 DIFFERENTIAL FAULT LOCATION PROCESS............................................................ 92
FIGURE 4. 3 GRAPHIC MAPPING ................................................................................................ 93
FIGURE 4. 4 THE FLOWCHART FOR DIFF RING FAULT LOCATION ALGORITHM......................... 96
FIGURE 4. 5 PRIMARY PROTECTION SYSTEM............................................................................. 98
FIGURE 4. 6 SCHEMATIC DIAGRAM OF THE WADP EXPERIMENTAL TESTBED........................ 105
FIGURE 4. 7 THE WADP EXPERIMENTAL SYSTEM.................................................................. 106
FIGURE 4. 8 SCRIPT FILE FLOW CHART................................................................................... 108
FIGURE 4. 9 PRIMARY PROTECTION FOR AB PHASE TO G FAULT ON BUS4.......................... 110
FIGURE 4. 10 BACKUP PROTECTION FOR AB PHASE TO G FAULT AT BUS4........................ 113
FIGURE 5. 1 TRIANGULAR FUZZY MEMBERSHIP FUNCTION..................................................... 120
FIGURE 5. 2 TRAPEZOIDAL FUZZY MEMBERSHIP FUNCTION ................................................... 121
FIGURE 5. 3 FUZZY INFERENCE SYSTEM.................................................................................. 123
FIGURE 5. 4 MEMBERSHIP FUNCTIONS FOR INPUT 1 (RATIO_1) .............................................. 132
FIGURE 5. 5 MEMBERSHIP FUNCTIONS FOR INPUT2 (RATIO_2) ............................................... 133
FIGURE 5. 6 MEMBERSHIP FUNCTIONS FOR INPUT 3 (ANGLE) ................................................. 134
FIGURE 5. 7 FUZZY DIFFERENTIAL ALARM SYSTEM................................................................ 137
FIGURE 5. 8 VOLTAGES AND CURRENTS FOR AG FAULT AT F1 WITH RF=0.01OHM................ 138
FIGURE 5. 9 MAGNITUDES AND ANGLES FOR POSITIVE SEQUENCE DIFFERENTIAL CURRENT . 139
FIGURE 5. 10 DIFFERENTIAL FAULT FACTORS AND CLASSIFIED RESULTS............................. 140
FIGURE A. 1 SHIPBOARD TESTBED SIMULATED ....................................................................... 148
FIGURE B. 1 SEQUENCE COMPONENTS..................................................................................... 154
FIGURE C. 1 DIFFERENTIAL TRIP LOGIC .................................................................................. 159
FIGURE C. 2 DIFFERENTIAL ELEMENT BZ1 AND ITS APPLICATION IN OUTMOST RING............ 160
FIGURE C. 3 SEL RELAY LOW-LEVEL INTERFACE AND CONNECTIONS ................................... 163
FIGURE C. 4 ANALOG SIGNALS FROM RTDS PARALLEL PROCESSOR, ..................................... 165
FIGURE C. 5 DOPTO CARD FRONT VIEW................................................................................ 167
FIGURE C. 6 RELAY TRIP SIGNALS TO THE RTDS DOPTO CARDS FRONT PANEL INPUTS ...... 168
FIGURE C. 7 FRONT VIEW OF HIGH VOLTAGE DIGITAL INTERFACE PANEL ............................. 169
FIGURE C. 8 HIGH VOLTAGE DIGITAL PANEL CONNECTIONS .................................................. 170
FIGURE C. 9 RELAY COORDINATION IN THE RTDS.................................................................. 172
FIGURE C. 10 COORDINATION BETWEEN OUTMOST RING RELAY TRIP AND.......................... 173
FIGURE C. 11 COORDINATION BETWEEN HARDWARE RELAY TRIP AND................................ 174
FIGURE C. 12 CIRCUIT BREAKER TRIP CIRCUITS IN THE RTDS............................................. 175

ix

LIST OF SYMBOLS & TERMS
ATM Asynchronous Transfer Mode
Burden Load of CTs and PTs
CB Circuit Breaker
CT Current Transformer
Diff Differential
EMTDC Electromagnetic Transients Program
FBDA Fuzzy Based Differential Alarm
GPS Global Position System
IED Intelligent Electronic Devices
IOC Inverse Over Current
mf Membership Function
OC Over Current
PG Phase to Ground
Pick up A mono-stable relay picks up when it changes from the un-energized condition to
an energized condition
PP Phase to Phase
PPG Phase to Phase to Ground
PT Potential Transformer
RTDS Real Time Digital Simulator
UDC User Defined Component
WADP
Protection Time

Diff Ring
Wide Area Differential Protection
The time interval from the instant that a fault occurs to the instant that the circuit
breaker operates
Equivalent to a Zone that defines an effective differential comparison area
x

ABSTRACT

This dissertation is concerned with the development of a new protection philosophy and
methodology applicable to ship characteristic power systems (ac part) for fault detection and
isolation. A wide area differential protection system and a fuzzy based differential alarm system
are the applications of the theories developed in this dissertation.

In the introduction part, the dissertation studies the conventional protection techniques and
analyzes a short-cable problem associated with protecting a power system on board a ship. The
differential method has been identified to have the most potential application in the ship area.
The historical development of differential protection methods and differential protective relays
are considered in the next chapter.

Subsequent chapters develop new differential theories oriented to the ship protection application:
symmetrical component based differential fault characteristics analysis for an ungrounded ship
power system, fuzzy differential fault factor, and differential ring fault detection/location
principle; and investigate the most desirable fault detection and protection systems: a Fuzzy
Based Differential Alarm System (FBDA) and a wide area differential protection (WADP)
system.

The experimental section deals with the development and testing of the WADP system for time
critical events. The simulation section deals with the development and testing of the FBDA
system for not critical time events.

Finally, the issues on ship power system protection and an overall differential type protection
system are discussed.
xi

CHAPTER 1
INTRODUCTION
1.1 Background
1.1.1 Backup Protection
To prevent personnel injury and property damage, and to help maintain system stability,
electrical faults in a power system must be cleared fast. In the early days of electrical power
systems, fault clearing was administered by the maintenance staff. They visually detected a fault
and manually operated a switch to clear the fault. As fault currents became larger and the
operating requirement of the electric power system became more stringent, automatic fault
clearance became necessary [1].
An automatic fault clearing system consists of a circuit breaker and a protective relaying
system. The latter consists of transducers (CT/PT), wiring, relay, auxiliary power supply, and the
operating coil of circuit breakers. Transducers (CT/PT) are observing power system
voltage/current signals and reduce their magnitudes to the levels suitable for inputs to a
protective relay. The protective relay then uses these secondary quantities to determine if there
is a fault present in the protected section. Fault detection principles are based on signal
magnitude, direction, ratio and the like. As a fault is located, the protective relay initiates a trip,
attempting to isolate the fault. In the United States, the auxiliary power supply (station battery) is
in general 125V dc. It supplies direct current to the breaker trip coil to operate the circuit breaker
1

is a relay contact. When a system fault operates the protective relay, its output contact closes to
energize the breaker trip coil, thereby opening the breakers.
It is important to have a degree of redundancy. Because even with the greatest care in
manufacture and installation, it is never possible entirely to eliminate the possibility of a mistake
or a defect in a mechanism. For instance, a trip coil and a linkage may have been overlooked in
maintenance. Without backup protection, a short circuit in a line or piece of equipment would
not be cleared at all and might result in the destruction of the equipment.
The backup literally could be the duplication of either piece of devices involved in the
protection system: CTs/PTs, station battery, breaker trip coil, or protective relay itself. The dual
circuit involves extra expense and complication. With years of practice, engineers have
developed and used three types of backup protection.
1.1.1.1 Local Relay Backup
A B
P.T
C.Ts
Duplicate
relay
Normal
relay
Breaker
Line
Line
B
u
s
B
u
s

Figure 1. 1 Duplication of relays and CTs
Two relays (primary and backup) are provided locally. They work in parallel and trip the
same circuit breaker. In some application, a small constant delay may be inserted to separate the
trips from primary or backup. To achieve a better performance, backup relays may use a
different operating principle from that of the primary relays and to be supplied from separate
CTs. Figure 1. 1[1] shows an example of this arrangement. Duplication of the normal relays
would involve considerable cost and complexity. Hence it would be justified only on very
2

important interconnections. For instance, on transmission lines, distance relays are used to
backup pilot (wire or carrier) protection and vice versa.
1.1.1.2 Breaker Failure Backup
When a relay operates because of a fault but the breaker fails to open, this will be
identified as a breaker failure. If this happens, the breaker backup protection operates and sends a
trip signal to all local and remote circuit breakers that are adjacent to the failed breaker to clear
the fault. This is illustrated in Figure 1. 2[2]. For faults on L12, CB1 and CB2 are tripped. If CB2
fails to open, the breaker backup protection would operate and trip CB3, CB5 and CB7 at the
local substation and CB1 at the remote substation.

1
2
3
4
5
L12
L23
L24
L25
CB1 CB2
CB3 CB4
CB5 CB6
CB7 CB8

Figure 1. 2 CB2 Breaker Failure Protection
1.1.1.3 Remote Backup
Remote backup is provided by a relay at the next station in the direction towards the
source which trips in a delayed time if the breaker in the faulted section is not tripped. For
instance, RelayB in Figure 1. 3[1] forms a primary protection for line BC and Relay A is the
backup relay for RelayB. RelayA at the same time serves as the primary relay for line AB. If a
fault on line BC were not cleared within the primary trip cycle, Relay A would operate and open
CB1 and CB2 at the neighboring station to clear the fault. Since no common equipment is used,
the backup cannot fail from the same cause as the primary protection. Time coordination is
required between primary and backup relays. It usually consists of an over-current scheme or a
distance scheme.
3

The term Backup used in this dissertation refers to this form of backup protection, i.e.
using a remote relay and remote information for the backup decision.

= Breaker
Protected
Circuit
Neighbouring
Circuit
Source
Bus A Bus B Bus C
Relay B
C
CB1 CB2
Relay A
Fast local protection at B
Slow backup protection from A
Line BC
Line AB

Figure 1. 3 Remote Backup Protection
1.1.2 Backup Protection Scheme
A backup relay needs to cooperate with its primary relay for fault clearance. It should be
able to detect all the faults that its primary sees and have a delayed operation. Relaying schemes
are employed for this cooperation.
1.1.2.1 Time Graded Over-Current (OC) Scheme

IOC1 IOC2 IOC3
Time
L1 L2 L3
T1
T2
T3
CB3 CB2 CB1

Figure 1. 4 Time Graded OC Scheme
4

A typical OC scheme consists of a group of Inverse time Over-Current relays (IOC).
Backups are provided by the upstream IOCs. For instance, IOC1 in Figure 1. 4 is the primary
relay for L1 and IOC2 & IOC3 are its backups; IOC2 is the primary relay for L2 and its backup
is IOC3. For a fault on L1, IOC1 is set to operate CB1 at T1 instant to clear the fault. If the fault
were not cleared by IOC1, IOC2 would operate and trip CB2 at T2 instant. If the fault is still
there, IOC3 would trip CB3 to clear the fault at T3. The time interval between T2-T1 and T3-T2
should be at least 400ms to allow circuit breakers to operate. Since IOC3 and IOC2 also serve as
primary relays, they have to be properly set to achieve relatively a high-speed operation on their
own primary sections. This is the time grading process: to decide relay settings for each IOC
relay so that they can operate as fast as possible for its local fault and also have a stage of 400ms
delayed operation for the remote backup. Relay settings involve two parameters [3]. The relay
tap setting determines the minimum current at which the relay will start to operate. The time dial
setting determines the travel time of a contact at a particular operating current level. The large
time dial is, the longer the operation time will be. The process starts with the remote relay
(IOC1), setting it as sensitively as possible. Then the next task is to set the backup relay IOC2
and IOC3. The time grading setting may easily be obtained on the radial transmission or
distribution system. But it may become difficult for loop and mesh systems and directional relays
have to be added to assist the fault detection and discrimination.
1.1.2.2 Three Zone Distance Scheme

Zone1
Zone2
Zone3 without offset
Zone3 with offset
Zone1
CB2 CB3
Relay2
Relay3
Zone2
Zone3 without offset
Zone3 with offset
Relay1
Relay4
CB1 CB4
1 2 3 4
L23
CB5
Z3
Z2,Z3
Z1,Z2,Z3
Z2,Z3
CB6

Figure 1. 5 Zone Distance Scheme
5

The distance scheme consists of a group of impedance relays. Each relay has three zone
settings. The Zone1 element is set to see 80% of the line with immediate operation. Zone2 is
usually set to see a fault on the protected line and 50% of the shortest contiguous line. The zone2
delay time is typically 200/500ms. Zone3 is set to cover the complete contiguous line and its
operation is delayed for 500/1000ms. Zone3 also allows up to 20% offset. So, it can backup for
busbar protection in the reverse direction.
A fault on L23 can be detected by zone 2-3 elements of Relay2 at substation2 and zone
13 elements of Relay3 at substation3. It can also be detected by zone3 element of Relay1 at
substation1, zone2-3 elements of Relay4 at substation4. If communication is not involved,
Relay2 (zone2) and Relay 3(zone1) will trip their own local breakers CB3 and CB4 to isolate the
fault. If the zone1 element of Relay 3 failed to clear the fault, CB4 would be tripped again after
zone2 delay has expired. However, if Relay3 on substation 3 totally failed, then fault clearance
will rely on zone2/3 element of Relay4 and CB6 would be tripped.
If the main protection on the faulted line operates correctly but circuit breaker CB4 fails,
the breaker failure protection on L23 at substation 3 will trip both the adjacent circuit breakers
CB3 and CB5. Since the fault is also detected as a zone2 fault by Relay4 at substation 4, the
tripping of circuit breaker CB5 must be completed before the zone 2 time-delay of Relay4 has
expired because generally circuit breaker failure protection is more selective than remote backup
protection. If 300ms is required to detect a breaker failure and 100ms is to open a circuit breaker
and to reset a relay, then the minimum zone2 time delay setting should be 400ms. The same
principle is applied for setting the zone3 time delay.
1.2 The Research Project
1.2.1 Motivation
The research project involves shipboard power system protection.
The all-electric ship under study will have a much more extensive electrical power
system than present day warships. In addition to new weapon systems and radars the main
propulsion motors, ship services and vital control and command systems will all be powered
from the ships electrical power system. Reliability of such a network, and in particular the
maximum continuity of power flow to vital loads, is essential for mission accomplishment. The
6

main purpose of this research is to establish a new protection platform so as to improve the
overall performance of the electrical system.
In the event of damage caused by an external event or an internal fault the first task is to
identify the effects on the structure of the electrical power system and take corrective action to
isolate the damaged or faulted item from the system. This is the responsibility of the primary
protection system and its associated circuit breakers. This action will be automatic. If the circuit
breaker failed to open to clear the fault, circuit breaker failure backup protection can take
corrective action to trip the adjacent breakers for fault clearance. Up to this point, protection
employed on board the ship is the same as the land-based practice.
The next consideration is that backup protection should take corrective action when the
primary protection failed to clear the fault. However, test results on a typical ship system [4] did
not prove this point. Results showed that a conventional over-current scheme and distance
scheme had problems to achieve a selective trip on the shipboard testbed. The problem stems
from the short cables used to connect the various busbars on board. These cables are typically
10-200 feet long with impedance of the order 0.04ohm/1000feet. Such low impedance makes an
impedance measurement (distance) method impractical. The errors in measurement and
calculation of impedance are relatively large compared to the cable impedance itself and
therefore a fault discrimination boundary cannot be reasonably achieved. The impedance relay is
unsuitable for the application. Moreover, these low impedance cables link the whole shipboard
power system so closely that a remote fault could have almost the same fault current
magnitude as a close-up fault. This leads to difficulty in achieving time-graded over-current
coordination.

Figure 1. 6(a) represents fault impedance trajectories seen by the AB element of a
distance relay for faults simulated at two different places on Cable_C1 in a shipboard testbed
(Appendix A). In the first run, a close-in A-B-G fault was applied at 10 percent of C1. The solid
line shows the impedance trajectory for this case from the pre-fault value to the fault value. In
the second run, a far end A-B-G fault was applied at 90 percent of C1. The stars describe the
impedance trajectory for the second case from the pre-fault value to the fault value. Each star (or
dot) in the plot represents a calculated apparent ZAB=(VA-VB)/(IA-IB) at each plot step. The
enlarged portion in
7

Figure 1. 6(b) shows that the impedance locus of both cases entered into the mho region
and tripped the relays. In both cases, zone 1 setting of the relay is 80% of cable impedance. It is
seen that numerical calculation error at these very low impedances causes significant overreach
and renders the impedance relay unsuitable for this application. The 90% case should not have
tripped.
Figure 1. 7 explains the problem presented to the over-current scheme. A-B-G faults
were applied at two locations on two adjacent cables C1 & C2. The first fault was applied at 5%
of C1 to simulate a close-up internal fault of C1. The second fault was at 95% of C2 that, with
respect to C1 over -current relay, is a far end external fault. But measurements show that these
two fault currents are identical to the C1 over-current relay, leaving no margin to form time-
graded coordination.

The option now is: when the existing remote backup protection methods are
inappropriate for the application, should one resort to the local backup principle or should one
propose a new remote backup scheme.
In this dissertation a new remote backup scheme has been studied. This choice is based
on the viewpoint that remote backup is more reliable than local backup since remote backup uses
fewer common components with those of its primary one and thus has less possibility of
common mode failures involved. It is therefore preferred for the shipboard application.

-5 0 5 10 15 20 25
-6
-4
-2
0
2
10% of C1
90% of C1
Pre_Fault
Fault
Resistance - R (Ohm)
(a)
R
e
a
c
t
a
n
c
e

-

X

(
O
h
m
)
-0.015 -0.01 -0.005 0 0.005 0.01 0.015
-0.01
0
0.01
10% of C1
90% of C1
Resistance - R (Ohm)
(b)
R
e
a
c
t
a
n
c
e

-

X

(
O
h
m
)

Figure 1. 6 Fault Impedance Trajectories for AB-G Faults
(a) Fault Impedance Trajectories on Two Different Locations of C1
(b) Enlarged Portion of (a) Around the Fault Area
8

0.2 0.22 0.24 0.26
-4
-2
0
2
4
5% C1
95% C2
t (second)
C
u
r
r
e
n
t

(
k
A
)

Figure 1. 7 Phase A Currents Measured by C1 Over-current Relay
For AB-G Fault at 5% of C1 and 95% of C2
1.2.2 Scope of This Research
This dissertation assumes contact signals of protection relays and the open/closed states
of circuit breakers and disconnectors are available; all the analogue current phasor signals are
available; a communication network is available on board for data exchanges. Current phasors
derived by some form of local filters either in the primary relay or embedded in the CT itself are
sent to the WADP (Wide Area Differential Backup Protection system) for use in the decision
process. The WADP scheme then uses available sensor information, system topology
information and an extended differential principle to precisely locate a fault and trips only the
circuit breakers that are necessary to isolate the fault.
The dissertation addresses:
Typical fault characteristic patterns of shipboard power systems from the
differential viewpoint;
A wide area differential backup protection scheme to clear a detectable fault fast
and precisely;
Sensor failure scenarios and corrective protection mechanism;

The dissertation also studies a fuzzy differential alarm system. This system is used to
9

handle the low-current fault cases. These cases do not require an immediate trip from the WADP
system. The alarm system provides information on fault locations and fault types that will be
used for manual operations and system maintenance purpose.
1.3 Contributions of the Dissertation
The main contributions of the dissertation includes:
Analysis of Differential Fault Current Characteristics for Ungrounded Power
Systems
Development of a Fuzzy Based Differential Alarm System
Development of a Wide Area Differential Protection System
Implementation of a Real Time WADP System
1.4 Organizations of the Dissertation
The remainder of this dissertation is organized as follows.

Chapter 2 provides a literature review on current differential techniques. The differential
principle is introduced, along with various modifications to improve the sensitivity and stability
of differential comparison. Recent related researches on extended application of current
differential principle are also included.

Chapter 3 is the theoretical part. Symmetrical components and ungrounded system
modeling are introduced first. Then, fault analysis is performed. Symmetrical components are
used to derive fault characteristic patterns on an ungrounded power system. Magnitude and phase
relationship of symmetrical/phase differential fault currents are expressed in explicit formulae.
Theory is given to show how to distinguish tripping faults from alarm faults.
Chapter 4 presents a wide area differential protection (WADP) system. Section 4.2
establishes a fundamental theory for the WADP system. It includes a Differential (Diff) ring
concept, a differential ring formation mechanism and a differential ring search algorithm. Section
4.3 discusses the formation of the WADP system based on the Diff Ring theories. Section 4.4
and 4.5 present the WADP experimental system and test results.
10

Chapter 5 studies a fuzzy differential alarm detector. Fault classification factors are
introduced and fuzzy rules are described. Case studies are provided.

Chapter 6 summarizes the main work of this dissertation and presents the directions of
future research.

11

CHAPTER 2
DIFFERENTIAL PROTECTION
2.1 Introduction

An earliest differential system was introduced by Merz Price around 1905 [3]. It was
an analog type and applied for cable protection. Current signals at opposite ends of the cable
were conveyed by a pair of pilot wires laid alongside the cable and compared by local over-
current relays. Normally, current circulates through the pilot wires and the current transformers
but not through the relays. With an internal-fault, current redistributes and flows through both
relays, causing the breakers to trip (see section 2.2.1).
This differential system requires the current transformers at both ends of the protected
conductor have equal ratios at all values of current. In this way, there will be no difference
current passing through the relay during load conditions and external faults. But perfect CT
matching is hard to obtain. Even when the same type of CT is used and the same ratio selected,
manufacture processes still produce differences between CTs. This error may not be significant
but requires a lower limit setting on an over-current relay. The majority of the comparison error
is contributed to CT saturation under heavy external faults. When the CT core saturates, the
magnetic flux will cease to increase with the flow of the primary current. The secondary current
will hence drop to zero until the primary current begins to magnetize the core in the opposite
direction. If an external fault caused one of the CTs to be severely saturated and the other side
12

unaffected, current presented in the relay during the saturation period would be similar to that
caused by an internal fault fed from one end of the line. This presents a conflict between
sensitive fault detection and reliable relay operation, which cannot be resolved by only
increasing the pickup setting of the relay since large pickup setting may prevent a relay from
operating to clear ground faults for which the fault current may be less than full load current. A
bias or restraining quantity was introduced in the early 1920s [3] to partly overcome the problem
of instability on external faults due to CT saturation. The bias force was proportional to the
scalar quantity of current. One of the formations was the local current passing through a bias
winding, the differential current passing through an operating winding, and the relay was
operated when the ratio of current in the operating winding to current in the bias winding
exceeds a certain value. The fundamentals of differential protection were established around that
time. Section 2.2 reviews various types of differential relays developed since then, including the
principles of the Merz-Price system and a bias differential system. Section 2.3 is the latest
engineering and academic research activities. Section 2.4 briefly reviews the communication
issues.
2.2 Types of Differential Protection
2.2.1 Over-Current (O/C) differential protection
The O/C relay operates when differential current rises above the threshold. The
differential current passing through the relay coil is the vector sum of all of the secondary circuit
currents. This current is normally zero during load conditions and external faults, and becomes
large enough to operate the O/C relay for an internal fault. A basic O/C differential relaying
system [1][6] is shown in Figure 2. 1.
To produce a correct differential current, the CTs in use are of the same ratio and in the
correct polarity sense. Auxiliary or matching CT may be needed for ratio correction. But it
should be carefully handled because auxiliary CTs increase the burden of main CTs and the
chance and severity of CT saturation.
The O/C differential system is incapable of handling the CT saturation effect. Figure 2. 2
models a differential system and explains why. It considers an external fault case which causes

13

Busbar
I1
Polarity
CT1
I2
I1s I2s
CT2
F
Iop=I1s - I2s =0
(a) Extenral Fault
Busbar
I1
Polarity
CT1
I2
I1s I2s
CT2
F
Iop=I1s + I2s =If
(b) Intenral Fault
If
OC
Relay
OC
Relay

Figure 2. 1 The principle of over-current differential protection
Iop=I1s*(R)/(Zr+R)
Busbar
I1
CT1
I2
I1s
CT2
F
1/2RL
1/2RL
Zr
1/2RL
1/2RL
Rct
Zr: relay burden
RL: lead resistance
Polarity
Rct: CT resistance
R=RL+Rct

Figure 2. 2 External Fault with CT2 Saturation
one end of CT (CT2) to be completely saturated and leaves the other side (CT1) unaffected. It is
shown that the estimated differential current is
1 op s
r
R
I I
Z R
=
+
,which is very close to the fault
current measured from one end (
1s
I ) if we consider that the burden (Zr) of solid-state relay and
microprocessor relay is relatively low with respect to lead resistance (
r
Z R << ) [5].
Theoretically, the over-current relay could be set above this value to prevent false operation. But
this requires very unreasonable high setting and may not be sensitive enough for detecting an
internal fault. Another way had been discussed [5] to treat the problem which was to introduce a
time delay to the over-current function to allow for a certain amount of recovery of the saturated
14

CT. But it may not be possible to determine the exact delay time since CT saturation is an
unpredictable event and its degree depends on various factors (CT materials, CT burden,
remanent flux and the like) and power system conditions (X/R, fault angle). Even though this
time could be determined accurately, it may be too long from a system viewpoint and could lead
to a stability problem.
In general, this type of differential system is simple, fast but is not quite reliable.
2.2.2 High Impedance Differential Protection

Rct
Busbar
I1
CT1
I2
CT2
F
1/2RL
I1s
1/2RL
1/2RL
Vr
Zs
Zr
Rct: CT resistance
RL: lead resistance
Polarity
Zs: stabilizing Resistance
Zr: relay burden
1/2RL
Ix

Figure 2. 3 High Impedance Differential Protection
High impedance is named because a high stabilizing resistance (Zs in Figure 2. 3) was
inserted into the differential circuit. This resistance is in series with the relay-operating coil, and
it reduces the amount of spurious differential current caused by CT saturation. In the saturation
case discussed in Figure 2. 2, differential current produced by CT saturation was in the inverse
ratio of Zr and R. If Zr is chosen to be high enough in relation to R, differential current will be
reduced and the relay can be prevented from undesirable operation. Zr is calculated based on
15

*
= <
x
r
I R
I I
Zr
[1], where Ir is the relay pickup. Zr need not be as high as indicated because the
formula is derived from the extreme case (one end completely saturated and the other end
unaffected). Experience with use in generators and transformers protection is that it can be about
one third of this value [1].
Todays high impedance differential relay operates on the voltage threshold. The voltage
(Vr) produced across the relay during CT saturation is assumed to be equal to the voltage drop in
the lead and relay resistance resulting from the total fault current flowing through, i.e.
Vr=I1s*(RL+Rct). The relay is then set greater than this voltage by a suitable margin [7].
High impedance differential protection displays better performances than over-current
differential type and is in wide use for bus-bar protection because busbar faults often create large
fault currents and cause CT to be severely saturated.
The limitations of this type of protection are:
(1) It needs a dedicated type of CTs;
In the model, the completely saturated CT is represented by a simple resistive component
(Rct). This representation is only valid for CTs being of toroidal construction with completely
distributed windings. When other CTs are used, the leakage reactance must be known in order to
determine a setting for the relay. This value could lead to a high voltage setting and make it
impossible to use the relay. Hence, the high impedance differential relay is recommended to use
with dedicated CTs.
(2) It needs a voltage-limiting device;
Extremely large voltages will be developed across the relay in internal faults because of
the high impedance and this could lead to damage to the relay and CTs if precautions are not
taken to limit the voltage to a reasonable level. Nowadays-high impedance relays are shipped
with built-in MOVs (Metal Oxide Varistors) to protect the CT wiring and relay against high
voltage surges during internal faults [7]. This adds to the cost.
2.2.3 Percentage or Biased Differential Protection
Percent differential relays create a restraining signal in addition to the differential signal
and the relay operates when the differential current is greater than a percentage of the total
restraint current. This operation requirement allows the relay to tolerate false differential current
caused by CT saturation. In the early analog type relay [1], the restraining signals were created
16

by adding restraining windings (REST.) into the differential current (Figure 2. 4a). The
magnetic force from differential current will tend to close the relay contact and the magnetic
force created by the restraining current will work on the opposite way to resist this operation.
Differential current is the phasor sum of all circuit currents and restraining effect is proportional
to scalar currents. The amount of restraint is adjustable by changing its turn-taps [5]. During the
external faults, CT may saturate and produce differential current but the external faults will also
increase the current through the restraining winding and produce more restraint to prevent the
undesirable operation. The differential current required to operate the relay is usually expressed
as a percentage of the through current in the restraining winding and the ratio is termed percent
slope.

Busbar
I1
CT1
I2
CT2
F
Iop
I1s I2s
REST. REST.
Polarity
(a) The Principle of Percentage
Differential Protection
(b) Dual Percentage Slope
Iop
IRest.
operate
restrain
Is2
Is1

Figure 2. 4 Bias Percentage Differential Protection
A modern numerical relay uses mathematical expressions to calculate the restraining
signal. The restraining signal can be SUM, AVERAGE or MAX of all terminal currents in
magnitudes. The operating slope can be a single-slope, a double slope characteristic or a non-
linear curve. Equation (1-6) [8] gives an example of a dual slope differential characteristic
(Figure 2. 4b), where Is1, Is2, K1 and K2 are user-defined settings.

17

1 2
1 2
Re
Re 2
Re 1 Re 1
Re 2
Re 2 Re 2 1 2 1
| | | |
2
| |
| | | | , then trip;
| |
| | | | ( ) , then trip;
op
st
st s
st st s
st s
st st s s
I I I
I I
I
If I I
I K I I
If I I
I K I K K I I
= +
+
=
<
> +
>=
> +

(2. 1)
(2. 2)
(2. 3)
(2. 4)
(2. 5)
(2. 6)

Percentage differential relays are specifically useful for transformer protection [5]. The
current transformers on the two sides of the power transformer have different ratios and voltage
ratings. During external faults, their ratios may depart unequally from the nominal values
resulting in differential current. Also, some power transformers are with tap changes (usually
10%), but it is not feasible to change taps on the current transformers correspondingly.
Therefore, the relay will experience certain amount of differential current as the tap is not on the
nominal. With the percentage relay, both problems can be resolved. The first slope (K1) is
typically in the range of 25% to 50% for transformer protection to cover the effect of tap change
and CT phenomena.
2.2.4 Harmonic Restrained/Blocking Differential Protection
In harmonic restrained type, d.c. and harmonic currents became the restraint force and the
operating winding carried only the fundamental frequency current [6]. For blocking type,
harmonic components are directly used to block the relay operation. These harmonics assisted
methods are considered when differential comparison is applied for transformer protection.
When a transformer is energized, there is a transient inrush of magnetizing current that
may be as great as several times the transformer full load current and decays relatively slowly.
This current generally flows in one side of the differentially connected relay only and will tend to
make differential relays operate falsely if some form of restraint/blocking is not provided. The
analysis and tests showed that the inrush current contains significant amount of second
harmonics. Even though second harmonic is also present in fault currents, it is generally very
small. This even harmonic can then be used to identify the inrush phenomenon and to block the
relay from false operation.
18

Other harmonics being used as the blocking/retraining function are: fourth and fifth.
Fourth adds additional security against inrush current. Fifth is to prevent relay mis-operation
during allowable over-excitation conditions. Transformer over-excitation produces odd-order
harmonics that can appear as differential current to operate the relay [9]. The methods to separate
the harmonics and to distinguish the inrush have been well studied. Habib and Marin [10] gave
an extensive review on these algorithms.
2.3 Advances in Digital Differential Relaying Technique
Modern differential relays are digital type. They have better performances and are more
reliable than earlier analog/solid state relays. A digital relay can detect any internal malfunction
that may occur and take itself out of service automatically [11]. It is a self-check procedure.
Multiple-functions can be realized in digital relays. For example, a digital transformer relay can
have differential protection, over-current protection and thermal protection integrated and these
functions can be programmed to work independently or to supervise one another [9][12]. But
implementation of multi-functions was a challenging task for older type analog relays. The
individual analog relay needs to be wired to current transformers (CT) or potential transformers
(PT) and their output contacts have to be connected in series or parallel for the multiple function
purpose. This relaying system would involve additional auxiliary circuits, cumbersome wirings
and considerable installation and maintenance cost. Reliability improved by multi-functions
detection would be deteriorated by a high risk of wiring errors. Hence, digital relays are taking
their place in the relaying field.
Most digital relays are now equipped with DSPs and are capable of handling demanding
signal-processing techniques within a power cycle, which allows advanced differential relaying
techniques to be implemented. The development of advanced differential techniques can be
roughly divided into two categories:
2.3.1 Sensitive Differential Protection
The percentage differential relay can mostly inhibit the false tripping caused by CT
saturation but it requires a higher slope setting. If CT saturation could be detected beforehand,
the differential relay will be allowed to set more sensitively.
19

A method to detect the onset of CT saturation was suggested in [11], which is based on
the fact that current will experience abrupt change when CT saturation sets in. The method can
detect the saturation onset successfully if the current collapses to zero as soon as CT saturates but
may become difficult if current does not collapse to zero after saturation.
One of the earliest works on the CT saturation detector and its application in the
differential system was published by G. Hosemann in the early 90s [13]. The idea was if
saturation occurred with an external fault, the differential trip would be blocked. On the other
hand, if saturation occurred with an internal fault, then trip would be released. In this way, their
relay was able to achieve a higher sensitivity than known devices at that time. The saturation
detection was based on model transformation. Three phase current time domain signals were
transformed to space phasors that preserve a circle type of trajectory when they were in the
unsaturated state. The deviation from this characteristic indicates the inception of current
transformer saturation. An internal or an external fault event was distinguished by the saturation
criterion being fulfilled before the differential detection criterion. For an internal fault, the
differential threshold would be reached before the saturation criterion was satisfied; but for an
external fault, the saturation criterion would be satisfied first. Similar work was carried out by
Kang et al. [14][15][16]. The method they used to distinguish external from internal event was
the same as that of G. Hosemann. But a third-difference function [16] was proposed to detect
CT saturation. The magnitude of the third-difference function became significantly large at the
start and end of each saturation period, while it remained small if the CT was unsaturated. The
authors implemented this relay algorithm in a DSP. Kang et al. [17] also suggested a
compensated-current differential relay for treating the CT saturation effect. The relay used the
same restraining current as conventional relays, but derived a modified differential current that
compensated for the exciting current. It was implemented in an EMTP simulation.
Kasztenny et al. [18] described another detector and implemented it in busbar differential
protection. The saturation detection principle utilized the fact that the CT would operate correctly
for a short period of time even under very large primary current. As a result of this, during an
external fault, differential current developed slowly but the restraining signal increased rapidly.
Once one or more CTs saturate, the differential current would increase. For internal faults both
the differential and restraining current developed simultaneously. In the differential protection
algorithm presented in the paper, the CT saturation signal was used to select 1 out of 2 or 2 out
20

of 2 detection criterion. If saturation is not detected, a trip signal is activated only if differential
comparison is operated; if saturation is detected, a trip signal will be activated if both the
differential and phase comparison operate. Yang et al. [19] take advantage of the same fact that a
CT will not saturate immediately at the beginning of a short circuit fault and suggested an S out
of N sampled value differential comparison. CT saturation by an external fault may cause M
samples beyond the differential threshold but as long as M<S, the mal-operation can be avoided.
Li et al. [20] in 2001 proposed a wavelet method to distinguish the differential current caused by
CT saturation or by internal fault event. The authors observed the differential current caused by
CT saturation event develops relatively slowly compared to an internal fault.
Around the same time, Cesareo Fernandez [21] proposed an impedance measurement
method to detect CT saturation and tested it in their busbar differential relaying system. Signals
in use are busbar voltage and current signals. The detector measures incremental impedance
(
V
I
) and this value becomes different for CT saturation.

The major breakthrough was published in 2003 by Villamagna et al. [22]. They suggested
a symmetrical component based current differential system. The algorithm detected CT
saturation by means of the rate of change of differential current. The instant of a significant rate
change of differential current indicates the start of CT saturation, while its polarity distinguishes
an internal fault from an external fault. A positive polarity of
diff
bias
di
di
will be an external fault and
a negative polarity for an internal fault. The magnitude of the symmetrical fault components will
be used to determine bias settings, if an in -zone fault is detected. The system has a higher
sensitivity and stability than the conventional differential system. In a later paper [23] published
in 2004, the authors explained if the angle displacement of symmetrical current components
would be combined with the conventional magnitude detection, the sensitivity of the system
would be further improved and able to detect high impedance in-zone faults.
2.3.2 Reliable Differential Protection
Li et al. [24] published their GPS synchronized differential protection system in 1996.
This system is especially useful when differential protection covers a long distance and
communication is involved, for instance in the case of transmission line/feeder differential
21

protection. Most digital feeder protection relays in the past were unsynchronized and the samples
at each end of the feeder are obtained based on a local free running clock. This causes significant
errors. To overcome the sampling time alignment problem, these relays will compensate for the
communication channel delay. One of the techniques for aligning data is known as the ping-pong
technique, which measures the time delay between the sampling pulses at two different locations
and applies the appropriate compensation rotation to the received remote power signal. But for
the condition of unequal delay or unsymmetry in the sending and receiving communication
channels, the ping-pong technique may not be able to compensate for the delay accurately. The
level of asymmetry depends on the architecture of the communication system and the delay
differences often range from 1 to 2ms [25], which may result in unintended breaker operation or
mis-operations.
GPS -- Global Position System is a satellite-based navigation, positioning and timing
system of the U.S.A. It can provide accurate time information to users anywhere in the world
with a GPS receiver. The accuracy is better than 1us. In Li et al.s GPS differential system, the
GPS receivers were installed at each end of the feeder, synchronizing the local sampling. The
sampled signal includes three-phase currents and neutral current. The synchronized samples at
each end were processed and encoded by the local relay. This relay then transmitted its data to
the relay at the remote end via a communication channel and simultaneously received data from
that remote relay. The differential comparison algorithm used by Li et al. was the dual slope
percentage differential characteristic. The system demonstrated a high level of stability on
external faults and a high level of sensitivity on internal faults. In 1997, Southern and Li et al.
[26] published their revised system that took account of the possibility of temporary loss of GPS
signal. The revised system can achieve 4us synchronization accuracy. In 1998, Gao et al. [27]
published their study on GPS differential system. In the same year, Serizawa et al. [28] published
their work. They [29][30][31] eventually set up a station wide experiment system.
Kangvansaichol et al. [33][34] took a step further and proposed a concept of multi-zone GPS
differential protection for transmission networks by considering the likelihood of loss of remote
sensor data.
Li et al. [35] also described how the stability of current differential protection could be
improved by replacing current transformers with Fiber Optical Current Transducers (FCOT)
since there was no CT saturation problem involved for FCOT. The authors conducted the
22

comparison studies on both differential protection systems with conventional CT and with
FCOT. The latter demonstrated promising results.
2.4 Communication Issues
Merz-Price differential system used the pilot wire as a medium to convey the signal. Yet,
as the length of the wire significantly increases, the accuracy of pilot wires will decrease due to
accumulated capacitive currents along the pilot wire [5]. It is, therefore, necessary to replace
them with communication links for the accuracy concern. Another reason for replacing the pilot
wires with other communication media is the cost. AC pilot wire relaying was popular in use in
the past when dedicated twisted pair copper was available for relay end-to-end continuous
communications [38]. Now this service is no longer available from telephone companies and
leased phone lines tend to be expensive when many channels over different areas are required
[36].
Communication can influence the differential relaying in every aspect [36]. The channel
bandwidth limits the rate at which the current phasors necessary for the differential calculation
can be inter-changed among the terminals and this in turn limits the operating speed of the
differential relay. Channel degradation such as variable channel delay, noise, channel
interruption and fading often occurs during power system faults. Reliable operation of
differential relays must be assured under these conditions. The communication media which
have been used so far in protective relaying includes power line carrier, radio system,
microwave, and optical fiber. [36][37][38] described the advantages and limitations of these
media. Among them, the optical fiber appears to be the most efficient media to use. It has a good
immunity to RF and atmospheric interference and a high bandwidth needed for the modern data
communications. The wide area protection system proposed in this dissertation encourages using
the optical networks. The propagation delay should be limited to less than 500ms so as to form a
reasonable backup protection. When this requirement is first satisfied, the available bandwidth
can be utilized for communications needs of control and integrated command center on board a
ship.
Another issue involved in communication is the communication protocols. Two most
common protocols used with optical systems are Synchronous Optical Networks (Sonet/SDH)
and Asynchronous Transfer Mode (ATM). Wide band Ethernet also gains popularity but is not
23

used for a backbone system. Sonet (Synchronous Optical Networks) is the American System
under ANSI T1.105 and Bellcore GR Standards and SDH (Synchronous Digital Hierarchy) is
under the International Telecommunications Union (ITU) Standards [36].
The basic difference between Sonet systems and ATM systems are: for Sonet systems, if
there is no data for a particular channel at a particular time, the system just sends a null packet.
But for ATM system, it only puts data on the system as it arrives in private packets. It will not
send null packets when there is no data at a particular time. The transmission rate of both
systems can be up to 155Mbps. The microprocessor-based current differential experimental
system [28][29][30][31] set up by Serizawa et al. in Japan was based on a 155-Mbs ATM
backbone network equipped with a LAN interface and a GPS system.
Recent movement in integrated utility systems is favoring the developing and adopting of
a common and universal communication protocol so that IEDs (including phasor measuring
devices) from different vendors can transfer data over substation LANs/WANs without
additional protocol converter [39][40]. The new protocol is UCA (Utility Communication
Architecture). It addresses, specifies and standardizes all the communication needs involved in
the utility electric system. The project started in 1986 and was supported by EPRI. Participants
include major manufactures such as ABB, Alstom, GE, SEL, Siemens and utilities. UCA 1.0 was
completed by the end of 1991. Between 1993 and 1994, several pilot projects were launched to
examine the results of its real applications. Results from these projects led to the development of
UCA 2.0 which was finally published by IEEE in 1999. With the effects over past years, it is
now accepted as an international standard (IEC 61850). IEEE PSRC published a special report
in May 2005, on Application Considerations of IEC 61850/UCA 2 for Substation Ethernet
Local Area Network Communication for Protection and Control. The document lists examples
of utility applications of UCA for integrated protection.
A particular communication network can be arranged as: point-to-point, star, linear drop
and insert or a ring bus structure [38][41]. The point-to-point system is the simplest one and
channels are connected only between two nodes. The star system consists of multiple point-to-
point systems and all of them are with a common node. In a drop and insert system, the channel
can be configured to connect between any of two nodes in the system. A ring structure allows a
single node to send/receive data to/from any node connected in the system. The advantage of
ring topology is that it provides a network self-healing mechanism when a ring is broken at any
24

point. The nodes on the ring will detect where the break is relative to the other nodes and
automatically reverse transmission direction to re-establish the data link. So the ring structure is
more reliable compared with others. The Sonet/SDH networks are based on ring topology. It is
able to re-establish the traffic within 4ms if the communication between two nodes is lost [36].
The planning and design of a communication network for use on board the ship will, to a
large extent, be separate from the design of protection schemes since the communication network
infrastructure in a Navy ship will be built to serve sophisticated control and command tasks as
well. They pose more stringent requirements on communication. Thus, this dissertation will
focus on the study of the reliable protection schemes and assume that a communication network
(Figure 2. 5) required to transfer the synchronous measurement data to the WADP system and
convey tripping signals from the WADP unit to local CB trip units, is available for use on the
board the ship.

WADP Unit
A Power System Region
PMU
PMU
PMU
Current Signals
Relay/CB Status
Communication Network
WADP Signal
GPS
Satellite
PMU
WADP Unit
A Power System Region
PMU
PMU
PMU
Current Signals
Relay/CB Status
Communication Network
WADP Signal
GPS
Satellite
PMU

Figure 2. 5 Wide Area Communication Network for WADP System

25

CHAPTER 3
SYMMETRICAL COMPONENTS FAULT CHARACTESTICS
ANALYSIS FOR UNGROUNDED POWER SYSTEMS

3.1 Introduction
An ungrounded system is a power system that has no intentional ground in the system.
However, as in any system, there will be a ground path from stray capacitances of the system to
ground. So, the ungrounded system in reality is a capacitively grounded system. This
distributed capacitance causes no problem to the normal operations of a system, but it forms a
natural impedance to limit ground fault current under a single-phase-to-ground fault. The path
for ground fault current under this condition will be through the line to ground distributed
capacitance of surrounding systems and the two remaining un-faulted phases. The impedance of
the distributed capacitances is quite large, so they will reduce the fault current to a low value,
typically several to twenty amperes on a distribution system [6]. Since the system experiences a
very low ground fault current, it is essentially not required to isolate the faulted area
immediately. It may be allowed to continuously operate under a phase-to-ground fault for a
certain period and repairs can be scheduled at a convenient time. This advantage is the main
reason for it being adopted in the ship application.
A ground fault (conductor to hull for the shipboard case) has to be cleared in a reasonable
time before an involvement of a second ground fault. A phase-phase fault creates a large
potentially destructive fault current on an ungrounded system and requires to be interrupted
26

immediately. In addition, a ground fault (solid fault) on one phase results in a full line-to-line
voltage appearing throughout the system on the other two phases. Thus, a voltage 1.73 times the
normal voltage is present on all insulation in the system. Appropriate clearance of the ground
fault reduces this voltage stress.
This chapter proves that the differential principle can be used to detect both ground faults
and phase-to-phase faults on an ungrounded power system. The symmetrical components method
(Appendix B) is used in this chapter to analyze the fault characteristic patterns on an ungrounded
ship type of power system. The focus is on the fault current quantities seen by the current sensors
and a differential relay installed on the system. These quantities are expressed as explicit
formulae, in terms of distributed capacitance, system impedances and fault resistance. Physical
phenomena are interpreted. The characteristic formulae are again verified by simulation results.
The analysis concludes that sequence differential quantities can sensitively detect the ground
faults and high impedance phase-to-phase faults; phase differential quantities are able to detect
phase-to-phase faults. Therefore, from these formulae, a theory is established to define the
tripping faults and alarm faults; how to distinguish tripping faults from alarm faults.
This chapter is arranged as follows:
Section 3.2 briefly introduces the symmetrical components fault analysis method;
Section 3.3 describes an ungrounded ship type of power system model and its sequence
network representation;
Section 3.4 is an analysis of the normal operating conditions;
Section 3.5 is devoted to the study of a single phase to ground type of faults;
Section 3.6 studies phase-to-phase types of faults;
Section 3.7 provides results from EMTDC simulations, verifying the characteristics
patterns;
Section 3.8 summarizes the theory of differential fault detection.
3.2 Ungrounded Power System Model
3.2.1 Ungrounded Power System Model
An ungrounded ship type of power system model (Figure 3. 1) used in this analysis,
consists of a voltage source, an Y/ connected transformer with grounded neutral, two cable
27

sections and static loads. The load-side circuits of this model are ungrounded. The transformer
can also be connected in Y/ with the isolated neutral, Y/Y with primary neutral grounded, /
configurations. They all produce ungrounded load-side circuits. For this study, only one of these
cases is considered. The results from this study, however, are valid for all types of ungrounded
circuits.

A
B
C
A
B
C
A
B
C
CI
C
BI
C
AI
C
Cable I
Cable II
C
B
A
Load II
Load I
CII
C
BII
C
AII
C
Sa
Sb
Sc
Ra
Rb
Rc
Bus 1 Bus 2
Bus 3

Figure 3. 1 An Ungrounded Ship Type of Power System Model
Cable I section represents the faulted section; Cable II section represents the entire
remaining healthy distributed circuits. C C are the lumped phase to ground capacitances
of Cable I; are the lumped phase to ground capacitances of Cable II. To preserve a
balanced operation under normal load conditions, it is assumed that:
, ,
AI BI CI
C
, ,
AII BII CII
C C C
AI BI CI I
AII BII CII I
C C C C
C C C C
= = =
= = =
I

Phase-to-phase capacitances are disregarded in this study since they have no significant
contribution to fault currents under ground or phase to phase faults. Eliminating it simplifies the
derivation. Cable impedance is not represented either. As mentioned in chapter 1, cables on
28

board a ship are short, with very low impedance. Compared to transformer impedance and fault
resistance, this impedance has little effect on the fault current distribution. So it is neglected here.
Sa, Sb, Sc, Ra, Rb and Rc are current measurement sensors.
3.2.2 Sequence Networks
The sequence network is a single-phase representation of a three-phase system. For the
model shown Figure 3. 1, the equivalent sequence network circuits are drawn in Figure 3. 2.
Table 3.1 describes the label convention. The step-by-step derivation procedure for sequence
networks is introduced in details in [6][43][44], and not presented here. One thing that should be
noticed is that the Y/ transformer configuration causes an isolation in the zero sequence
network between the primary and the secondary sides, which leaves a zero sequence network
dominated by capacitive reactance that in turn affects the phase to ground fault current.

Table 3. 1 Label and Their Descriptions
Label Description
N Neutral point
Va1 Positive sequence source voltage
Rs1, Rs2, Rs0 Positive, Negative, Zero sequence source resistors
XTR1, XTR2, XTR0 Positive, Negative, Zero sequence transformer leakage
impedance
X1_C3, X2_C3, X0_C3 Positive, Negative, Zero sequence reactance for cable II,
where, C3=C
II

Z1_load2, Z2_load2,
Z0_load2
Positive, Negative, Zero sequence impedance for load 2
X1_C1, X1_C2
X2_C1, X2_C2
X0_C1, X0_C2
Positive, Negative, Zero sequence reactance of cable I; cable
I is separated into two parts: C1 is the distributed capacitance
ahead of the fault location; C2 is the distributed capacitance
behind the fault position, and C1+C2=C
I.

Z1_load1, Z2_load1,
Z0_load1,
Positive, Negative, Zero sequence impedance for load1
S1, S2, S0 Sensor location; If placed, the sensor would see the Positive,
Negative, Zero sequence current quantities through the front
end sensor S;
R1, R2, R0
Sensor location; If placed, the sensor would see the Positive,
Negative, Zero sequence current quantities through the
terminal sensor R;
The positive direction of current flow into the sensor

29

N
Rs1
Va1
X1_C1 X1_C2
XTR1
S1 R1
Z1_Load1
X1_C3
Z1_Load2
(a)
N
Rs0
X0_C1 X0_C2
XTR0
S0 R0
Z0_Load1
X0_C3
Z0_Load2
(c)
N
Rs2
X2_C1 X2_C2
XTR2
S2 R2
Z2_Load1
X2_C3
Z2_Load2
(b)

Figure 3. 2 Sequence Network for the Ungrounded System Model
(a) Positive Equivalent Sequence Network
(b) Negative Equivalent Sequence Network
(c) Zero Equivalent Sequence Network

30

3.3 Nominal Current Quantities
Nominal current quantities refer to the currents and differential currents present during
normal operating conditions. These values form the reference values to determine if a particular
differential characteristic pattern under consideration is sensitive and reliable enough to detect a
fault.
Under normal load conditions, current sensors (Sa, Sb, Sc, Ra, Rb and Rc) will see the
load currents and currents seen by the phase differential relays (IdA=Sa+Ra, IdB=Sb+Rb,
IdC=Sc+Rc) are the leakage currents passing through the distributed capacitances. These are
observable from the three-phase model in Figure 3. 1. With the phase quantities, phase-sequence
transformation provides sequence current quantities.
The nominal values can also be calculated from the equivalent sequence networks on
Figure 3. 2. A voltage source is not present in the negative and zero sequence networks and
hence the corresponding sequence currents will be zero, i.e.

0 0 2 2 IS IR IS IR = = = = 0 (3. 1)

As a result, negative and zero sequence differential currents (Id0, Id2) are zero too, i.e.

The positive sequence network gives the approximation:

Since, | | | 1_ 1| | 1 1| .
I
XC Z Load Rs XTR >> >> +
1 2
1 1
1 { ; }
2
1
1
1_ 1
1 1 1
1 1 1
1_ 1 1_ 1
I I
I I
I
Va
Id XC j C C C
XC fC
Va
IR
Z Load
Va Va Va
IS IR Id
Z Load XC Z Load
= =
= + = +
+
0

(3. 3)

(3. 4)

(3. 5)
0 2 Id Id = = (3. 2)
31

Using Equation (B. 1), gives phase quantities:
2
2
1
1 1 1 0
1
1 1
1 2
1
I
I
I
Va
XC
IdA Id
Vb
IdB a a Id
XC
IdC a a Id
Vc
XC
(
(
(
( ( (
(
( ( (
= =
(
( ( (
(
( ( (

(
(

(3. 6)
2
2
1
1_ 1
1 1 1 0
1
1 1
1_ 1
1 2
1
1_ 1
Va
Z Load
IRa IR
Vb
IRb a a IR
Z Load
IRc a a IR
Vc
Z Load
(
(
(
( ( (
(
( ( (
= =
(
( ( (
(
( ( (

(
(

(3. 7)
1 1 1
1_ 1 1_ 1
1 1 1
1_ 1 1_ 1
1 1 1
1_ 1 1_ 1
I
I
I
Va Va Va
XC Z Load Z Load
ISa IRa IdA
Vb Vb Vb
ISb IRb IdB
Z Load XC Z Load
ISc IRc IdC
Vc Vc Vc
Z Load Z Load XC
( (
(
(
(
(
(
(
( ( (
(
(
(
( ( (
= + = +
(
(
(
( ( (
(
(
(
( ( (

(
(
(
(
(
( (

(3. 8)
3.4 Characteristics Analysis For Single-Phase-Ground Faults
Faults will be applied at five different locations. Location one (F1) in Figure 3. 3 is on
the cable I and it represents an internal fault. Locations F2-F5 are outside cable I. F2 is on the
left side of the sending end sensors (IS), F3 is on the right side of the receiving sensors (IR), F4
and F5 are on the busbar location and Cable II. Location F2-F5 all represent external faults. For
the analysis, each case (F1-F5) is represented by its equivalent sequence network.
32

The analysis is to derive the fault quantities for each case and to identify the
characteristic patterns that define an internal fault. Section 3.5.1 describes the voltage patterns
under a single phase to ground fault. Section 3.5.2- 3.5.5 are the derivations for current patterns.
The derivation of current patterns starts from the fault location, and continues with the sensor
locations and differential quantities.
3.4.1 Voltage Patterns for Internal/External Phase-A-Ground Fault
For a single phase to ground fault, the sequence networks are in series connected at the
fault position [6][43][44]. Figure 3. 3 gives the equivalent sequence network for a fault at the
position F1. V0, V1, V2 are sequence voltages and Zf is fault resistance. For faults at F2, F3, F4,
F5, connection points are shifted to the corresponding positions (F2, F3, F4 or F5).
To estimate the voltage patterns during the fault, the circuit on Figure 3. 3 is further
reduced at the fault point F1. Capacitances on the positive circuit can be taken off because of
|X1_C3|>>|Z1_load2|; |X1_C1|>> |Z1_load2|, and |X1_C2|>>|Z1_load1|. The negative circuit
can be simplified in the same way and presents with only source impedance and transformer
impedance, considering |Rs2+XTR2|<<|Z2_load2//Z2_load1|. Figure 3. 4 gives the reduced
circuit. The simplification process is applied for faults at F2- F5 as well. But, it was found that
they resulted in the same reduced circuit as shown in Figure 3. 4. This in fact indicates that
voltage patterns, if available, may be possible to indicate a ground fault but they cannot
determine the exact position at which a fault is located on an ungrounded circuit since faults at
different positions produce the same voltage patterns.

The following voltage equations are derived from the reduced circuit:
Positive sequence voltage:

1 1 V Va (3. 9)

The positive sequence voltage (V1) is approximately equal to the positive sequence
source voltage because of |Z1_load2//Z1_load1| >> |(Rs1+XTR1)|, i.e. load impedance is larger
than impedance of the supply circuit.

33

N
Rs1
Va1
X1_C1 X1_C2
XTR1
S1 R1
Z1_Load1
X1_C3
Z1_Load2
N
Rs2
X2_C1 X2_C2
XTR2
S2 R2
Z2_Load1
X2_C3
Z2_Load2
N
Rs0
X0_C1 X0_C2
XTR0
S0 R0
Z0_Load1
X0_C3
Z0_Load2
+
_
V1
+
_
V2
+
_
V0
3Zf
I1
I2
I0
F1
F1
F1

F2
F2
F2
F3
F3
F3
F4
F4
F4 F5
F5
F5
Figure 3. 3 Sequence Networks and Interconnections for a Phase-A-to-ground Fault
34

N
Rs1
Va1
XTR1
Z1_Load=
Z1_Load1//Z1_Load2
N
Rs2
XTR2
N
X0_C
+
_
V1
+
_
V2
+
_
V0
3Zf
I1
I2
I0
F
F
F

Figure 3. 4 Reduced Sequence Circuit

35

Negative sequence voltage:
2 0 V (3. 10)

The negative sequence voltage (V2) is close to zero due to |(Rs2+XTR2)|<<|X0_C|.
Where,
1 2 3
1
X0_C ; }
2 ( )
j
f C C C
=
+ +
{

Zero sequence voltage:
1 2 0 3 0
0 3 0 1 2
3 0 1
V V V I Zf
V I Zf V V
I Zf Va
+ + =
=

0

(3. 11)

With a solid fault (Zf =0), therefore this voltage equals the nominal phase to ground
voltage. During normal conditions, on the other hand, this voltage is zero.

Phase A voltage:
0 1 2
3 0 1 1 0
3 0
Va V V V
I Zf Va Va
I Zf
= + +
= + +
=

(3. 12)

For the faulted phase, its voltage drops to zero for a solid fault or the voltage cross the
fault resistance for a resistive fault.

Phase B voltage:
2
2
2
0 1 2
3 0 1 1 0
3 0 ( 1) 1 0
1 3
3 0 ( 1) 1
2 2
3 1
3 0 3( ) 1
2 2
3 0 3 1 210
Vb V a V a V
I Zf Va a Va
I Zf a Va
I Zf j Va
I Zf j Va
I Zf Va
= + +
= + +
= + +
= +
= +
= +

(3. 13)

36

For a solid ground fault on phase A, phase B voltage during the fault, rises to 1.73 times
the normal phase voltage with a 210 lead with respect to the pre-fault phase A voltage.

Phase C voltage:

2
0
0 1 2
=3 0 1 1 0
=3 0 ( 1) 1
1 3
=3 0 ( 1) 1
2 2
3 1
=3 0 3( ) 1
2 2
=3 0 3 1 150
Vc V a V a V
I Zf Va a Va
I Zf a Va
I Zf j Va
I Zf j Va
I Zf Va
= + +
+ +
+
+ +
+ +
+

(3. 14)

For a solid ground fault on phase A, phase C voltage during the fault, rises to 1.73 times
the normal phase voltage with a 150 lead with respect the pre-fault phase A voltage.
Figure 3. 5 plots the voltage patterns before the fault and during the fault. As indicated, a
phase to ground fault shifts the neutral point but leaves the voltage triangle untouched. The
phase-to-phase voltages supplying the loads are intact. That is why this system still remains
operational during this sustained, low magnitude fault current condition. But the voltage pattern
cannot tell an internal fault from external faults.
Figure 3. 5 is based on the data that:
Before the fault:
1 90
1 30
1 210
During the fault:
Zf=0
0 0
3 1 210 3 300
3 1 150 3 240
Va
Vb
Vc
Vag
Vbg Va
Vcg Va
=
=
=
=
= =
= =

37

Van
Vbn Vcn
n=g
Vag=0
Vbg
n
Vcg

(a) (b)
Figure 3. 5 Voltage Patterns for A Solid Phase-A-to Ground Fault
(a) Before the fault (b) During the fault
3.4.2 Current Characteristics for Phase-A-Ground Fault on Location I
The equivalent sequence circuit for this case has been given in Figure 3. 3. The sequence
networks are interconnected in series through the fault point (F1), the neutral point (N) and fault
resistance (Zf). This time, this circuit will be used to solve the current quantities seen during the
fault.
3.4.2.1 Current Quantities Seen at the Fault Location

It is impossible to place a sensor at the fault position. So the value calculated here is in
fact an unavailable quantity. It is used for explanation and as an intermediate variable for
calculating other quantities.
For the sequence system given, it is seen that sequence currents (I0, I1, I2) at the fault
position are equal to each other and with a value of

1 1
0 1 2
0 _ 3 0 _ 3
f f
V Va
I I I
X C Z X C Z
= =
+ +

(3. 15)
38

Clearly, these values are entirely limited by the distributed capacitance of the system and
fault resistance. A typical value for distributed capacitance is in the range of a few , and fault
impedance may vary from 0~10k, depending on the conditions of line to ground contact. These
bring down the fault sequence currents to several amperes, considering that supply voltage for a
distribution system is at 13.8kV, 4.16kV or below. This means that a single phase to ground fault
on an ungrounded system will not produce appreciable fault current. Instead, if compared to the
nominal values calculated in section 3.4, its magnitude is on the same level as the nominal
leakage current - Equation (3. 6). In addition, fault sequence currents are independent of the
fault locations (F1-F5).
F
3.4.2.2 Current Quantities Seen at the Sensor Location
Current sensor locations are indicated with blue dots in Figure 3. 5. Sequence quantities
are derived from individual sequence networks.

Zero sequence quantities (IS0, IR0, Id0):
In the zero sequence network, the right side sensor does not pass current, so 0 0 IR = ; the
current passing the left side sensor IS0, contributes to zero sequence fault current and its value
can be calculated according to the current distribution:

3
0 0
1 2 3
II
I II
C C
0 IS I
C C C C C
= =
+ + +
I

(3. 16)

This explains that the zero sequence current measured at the sensor location is the zero
sequence current supplied from the remaining un-faulted circuit.
Zero sequence differentials current (Id0) is the sum of these two currents:

0 0 0 0
0
II
I II
II
I II
C
Id IS IR I
C C
C
I
C C
= + = +
+
=
+
0

(3. 17)

39

Positive sequence quantities (IS1, IR1, Id1):

The positive sequence network gives equations (3. 18) and (3. 19):

1 1
1
1_ 1 1_ 1
V V
IR
a
Z load Z load

= =
(3. 18)

1
1 1 1
1_ 1// 1_ 2
1
1 1 1
1_ 1// 1_ 2
V
IS IR I
X C X C
V
IS I IR
X C X C
+ = +
= +

(3. 19)

Substituting (3. 9) in equation (3. 18),

1
1
1_ 1
Va
IR
Z load
=

(3. 20)
Substituting (3. 20) and { in equation (3. 19), 1 0 } I I =

1 1
1 0
1_ 1 1_ 1// 1_ 2
V V
IS I
Z load X C X C
= + +

(3. 21)


1 1
1 0
1_ 1 1_ // 1_ 2
Va Va
IS I
Z load X C X C
= + +

(3. 22)


f
1 1 2
1 0 0 3 2 ( 1 2)
1_ 1 1 2 3
1 1 2
= 0 0 1131 ( 1 2) 0
1_ 1 1 2 3
1
= 0 0 1.13 0
1_ 1
where, Z in k , , in F.
f
f
I
f I
I II
I II
Va C C
0 IS I I Z f C C I
Z load C C C
Va C C
I I Z C C
Z load C C C
C Va
I I Z C I
Z load C C
C C
I
+
= + + + +
+ +
+
+ + + +
+ +
+ + +
+

(3. 23)
40

For solid fault (Zf=0),

1
1= 0 0
1_ 1
I
I II
C Va
IS I I
Z load C C
+ +
+
;

(3. 24)

Positive sequence current seen at the sensor position contains load current and a multiple
of zero sequence fault current. Obviously, the load current is a dominant part.

Summing equations (3. 20), (3. 23), gives positive differential current (Id1):

1 1 1
0 0 1.13 0
I
f I
I II
Id IS IR
C
I I Z C
C C
= +
= + +
+
I

(3. 25)

It is seen that positive differential current does not contain load current. It is only a
function of zero sequence current.

Negative sequence quantities (IS2, IR2, Id2):
Most current in the negative sequence circuit will pass through the circuit containing
(Rs2+XTR2) since it is a low impedance path. Current in the left side sensor (IS2) is thus
approximately equal to the negative sequence fault current; current in the right side sensor (IR2)
is small enough to be neglected. A term Small is used to define its value, to avoid confusion
with the condition of open circuit or absolute zero. Equations (3. 26), (3. 27), (3. 28) give the
negative sequence currents.
2 2 0 IS I I = ;

(3. 26)
path of Rs2+XTR2
2
0
( 2 2)
2
2 _ 1 2 _ 1
Rs XTR I
V
IR I
Z load Z load
+
= << small

(3. 27)
41

0 0
2 2 2 Id IS IR I small I = + = +

(3. 28)

Phase Quantities (IdA-C):
Sequence to phase transformation, provides phase quantities:
2
2
1 1 1 0
1 1
1 2
IdA Id
IdB a a Id
IdC a a Id
( (
( (
=
( (
( (

(
(
(
(

(3. 29)

Substituting (3. 17), (3. 25), (3. 28)in equation (3. 29),
f
0 1 2
( 0) ( 0 0 1.13 0) 0
3 0 1.13 0
3 0 (if Z 0)
II I
f I
I II I II
f I
IdA Id Id Id
C C
I I I Z C I
C C C C
I Z C I
I
= + +
= + + +
+ +
= +
= =
I +

(3. 30)
2
2
2 2
2
0 1 2
( 0) ( 0 0 1.13 0) 0
0 0 0 0
1.13 0
II I
f I
I II I II
II I
I II I II
f I
IdB Id a Id a Id
C C
I a I I Z C I a I
C C C C
C C
I a I a I a I
C C C C
a Z C I
= + +
= + + + +
+ +
= + + +
+ +
+

Consider: { ,
2
1 0 } a a + + =

2 2
2 2
2 2
0 0 0 1.13 0
0 0 1.13 0
0 0 1.13 0
II I
f I
I II I II
I I
f I
I II I II
I I
f I
I II I II
C C
IdB I a I I a Z C I
C C C C
C C
a I I a Z C I
C C C C
C C
a I I a Z C I
C C C C
= + +
+ +
= +
+ +
= +
+ +

42

0 2
0
f
3 0 210 1.13 0
3 0 210 (if Z =0)
I
f I
I II
I
I II
C
I a Z C
C C
C
I
C C
= +
+
=
+
I

(3. 31)
2
2
2
0 1 2
( 0) ( 0 0 1.13 0) 0
0 0 0 0
1.13 0
0 0 1.13 0
3 0 150
II I
f I
I II I II
II I
I II I II
f I
I I
f I
I II I II
IdC Id a Id a Id
C C
I a I I Z C I a I
C C C C
C C
I a I a I a I
C C C C
a Z C I
C C
I a I a Z C I
C C C C
I
= + +
= + + + +
+ +
= + + +
+ +
+
= + +
+ +
=

f
1.13 0
3 0 150 ( if Z 0 )
I
f I
I II
I
I II
C
a Z C I
C C
C
I
C C
+
+
= =
+

(3. 32)

It is seen that differential currents on two un-faulted phases rise to 1.73 times normal
leakage current. Physically, this increase of differential currents is caused by the increase of
phase voltages on two un-faulted phases during phase A to ground fault. IdA can be seen as a
return path for phase differential currents from both cable I ( , IdB IdC ) and cable II
( ,
II II
IdB IdC ), i.e.,

(
II II
) IdA IdB IdC IdB IdC = + + +

(3. 33)

3.4.3 Phase-A-Ground Fault on Location II-V
This section analyzes the current patterns for external faults. There are four external fault
positions: F2, F3, F4, F5. Their effects on the current patterns are identified.

Fault Position II (F2)
43

The equivalent sequence network is shown in Figure 3. 6. The zero sequence network
provides,
1 2
0 0
1 2 3
I
I II
C C C
0 IS I
C C C C C
+
= =
+ + +
I

(3. 34)
0 0 IR = (3. 35)
1 2
0 0 0 0
1 2 3
I
I II
C C C
0 Id IS IR I I
C C C C C
+
= + = =
+ + +

(3. 36)
Zero sequence differential current now is produced by the internal circuit itself, which is
different from the previous internal fault case. For an internal fault, it was contributed by the
remaining healthy circuit.

Positive Sequence Quantities (IS1, IR1, Id1):
Current flowing through the right hand sensor does not change when the fault position is
moved from F1 to F2.
1
1
1_ 1
Va
IR
Z load

But the left sensor sees a different value,

1
1 1
1_ 1// 1_ 2
V
IS IR
X C X C
+ =

Comparing with equation (3. 23), gives
f
1
1 0 1.13 0
1_ 1
1
0 ( if Z 0 )
1_ 1
I
f I
I II
I
I II
C Va
IS I
Z load C C
C Va
I
Z load C C
Z C I = + +
+
= + =
+

(3. 37)

44

N
Rs1
Va1
X1_C1 X1_C2
XTR1
Z1_Load1
X1_C3
Z1_Load2
N
Rs2
X2_C1 X2_C2
XTR2
Z2_Load1
X2_C3
Z2_Load2
N
Rs0
X0_C1 X0_C2
XTR0
Z0_Load1
X0_C3
Z0_Load2
+
_
V1
+
_
V2
+
_
V0
S1 R1
I1
F2
S2 R2
I2
F2
S0 R0
3Zf I0
F2

Figure 3. 6 Sequence Networks and Interconnections for a Phase-a-to-ground Fault at F2
45

The positive differential current becomes,

f
1 1 1
1 1
0 1.13 0 ( )
1_ 1 1_ 1
0 1.13 0
0 (if Z 0 )
I
f I
I II
I
f I
I II
I
I II
Id IS IR
C Va Va
I Z C I
Z load C C Z load
C
I Z C I
C C
C
I
C C
= +
= + + +
+
= +
+
= =
+

Both sensors still see the load current. The fault position does not change this property.
But compared with the internal fault, the positive differential current is reduced under the
external fault. For an internal fault, it includes an additional term, i.e, the sequence fault current
flowing into the ground.

Negative Sequence Quantities (IS2, IR2, Id2):
Two sensors are now at the right side of the circuit so they will see negligible currents.
2
2
2 2 2
IS small
IR small
Id IS IR sma
=
=
= + = ll

From equation (3. 29),
f
0 1 2
( 0) ( 0 1.13 0)
1.13 0
(if Z 0)
I I
f I
I II I II
f I
IdA Id Id Id
C C
I I Z C I s
C C C C
Z C I small
small
= + +
= + + +
+ +
= +
= =
mall
2

2
0 1 IdB Id a Id a Id = + +

(3. 38)
46

2
( 0) ( 0 1.13 0)
I I
f I
I II I II
C C
I a I Z C I a
C C C C
= + + +
+ +
small

0 2
0
f
3 0 210 1.13 0
3 0 210 (if Z 0 )
I
f I
I II
I
I II
C
I a Z C
C C
C
I
C C
= +
+
= =
+
I

(3.39)

2
2
0 2
0
f
0 1 2
( 0) ( 0 1.13 0)
3 0 150 1.13 0
3 0 150 (if Z 0 )
I I
f I
I II I II
I
f I
I II
I
I II
IdC Id a Id a Id
C C
I a I Z C I a
C C C C
C
I a Z C I
C C
C
I
C C
= + +
= + + +
+ +
= +
+
= =
+
small

(3. 40)

Differential currents for phase B and phase C do not change compared with the internal
fault case. But there is notable decrease in phase A differential current. For an external fault, this
value is close to zero for a solid fault.

Cleary, the external fault at location II (F2) displays a different current pattern from an
internal fault. To investigate whether these changes are consistent for external faults at other
positions, we continue to derive and verify these characteristic patterns.

Fault Position III (F3)
The equivalent sequence network is shown in Figure 3. 7. It provides equations:
3
0 0 0
1 2 3
0 0
0 0 0 0 0
II
I II
II I
I II I II
C C
IS I I
C C C C C
IR I
C C
0 Id IS IR I I I
C C C C
= =
+ + +
=
= + = =
+ +

(3. 41)

47

Positive Sequence Quantities (IS1, IR1, Id1):
1 1
1 1
1_ 1 1_ 1
V Va
0 IR I
R load R load

= I

f
1
1 1
1_ 1// 1_ 2
1 1
1 0
1_ 1 1_ 1// 1_ 2
Refering to Equation (3. 25), gives
1
1 0 0 1.13
1_ 1
1
0 0 (if Z =0 )
1_ 1
I
f I
I II
I
I II
V
IS IR
X C X C
V V
IS I
R load X C X C
C V
0 IS I I Z
R load C C
C V
I I
R load C C
+ =
= + +
= + + +
+
= + +
+
C I

1 1 1
I
I II
C
0 Id IS IR I
C C
= + =
+

(3. 42)

Negative Sequence Quantities (IS2, IR2, Id2):

2 0
2 0
2
IS I
IR I
Id sma

= ll

(3. 43)

Compared with the current patterns in F2, it is seen that the sequence differential currents
displays the same patterns for a fault either at F2 or F3, though sensors (S, R) may see different
currents in each case.

From equation (3. 29),
0 1 2
( 0) ( 0)

I I
I II I II
IdA Id Id Id
C C
I I sma
C C C C
small
= + +
= + +
+ +
=
ll

(3. 44)

48

N
Rs1
Va1
X1_C1 X1_C2
XTR1
Z1_Load1
X1_C3
Z1_Load2
N
Rs2
X2_C1 X2_C2
XTR2
Z2_Load1
X2_C3
Z2_Load2
N
Rs0
X0_C1 X0_C2
XTR0
Z0_Load1
X0_C3
Z0_Load2
+
_
V1
+
_
V2
+
_
V0
S1 R1
S2 R2
I2
F3
S0 R0
3Zf I0
F3
I1
F3

Figure 3. 7 Sequence Networks and Interconnections for a Phase-a-to-ground Fault at F3
49

2
2
0 1 2
( 0) ( 0)
3 0 210
I I
I II I II
I
I II
IdB Id a Id a Id
C C
I a I a
C C C C
C
I
C C
= + +
= + +
+ +
=
+
small

(3. 45)

2
2
0 1 2
( 0) ( 0)
3 0 150
I I
I II I II
I
I II
IdC Id a Id a Id
C C
I a I a
C C C C
C
I
C C
= + +
= + +
+ +
=
+
small

(3. 46)

Comparing with equations (3. 38), (3.39) and (3. 40), it is seen that phase differential
currents keep the same patterns for external faults at F2 or F3.

Fault Position III (F4-5)
Figure 3. 8 gives the equivalent sequence network for this case. But detailed derivations
are omitted here. Results for this case, together with previous formulae, are summarized in Table
3. 2.
Table 3. 2(a) are the sequence fault currents seen at the sensor positions; (b) are the
results for differential currents and (c) are the voltage patterns during the faults.
Formulae show that the voltage patterns cannot identify fault positions; sequence
currents alone are not good at it either. Positive sequence currents (IS1 or IR1) are mainly the
load currents and did not vary with the fault positions. Negative and Zero sequence currents
(IS2, IR2, IS0 and IR0) are not good at it because their quantities are not consistent for external
faults. For instance, IS0 sees an amount of current ( 0
I
I II
C
I
C C +
) when a fault is at F2, but it
will see a different value ( 0
II
I II
C
I
C C +
) as a fault is at F3. And, in fact, 0
II
I II
C
I
C C +
is the value

50

N
Rs1
Va1
X1_C1 X1_C2
XTR1
Z1_Load1 X1_C3
Z1_Load2
N
Rs2
X2_C1 X2_C2
XTR2
Z2_Load1 X2_C3
Z2_Load2
N
Rs0
X0_C1 X0_C2
XTR0
Z0_Load1 X0_C3
Z0_Load2
+
_
V1
+
_
V2
+
_
V0
S1 R1
S2 R2
I2
F5
S0 R0
3Zf I0
I1
F5
F5

F4
F4
F4

Figure 3. 8 Sequence Networks and Interconnections for a Phase-A-to-ground Fault at F4/5
51

Table 3. 2 Characteristic Equations for Phase-A-to-Ground Fault at Selected Positions
(a) Sequence Currents
Fault Location IS0 IR0 IS1 IR1 IS2 IR2
F1
0
II
I II
C
I
C C +

0 1
0 0
1_ 1
I
I II
C Va
I I
Z load C C
+ +
+

1 Va
1_ 1 Z load

0 I Small
F2
0
I
I II
C
I
C C
+

0 1
0
1_ 1
I
I II
C Va
I
Z load C C
+
+

1
1_ 1
Va
Z load

Small Small
F3
0
II
I II
C
I
C C +

0 I 1
0 0
1_ 1
I
I II
C V
I I
R load C C
+ +
+

1
0
1_ 1
Va
I
R load

0 I 0 I
F4/5
0
I
I II
C
I
C C
+

0 1
0
1_ 1
I
I II
C Va
I
Z load C C
+
+

1
1_ 1
Va
Z load

Small Small

(b) Differential Currents
Fault
Location
Id0 Id1 Id2 IdA IdB IdC
F1
0
II
I II
C
I
C C +
0 0
I
I II
C
I I
C C
+
+
0 I 3 0 I
0
3 0 210
I
I II
C
I
C C

+
0
3 0 150
I
I II
C
I
C C

+
F2
0
I
I II
C
I
C C
+
0
I
I II
C
I
C C

+

Small Small
0
3 0 210
I
I II
C
I
C C

+
0
3 0 150
I
I II
C
I
C C

+
F3
0
I
I II
C
I
C C
+
0
I
I II
C
I
C C

+

Small Small
0
3 0 210
I
I II
C
I
C C

+
0
3 0 150
I
I II
C
I
C C

+
F4/5
0
I
I II
C
I
C C
+
0
I
I II
C
I
C C

+

Small Small
0
3 0 210
I
I II
C
I
C C

+
0
3 0 150
I
I II
C
I
C C

+

(c) Voltages
Fault Location V0 V1 V2 VA VB VC
F1-F5 3 0 1 I Zf Va 1 Va 0 3 0 I Zf
3 0 1 210 I Zf Va +

3 3 0 1 150 I Zf Va +

3
52

seen by IS0 under an internal fault. Quantities IS2, IR0, IR2 also experienced the same
problem. Therefore, they cannot be used for fault detection.
On the other hand, differential currents (sequence or phase) are able to distinguish
internal from external faults. As a fault moves from an internal position to an external position,
zero sequence differential current (Id0) changes direction; positive and negative sequence
differential current (Id1 and Id2) change magnitude; phase differential current (IdA) for the
faulted phase changes magnitude. They provide information for detecting and identifying a
fault. These currents require an adequate measurement system.
3.4.4 Differential Current Characteristics Modified for Phase B or C-to
Ground Fault
For a phase B or C-to-ground fault, the voltage source in the positive network needs to
be replaced with Vb1 or Vc1. In addition, it should be kept in mind that sequence quantities
derived from the phase B/C sequence network are with reference to phase B or phase C, i.e.
0, 1, 2, 0, 1, 2 b b b c c c
I I I I I I . They have to be transferred back to the quantities with reference to phase A.
Phase A has been chosen as the reference phase for sequence quantities. Transformation
equations are:
0 0 0
2
1 1
2
2 2
a b c
a b
a b
I I I
1
2
c
c
I a I a I
I a I a I
= =
= =
= =

(3. 47)
Consider these two conditions, the modified differential current characteristic equations
for phases B or C ground fault are given in Table 3. 3, where
1
0
0 _ 3
f
Va
I
X C Z
=
+
referred to
phase A.
3.5 Characteristics Analysis for Phase to Phase Types of Faults
Distributed capacitance currents do not significantly affect the fault currents under phase-
to-phase type of faults. The circuit will normally experience large fault currents under such
faults and the faulted section should be isolated rapidly. The exception case is for a high

53

Table 3. 3 Characteristic Equations for Phase-B/C-to-Ground Fault at Selected Positions

(a) Differential Currents Pattern for Phase B-to-Ground Fault
Fault
Location
F1
2
0
II
I II
C
a I
C C

+
0 0
I
I II
C
I I
C C
+
+
0 a I
0
3 0 30
I
I II
C
I
C C

+
2
3 0 a I 0
3 0 90
I
I II
C
I
C C

+

F2
2
0
I
I II
C
a I
C C

+
0
I
I II
C
I
C C

+

Small
0
3 0 30
I
I II
C
I
C C

+
Small
0
3 0 90
I
I II
C
I
C C

+

F3
2
0
I
I II
C
a I
C C

+
0
I
I II
C
I
C C

+

Small
0
3 0 30
I
I II
C
I
C C

+
Small
0
3 0 90
I
I II
C
I
C C

+

F4/5
2
0
I
I II
C
a I
C C

+
0
I
I II
C
I
C C

+

Small
0
3 0 30
I
I II
C
I
C C

+
Small
0
3 0 90
I
I II
C
I
C C

+

(b) Differential Currents Pattern for Phase C-to-Ground Fault
Fault
Location
F1
0
II
I II
C
a I
C C

+
0 0
I
I II
C
I I
C C
+
+
2
0 a I 0
3 0 30
I
I II
C
I
C C

+
0
3 0 90
I
I II
C
I
C C

+
3 0 a I
F2
0
I
I II
C
a I
C C

+
0
I
I II
C
I
C C

+

Small
0
3 0 30
I
I II
C
I
C C

+
0
3 0 90
I
I II
C
I
C C

+
Small
F3
0
I
I II
C
a I
C C

+
0
I
I II
C
I
C C

+

Small
0
3 0 30
I
I II
C
I
C C

+
0
3 0 90
I
I II
C
I
C C

+
Small
F4/5
0
I
I II
C
a I
C C

+
0
I
I II
C
I
C C

+

Small
0
3 0 30
I
I II
C
I
C C

+
0
3 0 90
I
I II
C
I
C C

+
Small
54

impedance fault. Fault resistance may reduce the fault current to an insignificant level (close to
the load current) and creates a difficulty in fault detection. Analysis will indicate the influence
of fault resistance and identify a differential current pattern for sensitive fault detection. Analysis
will also look at whether the pattern developed during a phase phase type fault will overlap with
the ground fault pattern.
3.5.1 Differential Current Characteristics for Phase-Phase Faults
3.5.1.1 Current Quantities Seen at the Fault Location
Figure 3. 8(a) gives the sequence network for phases B-C fault at location F1. For phase-
to-phase fault, the positive sequence network is in parallel with the negative sequence network
and fault resistance. To calculate the sequence fault currents at the fault position, the circuit is
further reduced at the fault position. The simplification process is similar to section 3.5.1. The
reduced circuit is given in Figure 3. 8(b). The sequence currents I1 and I2 can be derived as:

1
1 2
1_ ( 2 2 )
( 1 1)
1_ 2 2
Va
I I
Z load Rs XTR Zf
Rs XTR
Z load Rs XTR Zf
= =
+ +
+ +
+ + +

(3. 48)

It was observed that if the circuit of Figure 3. 8 (a) is reduced at the fault positions F2-F5,
there will still be the same reduced circuit and the same sequence fault currents. This result is
caused by the short cable effect.
3.5.1.2 Differential Current Quantities for Faults at F1
The equivalent sequence network in Figure 3. 8 (a), gives equations:

1
1 1 1 1
1_ 1// 1_ 2
2
2 2 2 2
1_ 1// 1_ 2
0 0
V
Id IS IR I
X C X C
V
Id IS IR I
X C X C
Id
= + = +
= + = +
=

(3. 49)

55

N
Rs1
Va1
X1_C1 X1_C2
XTR1
S1 R1
Z1_Load1
X1_C3 Z1_Load2 Zf
N
Rs2
X2_C1 X2_C2
XTR2
S2 R2
Z2_Load1
X2_C3
Z2_Load2
+
_
V1
+
_
V2
I1
I2
1/2Zf
1/2Zf

F1
F1

(a)

N
Rs1
Va1
XTR1
N
Rs2
XTR2
+
_
V1
+
_
I1
I2
1/2Zf
1/2Zf
Z1_Load=
Z1_Load1//Z1_Load2
V2

(b)
Figure 3. 9 Sequence Networks and Interconnections of Phase B-C Fault
(a) Equivalent Sequence Networks
(b) Reduced Circuit of (a)

56

Substituting I1, I2, V1 and V2 into equation (3. 49) will give complicated formulae,
involving multiplication and division of variables, similar to the complexity of (3. 48). It may be
hard for us to directly identify the relationship between differential currents and fault resistance.
To simplify the process, Zf is therefore classified into three levels:
0, 1_ , and 1_ .
f f f
Z Z Z load Z Z load = >>

For the case , 0
f
Z =

Equation (3. 48) becomes,

1
1 2
( 1 1) 1_ //( 2 2)
Va
I I
Rs XTR Z load Rs XTR
= =
+ + +

Considering Z1_load >> (Rs2+XTR2) and Rs1=Rs2; XTR1=XTR2, the above equation
becomes

1
1 2
2*( 1 1)
Va
I I
Rs XTR
= =
+

(3. 50)

Substituting (3. 50) into (3. 49), then
1 1/ 2 1
1
2*( 1 1) 1_ 1// 1_ 2 2*( 1 1)
1 1/ 2
2
2*( 1 1) 1_ 1// 1_ 2 2*( 1 1)
0 0
Va Va Va
Id
Rs XTR X C X C Rs XTR
Va Va Va
Id
1
Rs XTR X C X C Rs XTR
Id
= +
+ +
= +
+ +
=

(3. 51)

From (3. 51), phase differential currents can be derived as:

57

2
2 0
2
2 0
1
0 1 2
1_ 1// 1_ 2
0 1 2
1 1
( ) 3 90
2*( 1 1) 2*( 1 1)
0 1 2
1 1
( ) 3 90
2*( 1 1) 2*( 1 1)
Va
IdA Id Id Id
X C X C
IdB Id a Id a Id
Va Va
a a
Rs XTR Rs XTR
IdC Id a Id a Id
Va Va
a a
Rs XTR Rs XTR
= + +
= + +
= =
+ +
= + +
= =
+ +

(3. 52)

For the case 1_
f
Z Z load ,

Equation (3. 48) becomes,

1
1 2
Va
I I
Zf
=
(3. 53)

Substituting (3. 53) into (3. 49) gives
1 1
1
1_ 1// 1_ 2
1 0
2
1_ 1// 1_ 2
0 0
Va Va Va
Id
Zf X C X C Zf
Va Va
Id
1
1
Zf X C X C Zf
Id
= +
+
=

(3. 54)

From (3. 54), phase differential currents can be derived as:
2 0
2 0
1
0 1 2
1_ 1// 1_ 2
1
0 1 2 3 90
1
0 1 2 3 90
Va
IdA Id Id Id
X C X C
Va
IdB Id a Id a Id
Zf
Va
IdC Id a Id a Id
Zf
= + +
= + + =
= + + =

(3. 55)

Equations (3. 54) and (3. 55) show that the differential quantities can identify the fault,
even when fault resistance is increased and comparable to the load level.
58

For the case 1_ 1
f
Z Z load >> ,

As the Zf further increases, the capacitance effect needs to be taken into consideration.
Therefore, equations (3. 54) and (3. 55) need to be modified to include the terms involving
capacitance.
3.5.1.3 Differential Current Quantities for Faults at F2-F5

The analysis is carried out for fault locations at F2-F5. Results are summarized in Table 3. 4.
Equation (3. 47) can be used for modifying equations for calculating the quantities under AB or
AC type of faults.
Table 3. 4(a) are differential current equations for phase B-C fault with zero fault
resistance; (b) are equations when fault resistance is in the range of load impedance; (c) are when
fault resistance is larger than load impedance.
For a solid fault case (a), an internal fault produces large magnitude of phase differential
currents on two-faulted phases, i.e. IdB and IdC. The magnitude is typically 10-100 times
nominal load current, determined by source impedance and transformer impedance. External
faults only produced a portion of leakage currents. So in this case, the magnitudes of phase
differential currents are good enough to detect a fault.
For a resistive internal fault (b)(c), the magnitude of phase differential currents (IdB and
IdC) are determined by the fault resistance; and the higher fault impedance, the lower IdB and
IdC. When fault impedance reduces the magnitude of IdB and IdC below the pickup settings
(10-30% of load current), the phase differential relay may not be able to detect a fault. But there
is a good feature of sequence differential currents to distinguish such faults. An internal phase B-
C fault produces an equal amount and opposite direction of positive and negative differential
currents (Id1 and Id2). This pattern was well-known before at the fault position but now is
preserved by the sequence differential currents seen at the sensor position. External faults create
leakage current on Id1 and negligible current on Id2. This indicates that the sequence differential
current pattern can be used to detect an internal high impedance fault event. More importantly,
59

Table 3. 4 Differential Currents For Phase B-C Fault

(a) Differential Currents Pattern for Phase B-C Fault (Zf=0)
Fault
Location
F1 0 1
2*( 1 1)
Va
Rs XTR +

1
2*( 1 1)
Va
Rs XTR
+
1
1_
Va
X C

0
1
3 90
2*( 1 1)
Va
Rs XTR

+
0
1
3 90
2*( 1 1)
Va
Rs XTR

+
F2-F5 0 1
2* 1_
Va
X C

1
2* 1_ 1
Va
X C

1
1_
Va
X C

1
2* 1_
Va
X C

1
2* 1_
Va
X C

X1_C=X1_C1//X1_C2;

(b) Differential Currents Pattern for Phase B-C Fault (Zf ~Z1_load)
Fault
Location
F1 0 1 Va
Zf

1 Va
Zf

1
1_
Va
X C

0
1
3 9
Va
Zf
0
0
1
3 90
Va
Zf

F2-F5 0 1
1_
Va
X C

small 1
1_
Va
X C

0
1
120
1_
Va
X C

0
1
120
1_
Va
X C

(c) Differential Currents Pattern for Phase B-C Fault (Zf>>Z1_load)
Fault
Location
F1 0 1 1
1_
Va Va
Zf X
+
C

1 Va
Zf

1
1_
Va
X C

0
1
3 9
Va
Zf
0 +
0
1
120
1_
Va
X C

0
1
3 90
Va
Zf
+
0
1
120
1_
Va
X C

F2-F5 0 1
1_
Va
X C

small 1
1_
Va
X C

0
1
120
1_
Va
X C

0
1
120
1_
Va
X C

60

this pattern does not overlap with a single phase to ground fault, and can therefore be
distinguished from it.
3.5.2 Differential Current Characteristics for Phase-Phase-Ground Faults
The equivalent sequence network for phase B-C-G fault is given in Figure 3. 10.
A zero sequence network is included in the circuit this time because a fault of this type
involves a ground path.
But the zero sequence network has less impact on the overall current distribution due to
its high capacitive reactance. The positive sequence current (I1) will flow out of the positive
sequence network, then mainly passes through the negative sequence network, and finally turns
back to the neutral point. As the zero sequence path is neglected, the phase-phase-ground
equivalent circuit will be similar to that of the phase-phase circuit, except that now there is 2Zf in
series. So, the formula in Table 3. 4 can still be used to calculate the quantities for this case and
the only change is replacing Zf with 2Zf in the equations.
But the zero sequence path will produce a zero sequence leakage current on its own
circuit. This should be taken into consideration during the derivation.
In general, detection methods for this case are the same as those for the phase-phase type.

3.5.3 Differential Current Characteristics for Three Phase Fault
Under a three-phase fault, the system still operates in balance. Hence, a positive network
(Figure 3. 11) is enough to represent a fault condition. For an internal fault (F1),
1
1 1 1
1 1
Va
Id IS IR
Rs XTR Zf
= + =
+ +
. For external faults (F2-F5), most of the current passes
through the fault location and the differential current will be approximately
1
1 1
1 1
I I
Vf Zf
Id Va
XC Rs XTR Zf XC
=
+ +
.
3.6 Verification of Characteristic Formulae
The circuit Figure 3. 1 discussed in section 3.3, is simulated in PSCAD/EMTDC.
Waveforms and data from simulation scenarios are analyzed and compared with the
61

N
Rs1
Va1
X1_C1 X1_C2
XTR1
S1 R1
Z1_Load1 X1_C3 Z1_Load2 Zf
N
Rs2
X2_C1 X2_C2
XTR2
S2 R2
Z2_Load1
X2_C3
Z2_Load2
+
_
V1
+
_
V2
I1
I2
N
X0_C1 X0_C2
S0 R0
X0_C3
+
_
V0
I0
Zf
Zf
Zf

F1
F1 F1
F5 F4 F2
F5 F4 F2 F4/5 F2
F3
F3 F3
Figure 3. 10 Sequence Network and Its Interconnections for Phase B-C-Ground Fault
62

N
Rs1
Va1
X1_C1 X1_C2
XTR1
S1 R1
Z1_Load1
X1_C3 Z1_Load2 Zf

F5 F4
F3
F2
F1
Figure 3. 11 Sequence Network for Three-Phase Fault

63

characteristic formulae derived in previous sections. This will verify if the characteristic
formulae correctly summarize the physical phenomena and if the estimations in the formulae are
valid.
Parameters used in the simulation case are provided in Table 3. 5.
Table 3. 5 Simulation Parameters
VL-L 13.8kV
Rs 0.1ohm
Transformer 13.8kV /13.8kV, Y/; 100MVA, X
Leakage
=0.01p.u.
C1 0.05uf
C2 0.01uf
C3 0.03uf
Load1 100ohm/ph-ph
Load2 200ohm/ ph-ph

3.6.1 Nominal Condition
The nominal L-L voltage (RMS) for both primary and secondary sides is 13.8kV. The
phase to ground voltage on the secondary side circuit is formed by the distributed capacitances
and its value is equal to the L-L voltage divided by 3 , i.e. 13.8 kV. The peak
value is
/ 3 7.967 =
7.967 kV. Figure 3. 12 gives three phase nominal secondary voltages. Ea,
Eb, Ec are the voltages measured at the Bus1 position (Figure 3. 1). The transformer secondary
side and the ungrounded circuits are interconnected at the Bus1 position.
2 11.27 =
Using equations (3. 7) and (3. 8), the nominal current seen by the sensors S and R is
estimated as:
7.967 1000
239
1
100
3
(A). The peak value is around 239 2 338 = (A). Figure

64

3.13 gives sensor currents for nominal conditions. They (Sa, Sb, Sc, Ra, Rb and Rc) are showing
the same amount of magnitude as estimated.
Equation (3. 6) gives the nominal value for the differential current, i.e.
6
7.967 1000
0.18
1
2 (0.05 0.01) 10 f

=
+
(A). The peak value is 0.26A. Figure 3. 14 gives three
phase nominal differential currents (IdA, IdB, and IdC).

0.15 0.16 0.17 0.18 0.19 0.2 0.21 0.22 0.23 0.24 0.25
-15
-10
-5
0
5
10
15
Ea
Eb
Ec
Time (s)
V
o
l
t
a
g
e

(
k
V
)

Figure 3. 12 Nominal Line to Ground Voltages
0.15 0.16 0.17 0.18 0.19 0.2 0.21 0.22 0.23 0.24 0.25
-400
-200
0
200
400
Sa
Sb
Sc
0.15 0.16 0.17 0.18 0.19 0.2 0.21 0.22 0.23 0.24 0.25
-400
-200
0
200
400
Ra
Rb
Rc
Time (s)
C
u
r
r
e
n
t

(
A
)

Figure 3. 13 Nominal Currents Measured By Sensors S and R
65

0.15 0.16 0.17 0.18 0.19 0.2 0.21 0.22 0.23 0.24 0.25
-0.4
-0.2
0
0.2
0.4
IdA
IdB
IdC
Time (s)
C
u
r
r
e
n
t

(
A
)

Figure 3. 14 Nominal Differential Currents
3.6.2 Verification of Voltage Patterns for a single phase to ground fault
Equations (3. 12), (3. 13) and (3. 14) express that for a single phase to ground solid fault
on an ungrounded circuit, the phase voltage of the faulted phase drops to zero and phase voltages
for the two un-faulted phases rise up to L-L voltage. This pattern is independent of fault
positions.
Figure 3. 15 gives the simulated results. The simulated event is a phase A-ground solid
fault. It was applied at 0.2s and at five positions (F1-F5). The overall simulation running period
is 0.3s. Figure 3. 15(a) are the results for the fault applied at F1 position and Figure 3. 15 (b) are
the results for the fault at F5. The time interval for the plots are from 0.15s 0.25s, including the
pre-fault data and the fault data.
The first observation on the results is that two graphs display the same results. This is
also true for results at F2-F4, which are not represented here. This verified the fact that the
voltage pattern is independent of fault position.
There is a short period of transient when the fault is applied. This is a normal
phenomenon when switching off/on a path in a R-L-C circuit. Voltages soon reach their steady
states, within less than 1/4 cycle. The pre-fault peak voltage for all three phases is 11.2kV; the
peak value for phase B and phase C during the fault is 19.4kV (~13.8*sqrt (2)), and for faulted
phase -- phase A, its voltage drops to zero during the fault. The fault event also causes a change
66

0.15 0.16 0.17 0.18 0.19 0.2 0.21 0.22 0.23 0.24 0.25
-20
-10
0
10
20
Ea
Eb
Ec
Data: AGF1, Solid
19.4
11.2
2.8ms
5.5ms
Time (s)
V
o
l
t
a
g
e

(
k
V
)

(a)
0.15 0.16 0.17 0.18 0.19 0.2 0.21 0.22 0.23 0.24 0.25
-20
-10
0
10
20
Ea
Eb
Ec
Data: AGF5, Solid
Time (s)
V
o
l
t
a
g
e

(
k
V
)

(b)
Figure 3. 15 Voltages During a Phase A Ground Solid Fault
(a) Zf=0, Fault position =F1
(b) Zf=0, Fault position =F5
of angle displacement between un-faulted phases, from 120 (~5.5ms) to 60 (~2.7ms). These
magnitude and phase changes can be better seen on a voltage phasor diagram given in Figure 3.
16. During the fault, phasors Eb and Ec are taking the positions that previously their line phasors
were holding, i.e. Eb
_fault
=(Eb-Ea)
pre_fault
, Ec
_fault
=(Ec-Ea)
pre_fault
. So, the line voltage triangle has
not been changed by the fault.
0 0
All these observations on the simulated results agree with the characteristics revealed by
the formulae (3. 12), (3. 13) and (3. 14).
67

The voltage phasor diagram also displays a zero sequence voltage quantity (V0). It is
seen from the graph that the magnitude of zero sequence voltage is equal to the pre-fault phase
voltage and its direction is opposite to the direction of pre-fault voltage of the faulted phase (Ea).
This result agrees with Equation (3. 11).
Figure 3. 17-Figure 3. 20 are the results for a phase B-ground fault and a phase C-ground
fault. They displayed the similar pattern. Therefore, formulae (3. 12), (3. 13) and (3. 14) derived
from a phase A-ground fault case, can be modified to calculate the voltage quantities for faults
occurring on the other two phases.

-5 0 5
-5
0
5
Ea Eb
Ec
Data: Nominal
VRe (kV)
V
I
m

(
k
V
)

-15 -10 -5 0 5
-5
0
5
10
15
Eb
Ec
V0
Data: AGF1, Solid
VRe (kV)
V
I
m

(
k
V
)

(a) (b)
Figure 3. 16 Voltage Phasor Diagram (RMS)
(a) Before the Fault
(b) For a Phase A-Ground Solid Fault
0.15 0.16 0.17 0.18 0.19 0.2 0.21 0.22 0.23 0.24 0.25
-20
-10
0
10
20
Ea
Eb
Ec
Data: BGF1,Solid
Time (s)
V
o
l
t
a
g
e

(
k
V
)

Figure 3. 17 Voltages for Phase B-Ground Fault
68

-5 0 5 10 15
-5
0
5
10
15
Ea
Ec
V0
Data: BGF1, Solid
VRe (kV)
V
I
m

(
k
V
)

-5 0 5
-5
0
5
Ea Eb
Ec
Data: Nominal
VRe (kV)
V
I
m

(
k
V
)

(a) (b)
(b) For a Phase B-Ground Solid Fault
0.15 0.16 0.17 0.18 0.19 0.2 0.21 0.22 0.23 0.24 0.25
-20
-10
0
10
20
Ea
Eb
Ec
Data: CGF1, Solid
Time (s)
V
o
l
t
a
g
e

(
k
V
)

Figure 3. 19 Voltages for Phase C-Ground Fault

69

-5 0 5
-5
0
5
Ea Eb
Ec
Data: Nominal
VRe (kV)
V
I
m

(
k
V
)

-5 0 5
-10
-5
0
Ea
V0
Eb
Data: CGF1, Solid
VRe (kV)
V
I
m

(
k
V
)

(a) (b)
(b) For a Phase C-Ground Solid Fault
-15 -10 -5 0 5
-5
0
5
10
15
Ea
Eb
Ec
V0
VRe (kV)
V
I
m

(
k
V
)

Data: AGF1, Zf =5000
-15 -10 -5 0 5
-5
0
5
10
15
Eb
Ec
V0
Data: AGF1, Solid
VRe (kV)
V
I
m

(
k
V
)

(b) (c)
Figure 3. 21 Voltage Phasor Diagram for High Impedance
Phase A- Ground Fault at F1
(a) Zf=0, Fault position =F1
(b) Zf=5000, Fault position = F1

Figure 3. 21 show the influence of the fault resistance. Fault resistance increases the
voltage of faulted phase (Ea) and reduces the zero sequence voltage (V0). If zero sequence
voltage is used as a ground fault detector for ungrounded systems, this reduction in the
magnitude will decrease the sensitivity in fault detection. This is one of the limitations for the
voltage based detection method. Another limitation is that it has no ability to reveal the fault
position, which has been demonstrated in the previous results. The relationship between fault
resistance and zero sequence voltage can be derived from equations (3. 11) and (3. 15), i.e.
70

1
0 1 (1
0 _
1
3
V Va
X C
Zf
= )
+

(3. 56)

3.6.3 Verification of Current Patterns for a single phase to ground fault
Table 3. 2 and Table 3. 3 summarize the characteristic equations for a phase to ground
fault. This section provides the simulation results for verification.
3.6.3.1 Phase Differential Currents In Time Domain

0.15 0.16 0.17 0.18 0.19 0.2 0.21 0.22 0.23 0.24 0.25
-2
-1
0
0.5
1
1.5
2
IdA
IdB
IdC
Data: AGF1, Solid
0.459
1.16
0.425
Time (s)
C
u
r
r
e
n
t

(
A
)

(a)
0.15 0.16 0.17 0.18 0.19 0.2 0.21 0.22 0.23 0.24 0.25
-1
-0.6
-0.4
0
0.4
0.6
1
IdA
IdB
IdC
Data: AGF5, Solid
0.459
0.425
Small
Time (s)
C
u
r
r
e
n
t

(
A
)

(b)
Figure 3. 22 Phase Differential Currents for a Phase A Ground Solid Fault
(a) Zf=0, Fault Position = F1; (b) Zf=0, Fault Position= F2-F5
71

Figure 3. 22(a) are the simulated results for an AG fault at F1. Figure 3. 22(b) are the
results for an AG fault at F5. The fault was applied at 0.2s. F1 is an internal fault and F5 is an
external fault. Diagrams show three-phase differential currents during the time interval between
0.15-0.25s, including the pre-fault data and the fault data.
It can be seen from the diagrams that an internal fault (F1) caused an increase in all three
phase differential currents (IdA, IdB and IdC), among which differential current of the faulted
phase (IdA) has the largest magnitude; on the other hand, an external fault (F5) only increased
IdB and IdC but reduced the magnitude of IdA. The magnitude of IdB or IdC during an internal
fault is the same as it is for an external fault. These observations agree with the characteristic
equations derived.
Equations (3. 30),

(3. 31), and (3. 32) provide the estimations for the magnitudes of differential currents
during an internal fault. They yield,

1
| | 3 0 3
0 _
1
3 3 2 ( )
1
2 ( )
1.15 (A)
peak
peak peak
peak
I II pea
I II
Va
IdA I
X C
Va
f C C Va
f C C
= =
= = +
+
=
1
k

6
| | | | 3 0 3 0
9
1 2
| | ( )
3 3
0.44 (A)
I
peak peak peak peak
I II
peak
C
IdB IdC I I
C C
IdA
= = =
+
=
=

Equations (3. 38), (3.39), and (3. 40) provide the estimations for differential currents for
an external fault. According to that, get:

72

| |
| | | | 0.44 (A)
peak
peak peak
IdA small
IdB IdC
=
= =

The simulation results in Figure 3. 22 are close to these estimations.

Figure 3. 23 and Figure 3. 24 are the results for BG and CG fault. They displayed a
similar pattern as Figure 3. 22.
0.15 0.16 0.17 0.18 0.19 0.2 0.21 0.22 0.23 0.24 0.25
-2
-1
0
1
2
IdA
IdB
IdC
Data: BGF1, Solid
Time (s)
C
u
r
r
e
n
t

(
A
)

(a)
0.15 0.16 0.17 0.18 0.19 0.2 0.21 0.22 0.23 0.24 0.25
-2
-1
0
0.5
1
1.5
2
IdA
IdB
IdC
Data: AGF5, Solid
0.459
0.425
Small
Time (s)
C
u
r
r
e
n
t

(
A
)

(b)
Figure 3. 23 Phase Differential Currents for a Phase B Ground Solid Fault
(a) Zf=0, Fault position =F1; (b) Zf=0, Fault position =F2-F5

73

0.15 0.16 0.17 0.18 0.19 0.2 0.21 0.22 0.23 0.24 0.25
-2
-1
0
1
2
IdA
IdB
IdC
Data: CGF1, Solid
Time (s)
C
u
r
r
e
n
t

(
A
)

(a)
0.15 0.16 0.17 0.18 0.19 0.2 0.21 0.22 0.23 0.24 0.25
-1
-0.5
0
0.5
1
IdA
IdB
IdC
Data: CGF5, Solid
Time (s)
C
u
r
r
e
n
t

(
A
)

(b)
Figure 3. 24 Phase Differential Currents for a Phase C Ground Solid Fault
(a) Zf=0, Fault position =F1; (b) Zf=0, Fault position =F2-F5

74

3.6.3.2 Phase Differential Currents In Phase Domain

is the corresponding phasor plots for the previous six simulated fault scenarios (AGF1,
AGF5, BGF1, BGF5, CGF1 and CGF5). In addition to the magnitude information, the phasor
plots provide a picture of angle displacements under different scenarios. The phasor quantities
are obtained by using the FFT toolbox within EMTDC.
(a) is the differential current phasors for nominal conditions. Before the fault, IdA, IdB,
and IdC are with the same magnitude and an angle displacement of
120
to each other.

-0.1 0 0.1
-0.1
0
0.1
Data: Nominal
IdA
IdB
IdC
IRe (A)
I
I
m

(
A
)

(a)

39.4
120
80.6
-0.2 0 0.2
-0.2
0
0.2
Data: AGF5, Solid
IdB
IdA
IdC
IRe (A)
I
I
m

(
A
)

-0.5 0 0.5
-0.5
0
0.5
Data: AGF1, Solid IdA
IdB
IdC
IRe (A)
I
I
m

(
A
)

(b) (c)
150

62 62

Figure 3. 25 Phase Differential Current Phasor Diagram
For a Single Phase Ground Fault
(a) Nominal
(b) AG, Zf=0, F1
(c) AG, Zf=0, F2-F5
75

-0.2 0 0.2
-0.2
0
0.2
Data: BGF5, Solid
IdA
IdB
IdC
IRe (A)
I
I
m

(
A
)

-0.5 0 0.5
-0.5
0
0.5
Data: BGF1, Solid
IdA
IdB
IdC
IRe (A)
I
I
m

(
A
)

(d) (e)

62
62
62
62
-0.2 0 0.2
-0.2
0
0.2
Data: CGF5, Solid
IdA
IdB
IdC
IRe (A)
I
I
m

(
A
)

-0.5 0 0.5
-0.5
0
0.5
Data: CGF1, Solid
IdA
IdB
IdC
IRe (A)
I
I
m

(
A
)

(f)
(g)

Figure 3.25 Continued
(d) BG, Zf=0, F1; (e) BG, Zf=0, F2-F5
(f) CG, Zf=0, F1; (g) CG, Zf=0, F2-F5
For an AG internal fault Figure3. 25(b), phasor IdA increases in the magnitude but its
direction has not been changed. It keeps the pre-fault angle ( ). For the un-faulted phases,
phasors IdB and IdC both change in magnitude and in angle. IdB and IdC move close to each
other. IdB rotates clockwise and IdC rotates counterclockwise. As a result of this, the angle
difference of phasors between the two un-faulted phases IdB and IdC has been changed to 62 ;
IdA is leading IdB by 1 and lagging by IdC by 1 . The increase in magnitude for both IdB
and IdC can be seen from the scale. For an AG external fault Figure 3.25(c), IdA decreases to a
negligible value; But IdB and IdC exhibit the same pattern as in the internal fault.
39.4
50
48
76

Characteristic equations (3. 30), (3.31) and (3. 32) estimate that for an internal AG fault,
IdA will lead IdB by 150 and lag IdC by 150 ; IdB will lead IdC by 60 . Characteristic
equations

(3. 31)(3.31), (3. 32), (3.39) and (3. 40) describe that an external fault causes the same
changes in IdB and IdC as an internal fault.
Hence, the simulation results get very similar conclusions to those that the characteristic
equations have disclosed.
Figure 3.25(d) and (e) are the phasor plots for BG faults; (f) and (g) are the phasor plots
for CG faults. They exhibit the same patterns as AG. For an internal fault, the differential current
for the faulted phase keeps its pre-fault direction and only increases in magnitude but differential
currents for the two un-faulted phases change in both magnitude and angle. The angle difference
between the two un-faulted phases is around 60 . In addition, external and internal faults have
the same influence on the un-faulted phases. But the external fault will drop the magnitude of
differential current on the faulted phase to a negligible value.
3.6.3.3 Sequence Differential Currents In Phasor Domain

Figure 3.26 is phasor plots of sequence differential currents under testing scenarios.
Figure 3.26(a) is the nominal values. Under normal conditions, only positive sequence
differential quantity is present and is with the same value as the IdA. An internal fault (b, d, f)
produces appreciable pos., neg., zero sequence differential currents and their magnitudes are in
the order of Id1>Id2>Id0. {Appreciable is used here to describe a quantity if it is not less than
1/5th of pre-fault Id1}. Furthermore, for an AG internal fault, these sequence differential currents
are in alignment with each other, with nearly the same phase angle; for a BG internal fault, Id0,
Id1 and Id2 are in a displacement of 120 , rotating counterclockwise; for a CG internal fault, Id0,
Id1 and Id2 are still in a displacement of 120 but they rotate clockwise.
An external fault, Figure 3.26 (c, e, g), creates an equal amount of pos. and zero sequence
differential current but no negative sequence quantity. In addition, for an AG external fault, Id0
and Id1 are in almost an opposite direction; for BG and CG external faults, Id1 keeps the same
direction but Id0 rotates 120 clockwise or counterclockwise.
77

These observations from the simulation scenarios are consistent with the characteristic
formulae derived.
-0.1 0 0.1
-0.1
0
0.1
Data: Nominal
Id1
IRe (A)
I
I
m

(
A
)

(a)
|
I
d
1
|
=
0
.
1
9
-0.1 0 0.1
-0.1
0
0.1
Data: AGF5, Solid Id1
Id0
IRe (A)
I
I
m

(
A
)

-0.2 0 0.2
-0.2
0
0.2
Data: AGF1, Solid
Id1
Id2
Id0
IRe (A)
I
I
m

(
A
)

(b) (c)
|Id1|=0.46
|Id2|=0.27
|Id0|=0.09
194.4
|I
d
1
|
=
0
.
1
9

39.4
39.4
-0.1 0 0.1
-0.1
0
0.1
Data: BGF5, Solid
Id0
Id1
IRe (A)
I
I
m

(
A
)

-0.2 0 0.2
-0.2
0
0.2
Data: BGF1, Solid
Id0
Id1
Id2
IRe (A)
I
I
m

(
A
)

(d) (e)
123.5 74.4
|
I
d
1
|
=
0
.
4
6
|Id2|=0.27
|Id0|=0.09
|
I
d
1
|=
0
.
1
9

Figure 3. 26 Sequence Differential Currents Phasor Diagram
For a Single Phase Ground Fault
(a) Nominal
(b) AG, Zf=0, F1 (c) AG, Zf=0, F2-F5
(d) BG, Zf=0, F1 (e) BG, Zf=0, F2-F5
78

-0.1 0 0.1
-0.1
0
0.1
Data: CGF5, Solid
Id0
Id1
IRe (A)
I
I
m

(
A
)

-0.2 0 0.2
-0.2
0
0.2
Data: CGF1, Solid
Id0
Id1
Id2
IRe (A)
I
I
m

(
A
)

(f) (g)
115.4
45.5
|
I
d
1
|
=
0
.
4
6
|
I
d
2
|
=
0
.
2
7
|Id0|=0.09
|
Id
1
|
=
0
.
1
9

(f) CG, Zf=0, F1; (g) CG, Zf=0, F2-F5
Table 3. 3(a) gives the equations for sequence differential currents during BG type of
faults. According to that, a BGF1 gives,

2 2
0 3
0
0.03 1
0 0
1
0.09
2 ( )
1
1 240 7.967 376.8 0.09 90 10
3
1
1 240 0.27 ( 90 ) where is the prefault voltage angle.
3
II
I II
I II
C Va
Id a I a
C C
f C C
= =
+
+
=
= +

0.06 5
1 0 0 0 (1 ) 0
0.09 3
5
0.27 ( 90 )
3
I
I II
C
Id I I I I
C C
= + = + =
+
= +

2 0
1 120 0.27 ( 90 )
Id a I
=
= +

BGF5 characteristic equations give,
79

2 2
0
0
0.06
0 0
0.09
2
1 240 0.27 ( 90 )
3
2
1 60 0.27 ( 90 )
3
I
I II
C
0 Id a I
C C
= =
+
= +
= +
a I

0.06
1 0
0.09
2
0.27 ( 90 )
3
I
I II
C
0 Id I
C C
= =
+
= +

I

2 Id sma = ll

It is seen that the estimations from the characteristic equations match with the simulated
results of (d)(e).

3.6.4 Verification of Current Patterns for Phase to Phase Faults
Simulations were run to verify the characteristic equations derived in section 3.6. Test
scenarios include Phase-Phase fault, Phase-Phase-Ground fault, three-phase fault, solid fault,
impedance type fault, internal faults and external faults. Data analysis shows that the simulated
results matched with the characteristics derived by the formulae.
Error! Reference source not found. -- Error! Reference source not found. summarize
the key results.
3.6.4.1 Phase Differential Currents
Error! Reference source not found. is the phase differential current patterns for phase
to phase faults with Zf=200ohm.
Error! Reference source not found.(a) is the nominal differential current phasors. They
are the same magnitude (0.19A) and displaced by 120 .
Error! Reference source not found.(b) is the results for a phase B-C internal fault (F1).
The fault increases the differential currents of the two faulted phases (IdB and IdC), to about
80

68A; and differential current on phase A is negligible in the diagram. Characteristic formulae (3.
55) estimate that this case will give:

1
1_ 1// 1_ 2
0.18 ( +90 ) (A)
1 7.967
3 90 3 90
200
68.9 ( 90 ) (A)
1 7.967
3 90 3 90
200
68.9 ( 90 ) (A)
nom
Va
IdA IdA
X C X C
Va
IdB
Zf
Va
IdC
Zf
= =
=
= =
=
= =
= +

Estimations show that compared with IdB and IdC, IdA is too small to be shown; and IdB
and IdC are the same magnitude and in the opposite direction. These agree with the simulation
results.
It is noticed that there is an error in the phasor angle between the simulated result and the
estimation. The estimated angle for IdC is equal to the pre-fault phase angle of IdA, i.e.
and the simulated result is around 59 . This error is caused by the sampling
alignment of the FFT. But this alignment error will not influence the angle displacement
between different phases. So, IdB and IdC are in the opposite direction in the simulation.
( +90 )=39.4

Figure 3.27(c) is the results for a phase B-C fault at external positions (F2-F5). The fault
did not cause changes of differential currents. It keeps the nominal values, which is exactly
expected from the characteristic equations.
Figure 3.27 (d) is the results for an internal phase-B-C ground fault. Compared with the
B-C fault, the differential currents of IdB and IdC are reduced to half for this case. Their values
are now around 34A. This agrees with the estimation formula.
Figure 3.27 (e) is the results for external phase-B-C-G fault. It may be hard to directly tell
from this phasor plot why the differential currents exhibit such a pattern. But at least we can say
81

that the stray capacitance is still the main factor determining the current pattern since the
magnitude of the differential currents is in the range of 0.1 A-0.3 A.
Figure 3.27(f)(g) is the results for three phase faults. They verified the formulae in
section 3.7.6.

-0.1 0 0.1
-0.1
0
0.1
IdA
IdB
IdC
Data: Nominal
IRe (A)
I
I
m

(
A
)

(a)
|
I
d
B
|
=
0
.
1
9

39.4
120
39.4
120

-50 0 50
-50
0
50
IdB
IdC Data: BCF1-R200
IRe (A)
I
I
m

(
A
)

(b) (c)
59
180
|
I
d
B
|
=
6
8
.
8
|
I
d
C
|
=
6
8
.
6
-0.1 0 0.1
-0.1
0
0.1
Data: BCF5-R200
IdA
IdB
IdC
IRe (A)
I
I
m

(
A
)

|
I
d
B
|
=
0
.
1
9

Figure 3. 27 Phase Differential Current Phasor Diagram
For Phase Type Internal Faults with Zf=200Ohm
(a) Nominal
(b) BC, Zf=200, F1;
(c) BC, Zf=200, F2-F5

82

-20 0 20
-20
0
20
IdB
Data: BCGF1-R200
IdC
IRe (A)
I
I
m

(
A
)

(d) (e)
|
I
d
B
|
=
3
4
.
6
180
|
I
d
C
|
=
3
4
.
2
-0.2 -0.1 0 0.1 0.2
-0.2
-0.1
0
0.1
0.2
Data: BCGF5-R200
IdA
IdB
IdC
IRe (A)
I
I
m

(
A
)

|
I
d
A
|
=
0
.
2
8
|
I
d
B
|
=
0
.
1
4
|
I
d
C
|
=
0
.
1
9
97.5

-40 0 40
-40
0
40
Data: ABCG
- F1R200
IdA
IdB
IdC
IRe (A)
I
I
m

(
A
)

(f)
(g)
120
|Id
B
|=
3
9
.7
-0.1 0 0.1
-0.1
0
0.1
Data: ABCGF5-R200
IdA
IdB
IdC
IRe (A)
I
I
m

(
A
)

|
I
d
B
|
=
0
.
1
9

39.4
120

(d) BCG, Zf=200, F1; (e) BCG, Zf=200, F2-F5
(f) ABC, Zf=200, F1; (g) ABC, Zf=200, F2-F5
3.6.4.2 Sequence Differential Currents
Figure 3.28 are the sequence differential current patterns for phase faults with
Zf=200Ohm. Generally, an internal fault increases the magnitude of positive sequence
differential current; a BC or a BCG fault produced equal positive and negative sequence
differential currents. For an external fault, positive sequence current keeps its pre-fault value for
all phase faults. In addition, as expected a BCG external fault produces an amount of zero
sequence differential current but its magnitude is less than the positive quantity. These
observations agree with formulae and discussions in section 3.5 and 3.6.

83

-0.1 0 0.1
-0.1
0
0.1
Data : Nominal
Id1
IRe (A)
I
I
m

(
A
)

(a)
|I
d
1
|
=
0
.
1
9

39.4
39.4
-20 0 20
-20
0
20
Id1
Id2
IRe (A)
I
I
m
(
A
)

Data: BCF1-R200
(b) (c)
180
|I
d
1
|=
3
9
.7
|I
d
2
|=
3
9
.6
-0.1 0 0.1
-0.1
0
0.1
Data: BCF5-R200
IRe (A)
I
I
m

(
A
)

Id1
|I
d
1
|
=
0
.
1
9

Figure 3. 28 Sequence Differential Current Phasor Diagram
For Phase Type Internal Faults with Zf=200Ohm
(a) Nominal
(b) BC, Zf=200, F1;
(c) BC, Zf=200, F2-F5

84

-10 0 10
-10
0
10
Data: BCGF1-R200
Id1
Id2
IRe (A)
I
I
m

(
A
)

(d) (e)
180
| I
d
1
|=
1
9
.9
|
I d
1
|
=
1
9
.
8
-0.1 0 0.1
-0.1
0
0.1
Data: BCGF5-R200
IRe (A)
I
I
m

(
A
)

Id0
Id1
|I
d
1
|
=
0
.
1
9
53.2
|
I
d
0
|
=
0
.
1

39.4
39.4
(f) (g)
-20 0 20
-20
0
20
Data: ABCGF1-R200
IRe (A)
I
I
m

(
A
)

Id1
|I
d
1
|=
3
9
.
7
-0.1 0 0.1
-0.1
0
0.1
Data: ABCGF5-R200
Id1
IRe (A)
I
I
m

(
A
)

|
I
d
1
|
=
0
.1
9

(d) BCG, Zf=200, F1; (e) BCG, Zf=200, F2-F5
(f) ABC, Zf=200, F1; (g) ABC, Zf=200, F2-F5
3.7 Differential Type of Fault Detection
As indicated by the characteristic analysis, a solid phase to phase type of fault produces
large destructive fault currents and should be isolated rapidly. So, it is defined as a tripping type
of fault--once a fault is identified, the circuit breakers around that faulted section will be tripped
immediately. The system cannot be allowed to continuously operate under this situation. The
fault detection principle will be based on phase differential currents comparison. The quantity
compared is the magnitude of differential currents. If the magnitude of differential currents of
two or three phases is larger than the threshold, a fault is announced. There is no necessity to
identify the fault type, i.e. whether it is a phase-phase fault, phase-phase ground fault, three
85

phase fault or which phases are involved since a phase to phase type fault will issue a three-pole
trip command.
A high impedance phase type fault, theoretically, should be a tripping fault since it
belongs to a phase type of fault and introduces fault currents and voltage unbalances or
distortions into the system. Hence, it should be tripped by any means. However, in practice, we
are never able to handle it so ideally due to the sensitivity issue. Fault resistance could reduce the
differential currents below the pickup setting of differential comparison, and hence hide the fault
event. In this dissertation, a high impedance phase to phase fault is divided into three levels: a
low high impedance fault, a medium high impedance fault and a high high impedance fault.
Differential currents under a low high impedance phase to phase fault will be higher than the
pickup setting and are detectable by differential magnitude comparison. A low high impedance
phase to phase fault is, therefore, defined as a tripping type of fault. Under a medium high
impedance phase-to-phase fault, differential currents produced are below the pickup up setting
but are still 10-20 times nominal leakage currents. Differential currents produced by a high
high impedance phase fault, in magnitude, will be close to a single-phase ground fault. Either of
these two types is categorized as an alarm fault.
A single-phase ground fault is defined as an alarm fault too.
An alarm fault will be tripped manually by an operator. The detection principle for an
alarm fault is based on both the angle and magnitude information of sequence differential
currents. The fault type needs to be identified for an alarm fault. A medium high impedance
phase fault requires a fast decision from the operator. He will decide to clear the fault
immediately or reconfigure the system before the operation. If no decision were made during an
allowable time interval (10-30mins depending on the system design), the alarm system would
initiate a three-pole trip.
A high high impedance phase fault and a single-phase ground fault can be allowed to
exist a longer time until a convenient scheduled-shut-down time. No operation is issued from the
alarm system for these two faults, only an alarm for indication.
86

CHAPTER 4
WIDE AREA DIFFERENTIAL PROTECTION SYSTEM
4.1 Introduction
A Wide Area Differential Protection (WADP) system is proposed for clearing solid or
low impedance phase faults on board a ship power system. These types of faults produce large
fault current. In most cases simulated, it reaches hundreds times current produced by single-
phase faults or normal load conditions. The fault situation is quite severe, comparing to the
similar fault cases on land. This is due to a lack of effective current limiting impedance in the
ship distribution system. For such large fault currents, it is not wise to leave the faults there un-
cleared or rely on the alarm system for manual operation. They will cause damage. Even though
cables and equipment on board are all selected with a larger size and capability, they are mainly
designed for withstanding temporary overload conditions due to the mission requirements. It is
impropriate to risk the system for fault situations. So, an immediate operation of the protection
system is required for phase-to-phase faults. For a power system installed with a current limiting
device, a delay protection trip is still required.
The WADP system proposed includes primary protection, backup protection and two trip
mechanisms (trip confirmation mechanism and sequential priority trip mechanism), to ensure
that a fault be cleared precisely, reliably and fast. Precise is the first consideration. Components
or loads onboard need the maximum reliability and availability, especially vital
87

loads such as weapons and defence mechanisms etc. Any unnecessary interruption of vital loads
could be disastrous in a combat scenario. The WADP system takes this into consideration and
adopts the differential fault detection principle to avoid unnecessary protection interruptions.
Primary protection of the WADP system uses conventional differential relays. They are installed
at each power system component to form individual busbar, cable, and transformer protection.
Differential relays have no inherent backup. So, a new differential backup scheme is proposed in
the WADP system to coordinate with the primary protection. New backup scheme includes (1) a
new differential ring concept (2) a new differential ring detection and location mechanism and
(3) a new self-check mechanism. These features help backup protection to achieve a minimum
isolation trip region. They are described in section 4.2.
Reliability is the second criterion. Defects in protection circuits should not lead to fail to
trip a fault or initiate a false trip. Installation of backup protection can avoid the former.
Conventional backup protection works on the condition that the primary protection fails to trip a
fault. But it has no influence with the false trip of primary relays. In the WADP system, the
unnecessary interruptions resulting from a false primary trip due to a sensor failure or a relay
mal-operation, are considered too. A trip confirmation mechanism in the WADP verifies that the
backup should also see a fault before allowing the primary system to trip a breaker. In this sense
it acts like the Starter Unit in a conventional relay although the back-up confirmation will
come from remote sensors/measurements. A situation that a sensor failure occurs simultaneously
with a fault, is also discussed. A sequential priority trip mechanism is proposed in the WADP
system to handle unnecessary multiple trips under this case. Section 4.3 contains the detailed
contents.
Section 4.4 describes a real time WADP experimental system. The experimental system
will test the protection mechanisms and overall protection results. Most importantly, the system
will provide an accurate time margin for protection studies since it uses commercial relays
directly for the development. Speed becomes an absolute necessity. The prototype real time
WADP system established in the lab consists of a Real Time Digital Simulator (RTDS) and two
commercial hardware relays. Primary protection is implemented in one hardware relay. Another
hardware relay is used for the function of trip-confirmation. Other functions in the WADP are
simulated in RTDS. Signals between RTDS and hardware relays include 44 digital signals and
28 analog signals and they are all exchanging in real time (80us). In this system, one can observe
88

the responses of a number of relays in the WADP system to a particular system event and the
consequence of the protective trips. It is closer to the field applications. Most current research
work is still staying in simulating a relay, and then using it for protection studies. But, generic
relay models or detailed relay models cannot achieve the same accuracy as the commercial relay
itself. Private information on a particular relay will be lost during the modeling due to
proprietary protection. In this aspect, the WADP system is more accurate. In addition, using
commercial relays to form part of the WADP system speeds the development duration.
Section 4.5 discusses the test results, including primary protection trip, backup protection
trip, and protective trips for sensor failure cases.
4.2 Differential Ring Principle
4.2.1 Differential (Diff) Ring Concept
The differential principle (implemented in the form of a restrained differential
calculation) is used in the WADP scheme but in an extended manner called Differential (Diff)
Ring. The Diff Ring is formed by its boundary CTs denoted by the dot points in Figure 4. 1.
Diff Ring defines a region within which the differential principle can be applied. With the
Diff Ring, the differential comparison region has been enlarged from a single component to a
wide area as is indicated by various rings in Figure 4. 1. The explanation on Diff Rings is given
as below:
Under normal conditions, it is seen that:
1 2 8 0 Ict Ict Ict + + =
(4. 1)
2 3 Ict Ict 0 + =
(4. 2)
3 4 0 Ict Ict + =
(4. 3)

The property of equations(4. 1)-(4. 3) is the conventional differential principle.
From (4. 2):

2 3 Ict Ict =
(4. 4)

Substituting (4. 4) into (4. 1):

1 ( 3) 8 0 Ict Ict Ict + + =
(4. 5)
89

CT3
Busbar 01
T2
03
CT10
CT5
CT6
CT7
04
05
02
G
C1
C2
T1
CT11
CT8
CT9
3
1
CT1
M1
M2
CT2
CT4 (a,b,c)
2
CB4
CB1
CB2
CB5
CB3
CB6
CB7
CB10

CT: Current Transformer CB is Circuit Breaker T: Transformer
G: Generator M: Motor load C: Cable
Figure 4. 1 Differential Rings
From (4. 3):

4 3 Ict Ict =
(4. 6)

Substituting (4. 6) into (4. 5):

1 4 8 0 Ict Ict Ict + + =
(4. 7)

The property of equations (4. 5) and (4. 7) is what have been called Diff Ring
conservation. Multiple system items are involved in the Diff Ring.

90

A ring is conserved when the sum of the CT sensor currents around that ring is zero. By
implication all the components contained inside that ring are un-faulted. On the other hand, a
ring is violated or active if the summation is non-zero and this could be caused either by an
internal component fault or by the failure of a sensor in the ring. The latter possibility can be
eliminated by verifying that another ring which contains the ring in question also has a non-zero
summation.
Diff Ring operates on the basis of five Diff Ring Rules. They are:
Rule 1: Under normal conditions, all Diff Rings are conserved/inactive.
Rule 2: The fault position changes the conservation property of certain Diff Rings.
Rule 3: The outermost ring is always active no matter where a fault is placed in
the system.
Rule 4: If a ring is active, its outer layer rings are all active.
Rule 5: If a ring is inactive, all of its inner rings are inactive.
4.2.2 Diff Ring Formation Mechanism
Diff Ring varies in its size and location. For instance, Ring1 in Figure 4. 1 contains only a
single component and Ring2 contains three components (busbar1, C1 and busbar2). For fault
detection and location purpose, three types of Diff Rings are defined in the WADP system.
1. Inner Diff Ring
An Inner Diff Ring is a ring that is formed by CTs around a single component and its
region is the same as the one covered by a conventional differential relay. Ring 1 in Figure 4. 1 is
an Inner Diff Ring
2. Augmented Diff Ring
An Augmented Diff Ring is developed by expanding the Inner Ring to its next connected
CTs from both ends or one end if that is the only one available. In Figure 4. 1, Ring2 is the
Augmented Diff Ring formed by Ring1 Inner Ring.
3. Outermost Diff Ring
An Outermost Diff Ring (Ring 3) is the one formed by CTs located at the boundary of the
protected region. It covers the whole protected area.

91

The Inner Ring is mainly used in the fault location routine since its violation will directly
announce a minimum isolation area. Applying Rules 1-5, the Outermost Ring or Augmented
Rings are used to supervise the primary relay and Inner Ring. The verification process
determines whether a trip is caused by a fault or a defect in protection itself.
4.2.3 Diff Ring Fault Detection and Location Algorithm
A fault event on the system changes the status of Diff Rings. Some Rings will become
active and others may still remain inactive. This property is utilized in the WADP system for
fault detection and location.
Diff Ring fault detection starts with the Outmost Ring. A fault event, anywhere within
the system, will activate this ring. If the Outmost Ring is inactive, on the other hand, it will
indicate that the system is operating properly. An active Outmost Ring then initiates a
Differential Searching (DS) routine to locate the fault. To coordinate with primary protection, the
DS routine is only activated in the absence of a signal from any primary protection unit
accompanied by a trip signal from the Outermost Ring. The idea of the DS routine is to form
Inner Diff Rings sequentially along the system and to identify a single active one. That one will
be the fault location since the Inner Diff Ring only contains a single component and is a
minimum area. Figure 4. 2 demonstrates this fault location process. The outermost Diff Ring
sees a sustained fault indicated by 1 8 6 Ict Ict Ict threshold + + > . The DS routine is called and the
Inner Diff Rings start forming from Bus1 (CT1&2&8), continue with C1 (CT2&3) and Bus2
(CT3&4), and finally stop at C2 due to the active status of its Inner Ring i.e. C2 is then claimed
as the fault isolation area.

Figure 4. 2 Differential Fault Location Process
92

To speed up the searching process, a subroutine is included in the DS routine. This
subroutine decides where the first Inner Ring starts and which path has priority, once parallel
branches are met. The priority can be defined as vital/non-vital supplies, vital/non-vital loads,
weak links and so on, depending on the system requirement. In the WADP system, the weak
link concept is used. A weak link is defined as a power system component that has a high
failure rate in the past.
Topology information is needed for use in the searching process and it will be provided
offline and updated online according to circuit breaker information. Topology information is
stored in an incidence matrix. In forming the incidence matrix, the power system structure is first
mapped into a unidirectional graph with Nodes and Edges. An edge is a path connecting nodes.
In the mapping, power system components like busbar, cable, and transformer are represented by
Nodes, and circuit breakers are represented by Edges. Figure 4. 3 is a graphic representation for
the power system shown in Figure 4. 1.

B: Busbar
C: Cable
CB: Circuit Breaker
G: Generator
M: Motor load
N: Node
T: Transformer
B5
CB9
CB11
CB8
C1
CB2
G
B1
CB1
CB3
CB4
CB5
CB6
T1
CB7
CB10
B2
C2
B3
T2
B4
M1
M2
G
M1
M2

N2
N3
N4
N9
N1
N8
N5
N6
N7
Figure 4. 3 Graphic Mapping
93

The incidence matrix stores the conductivity information on the graph. It is formed as:
Let A denote the nn matrix ( ). n is the number of nodes and be the element of
A. Then A=( ) is defined as,
ij
a
ij
a
ij
a
1 if there is an edge between nodes i and j
,
0 otherwise.
0, 1,...
ij
ii
a i
a i n
= =
j

Conductivity matrix for Figure 4. 3 is expressed as:
0 1 0 0 1 0 0 0 0
1 0 1 0 0 0 0 0 0
0 1 0 1 0 0 0 0 0
0 0 1 0 0 0 0 0 0
1 0 0 0 0 1 0 0 0
0 0 0 0 1 0 1 0 0
0 0 0 0 0 1 0 1 0
0 0 0 0 0 0 1 0 1
0 0 0 0 0 0 0 1 0
A
(
(
(
(
(
(
(
=
(
(
(
(
(
(
(

Matrix A will be updated with the operation of circuit breakers.

Sensor data are also stored in the same way. Matrix B defines sensor matrix.
Let B denote the nn matrix ( ). n is the number of nodes and is the element of B.
Then B=( ) is defined as,
ij
b
ij
b
ij
b
if sensor k locates on an edge between nodes i and j
,
0 otherwise.
, if loads or generators are attached to node i, 1,...
k
ij
ii k
CT
b i
b CT i n
= =
j

Considering Figure 4. 1 and Figure 4. 3, sensor matrix B is expressed as:

94

0 2 0 0 3 0 0 0 0
2 1 8 0 0 0 0 0 0
0 8 0 9 0 0 0 0 0
0 0 9 11 0 0 0 0 0
3 0 0 0 0 4 0 0 0
0 0 0 0 4 0 5 0 0
0 0 0 0 0 5 0 6 0
0 0 0 0 0 0 6 0 7
0 0 0 0 0 0 0 7 1
CT CT
CT CT CT
CT CT
CT CT
B CT CT
CT CT
CT CT
CT CT
CT CT
(
(
(
(
(
(
(
=
(
(
(
(
(
(
(

0

Based on matrix B, the Diff Ring is constructed dynamically in the WADP system
through a software process. All CT sensors send a synchronized current amplitude and phase
through the communication channel to a WADP unit in which the WADP scheme is running. A
software algorithm is responsible for gathering the CT information regarding which CTs are
required to form a particular ring and for doing a differential calculation to detect the status of
the ring or rings.
Figure 4. 4 gives the flowchart of Diff Ring fault location algorithm.
4.2.4 Diff Ring Self-Check Mechanism
Diff fault location routine includes a Diff Ring self check mechanism. The mechanism is
defined as:

Diff Ring Self-Check Mechanism
If an Inner Diff Ring detects a fault, its trip signal will not be released
immediately unless it gets confirmation from the Augmented Ring.
This process is to reduce the false trip introduced by CT problems.
Differential protection is sensitive to the deficiencies of CTs. CT remanence, saturation
or failure can lead to a false differential trip. In Diff Ring fault location routine, an Augmented
Ring is used to verify a ready-to-release backup trip so as to diminish the possibility of mal-

95

N
Fault
Location
Routine
Y
Y
Form outmost ring
N
Topology Input
Update CTs Data
Active?
Augmented
Ring Routine
Fault?
Y
Trip CBs
Update
Topology Data
N
Form Inner
Diff Ring
N=N+1
Active?
Node Index N=1

Figure 4. 4 The Flowchart for Diff Ring Fault Location Algorithm

96

operations. For instance, a deficiency in CT2 (Figure 4. 2) may also result in C1 being identified
as a minimum fault area. But its Augmented Ring formed by CT1, CT8 & CT3 will not be
affected and is conserved, which eventually prevents the false trip. This process will not
influence the protection trip on a fault because the Augmented Ring and Inner Ring are both
violated under this case.
4.3 Wide Area Differential Protection
4.3.1 Primary Protection
Primary protection in the WADP system uses conventional differential relays.
Differential relays are installed at each component to form individual busbar, cable, and
transformer protection. This kind of protection design is illustrated in Figure 4. 5. These relays
implement dual slope restraint calculation for differential comparison. For transformer
protection, in addition to dual slope comparison, harmonic restraint comparison is also applied.
4.3.2 Primary Confirmation Mechanism
This mechanism is designed to avoid the false trips from primary relays. A local CT
saturation or CT open/short circuit may lead to the false operation of local primary differential
protection. To prevent this from happening, the Outmost Ring is used to supervise the primary
relays. The primary confirmation mechanism is:

Primary Confirmation Mechanism
If a primary relay detects a fault, its trip signal will not be released immediately
unless it gets confirmation from the Outmost Ring.
The principle is based on Rule 3 in section 4.2 which states that the Outermost Ring is
always active no matter where a fault is placed in the system. So, if there is a fault in the system,
the primary relay and the Outmost Ring should both see the fault. If only the primary relay
detects a fault and the Outmost Ring does not, this will be treated as a false primary trip and be
inhibited. In the WADP system, an Outmost Ring supervises all the primary relays.

97

Busbar 01
05
02
G
C1
T1
CT1
T2
03
04
C2
M1
T2
03
04
C2
M1
M2
CB1
Primary Primary
Differential Differential
Protection Protection
C: Cable
CB: Circuit Break
CT: Current Transformer
M: Motor load
CT3
CT5
CT4
CT11
CT8
CT9
CT6
CT2
CT7
CT10
CB2
CB3
CB4
CB5
CB6
CB7
CB10
CB8
CB9
CB11

Figure 4. 5 Primary Protection System
Could a correct primary trip be inhibited because of an incorrect decision from the
Outermost Ring? The chance would be a loss of the entire boundary CTs of the Outmost Ring
simultaneously. If this happens, boundary CTs have no data and their summation will be zero, so
the Outmost Ring will be always inactive. Consequently, a correct primary trip would be
wrongly restrained. But it is a rare event and could happen only if the entire communication
network fails. In the WADP system, the communication channel is self-checking. In the event
that the communication link to the WADP processor is down, primary protection will act on its
own.
98

4.3.3 Wide Area Backup Protection
Wide area backup protection applies the Diff Ring principle to trip a fault.
During the normal condition, only the Outermost Ring is formed in the WADP system
and monitors the system status. If a fault occurs somewhere in the system, the Outermost Ring
and a primary relay will both detect this event. The primary protection system (gated by the
Outermost Ring) should clear the fault within typically 2-3 cycles. After this period, if a fault
still persists, being indicated by the continued violation of the Outermost Ring, backup
protection will take over and perform its function. The Diff Ring fault location algorithm is
activated in the backup system to identify the faulted component and a minimum area.
If the WADP has received a trip indication from the primary protection then it must be a
breaker failure problem and a breaker failure procedure will be activated for the breakers
involved. If there is no signal from a primary protection, then a backup trip is released.
4.3.4 Sequential Priority Trip Mechanism
A fault accompanied with a sensor failure may result in multiple items being identified as
the faulted components. The sequential priority trip mechanism is introduced in the backup
system to achieve a minimum isolation area under this situation.

Sequential Priority Trip Mechanism
When protection involves multiple trips and at the same time some
decision CTs are questionable, then the trip will be released based on the
facts that:
(1) If the questionable CT is not the boundary CT, then the breaker
closest to the questionable CT will be tripped sequentially.
(2) If the questionable CT is the boundary CT, then the breaker
closest to the questionable CT will be tripped last and the Inner
Ring involved the boundary CT changes to over-current
detection.

Sensor Failure on Internal Ring
99

The first case to be considered is that a bad sensor is located on an Internal Ring. For
instance, CT4 in Figure 4. 5 has problems. Meanwhile, there is a fault occurring on C2.
The Outmost Ring becomes active due to the fault on C2. It starts the Diff Ring location
routine. Busbar02 and Cable2 will be finally identified as faulted components. Busbar02 is one
of the fault candidates because its Inner Ring and Augmented Ring are both active. The Inner
Ring of busbar02 uses CT3&4 to form differential comparison and CT4 failure produces
differential current. Its Augmented Ring become active because the region (CT2&5) formed by
the Augmented Ring contains faulted component (C2). The same reason results in Cable2
becoming the faulted candidate too.
The normal trip routine would trip circuit breakers CB3&4&5. But this is not the
minimum isolation region since Busbar02 is an un-faulted component and it should not be
tripped.
To avoid this situation, the sequential priority trip mechanism is executed. Since CT4 is
the questionable CT and it is not located on the boundary, so circuit breaker CB4 will be tripped
first. This action actually clears the fault and the isolation area is minimum. After the switch
event, topology information is updated and the new Outmost Ring is formed. The new one uses
sensor CT1&3&11. Since the fault has been cleared, this Outmost Ring will keep inactive until
another fault event occurs.

Sensor Failure on Outmost Ring
The second case is that a bad sensor is located on the Outmost Ring. For instance, CT1 in
Figure 4. 5 has problems. Meanwhile, there is a fault occurring on C2.
The Outmost Ring becomes active due to the fault on C2. It starts the Diff Ring location
routine. Busbar01 and Cable2 will be finally identified as faulted components. Busbar01 is one
of the fault candidates because its Inner Ring and Augmented Ring are both active. The Inner
Ring on busbar01 uses CT1&2&8 to form differential comparison and CT1 failure produces
differential current. Its Augmented Ring become active because it is formed by CT1&3&9 and
CT1 failure make it be active too.
The normal trip routine would trip circuit breakers CB1&2&8&4&5. But this is not the
minimum isolation region since Busbar01 is an un-faulted component and it should not be
tripped.
100

To avoid this situation, the sequential priority trip mechanism is executed. Since CT1 is
the questionable CT and it is located on the boundary, so circuit breakers (CT1&2&8) closest to
it will be tripped last. This result that CT4&5 are tripped first. The action actually clears the fault
and the isolation area is minimum. After the switch event, topology information is updated and
the new Outmost Ring is formed. The new one uses sensor CT1&3&11 and it may still be active
due to CT1 failure. The Diff Ring location routine starts but busbar01 will not be identified as
the faulted component because the Inner Ring around it has been changed to over-current
detection. CT1, CT2 and CT8 are not greater than the threshold, so the Inner Ring around
busbar01 is inactive.
The fault has been cleared with the minimum isolation region.
4.3.5 Coordination
Coordination includes two aspects. One is cooperation between primary protection and
backup protection. Conventional design philosophy adopts time-delayed coordination. To clear
a fault, primary protection operates first, then the circuit breaker failure protection, and finally
backup protection. The decision time for primary relays is around 2-3 cycles and then circuit
breaker takes 3-5 cycles to operate. So, primary protection will take 100-150ms. This is the
primary operation period. Circuit breaker failure protection has to wait for the elapse of this time
period before it declares the circuit breaker failure event and initiate an action. Another 100-
150ms will be considered for circuit breaker failure protection. So, the time delay between
primary and backup will be 300ms.
The WADP system follows the time-delayed coordination method but revises the
coordination between primary and wide area backup protection. The Outmost Ring will start the
backup protection routine immediately once it becomes active. There is no need to delay the
backup protection at this point. The Diff Ring fault location routine can run in parallel with
primary protection or circuit breaker failure protection. When the faulted component has been
located and the backup decision time is shorter than the primary protection, it is actually not
harmful to release this backup trip since the backup trip area is also minimum. This means that,
from the protection viewpoint, a delayed coordination between primary and wide area backup is
unnecessary.
101

In addition to the coordination between primary and backup, the other aspect of
coordination is the interactions between the WADP system and the power system itself. The
WADP system requires all the CT data to make a decision. But remote data takes time to be
transferred to the wide area center. Synchronization is important. If some CT data are updated
but others were not, then Diff Ring may produce false differential current and a false decision.
To ensure that all the CT data will be updated, a 100ms communication period is included in the
WADP system. During this 100ms period, the WADP system receives data and writes into its
database. When this time is expired, the communication will be set as idle until the next routine
starts.
The WADP system also uses the topology information of a power system. But the
protection trip changes the topology. To keep the validation of the WADP system, the WADP
system will be frozen after a protection trip until the new circuit breaker status are updated.
4.4 WADP Experimental System
4.4.1 Overview
A WADP experimental system was setup in the lab to test the performances. The
performances considered are:
(1) Reliability
Reliability has two aspects. One is that the WADP system should be able to detect a fault
(dependability) anywhere in the system and clear it. Meanwhile, it should not cause any false trip
(security).
Reliability is evaluated by initiating a fault in the power system and then recording the
trip status of the WADP system. The trip status includes the status of all primary relays and the
wide area backup trips. The recorded trip status will be used to determine whether it is a correct
trip or a false trip based on the location of the fault. If the relay protecting the faulted component
trips, then it is a correct trip. Otherwise, it will be an incorrect trip. Also, if there is no fault in the
system but a relay trips, this trip will be a false trip. Each test scenario provides a set of data
associated with Trip/No_Trip /Correct_Trip/False_Trip. A complete test provides a statistical
value concerning the reliability performance.
(2) Isolation Area
102

In the WADP system, primary relays only trip the circuit breakers surrounding the faulted
component. The wide area backup protection system has a fault location algorithm to ensure that
backup protection trips the minimum area. So, the isolation area of the WADP will be minimum
area. This requirement is important to the ship power system. Ship vital loads should not be
unnecessarily interrupted due to protective actions.
The circuit breakers tripped under a fault by the WADP system will be evaluated to see if
this criterion is satisfied. The fault location algorithm is examined to see if it finds the faulted
element and the confirmation mechanisms also needs to be assessed to see if they cover the worst
scenarios.
(3) Speed
Conventional primary differential relays clear a fault within 2-3 cycles. In the WADP
system, primary relays are supervised by the Outmost Ring. Therefore, there will be a delay in
primary trips. In this aspect, the WADP system sacrifices speed for reliability. On the other
hand, the WADP system changes the conventional coordination scheme and this change speeds
up the backup trips. These differences and their effects need to be studied.

The WADP experimental system is constituted with a Real-Time Digital Simulator
(RTDS) and two commercial relays. The RTDS is a digital simulator designed for power system
studies. It can simulate complex electric networks and control systems in real time. It also
provides substantial I/Os from which the real time simulation signals can be accessed and
through which the outside signals (control/command/power) can be supplied to the simulation
cases. One of the ways in which the user can use these I/Os is to directly connect external
hardware to the RTDS, to form a real time hardware-in-loop system. This setup becomes more
and more useful as one is ready to test new prototype equipment and to explore detailed
interactions between electric networks and equipment, especially for those interested in time
critical events, over-limit tests or longer duration tests. Protection studies fall into these
categories and the RTDS provides a cost-saving, time-saving, and hazard-immune testing
environment to perform those tests. Therefore, the RTDS is selected as the platform to develop
the WADP experimental system.
The WADP functions are divided into two parts. One part is those functions that can be
directly realized or modified with existing relay hardware. For those functions, external hardware
103

is selected and interfaced with the RTDS. These functions are primary protection and the
Outmost Ring function. Another part is those functions that are not available in the present
commercial products. They require custom programming and codes, and are therefore simulated
in the RTDS. Those functions include Diff Ring fault location routine, priority trip mechanisms,
wide area protection co-ordinations and circuit breaker trip circuits. A ship-type power system
testbed of Figure 4. 5 has also been simulated in the RTDS and integrated with the WADP
system for the test.
Figure 4. 6 gives a schematic diagram of the experimental system. In the bottom are two
commercial relays. One of the relays (Relay1 in Figure 4. 6) is used for dedicated primary
protection functions. The other relay (Relay2) is used to develop the Outmost Ring and
perform the fault detection and verification function. The middle is I/O interfaces. Relays need
power system signals as inputs. These inputs come from the RTDS I/O board and from a
simulated ship type power system. The ship power system model simulated includes a high
impedance grounded generator model, two coupled pi section cable models, two transformer
models, two static load models, circuit breakers and switchable symmetrical/asymmetrical fault
components. When compiling this model, the user can dictate certain system variables to be sent
to digital and analog output ports of the RTDS rack to which hardware relays are connected.
Inputs to the relays are power system current signals, voltage signals and the status of the circuit
breakers. The relay output contacts are connected to the digital input port (DIN) on the rack. The
logic value (trip=1, no_trip=0) received from this digital input port is then written to a trip
control variable within the simulation model to control the circuit breakers. On the top is the
RTDS simulation environment. Power system circuits and most control circuits (signal
conditioning circuits, breaker trip circuits and coordination circuits) required in the WADP
system are built with standard library components provided by the RTDS. An exception is the
Diff Ring fault location routine. It does not use library components. Instead, it was written with a
RTDS C- type language and defined as a User Defined Component (UDC) modelDiff_UDC.
Inputs to Diff_UDC are power system current signals and the status of the Outmost Ring. The
outputs are the locations of the faulted components. These outputs are then in turn connected to
trip and coordination circuits as one of the protection trip criteria. Lines in Figure 4. 6 indicate
signal flows back and forth between different function models and arrows indicate their
directions.
104

Outmost
Ring Trip
RTDS
Rack I/O
DOUT D/A D/A
Currents Voltages CB Status
Primary
Trips
Relay1
Relay2
Primary
Function
Outmost
Ring
DIN DIN
Signal
Conditioning
RTDS Environment
Simulated
Ship Power
System
Diff Ring
Fault
Location
Trip/
Coordination
RTDS
Simulated
Model

Figure 4. 6 Schematic Diagram of the WADP Experimental Testbed

105

Relay1 Relay2
RTDS
Rack
Relay Low -Level
Input Terminals
RTDS
Workstation
Relay1
Relay2
RTDS
Rack
Digital
Inputs
TO RTDS
Digital
Inputs
TO RTDS
Digital
Inputs
TO RTDS
Digital
Inputs
TO RTDS
Relay Low - Level
Input Terminals
125V
Power
Source
Communication
Cable
RTDS
Workstation

Figure 4. 7 The WADP Experimental System
4.4.2 Experimental Setup
Appendix C.
4.4.3 Testing Procedure
Figure 4. 7 gives a front view of the WADP experimental system. Relays, RTDS, and
their interfacing have already been discussed in the previous sections. A communication cable
link between the relay and the PC is for downloading the setting data to the relay and for
selecting an active group setting for use in the experiment.
To avoid damage to the relay and auxiliary equipment, the experimental system always
follows a routine starting procedure. Steps are:
Step1: Compile and run the RTDS WADP case on the RTDS workstation
Step2: Check nominal currents and voltages applied on the low-level test terminals
106

Step3: Turn on AC power supply to the relay
Step4: Turn on DC power supply
Step5: Check relay readings
Step6: Check relay front panel LEDs
Step7: Select an active relay setting group
Step8: Be ready for protection tests
Protection tests may be done manually. A fault can be switched onto a branch by simply
clicking a switch-button through the RTDS run-time environment. Then current, voltage and
circuit breaker signals are sampled and plotted to see whether protection responses are correct.
Conclusions are drawn on the performance of the WADP to a particular event. The manual test
was used in the early debug stage. In the final stage, the WADP experimental system was tested
using a script file. A script file, in short, is a batch running file that contains commands/functions
to control and continuously run many simulation cases without direct user interaction. For each
case, output data can be stored and analyzed automatically. So, it is an efficient and systematic
way to test the performance of a system.
The script file created for testing the WADP system follows the flow chart of Figure 4. 8
[63] and studies the following faults on different locations.
Phase-ground faults
Phase-phase faults
Impedance faults
Faults with controllable fault inception angles.
And faults with questionable CT measurements
The script file for the WADP contains a section of codes for storing the real time fault
data and a section of codes for the performance evaluation on the WADP. The evaluation
summary is written to a file that can be opened and reviewed later when all tests are completed.
For any suspicious event recorded in the summary report, it will be looked at again through a
manual operation mode.
4.5 Case Studies and Results
The section discusses some test results related to the WADP system.

107

Set Fault Type
Set Fault Resistor
Set The Fault
Point on Wave
Start
Apply Fault
Stop
Change The Fault
Point on Wave
Fault Point on Wave
Loop Counter=2 ?
Evaluate
Protection
Trip
Get Fault Data
Save Data
Change Fault Resistor
Fault Resistor Loop
Counter=2 ?
Change Fault Type
Fault Type Loop
Counter =10 ?
End
NO
YES
NO
NO
YES
YES

Figure 4. 8 Script File Flow Chart
108

Case 1: WADP- Primary Protection

Figure 4.9 (a)-(e) shows a primary trip event.
Figure 4.9 (a) shows the status of a fault switch. Before time of 12.7ms, its status was
logic 0 and after 12.7ms, it was changed to logic1. This switch was to control the fault
branch located on bus4. A logic 1 indicated that a fault was switched onto bus4. The actual
event was that an A-B-G fault was applied on bus4 at 12.7ms. Fault types applied were
controlled by the circuits simulated in the RTDS. In this case, the fault type selective switch was
set to A-B-G before the fault switch was initiated.
Figure 4.9 (b) and (c) give the currents and voltage waveforms measurement on bus4 for
this event. Currents were from the upstream sensor CT7 (Figure 4. 1). The waveform captured
pre-fault as well as fault values. The pre-fault peak current and voltage are 7.8kA and 3.4kV
respectively. Voltage waveforms show phase A and B voltages fall due to a fault on these two
phases. On current waveform, phase A and B experienced a large fault current. So, the voltage
and current waveforms would both indicate that it was a fault involving phase A and B. This
coincides with the actual event that had been initiated from the control panel. The peak fault
current occurred on phase A. In the first half cycle, it reached 47.2kA, six times the pre-fault
value. In the second cycle, it followed an exponential decay, reducing to 37kA. Then, in the next
zero crossing moment of T=40.8ms, it was interrupted due to protection trips. Time difference
from initiating a fault (12.7ms) to finally interrupting a fault (40.8ms) is 28.1ms, less than two
cycles. The trip was judged as a primary trip since a backup trip would involve 100ms delay
which is a time mark, introduced in the coordination circuit to distinguish primary trips from
backup trips.
Figure 4.9 (d) and (e) are pictures associated with the protection responses of the WADP
system, where
CB7=1/0, Circuit Breaker 7 is close (1) or open (0)
OUTR=1, Outmost Ring is active
RelayPri7=1, Relay primary trip to CB7 is active
Pri7=1, Confirmed Primary trip to CB7 is active
BP7=0, Backup trip to CB7 is inactive
and,
109

CB10=1/0, Circuit Breaker 10 is closed (1) or open (0)
OUTR=1, Outmost Ring is active
RelayPri10=1, Relay primary trip to CB10 is active
Pri10=1, Confirmed Primary trip to CB10 is active
BP10=0, Backup trip to CB10 is inactive

0 0.01 0.02 0.03 0.04 0.05
0
0.5
1
0 0.01 0.02 0.03 0.04 0.05
0
0.5
1
F
a
u
l
t

S
W
Time(s)
T=12.7ms
(a)
Switch on a fault

0 0.01 0.02 0.03 0.04 0.05
-50
0
50
C
u
r
r
e
n
t

(
k
A
)
0 0.01 0.02 0.03 0.04 0.05
-50
0
50
C
u
r
r
e
n
t

(
k
A
)
Time(s)
T=40.8ms
Clear
the
fault
(b)
Phase A
Phase C
47.2kA 37kA
7.8kA

Phase B
Figure 4. 9 Primary Protection for AB Phase to G Fault on Bus4
(a) The instant when fault occurs
(b) Currents from sensors CT7a, b, c
110

0 0.01 0.02 0.03 0.04 0.05
-6
-4
-2
0
2
4
6
V
o
l
t
a
g
e

(
k
V
)
0 0.01 0.02 0.03 0.04 0.05
-6
-4
-2
0
2
4
6
V
o
l
t
a
g
e

(
k
V
)
Time(s)
(c)
Phase A
Phase C
3.4kV
(d)
0 0.01 0.02 0.03 0.04 0.05
0
1
2
3
4
5
Time(s)
T=33.1ms
T=31.9ms
T=32.9ms
CB7 Open
Confirmed
Primary Trip
RelayPri7
CB7
OUTR
BP7

Pri7
(e)
0 0.01 0.02 0.03 0.04 0.05
0
1
2
3
4
5
Time(s)
RelayPri10
CB10
OUTR
BP10

Pri10

Phase B
(c) Voltages measured on Bus 4
(d) Protection response and CB7 status
(e) Protection response and CB10 status
111

0 0.05 0.1 0.15 0.2
0
1
2
3
4
5
Time(s)
(f)
5 cycles
T=0.11s
T=0.12s
RelayPri7
CB7
OUTR
BP
Pri7

(f) Extend Interval of (d)
It takes about 1 cycle for the WADP system to respond to the fault event. At the instant
of T=31.9ms, a trip signal of OUTR=1 was received from the hardware relay, indicating that the
Outmost Ring has seen a fault in the system. At T=32.9ms, primary trip signals (RelayPri7=1,
RelayPri10=1) arrived, requiring to open circuit breakers of CB7 and CB10. They are the circuit
breakers around Bus4. Primary trips got the confirmation from the Outmost ring. Pri7 and Pri10
became logic 1 at T=32.9ms. They are sent to the circuit breaker trip circuits. Estimation on
protection decision interval for this event is 20.2ms [32.9ms (Pri7=1) -12.7ms (Fault Start)
=20.2ms].
Figure 4.9 (f) includes the protection relay status after the fault event. The minimum trip
duration for the two hardware relays was set as 5 cycles. So, the trip signal will last at least 5
cycles once it is initiated. During this interval, both CB open status (CB7=0) and interruption of
fault currents (at T=40.8ms) are not able to unlatch the trip signal. Primary relay reset at T=0.11s
and the Outmost Ring resets at T=0.12s.

Case 2: WADP -- Backup Protection

For this test, the hardware primary relay was disabled to simulate a primary relay failure
event. The same fault as Case 1 (A-B-G fault on bus) was applied.
Figure 4.10 (a) gives the currents measured from sensor CT7 (Figure 4. 1). It showed the
fault occurred at T=22.2ms which caused an increase in the current magnitude in both phase A
112

and Phase B. The fault was eventually isolated at T=149.5ms by the protection trip. This was a
backup trip since the primary trip would be completed within 100ms and a 100ms delay was a
time mark for the backup.

0 0.05 0.1 0.15 0.2
-50
0
50
C
u
r
r
e
n
t

(
k
A
)
0 0.05 0.1 0.15 0.2
-50
0
50
C
u
r
r
e
n
t

(
k
A
)
(a)
Time(s)
T=22.2ms
T=149.5ms

Phase A
Phase C

Phase B
0 0.05 0.1 0.15 0.2
0
1
2
3
4
5
Time(s)
T=41.9ms
T=147.6ms
CB Open
Backup Trip
T=160.9ms
CB7
RelayPri7
OUTR
BP7
Pri7
(b)

Figure 4. 10 Backup Protection for AB Phase to G Fault at Bus4
(a) Currents from sensors CT7a, b, c
Protection response and CB7 status
113

0 0.05 0.1 0.15 0.2
0
1
2
3
4
5
CB10
RelayPri10
OUTR
BP10
Pri10
Time(s)
(c)

(b) Protection response and CB10 status
Figure 4.10 (b) and (c) are pictures associated with the protection responses of the
WADP system. The results are summarized in Table 4. 1.

Table 4. 1 Protection Results for Case 2
Event Signal Instant
Fault Start T=22.2ms
Outmost Ring Relay Trip OUTR=1 T=41.9ms
Primary Relay Trip RelayPri7=1
RelayPri10=1
T=
Confirmed Primary Trip Pri7=1
Pri7=1
T=
WADP Backup BP7=1
BP10=1
T=147.6ms
CB open CB7=0
CB10=0
T=147.6ms
Fault extinguish T=149.5ms

Backup protection tripped CB7 &10 which were the same circuit breakers tripped by the
primary relay in case1. So, the WADP has no overreach phenomena. The backup protection
decision interval for this case is 125.4ms [147.6ms (BP7=1) 22.2ms (Fault Start)=125.4ms].

114

Case 3: Effects of Loss of CT Data on Protection Decision

Simulate a data loss
A switch is inserted between the sensor CT and the D/A interface to simulate a loss of
data event. When the switch is open, sensor outputs are disconnected from the D/A channels and
both hardware relays would read a 0.0 value.

Hardware Relay Operation Mode
Digital differential relays may be able to block the operation under a loss of CT data.
SEL relay also has this function. In relay setting for this test, Outmost Ring relay is set to work
on Non-blocking mode and the primary relay was set to work on (1) non-blocking model (2) and
then blocking mode.

Test Scenarios and Results
Overall performances are evaluated and compared for load condition, local faults and
remote faults. Table 4. 2 gives the test results for a sensor problem associated with CT4a (Figure
4. 1).

Table 4. 2 Test Scenarios and Results Associated with Loss of CT4 Data
Local Faults Remote Fault NO
Fault Fault On Bus2 Fault On Line2 Fault On Bus4
Non-Blocking
Group1 No
Trip
Correct Primary Trip
CB3, 4
False Primary Trip
CB3, 4
Wide Area Primary Trip
CB3, 4,5,7,10
Blocking
Group2 No
Trip
Correct Backup Trip
CB3, 4
Wide Area Backup Trip
CB3, 4, 5
CB7, 10
Group3 No
Trip
Correct Backup Trip
CB3, 4
Sequential Backup Trip
CB4
CB7, 10

Local/remote is with respect to the location of CT4a.
Experiment results show that false trips (Group1_Line2 test) and wide area isolation
(Group1_Bus4 and Group2_Line 2 tests) appeared in Group1 and Group2 tests but Group3 test
115

got all the correct protective actions for scenarios under test.
Results from Group1 test show the primary relay should be disabled when loss of CT
data are detected. The Outmost verification can help with the primary relay passing through a
single contingency such as CT saturation or a loss of CT data. But the verification will not help
when CT problems are accompanied by a fault event since in this case the outmost ring will
become active.
Multiple trips appear on Group2 when the fault is applied on line2. This result shows that
a local CT problem along with a local fault will mislead the augmented ring.
The difference between Group2 and Group3 is that a prior sequential trip strategy was
applied in Group3 when backup protection involved multiple trips. The breaker closest to the CT
giving a zero output was tripped first. Therefore, a minimum isolation area was achieved even
under loss of CT data. In interpreting the results in Table 4. 2 it is necessary to bear in mind that
the system is radial and currents on the downstream side of any fault will be small. Failure of a
single CT/sensor will not cause sufficient differential operating current under load conditions but
may cause a trip when the remaining CTs carry through fault level currents.

116

CHAPTER 5
FUZZY DIFFERENTIAL ALARM SYSTEM
5.1 Introduction

A Fuzzy Differential Alarm System (FDAS) is described in this chapter. The fuzzy alarm
system was built using EMTDC and Matlab software. Its functions are to identify the faulted
section, classify the fault types for a low current fault, and indicate the phases involved.
The fuzzy method is a good tool to deal with the vagueness in the linguistic variable and
the concept without a sharp boundary. In the fuzzy domain, an element can partly belong to a set,
i.e. partially true to a set. So, one can say 151% is 0.99 close to a low fault current set defined
by a threshod of 150%. This kind of description is well suited in the protection-engineering field
since measurement errors, uncertainty and unknown parameters are always present there, leading
to difficulty in using a crisp detection threshold. Problems of using a deterministic only method
for fault detection and classification have already been addressed in papers published recently
[45][46][48]-[52][55]. One example was in the area of transmission line fault classification.
There, fault classification is employed for two main purposes. First, correct determination of the
fault type is a prerequisite for the single-pole tripping and reclosing scheme. Secondly, the fault
classification result is an input for the fault location algorithm in most modern distance relays
[48]. Pradhan et. al.[46], Ferrero et. al [49], Youssef [45][48][55] commented on the drawbacks
of conventional methods and their root causes: the underlying theories for all the deterministic
117

methods (under impedance technique, phase or amplitude comparison and overcurrent
technique) are based on a well-defined model of the system to be protected. They will have
problems when facing the complexity of a real system (mutual coupling from an adjacent line,
effect of remote end infeed, fault resistance, measurement errors, variable operating conditions)
and the lack of knowledge of system parameters. The authors agreed that the situations that are
not characterized by a simple and well-defined deterministic mathematical model, can be more
easily handled in a heuristic approach, in terms of the fuzzy set theory. Fuzzy logic based fault
classification methods were therefore used in their papers.
Another similar argument was in transformer differential protection [47][54]. A typical
task for a transformer differential relay is that it should be able to block the trip introduced by
transient magnetizing inrush current and rapidly operate the tripping during internal faults. The
conventional method uses the 2
nd
harmonic component as a signature for inrush current. A crisp
threshold (7%) is set. Recently, the frequency environment of a power system has become
complicated. At the same time, the 2
nd
frequency component in inrush current has been
decreased due to the improvement in core steel. As a result of that, the traditional approach with
a single crisp threshold setting will be likely to mal-operate in the case of inrush current with low
second harmonic component and internal fault with high second harmonic component. Shin et.
al. [47] therefore proposed a fuzzy logic based transformer differential relay. The idea was that
the fuzzy method could be an alternative to fill the gap, when a clear discrimination detection
boundary cannot be found in the multi-dimensional domain. A fuzzy solution indicates the
most likelihood of an output to a given input pattern. This makes sense in the engineering area.

Though in Ch3, fault classification patterns were given but they were based on a well-
defined system model. CT measurement errors, coupling effects (capacitance between phases),
fault resistance and feeder conditions, all of these factors that affect the performance of the
classification decision on a transmission level, will also have their influences on fault
classification on an ungrounded distribution system. In addition, it is hard to precisely define a
low fault current with a single crisp value, as it is hard to define a low or high 2
nd
harmonic in
the case of transformer protection.
The proposed fuzzy system (FDAS) takes current phasors as inputs and classifies fault
types into three main categories: single phase to ground (PhaseGround or PG), Medium high
118

impedance phase faults (M_PP/G), High high impedance phase faults (H_PP/G). In each
category, phases involved in the fault will be also identified. The fault classification algorithm is
based on the angular difference among the sequence components of the fundamental differential
current as well as on their relative magnitudes. The angle difference and relative magnitude are
described by fuzzy variables to allow for a range of variations introduced by uncertainties in a
real power system. The fault patterns derived in ch3 are translated into fuzzy IF-Then rules.
Mamdans mechanism [55] is chosen for the fuzzy inference. The proposed fuzzy system was
tested with data generated from ungrounded power systems simulated in EMTDC.
5.2 Fundamentals on Fuzzy Inference System
5.2.1 Classical Sets and Fuzzy Sets
In a classical (crisp, hard) set [58], a given element (x) is either a member of or not a
member of a set A. Mathematically, it is expressed as:
1 if and only if x A
( )
0 if and only if x A
A
x

=

where, (x)
A
is the characteristic function of a crisp set A and its value is 1 or 0.
Zadeh (1965) [57][59] introduced fuzzy sets as an extension of a crisp set. He extended
the notion of binary membership value (1 or 0) to a real value in a continuous space of [0, 1].
Under his concept, there is an infinite number of values between [0, 1] that can represent a
degree of membership for an element x to a given fuzzy set A, where the endpoints 0 and 1
conform to no membership and the full membership. A fuzzy set , is expressed as:
{ ( x, (x) ) | x U }
A
A =

where, (x)
A
is the characteristic function (or the membership function) of A and its value is
between [0, 1]. U is the universe of discourse.
5.2.2 Membership Functions

A membership function (MF) is a curve that defines how each point in the input space is
mapped to a membership value between 0 and 1. The function itself can be an arbitrary curve,
linear or non-linear, as long as the membership value sits between 0 and 1. The membership
119

function is usually determined by human expertise and observations on the available data. In the
FDAS system, triangular shaped and trapezoidal-shaped membership functions are used. The
triangular membership function is to describe the linguistic terms of close to and
approximately and the trapezoidal membership function is to define the linguistic terms of less
than and larger than.
5.2.2.1 Triangular Membership Function tri_mf (x; A, B, C)
0 x
A x
_ ( ; , , )
B x
0 C x
A
x A
B
B A
tri mf x A B C
C x
C
C B

A general triangular function is shown Figure 5. 1. The function can be completely
defined by three scalar parameters A, B and C.

A
B
C
1.0
x
x

Figure 5. 1 Triangular Fuzzy Membership Function
120

5.2.2.2 Trapezoidal Membership Function trap_mf (x; A, B, C, D)
0 x
A x
_ ( ; , , , ) 1 B x C
C x D
0 D x
A
x A
B
B A
trap mf x A B C D
D x
D C

A
B C
1.0
x
x
D

Figure 5. 2 Trapezoidal Fuzzy Membership Function
A general trapezoidal function is shown Figure 5. 2. The function depends on four scalar
parameters A, B, C, and D.
5.2.3 Fuzzy Logic Operations
Let a fuzzy set A be defined as: A , and a fuzzy set
{ ( x, (x) ) | x U }
A
=

be
defined as . { ( x, ) ) | x U }
B
B =
(x
Intersection (AND)
Let the fuzzy set C be the intersection of two fuzzy sets A and

B
, then C is expressed
as: C A
AND = { (x, (x) =min { (x), (x)} | x U}

B C A
B =

121

Union (OR)
Let the fuzzy set be the unit of two fuzzy sets and C
, then C is expressed as:
OR = { (x, (x) =max { (x), (x)} | x U}

B C A
C A B =

Complement (NOT)
Let a fuzzy set A be the complement of a fuzzy set A, then A is expressed as:
{ ( x, (x) 1 (x)) | x U }
A A
A = = .

The reader may refer to [58] and [60] for a detailed description of fuzzy set operations
that can be performed.
Operations AND= Min, OR=Max are usually called as classical operators [59], and they
are used in the FDAS system.
5.2.4 Fuzzy IF _Then Rules
A fuzzy IF-Then rule is expressed as:
IF <fuzzy proposition>, THEN <fuzzy proposition>.
Propositions are linguistic variables. Examples of these linguistic variables are slow,
medium, high, approximately and very. There could be a combination of these variables, very
slow and so on.
A general IF-THEN rule for a fault classification problem [53] formed in the FDAS, is
written as:

Rule R
j
: If x
1
is A
j1
and and x
n
is A
jn

Then, the fault is C
j
, j=1,2, N
where:
x=(x
1, ,
x
n
) input attribute factors;
A
ji
antecedent linguistic value such as approximately
or close to;
C
j
consequent class (i.e., one of the given fault types);
N number of fuzzy IF-THEN rules.

In the FDAS system, the rules were formed on the basis of differential fault patterns
derived in ch3 and their combination factors given in section 4.3.
122

5.2.5 Fuzzy Inference System
Fuzzy inference systems (FIS) employ the fuzzy set theory and fuzzy if-then rules to
reason about data, deriving an output and making a decision. The steps [48] include
fuzzification, fuzzy inference and defuzzification (Figure 5. 3).

Fuzzification
Fuzzy
Inference
Fuzzy Rule
Base
Defuzzification
System
Characteristic
Description
Input
Output
P
Q R
S

Figure 5. 3 Fuzzy Inference System
5.2.5.1 Fuzzification
The fuzzification process is for transforming the engineering input data into fuzzy
variables. These variables are the linguistic terms that constitute the antecedence of fuzzy rules.
So, fuzzification is a pre-step toward the fuzzy rule evaluation. During the fuzzification process,
the input values are compared with their membership functions and the membership values are
obtained for each linguistic term. Before the fuzzification, it is a crisp value (point P in Figure 5.
3) and after the fuzzification, it becomes a fuzzy value (point Q in Figure 5. 3).
5.2.5.2 Fuzzy Inference
After fuzzification, the fuzzified inputs are given to the fuzzy inference engine for fuzzy
reasoning. Rules are evaluated. The truth-value for the antecedence of each logic rule is
computed and applied to the consequence part of each rule. Then, one fuzzy set is assigned to
123

each output variable for each rule. This is the implication process. When more than one rule is
fired at the same time, a super fuzzy set is generated as a result of an overall evaluation. Its the
composition process. Different fuzzy inference mechanisms exist and their differences are in the
way how to mathematically perform implication and composition. Two classical mechanisms are
Mamdanis inference mechanism and Takagi-Sugenos mechanism. The FDAS applies the
Mamdanis inference mechanism. It is also known as Max Min method in that implication is
modeled by means of a minimum operator, and composition is modelled by a maximum
operator. Takagi-Sugenos mechanism is not used here because it requires that the output of each
rule is a linear combination of input variables plus a constant term, which is not the case for the
FDAS. Other inference mechanisms which have been discussed are Tsukamotos and Larsens
[54]. Tsukamotos was not adequate for power system relaying purposes and Larsens achieved
the same results as Mamdanis.
5.2.5.3 Defuzzification
The output from the inference engine is a fuzzy set. It has to be converted to a crisp
value. Defuzzification is the mathematical process whereby a fuzzy membership function is
reduced to a single scalar quantity that best summarizes the function.
There are several commonly used defuzzification formulas:
(1) The centroidal formula
( )
( )
U
U
x M x dx
A
M x dx
;
(2) The Maximum formulas
It chooses a point at which the associated membership function achieves its maximum
value. If more than one point satisfies this condition, then the Maximum, or Minimum, or Mean
of all such points is taken.

Of the various methods of defuzzification, the centroidal method is intuitive since it
represents the center of gravity of the area defined by the membership function, which is
therefore used in the FDAS.
124

5.3 Differential Fault Classifier Factors
The analysis of the fault differential sequence components in chapter 3, gives information
about the nature of the fault. This information is used in this section for faulted section
identification and fault type classification. The algorithm is based on the angular difference
among the sequence components of the fundamental differential current as well as on their
relative magnitudes.
5.3.1 Differential Magnitude Factors
Differential magnitude factors are defined as magnitude ratios of sequence differential
currents. These factors are to determine two things:
(1) Internal fault (INF) or external fault (EXF);
(2) Phase to ground fault (PG) or phase to phase fault (PP) or three phase fault (PPP);
Table 5. 1 lists possible combinations of magnitude factors. These ratios are ratios
between sequence fault differential currents, and ratios of sequence fault differential currents to
prefault positive differential current.

Table 5. 1 Choices of Differential Magnitude Factors
Type of
fault

0_
1_ Pr
Post
e
Id
Id

1_
1_ Pr
Post
e
Id
Id

2_
1_ Pr
Post
e
Id
Id

0_
1_
Post
Post
Id
Id

2_
1_
Post
Post
Id
Id

2_
0_
Post
Post
Id
Id

INF
II
I
C
C
2+
II
I
C
C
1+
II
I
C
C

2
II
I I
C
C C +
I
2
I II
I I
C C
C C
+
+
I
1+
II
I
C
C

PG
EXF 1 1 Small 1 0 0
INF 0
I
XC
Zf

I
XC
Zf

0 1 --
PP
EXF 0 1 Small 0 Small --
INF 0
I
XC
Zf

0 0 0 --
PPP
EXF 0 1 Small 0 Small --

125

0_
1_ Pr
Post
e
Id
Id
, Magnitude ratio of zero sequence fault differential current to pre fault positive
differential current;

1_
1_ Pr
Post
e
Id
Id
, Magnitude ratio of positive sequence fault differential current to pre fault positive

2_
1_ Pr
Post
e
Id
Id
, Magnitude ratio of negative sequence fault differential current to pre fault positive

0_
1_
Post
Post
Id
Id
, Magnitude ratio of zero sequence fault differential current to positive sequence fault

2_
1_
Post
Post
Id
Id
, Magnitude ratio of negative sequence fault differential current to positive sequence
fault differential current;

2_
0_
Post
Post
Id
Id
, Magnitude ratio of negative sequence fault differential current to zero sequence
fault differential current;
, Stray capacitance of protected section and its capacitive reactance; ,
I
C XC
I
, Stray capacitance of the rest of system;
II
C
Zf , Fault impedance;

Results in Table 5. 1 show that
0_
1_ Pr
Post
e
Id
Id
,
0_
1_
Post
Post
Id
Id
, and
2_
0_
Post
Post
Id
Id
are not good for
classification purposes since they can neither distinguish an external fault from an internal fault
nor distinguish PP from PPP. On the other hand, information in factors
1_
1_ Pr
Post
e
Id
Id
,
2_
1_ Pr
Post
e
Id
Id
and
126

2_
1_
Post
Post
Id
Id
, indicates the internal fault and fault type. But there is no necessity to use all three
factors since these three factors are dependent, i.e.,
2_
1_ Pr
Post
e
Id
Id
=
2_ 1_
1_ 1_ Pr
Post Post
Post e
Id Id
Id Id
. In the FDAS,
1_
1_ Pr
Post
e
Id
Id
and
2_
1_
Post
Post
Id
Id
are chosen as differential magnitude factors.
5.3.2 Differential Angle Factors
Differential angle factors are defined as angle difference between sequence fault
differential currents. These factors are to identify phases involved in the fault.
Table 5. 2 lists the candidates.

Table 5. 2 Choice of Differential Angle Factors (In degree)
TYPE OF
FAULT
0_
1_
arg( )
Post
Post
Id
Id

2_
1_
arg( )
Post
Post
Id
Id

0_
2_
arg( )
Post
Post
Id
Id

AG
0

BG
120

120
120

CG
120
120
120

AB/G --
60

--
AC/G
60

BC/G --
180

--
ABC -- -- --

0_
1_
arg( )
Post
Post
Id
Id
, Angle difference between zero sequence fault differential current to positive
sequence fault differential;
2_
1_
arg( )
Post
Post
Id
Id
, Angle difference between negative sequence fault differential current to positive
127

0_
2_
arg( )
Post
Post
Id
Id
, Angle difference between zero sequence fault differential current to positive

In the case of a phase-to-phase fault and a three-phase fault, no zero sequence differential
current is generated so one can not calculate the differential angle factor. Therefore, only
2_
1_
arg( )
Post
Post
Id
Id
is feasible. Fortunately, information on
2_
1_
) arg(
Post
Post
Id
Id
, already picked up all the
phase patterns.
5.3.3 Differential Fault Classifier Factors
The FDAS classifies faults into three categories and twelve types. Three categories are
single phase to ground fault, Medium high impedance phase fault, High high impedance
phase fault. Twelve types of faults are:
Phase-A-Ground (AG);
Phase-B-Ground (BG);
Phase-C-Ground (CG);
Medium high impedance Phase A-B fault (M_AB);
Medium high impedance Phase A-C fault (M_AC);
Medium high impedance Phase B-C fault (M_BC);
Medium high impedance Phase A-B-C fault (M_ABC);
High high impedance Phase A-B fault (H_AB);
High high impedance Phase A-C fault (H_AC);
High high impedance Phase B-C fault (H_BC);
High high impedance Phase A-B-C fault (H_ABC);
External fault (External).

Three differential fault classifier factors are used to identify these twelve types of faults.

Table 5. 3 lists their typical values for each type of fault.

128

Table 5. 3 Differential Fault Classifier Factors

Ratio_1 Ratio_2

Angle

Type of
Fault
1_
1_ Pr
Post
e
Id
Id

2_
1_
Post
Post
Id
Id

AG
2+ 1 1
II
I
C
K
C
= +
1
2 1
I II
I II
C C K
C C K 1
+
=
+ +
0
BG 1 1 K + 1
1 1
K
K +

120
CG 1 1 K + 1
1 1
K
K +

-120
M_AB
I
XC
Zf
>K2
1 60
M_AC
I
XC
Zf
>K2
1 -60
M_BC
I
XC
Zf
>K2
1 180
M_ABC
I
XC
Zf
>K2
0 ---
H_AB
I
XC
Zf
<=K2
1 60
H_AC
I
XC
Zf
<=K2
1 -60
H_BC
I
XC
Zf
<=K2
1 180
H_ABC
I
XC
Zf
<=K2
0 ---
External 1 --- ---
2_
1_
arg( )
Post
Post
Id
Id

There are two setting values for classifier factors K1 and K2. K1 is the ratio of
capacitance between the entire circuits and the protected circuit. It can be roughly estimated as
numbers of feeders in the ungrounded circuits assuming that these feeders are equal in length.
129

More accurate value can be obtained by using information on the cable length. The default value
for K1 is 2.
K2 is the parameter for description of a high impedance fault. As discussed in section
3.8, this value indicates that under a medium high impedance phase fault, detectable
differential currents produced will still be larger than K2 times nominal leakage currents. The
default value for K2 in the FDAS is 20.
5.4 Fuzzy Classification Rules
5.4.1 Fuzzy Rules
Based on the fault characteristics and differential fault classifier factors, fuzzy rules are
defined.

Rule1 -- Internal AG Fault
If Ratio_1 is approximately K1+1 and Ratio_2 is approximately K1/(K1+1) and angle
is approximately , then it is an internal AG' fault.
0
0

Rule2 -- Internal BG Fault
is approximately120 , then it is an internal BG' fault.
0

Rule3 -- Internal CG Fault
is approximately , then it is an internal CG' fault.
0
120

Rule4 -- Internal M_AB/G Fault
If Ratio_1 is larger than K2 and Ratio_2 is approximately 1 and angle is
approximately , then it is an internal M_AB/G' fault.
0
60

Rule5 -- Internal M_AC/G Fault
130

approximately , then it is an internal M_AC/G' fault.
0
60

Rule6 -- Internal M_BC/G Fault
approximately180 , then it is an internal M_BC/G' fault.
0

Rule7 -- Internal M_ABC Fault
If Ratio_1 is larger than K2 and Ratio_2 is approximately 0then it is an internal
M_ABC' fault.

Rule8 -- Internal H_AB/G Fault
If Ratio_1 is less than K2 and Ratio_2 is approximately 1 and angle is
approximately , then it is an internal H_AB/G' fault.
0
60

Rule9 -- Internal H_AC/G Fault
approximately , then it is an internal H_AC/G' fault.
0
60

Rule10 -- Internal H_BC/G Fault
approximately180 , then it is an internal H_BC/G' fault.
0

Rule11 -- Internal M_ABC Fault
If Ratio_1 is less than K2 and Ratio_2 is approximately 0then it is an internal
H_ABC' fault.

Rule12 -- External Fault
If Ratio_1 is approximately 1, then it is an external fault.

131

5.4.2 Descriptions for Fuzzy Variables
In the above fuzzy rules, the variables in the antecedent parts are all fuzzy variables; the
variables in the consequent parts should be represented by fuzzy variables too. To represent all of
these fuzzy variables (in both antecedent and consequent parts of the fuzzy rules), the triangular
and trapezoidal membership functions are used.

Membership Functions (MFs) for Input1:
The input 1 (Ratio_1) is described by fuzzy variables Approximately 1, Approximately
K1+1, Less than K2 or Larger than K2. A triangular function is the appropriate function to
cope with the term of Approximately, just simply putting the numeric value at the center of the
triangle (B point in Figure 5. 1) and then allowing +/- 50% percent of errors to form the other
two points (A and C in Figure 5. 1). Membership function (mf1) for Approximately 1 and
membership function (mf2) for Approximately K1+1 are shown in Figure 5. 4, where K1=2.
The range of influence of the third mf will extend from very small positive value to
values less than K2, while the influence of the fourth mf extends from larger than K2 to large
values. A trapezoidal function is the appropriate function to deal with this situation. Figure 5. 4
plots mf3 and mf4 for K2=20.

0.51.5 3 4.5 15 25 30
0
0.2
0.4
0.6
0.8
1
mf1 mf2 mf3
Ratio_1

mf4
Figure 5. 4 Membership Functions for Input 1 (Ratio_1)
132

Membership Functions for Input2:
The formulation of the mfs for Input 2 (Ratio_2) is based on the fact that the input2 is
Approximately 0, Approximately K1/(K1+1), or Approximately 1. Three triangular
functions (mf1, mf2, mf3) are defined to represent the terms (Figure 5. 5). Allowable error is +/-
. For Approximately 0, it extends from 0 to 0.1. 50%

0 0.1 0.3 0.5 0.7 1 1.5 2
0
0.2
0.4
0.6
0.8
1
mf1 mf2
Ratio_2

mf3
Figure 5. 5 Membership Functions for Input2 (Ratio_2)
Membership Functions for Input3:
The input 3 (angle) is described by fuzzy variables of Approximately ,
Approximately , Approximately 0 , Approximately 60 , Approximately 120 , or
Approximately 180 . So, six triangular functions (mf1, mf2, mf3, mf4, mf5, mf6) are defined
to represent the terms (Figure 5. 6). Allowable angle error is +/- .
0
120
0 0
60
0
0 0
0
30

Membership Functions for Outputs:
Outputs are fault types. There are twelve fault types in the FDAS so twelve mfs are
required. Triangular functions are chosen to represent fault types. The binary coding technique
discussed in [48] is used in the FDAS to systematically generate the numeric values for fault
133

-150 -120 -90 -60 -30 0 30 60 90 120 150 180
0
0.2
0.4
0.6
0.8
1
mf1 mf3 mf4 mf5 mf6
Angle

mf2
Figure 5. 6 Membership Functions for Input 3 (Angle)
types. The coding system uses a 4 bit binary number (D
3
D
2
D
1
D
0
) to represent a fault type. The
bit D
0
represents the ground or high, the bit D
1
represents the phase A, the bit D
2
represents the
phase B, and the bit D
3
represents the phase C. Hence, a phase to ground fault (AG) is coded
as 0-0-1-1. The numeric value is 3. Similarly, a Medium high impedance phase A-B fault
(M_AB) is coded as 0-1-1-0 and the numeric value is 6. The complete coding for all fault types
is listed in Table 5. 4.

Table 5. 4 Fault Type Coding
Fault Type D
3
D
2
D
1
D
0
Coding
AG 0 0 1 1 3
BG 0 1 0 1 5
CG 1 0 0 1 9
M_AB 0 1 1 0 6
M_AC 1 0 1 0 10
M_BC 1 1 0 0 12
M_ABC 1 1 1 0 14
H_AB 0 1 1 1 7
H_AC 1 0 1 1 11
H_BC 1 1 0 1 13
H_ABC 1 1 1 1 15
External 0 0 0 1 1

134

These numeric values form the middle points for the triangular functions (point B in
Figure 5. 1). Another two points of a triangular function (point A and point C in Figure 5. 1) are
displayed symmetrically on the two sides. Table 5. 5 lists their values.

Table 5. 5 Fuzzy Variable Representing Fault Type
Triangular Membership Function Fault Type
A B C
AG 2.5 3 3.5
BG 4.5 5 5.5
CG 8.5 9 9.5
M_AB/G 5.5 6 6.5
M_AC/G 9.5 10 10.5
M_BC/G 11.5 12 12.5
M_ABC 13.5 14 14.5
H_AB/G 6.5 7 7.5
H_AC/G 10.5 11 11.5
H_BC/G 12.5 13 13.5
H_ABC 14.5 15 15.5
External 0.5 1 1.5

5.5 Fuzzy Differential Alarm System
5.5.1 Fuzzy Differential Alarm System
The proposed fuzzy differential alarm system will identify three categories of faults, give
an alarm signal for the phases involved in the fault, and back-up for clearing Medium high
impedance phase-phase faults. The fuzzy inference system constitutes the core of the FDAS. It
reasons from the data and classifies the fault type. The fuzzy inference system of the FDAS was
programmed with Matlab software. Other functional blocks in the FDAS include sensors (data
acquisition), signal conditioning, feature extraction and post-processing.
Sensors or Data Acquisition
The data collected from the sensors provide inputs to the FDAS. The FDAS needs two
types of input signals. Power system current signals are used for fault classification. The raw
data are analogue types and collected from Current Transformers (CTs). It also needs an activate
135

signal, which triggers the FDAS to work. This signal could come from a zero sequence voltage
detector or a manual switch. The signal is a digital type.
The FDAS can also work on an offline mode of operation. Under this mode, the FDAS
can use the data from fault recorders.
Signal Conditioning
The signal conditioning operation modifies the raw measurements obtained from the
power systems in a useful way. The basic process includes filtering, A/D, DFT to extract
fundamental phasor signals and symmetrical transformation to get sequence current phasors.
The last two steps were modelled in EMTDC. The power system circuits modelled in EMTDC
generate digital signals directly so there is no need for A/D and the pre-filtering associated with
it. To completely suppress the transient effect introduced by switching on a fault, a 50ms delay
was inserted in the FDAS.
Feature Extraction
This is to calculate the differential fault factors.
Post-processing
Once an internal fault had been identified, it saves the results and initiates an alarm or trip
signals. The output signals are digital types.
The fuzzy differential alarm system is described in Figure 5. 7.

5.5.2 Case Studies
Fault data with different system conditions generated by EMTDC are used as inputs to
the FDAS for testing the effectiveness of the proposed classification algorithm. Faults with each
having an impedance of Rf=0.01, 100, 1000, or 5000ohm were applied at five locations (F1 to
F5 discussed in Ch3.) Then data were recorded and fed into FDAS for evaluation.

Phase-A-Ground Fault
Figure 5.8 gives line currents and phase voltages for an AG fault. Sa, Sb, Sc, Ra, Rb, and
Rc are currents measured at both ends. Ea, Eb, and Ec are voltages measured at bus1 location
(see ch3 Figure 3.2). Voltage waves show that a fault was initiated at 0.2s.
136

Sensors
(CTs)
Matlab
Program
EMTDC
Program
Events
Actions
1. Save Fault
Data
2. Save Classifi-
cation Results
3. Alarm or
Delayed Trip
Post-
Processing
Signal
Condition
-ing
1. Filtering
2. A/D
3. FFT
4. Symmetrical
Transformation
Feature
Extraction
Differential Fault
Factors
1. Ratio _1
2. Ratio_2
3. Angle
Fuzzy
Inference
System
1. Fuzzy Variables
2. Membership
Functions
3. Rule Base
4. Fuzzy Inference
5. Defuzzication
0: Settings
(K1, K2)
Alarm
Trips

Figure 5. 7 Fuzzy Differential Alarm System
137

0 0.05 0.1 0.15 0.2 0.25 0.3
-400
-200
0
200
400
Sa
Sb
Sc
S
e
n
d
i
n
g

E
n
d
C
u
r
r
e
n
t

(
A
)
Time (s)

0 0.05 0.1 0.15 0.2 0.25 0.3
-400
-200
0
200
400
Ra
Rb
Rc
Time (s)
R
e
c
e
i
v
i
n
g

E
n
d
C
u
r
r
e
n
t

(
A
)

(a)

0 0.05 0.1 0.15 0.2 0.25 0.3
-20
-10
0
10
20
Ea
Eb
Ec
Time (s)
V
o
l
t
a
g
e

(
k
V
)

(b)
Figure 5. 8 Voltages and Currents for AG fault at F1 with Rf=0.01ohm
(a) Currents
(b) Voltages

138

0 0.05 0.1 0.15 0.2 0.25 0.3
0
0.1
0.2
0.3
0.4
0.5
Id1-Mag
Id1-Mag-Pre
Id1-Mag-Post
Time (s)
C
u
r
r
e
n
t

(
A
)

0 0.05 0.1 0.15 0.2 0.25 0.3
-20
0
20
40
60
80
100
Id1-ph
Time (s)
A
n
g
l
e

(
D
e
g
r
e
e
)

0.2 0.21 0.22 0.23 0.24 0.25 0.26 0.27 0.28 0.29 0.3
0
0.1
0.2
0.3
0.4
0.5
Id2-Mag
Time (s)
C
u
r
r
e
n
t

(
A
)

0.2 0.21 0.22 0.23 0.24 0.25 0.26 0.27 0.28 0.29 0.3
0
50
100
150
Id2-ph
Time (s)
A
n
g
l
e

(
D
e
g
r
e
e
)

Figure 5. 9 Magnitudes and Angles for Positive Sequence Differential Current
And Negative Sequence Differential Current
139

Figure 5. 9 shows estimated fundamental differential sequence current phasors, in
magnitude and in angle quantities respectively. For positive sequence differential current, the pre
fault value is plotted as well, since it is used in calculating the decision factors.

Figure 5. 10 shows the calculated differential fault factors. These factors lead to the
classification result of An Internal AG Fault.

0.25 0.26 0.27 0.28 0.29 0.3
2.4
2.45
Ratio-1
Time (s)
S
c
a
l
e
0.25 0.26 0.27 0.28 0.29 0.3
0.59
0.595
0.6
Ratio-2
Time (s)
S
c
a
l
e
Appro.K1+1
Appro.K1/(K1+1)

Time (s)
D
e
g
r
e
e
0.25 0.26 0.27 0.28 0.29 0.3
4.5
4.55
4.6
Ang
Appro.0

Note: K1=2.

Ratio_1= 2.418
Ratio_2= 0.591 2.996 - IN_AG
Ang = 4.563

Figure 5. 10 Differential Fault Factors and Classified Results
Table 5.1 -- Table 5.3 summarizes test results for BG, CG, M_AB to H_ABC, all twelve
types of classified faults. The FDAS correctly identified them.

140

Table 5.1 Fuzzy Outputs Corresponding to
Internal Phase _Ground Fault with Rf=0.01
Factors AG BG CG
Ratio_1
2.418 2.418 2.418
Ratio_2
0.591 0.591 0.591
Ang
4.563 124.563 -115.437
Fuzzy Output
2.996 5.00 8.996

Internal Phase Faults with Rf=100 and Rf=1000
Factors M_AB M_AC M_BC M_ABC
Ratio_1
41.972 41.973 41.973 41.977
Ratio_2
0.992 0.992 0.992 0.000
Ang
58.713 -61.287 178.713 200.875
Fuzzy Output
5.995 10.005 11.995 14.000

Internal Phase Faults with Rf=5000
Factors H_AB H_AC H_BC H_ABC
Ratio_1
8.678 8.678 8.679 8.679
Ratio_2
0.956 0.956 0.956 0.000
Ang
53.763 -66.237 173.763 190.975
Fuzzy Output
7.006 11.000 13.005 14.995

141

CHAPTER 6
CONCLUSIONS AND FUTURE RESEARCH
This dissertation presents three differential theories and two applicable systems outlined
below for use in protecting a power system on board a ship. The objectives and goals of this
research have been accomplished. This section starts with a summary of the main contributions
of this work and finalizes with the recommended direction for the future research.

Main contributions
Theory 1: symmetrical component based differential fault characteristics analysis for an
ungrounded ship power system. The symmetrical component method is used and differential
fault patterns on an ungrounded ship power system are established.
Fault analysis today is mostly using simulations or fault analysis software. This
dissertation, however, chooses to use an analytical approach. The reasons are: (1) analysis can
find the mathematical relationship between differential fault current and system parameters.
Simulations or software studies, on the other hand, cannot provide it directly. (2) Ungrounded
power system simulation requires personnel with a knowledgeable understanding of the
characteristics for an ungrounded system. Existing simulation packages are all for ground system
study. To form an ungrounded system, those grounding points across the system have to be
isolated or lifted. Without the knowledge, a blind mind usually will leave a grounded system or
an incorrect ungrounded system. (3) The size of the ship type system is not large and its structure
is not complex which makes the analytical calculation possible.
142

In this dissertation, the fault analysis was carried out by hand derivation. The analysis
gives detailed fault differential characteristic patterns associated with fault types and fault
locations. Each fault pattern is expressed by a characteristic formula in terms of distributed
capacitance, system impedances and fault resistance. The analysis in the end leads to a
conclusion that sequence differential quantities can be used to sensitively detect the ground faults
and high impedance phase faults; and phase differential quantities are good for phase fault
detection.
The first theory is the fundamentals for fault detection in this dissertation.

Theory2: fuzzy differential fault detection and classification theory. Differential fault
classifier factors are identified and a fuzzy-rule base is formed.
Instruments and detectors currently installed on board a ship for ground fault detection
have lots of trouble in correctly doing their work. In a recent seminar held in CAPS on Feb. 03,
2006 on the topic Galvanic Isolation and Control Issue, Tom Fikse, a former system test
engineer, pointed out the serious consequences of failure to detect a single line to ground fault at
the first place and listed a number of associated system testing failure examples. The Navy looks
for new methods in this area.
The second theory studies a new detection approach. The new fault detection method is
based on the angular difference among the sequence components of the fundamental differential
current as well as on their relative magnitudes. They are defined as differential fault classifier
factors. Each factor is then described by a fuzzy variable to allow for a range of variations
introduced by uncertainties that may appear in a real power system. The fault patterns coming
from the first theory are translated into fuzzy IF-Then rule for fault detection and classification.

Theory3: wide area differential protection (WADP). The differential ring principle is
introduced and a wide area differential protection scheme is formed.
The WADP system has three objectives (1) to solve the short-cable problem; (2) to get
rid of those false trips due to measurement sensor failures; (3) to form a backup protection and
achieve minimum protection isolation.
The differential ring principle covers all needs of these three tasks. Differential type of
detection avoids the troubles from the short-cable problem. Verification coming from another
143

differential ring around the system can prevent a local false trip due to sensor problems.
Differential ring extends the differential comparison region to a wide area, which allows a
backup scheme to be formed using the differential principle. Differential backup protection
includes a differential ring fault location algorithm to find the exact faulted component so backup
protection trips the minimum region.

Based on three theories, two applicable fault detection and protection systems are tested:
A real time wide area differential protection (WADP) system which is for fast
clearing of phase type faults;
A simulated fuzzy based differential alarm system (FBDA) which is for handling low
fault current cases, including single line to ground faults.

Future Research
Fuzzy Differential Alarm System (FDAS)
The FDAS design developed in this dissertation was limited by the system data and fault
data available for access. The FDAS design could be expanded if the methodology is tested with
more advanced system model (such as phase-phase capacitances) or with fault data recorded
from a navy system that contains more detailed characteristic information about a navy ship
environment. Sensitivity issue will be studied when fault data are available for access.
Differential fault detectors developed in this dissertation currently includes three factors:
1_
1_ Pr
Post
e
Id
Id
,
2_
1_
Post
Post
Id
Id
and
2_
1_
) arg(
Post
Post
Id
Id
. A number of other different combinations of phasor ratio
and angle ratio could be added in order to enhance the reliability and sensitivity of the FDAS.
To continue this research, collaboration with the navy and industries are strongly
recommended. The common interest among the navy and the utilities regarding this topic could
be exploited and deployed in a research project. Ground fault detection experiences from both
sides and the theory developed in this dissertation can be combined into a common objective.

Wide Area Differential Protection (WADP) System
144

The WADP system came from the navy needs. The WADP design demonstrated a best
balance between dependability and security involved in the protection design. Defects in a local
protection circuit or its auxiliary equipment can be compensated by the information shared
among the neighboring area. The cost is a wide band communication network but it is not
additional investment for the navy since they need this network for control center and command
center in any case.
Thus, it is believed that the direction for further research should go towards the design
and development of an open WADP shell. To continue this research, collaboration with the navy
and a relay manufacturer company is highly recommended. In the future research project, CAPS
can develop an open WADP GUI environment; the relay manufacture company should be able to
provide an open relay shell that can contain the WADP codes download from the GUI
environment. The overall test will be carried out by the navy side.

Part of this research work was submitted to the IEEE conferences and journal paper. It
was well received. Utility today is facing the similar problem as the navy has: Demanded
Power! Navy consideration is from the load side. Critical load requires to be fed for 100 percent
of the time. Utility s concern is from the generation viewpoint. There is not much reserved
power available like what we had in 1960s. Unnecessary tripping of transmission lines shakes
the stability of the entire networks. The issue of re-think on the philosophy of the protection
schemes and adaptation them to the current demands of the power system and state of the
technology has been on discussion in IEEE power system relaying committee. This dissertation
presents a frontier work in this direction. For utility application of the WADP system, future
research should toward identifying a desirable differential ring formation mechanism around
large networks and studying the communication associated difficulties.

145

APPENDIX A
SHIPBOARD TESTBED SIMULATED
CT3
Busbar 01
T2
03
CT10
CT5
CT6
CT7
04
05
02
G
C1
C2
T1
CT11
CT8
CT9
CT1
M1
M2
CT2
CT4
CB4
CB1
CB2
CB5
CB3
CB6
CB7
CB10

Figure A. 1 Shipboard Testbed Simulated

146

Where:

G Generator 13.8kV/10MVA/Xd=0.2p.u
CTn Current Transformer n Three phases
CBn Circuit Breaker n Three phases
C1 Cable 1 36 feet, X1=0.042ohm/1000feet
C2 Cable 2 16 feet, X1=0.042ohm/1000feet
T1 Transformer 1 13.8kV/0.48kV, /, 1.825MVA, X1=0.2p.u
T2 Transformer 2 13.8kV/4.16kV, /, 10MVA, X1=0.08p.u
M1 Load 1 8MW static load
M2 Load 2 0.8MW/0.6Mvar Static load
147

APPENDIX B
Symmetrical Components Fault Analysis
The symmetrical components method is used for analyzing unbalanced faults and
unbalanced system conditions. For a three-phase balanced system, the analysis is usually applied
on a per phase based circuit. Results from that per phase system are then extended to the other
two phases by shifting +/- 120 on the phase angles. The symmetrical components allow
unbalanced phasor quantities to be replaced by three separate balanced symmetrical components.
In this way, a per phase based calculation can also be carried on a three-phase unbalanced
system.
The fundamental theory was published by C.L. Fortecue in 1918. He proposed that a
system with an unbalanced set of n phasors could be resolved into n-1 balanced n phase systems
of different phase sequence and one zero-phase sequence system [43]. In a three-phase system
the phase sequences are defined as: Positive, Negative and Zero sequence phasors. They are the
symmetrical components (Figure B. 1 (a, b, c)) referred to in this dissertation. A positive
sequence set defines a balanced three phase system with a phase sequence abc; an negative
sequence set consists of a balanced set with phase sequence acb; zero sequence phasors are in
phase and equal in magnitude.
The mathematical relationship between phase values and symmetrical component values
can be expressed as equations (B. 1) and (B. 2)[43][44]. Current quantities are used here for
example. Sequence components can be voltage and impedance components as well. Once all the
quantities (voltages, currents, impedances) are expressed in the sequence variables, fault analysis
can be performed on an equivalent sequence network, instead of on an unbalanced system itself.
148

The symmetrical components fault analysis procedure involves three steps:
(1) Sketch positive, negative, zero sequence system networks;
(2) Determine a proper interconnection to form an equivalent sequence network;
(3) Calculate sequence fault quantities, and then transform them back to phase values.
This procedure is followed in section 3.5 and 3.6 for deriving fault characteristic
formulae.

Ia0=Ib0=Ic0
Ia1
Ib1
Ic1
(a) (b) (c)
0 refers to Zero sequence
1 refers to Positive sequence
2 refers to Negative sequence
120
Ia2
Ib2
Ic2
1
2
0

Figure B. 1 Sequence Components
(a) Positive Sequence Currents
(b) Negative Sequence Currents
(c) Zero Sequence Currents

0
2
1
2
2
1 1 1
1 ;
1
a
a
a
IA I
IB a a I
IC a a I
( ( (
( ( (
=
( ( (
( ( (

(B. 1)
0
2
1
2
2
1 1 1
1
1 ;
3
1
a
a
a
I IA
I a a IB
I a a IC
( ( (
( ( (
=
( ( (
( ( (

(B .2)
149

a0 a1 a2
Where,
IA, IB, IC, are three phase current phasors;
I , I , I , are sequence currents referred to phase A. For the convenience, 'a' is
often omitted when phase A is referred to and this res
0 1 2
ults in (I , I , I );
a=1 120 ;

150

APPENDIX C
WADP EXPERIMENTAL SETUP
Hardware Relay Configuration
Two relays in use are SEL manufactured SEL487B digital relays [61]. SEL487B relay is
a differential relay and designed for bus differential protection. In the experiment, it was
reconfigured for the WADP purpose.

Relay 1
One SEL-487B (relay1 in Figure 4. 6) is for dedicated primary protection. SEL-487B has
multiple differential elements inside. Each differential element operates independently. So,
virtually one SEL-487B relay equals six independent differential relays. This is one of the
reasons for its being chosen in the experiment. Differential elements in SEL487B are BZ1
BZ6. To form primary protection, an individual differential element is assigned to protect a
power system item in the system (Figure 4. 5):
Assign primary protection of Cable1 (C1) to differential element BZ1;
Assign primary protection of Busbar02 to differential element BZ2;
Assign primary protection of Busbar01, T1 and Busbar05 together to differential element
BZ6.
151

Differential element assignment constitutes one part of relay settings.
After these assignments, only transformer_2 (T2) is left without primary protection.
Since there is no extra element that could be allocated to T2, T2 is therefore protected only by
backup protection. This arrangement will not influence the test results if the fault is not applied
on T2.
Most faults in the test will be applied around cable sections, i.e. components C1, C2,
bus02 and 03. These are the regions easy to appear short-cable problems. So, the WADP
system will look at them carefully to see whether these problems have been completely solved.
The first group setting (Group1) allows the study of faults on C1, C2, bus02, 03 and 04. These
components all have been assigned to an individual differential element (BZ1, BZ2, BZ3, BZ4,
BZ5). BZ6 includes multiple items (Busbar01, 05 and T1). Its trip will isolate all these
components. This does not comply with standard primary protection. So, to study a fault on these
locations and their associated protection, differential element assignment requires a modification.
For a fault on Bus05, new assignments are:
Assign primary protection of Busbar01, T1 and C1 together to differential element BZ6.

Underlines show the changes. Busbar05 has been assigned to an individual differential
element (BZ1) and C1 now is moved to BZ6, together with Busbar01 and T1 as a group. Any
modification is trying to allocate a single differential element to the new component where a
fault will be applied, to form a standard primary protection. New assignment is saved as
Group2 setting. Group2 setting can study faults on C2, bus02, 03, 04, and 05. SEL-487B allows
up to 6 customer settings (Group1, 2,3,4,5 and 6). The WADP study uses three of them.

Fault detection relies on differential elements BZ1-BZ6. If a differential element has
operated and all its supervising criteria [61] are met, the differential trip logic begins. Trip logic
is a software process embedded in the relay. It acquires all analog current input terminals
152

associated with the differential element and generates a trip output to the appropriate breakers.
Figure C. 1[61] shows the processing sequence for tripping the breakers as differential element
BZ3 (Group1 setting) operates. The same sequence applies for all six differential elements.

Start
BZ3 and Its
Supervision
Asserted?
Read
Terminals to
Trip for
Element BZ3
Generate Trip for
the Selected
Terminals CBkk
kk=01 ,,,11
NO
YES
C
B
4
&
C
B
5
End

Figure C. 1 Differential Trip Logic
Trip signals from the relay will be wired to the RTDS, to control the circuit breakers
simulated there. They are the primary protection trips for the WADP system.

Relay 2
SEL 487B relay2 in Figure 4. 6 is for the Outmost Ring function. The Outmost Ring
only requires a single differential comparison. So, differential element BZ1 is used. But
assignment for BZ1 for Outmost Ring function is different from its use in primary protection.
153

For primary protection, components around the system are assigned to six differential elements.
Once a setting is determined, a differential element, its protected component and the CTs
associated are fixed. This relationship will not change by switching on/off circuit breakers.
For Outmost Ring function, BZ1 may involve all of 11 current inputs Ict1, Ict2, Ict11
available in the system. These current inputs will not appear simultaneously but any of them
may be involved as the system topology changes due to fault isolation or system reconfiguration.
Consider the system in Figure 4. 5: the Outmost Ring consists of ct1, ct10 and ct11. However, if
bus04 was isolated due to a fault, then the Outmost Ring will change to ct1, ct6 and ct11. On the
other hand, if bus05 was isolated due to a fault, the Outmost Ring becomes ct1, ct8 and ct10.
This requires a special assignment for BZ1.

I01 I02 I03 I04 I05 I06 I07 I08 I09
BZ1 BZ2 BZ3 BZ4 BZ5 BZ6
Ict1
Ict2
Ict3
...
...
Six Differential Elements
11 Analog
Current Inputs
I10 I11 I12 I13 I14 I15 I16 I17 I18
Ict11
Ict10
...
Ictn
Circuit Breaker Status
Current Transformer n
18 Analog
Current Input
Terminals

Figure C. 2 Differential Element BZ1 and Its Application in Outmost Ring
Figure C. 2 illustrates configuration for element BZ1 for the Outmost Ring application.
All 11 available current inputs are wired into relay analog input terminals. SEL 487B provides
18 analog input channel, indicating by I01, I02, I18. At any instant, whether or not a current
154

input will be selected by BZ1 is determined by circuit breaker status. Table C. 1 gives a
selection table for a particular circuit breaker status and the CTs involved in the Outmost Ring.
This table then will be translated to the format that SEL relay can read and saved in the setting
(Group1).

Table C. 1 Outmost Ring CT Selection Table
Circuit Breaker (CB) Status Outmost Ring CT
CB1 CB2 CB3 CB4 CB5 CB6 CB7 CB8 CB9 CB10 CB11 CTn
1 1 1 1 1 1 1 1 1 1 1 CT1, 10, 11
1 1 1 1 1 1 1 1 1 1 0 CT1, 9,10
1 1 1 1 1 1 1 1 0 1 / CT1, 8,10
1 1 1 1 1 1 1 1 1 0 1 CT1, 7,11
1 1 1 1 1 1 0 1 1 / 1 CT1, 6,11
1 1 1 1 1 0 / 1 1 / 1 CT1, 5,11
1 1 1 1 0 / / 1 1 / 1 CT1, 4,11
1 1 1 0 / / / 1 1 / 1 CT1, 3,11
1 1 0 / / / / 1 1 / 1 CT1, 2,11
1: Circuit breaker closed
0: Circuit breaker open
/: Circuit breaker closed or open

The output from BZ1 is wired to the RTDS I/O interface and to the trip coordination
circuit in the RTDS. This trip starts the WADP system.
Signal Interfaces
There are three types of interfaces between SEL relays and the RTDS: analog input
interface, digital input interface and digital output interface. Direction of IN or OUT is with
respect to the relay.

Analogy Input Interface

SEL relay has two levels of analog input interfaces. One is through its terminal board.
This is a standard interface and used in the field. The nominal signals are 5A for current and
155

69V(110V) for voltage. In the field, they are directly connected with CT/PT secondary sides.
But this interface does not comply with the RTDS I/O. The RTDS D/A outputs are 10V
~+10V. Additional amplifiers are required for the connection.
The other SEL input interface is the low-level test interface. This interface in fact is the
relay internal link between the calibrated input module and the processing module [61]. SEL
allows the customer to access this interface for relay test purpose. Calibrated analog inputs can
be injected from this end instead of the standard terminals. Low-level interface accepts voltage
signals only. A 66.6mV on current channel from this interface equal 5A from the standard
terminal; a 446mV on voltage channel from this interface equal 67V from the standard terminal.
Allowable voltage peak value for low-level interface is 6.6V. Beyond this value, saturation
occurs and signals into the relay are distorted. Signal and the signal level of this end match with
the RTDS D/A. It is therefore used in the experiment. Two hardware relays (relay1 and relay2)
both use the low-level test interface connection.
To access the low-level interface, a small modification is required on the original relay
circuits. Relay front panel has to be open for the correction. Original ribbon cables between
input modules and processing module are removed. Two new 34-pin ribbon cables are inserted.
One end of the two cables connects with the processing module inside the relay. The other end is
to two outside terminal blocks (34 pin socket). These two blocks are now the low-level interface
connection terminals. Figure C. 3 shows a picture of low level interface connection terminals.
Signal channels associated with the terminals are listed
Table C. 2. Real-time analog signals from RTDS D/A cards are connected through these
terminals and into the relays.

The RTDS is equipped with two types of D/A cards: FDAC and DDAC. They are
mounted on the rear panel of RTDS cubicle. The FDAC board provides six, optically isolated
sixteen-bit analogue output channels and the DDAC board has twelve, optically isolated sixteen-
bit analog output channels. Channel resolution is 0.3mV (2*10V/2
16
=0.3mV). To configure the
WADP system, the primary relay occupies one DDAC card and one FDAC card, and the
Outmost Ring relay uses another group of them. Connections between the relays and D/A cards
are direct wire connections through the terminal block located on the D/A card (A in Figure C.
4.).
156

Real-Time Signals
From RTDS D/A Cards
Real-Time Signals
From RTDS D/A Card
Data Cables
Inside:
Relay Low_Level
Interfaces
Terminal
Block -1
T
e
r
m
i
n
a
l

B
l
o
c
k

-
2

Figure C. 3 SEL Relay Low-Level Interface and Connections

157

Table C. 2 Signal on Terminal Blocks
Terminal Signal Status Terminal Signal Status
1 I01 1 I10
3 I02 3 I11
In Use
5 I03 5 I12
7 I04 7 I13
9 I05 9 I14
11 I06 11 I15
13 I07 13 I16
15 I08 15 I17
17 I09 17 I18
19 V01 19 --
21 V02 21 --
23 V03 23 --
2,4,6,8,
10,12,14,16,
18,20,22,24
GND
In Use

2,4,6,8,
10,12,14,16,
18,20,22,24
GND In Use
25 -- 25 --
26 -- 26 --
27 -- 27 --
28 -- 28 --
29 -- 29 --
30 -5V 30 -5V
31 -- 31 --
32 -5V 32 -5V
33 +5V 33 +5V
Block_1
34 +5V
Block_2
34 +5V

On the RTDS side, each D/A card is linked to a RTDS parallel processor via a fiber optic
cable. The processor connected must have an optical port. Figure C. 4 is a picture illustrating the
signal flows from the RTDS simulator parallel processor (right), RTDS D/A card (middle) to
low-level terminal interface (left).
158

Fiber Optic
Link
Real-Time
Analog
Signals
To Low-Level
Test Terminals
RTDS FDAC
RTDS
Parallel
Processor
A

Figure C. 4 Analog Signals from RTDS Parallel Processor,
RTDS D/A Cards (only FDAC is provided) to Relay Low-Level Terminals
Except for the physical connection, additional work is on the RTDS software to get the data from
the simulator to the D/A card. Firstly, any processor to be connected to a D/A board must have a
FDAC or DDAC keyword included in its configuration file. Write/change to the
configuration file is from the RTDS workstation. For instance, the following data line in the
configuration file indicates that 3PC processor 1 in the rack is connected to a FDAC card [62].

41 3PC VER 3.01 FDAC

Then, in the RTDS draft file, a component rtds_sharc_ctl_FDAC (For the DDAC card, the
component rtds_sharc_ctl_DDAC is used) is copied from the library to the simulation case. This
component will transfer the simulated signals to the FDAC/DDAC card. The FDAC/DDAC
component takes as inputs up to six/twelve floating-point signals that are converted to 16 bit
scaled representations and written to the processor output port where the FDAC/DDAC card is
connected [62]. The input to D/A card must be within the range of +/- 10V. The FDAC/DDAC
159

component allows to set a scale factor for each input channel to limit the signal into the range.
This factor together with the low-level terminal signal ratio constitute the relay CT and PT
settings.

Digital Interface
Digital signals include circuit breaker status (open/close) indication signal from the
RTDS and trip signals from the relays. These signals are expressed by logic notation 1 or 0.
Relay sees logic 1 as a trip signal to open the circuit breaker. In a state of logic1, relay normal
open (NO) dry contact will be closed to initiate a trip signal. On the other hand, in a state of
logic0, relay normal open (NO) dry contact stays open. Table C. 3 [61] shows SEL relay output
status.

Table C. 3 SEL Relay Digital Output State
SEL Relay Digital Output
Logic Indication Contact (NO) Status Measurement
1 Trip Close 0 Ohm
0 No_Trip Open Inf Ohm

Relay trip signal logic 1 will open the circuit breakers simulated in the RTDS. To
achieve this purpose, the trip signal needs to be sent to the RTDS. RTDS DOPTO cards
accommodate this digital signal exchange. The DOPTO system interfaces up to 24 digital input
and 24 digital output signals between the RTDS and external equipment. Figure C. 5 [62] shows
the front view of DOPTO card. It has power indication LED, 24 digital input connections, 24
digital output connections, ground connection and a threshold setting. Threshold levels are used
to determine a valid logic 0 and logic 1 for digital input signals. A logic 1 is interpreted
when the digital input signal magnitude is higher than the V
HI
threshold and a logic 0 is read
when the input is below the V
LO
threshold. Thresholds are adjustable through the adjust-point
accessed from the front of the DOPTO card. For a 5V operation, Hi threshold is typically
2.0Volts and 0.8Volts for Lo threshold [62].

160

Power Supply Indication LEDs
Front Panel
Digital Input Connections
Ground Connections
Front Panel
Digital Output Connections
Digital Input Signal
Hi/Lo Threshold Settings
E
n
l
a
r
g
e
d
Adjust point

Figure C. 5 DOPTO Card Front View
DOPTO card accepts dry contact input. Relay trip signal to the DOPTO can therefore be
made directly to the front panel using pin tip jacks. Figure C. 6 is a picture showing the
connections between two hardware relays (the picture only captures one relay) and the DOPTO.
The WADP system uses 22 digital input connections.

The other side of the DOPTO card connects to the RTDS parallel processor. Connection
is located on the rear of the RTDS rack. The RTDS configuration file writes which processor has
been equipped with DOPTO card in the similar way as DDAC/FDAC card.

161

Relay1
R
e
l
a
y

O
u
t
p
u
t

C
o
n
t
a
c
t
s
Wire to
DOPTO
Pin Tip Jacks

Figure C. 6 Relay Trip Signals to the RTDS DOPTO Cards Front Panel Inputs
The corresponding logic status between dry contact and the RTDS signal has been
specified as: When the relay contacts are open, the RTDS will read a logic 1. When the relay
contacts are closed a logic 0 will be read.
This definition complies with the controllable circuit breaker model provided in the
RTDS library. For that model, when the control variable to a circuit breaker is 1, the circuit
breaker is closed; and the circuit breaker will be open when the control signal becomes 0
(Table C. 4). In the experiment, a trip signal (logic 1) released from the relay will intend to
open the circuit breaker (logic 0) as it supposes to be. An rtds_sharc_ctl_DOPTO component
in the RTDS case file will read the data from the DOPTO port and write to a RTDS variable
which is one of the criteria for the circuit breaker trip circuit simulated in the RTDS.

Table C. 4 Logic Relation Between Relay, DOPTO Card and Circuit Breaker
SEL Relay Output DOPTO Card RTDS Breaker
Logic Indication Contact (NO) Status Logic Measurement Status
1 Trip Close 0 0V Open
0 No_Trip Open 1 5V Close
162

SEL relay needs circuit breaker status signal from the RTDS. To SEL relay, it is a digital
input signal. The circuit breaker status determines if a breaker failure protection should be
initiated. The circuit breaker status, especially after a trip event, is also used to determine the
power system topology and to update CTs associated with a new Outmost Diff Ring. In the
experiment circuit breaker status indication from the RTDS is wired to the relay input contacts.
SEL specifies that the input contact picks up a logic 1 when the voltage (for 125V option)
applied to the contact is between the threshold of 105 150Vdc; and picks up a logic 0 when
the voltage applied drops below the threshold of 75Vdc.
To coordinate with this specification, RTDS High Voltage (HV) Digital Panel (Figure C.
7 [62]) is used as the interface between the RTDS and the relays. Each HV Panel has 16-signal
channels and can provide digital signals of up to 250Vdc to equipment external to the RTDS.

Figure C. 7 Front View of High Voltage Digital Interface Panel
HV Panel has three types of connectors: +Vdc, +Load, and Load. In the experiment, a
120V DC power supply is connected to the HV Panel connectors labeled +Vdc and Load.
Relay input contacts are connected to the connectors labeled +Load and Load. Circuit breaker
status indication signal from the RTDS will control the internal switches located between the
+Vdc and +Load connections. When a circuit breaker is closed which is indicated by a logic 1
in the RTDS, a digital 1 will close a switch between the +Vdc and +Load connections and a
120DC volts will be applied to the terminals label +Load and to a relay output contact connected.
Relay reads a logic 1, interpreting that the circuit breaker is closed. Thus, a circuit breaker
status indication signal has been correctly transferred from the RTDS to the relay. Figure C. 8 is
a picture showing the HV Panel connections in the experiment.

163

DOPTO
Pin Tip Jacks
HV Panel
Connections
+
_
+
_
Relay DC Power
Source
HV Panel

Figure C. 8 High Voltage Digital Panel Connections

Coordination in RTDS
Coordination in the RTDS includes three aspects:
(1) Coordinate trip signals sent from two hardware relays;
(2) Coordinate trip signals from hardware relays and the wide area differential
backup protection routine;
(3) Coordinate an overall trip signal with the circuit breaker trip logic;

Hardware Relay Coordination
A fault occurs in the system. Both hardware relays may detect the event and send trip
signals to the RTDS. Among them, one group is the primary protection trips and the other is the
Outmost Ring. According to the WADP confirmation mechanism, primary relay alone will not
164

trip the circuit breakers unless it gets the confirmation from the Outmost Ring. This is
implemented with a logic AND in the RTDS. Figure C. 9 gives the coordination circuit. The
rtds_sharc_ctl_DOPTO components (DOPTO Card_1 and DOPTO Card_2) read the trip signals
from two relays and DOPTO cards into the RTDS. The signal read into the RTDS from DOPTO
card is a 24bit word. It has to be converted into 24 integer signals before it can be used. In the
circuit of Figure C. 9, a bit shifter and two Word to Bit converters are used to extract the first 11
primary trip signals (Relay_Pri_1 to Relay_Pri_11) from a single 24 bit word. Relay_Pri_1 is
interpreted as a primary trip from hardware relay intends to open circuit breaker 1. One Word
to Bit converters is used to extract the Outmost Ring trip signal (OUTR). Then logic AND is
carried between the Outmost Ring signal and individual primary trips. The circuit in Figure C. 9
only shows an example that logic AND is performed between OUTR and Relay_Pri_7. The
result is a confirmed primary trip Pri_7 which will be finally connected with the circuit breaker
trip circuit in the RTDS to open circuit breaker 7.

Coordination between hardware relays and the WADP routine
Two hardware relays coordinate with the WADP routine in different ways. The trip from
the Outmost Ring relay is a prerequisite to start the WADP routine. Therefore, the OUTR signal
should be one of the inputs to the WADP routine. In the experiment, the OUTR signal is fed to
the input terminal of the WADP model written in a RTDS type C code. The WADP model
internal codes access the OUTR variable during each simulation time step. Based on the status of
OUTR, the WADP model will determine if there is a necessity for it to start a wide area
differential search. Figure C. 10 gives the WADP model and its connection with OUTR. Except
for OUTR, the WADP model also takes as inputs the current quantities that are expressed in the
phasor format. Outputs of the WADP model are fault locations.
Outputs from the WADP need to coordinate with the primary hardware relay to reach a
final trip decision. A fault will be tripped either by the WADP model or by the primary hardware
relay. Therefore, a logic gate OR is used for coordination. Figure C. 11 shows an example
circuit.

165

>>8
bit
word
bit
word
Relay_Pri_1
Relay_Pri_3
Relay_Pri_4
Relay_Pri_5
Relay_Pri_6
Relay_Pri_7
Relay_Pri_8
Relay_Pri_9
Relay_Pri_10
Relay_Pri_11
DOPTO
CARD_2
Dig I/O
bit
word
Relay_Pri_2
OUTR
OUTR
DOPTO
CARD_1
Dig I/O
AND Pri_7
Read
From
Primary
Relay
Read
From
Outmost
Ring
Relay
Bit Shift

Figure C. 9 Relay Coordination in the RTDS

166

Fault Location
Components t1-- t9
Current Phasor
Magnitude Inputs
I1M - I12M
Current Phasor
Phase Angle Inputs:
I1P- I12P
Integer
Value
Inter-middle
Signals Used
For Test Only

WADP Model
OUTR
Figure C. 10 Coordination Between Outmost Ring Relay Trip and
Wide Area Differential Backup Routine

167

p/u & d/o
Timer
DELAY
0.1
AND
OR
OR
Pri_7
BP7
t8
t9
Trip_7
Components (t8 &9)
Both Associated with
Circuit Breaker 7
Wide Area
Backup Trip
Pulse
0.1s Delay
Inserted For
Test Purpose
Pickup & Drop off
Timer
1
2
3

Outputs from
WADP Model
Coordination
Between Primary
and Wide Area
Backup
Confirmed
Primary Trip
Overall
Trip
Block to Generate Wide Area Backup Trip Pulse
Figure C. 11 Coordination Between Hardware Relay Trip and
Wide Area Differential Backup Routine
The breaker to be tripped is circuit breaker 7 (Trip_7). Coordination is between Pri_7 (the
confirmed primary trip) and BP7 (the wide area backup trip). They feed into a gate OR
(Block3). So, both of them have equal choice to trip the breaker. Block1 and Block2 together are
used to compose a WADP trip signal (BP7). Outputs from the WADP model are fault locations,
i.e, faulted components, not the breaker trip signals. So, Block1 is used to link the faulted
components to their associated circuit breakers and Block2 is to generate a delayed wide area trip
pulse. A 0.1second delay introduced is to distinguish a backup trip from the primary trip in the
final results. Before the DELAY function, there is a P/u & d/o timer that performs a hold-time
check for the WADP output. A trip signal has to be sustained for a couple of cycles. Otherwise,
it will be only treated as a temporary disturbance and does not cause the circuit breaker trip. SEL
hardware relay has an embedded function to check this process and thus there is no need for this
timer for the primary trip signal.
Similar coordination circuit to Figure C. 11 is built for each individual associated circuit
breaker.

Circuit Breaker Trip Logic Circuit
168

Trip from the relay is a pulse signal. But the circuit breaker model in the RTDS is
controlled by an integer value. Logic 1 closes the circuit breaker and logic 0 opens it. A pulse
signal to the circuit breaker will produce wrong status. It will firstly trip the breaker and then re-
close it. Therefore the pulse signal should not be directly used to trip the circuit breaker. A
standard circuit breaker trip logic circuit is created in the RTDS for breaker trip. Figure C. 12
gives the circuit. The trip circuit includes a manual reclose-function (Manu_RCL), a manual
open function (Manu_OP) as well as automatic operation (Trip_7) from the WADP system.

AND
OR
1
0
+Edge
Detector
S-R
FLIP
FLOP
S
R
Q
Q
Manu_RCL
Manu_OP
Trip_7
CB7
1
0
Pulse
Generator

Circuit
Breaker
Control
Signal
Manual
Reclose
Button
Manual
Open
Button
rtds_ctl_sharc_SRFF
Figure C. 12 Circuit Breaker Trip Circuits in the RTDS
The rtds_ctl_sharc_SRFF component in the figure is the main component for realizing
the functions. It operates according to the truth tables in Table C. 5 (Column_1-3). There are six
possible operational modes (Mode_1 to Mode_6) for it and the trip circuit uses five of them.
Mode_1 is an initial state which can be either logic 1 or logic 0, depending on the setting. In
the trip circuit, it was set as logic 1, to keep the circuit breaker staying closed when the case is
first run. Mode_2 and Mode_3 describe a circuit breaker open event. A pulse applied to the R
terminal either from the WADP system or from a manual operation, changes the status of the
output terminal Q from logic 1 to logic 0 and the output Q will hold the logic 0 value even
as the pulse applied elapsed. Mode_4 and Mode_5 describe a circuit breaker close event. A pulse
applied to the S terminal from a manual operation, sets the output terminal Q to logic 1. The
output Q will hold the logic 1 value even as the pulse applied elapsed.
169

Table C. 5 Operation Status of Circuit Breaker Trip Circuit
Column 1 2 3 4 5
Mode S R Q Switching Operation
1 0 0 1
Initial State
Breaker Closed
Manu_RCL=0
Manu_OP=0
NO Trip
2 0 1 0
Operation State
Breaker Opened
Manu_RCL=0
Manu_OP=Pulse
NO Trip
OR
Manu_RCL=0
Manu_OP=0
Trip=Pulse
3 0 0 0
Stay previous State
Breaker Opened

4 1 0 1
Operation State
Breaker Closed
Manu_RCL=Pulse
Manu_OP=0
NO Trip
5
0 0 1
Stay previous State
Breaker Closed

6 1 1 1 Not Used

170

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176

BIOGRAPHICAL SKETCH
Personal
Place of Birth: Wuxi, China

Education
Ph.D (candidate) in Mechanical Engineering, April 2006
Florida State University, Florida, USA
Dissertation Title: Wide Area Differential Protection
Course Work: Power System Protection, Power System Generation and Control, Power
System Transients, Power System Analysis, Adaptive Control,
Multivariable Control, Intelligent Control, Advance Control.

M.S in Power Machinery and Energy Engineering, February 2000
Shanghai Jiao Tong University, Shanghai, China
Thesis Title: CAN Network and Its Application in Automation System for Engine Room
Course Work: Optimization and optimal control, Advanced Control Theory, Interface and
Control Technique, Principles and Applications of Microcomputer,
Computing Methods, Matrix Theory, Advanced Thermodynamics.

B.S in Electrical Engineering, August 1992
ZhenJiang University, Jiangsu, China

Professional Experience
2000 2001:
Electrical Engineer, HID Research Center,
Philips&Yaming Lighting Co. Ltd. Shanghai, China
Areas of Work: PLC applications in HID (High Intensity Discharge) lamp manufacturing
process; PLC applications in HID lamp testing facility.
177

1992 1997:
Assistant Engineer, Zhenjiang Local Railway Company, China
Area of Work: Centralized control and management system

Research Interests
Power System Protection and Control; PowerPlant Technology; New Energy Sources and Their
Interfacing to Power Grid; Simulation and Modeling of electrical/mechanical systems.

Professional Societies
IEEE Student Member, 2002
Power Engineering Society

Publications
1. J. Tang, P. G. Mclaren, A Wide Area Differential Backup Protection Scheme for Shipboard
Application, accepted by IEEE Transactions on Power Delivery.
2. J. Tang, YanFeng Gong, Noel Schulz, M. Steurer and P.G. Mclaren, Hardware
Implementation of a Ship Wide Area Differential Protection Scheme, accepted by 2006
IEEE IAS Industrial and Commercial Power Systems Technical Conference.
3. J. Tang, P.G. Mclaren, A Wide Area Differential Backup Protection Scheme for Shipboard
Application, IEEE Electric Ship Technologies Symposium, July 25-27, 2005, Philadelphia,
PA, USA.
4. Jie Tang, Cartes. D, Baldwin. T, Economic Dispatch with Piecewise Linear Incremental
Function and Line Loss, Power Engineering Society General Meeting, 2003, IEEE, Volume:
2, 13-17 July 2003, pp.944 947.
178

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Te Florida State University

) and this value becomes different for CT saturation.

(A). The peak value is around 239 2 338 = (A). Figure

3.6.3.3 Sequence Differential Currents In Phasor Domain

5.2.2 Membership Functions

AND = { (x, (x) =min { (x), (x)} | x U}

, then C is expressed as:

OR = { (x, (x) =max { (x), (x)} | x U}

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