H5GQ1H24AFR (Rev1 0)

This document is a general product description and is subject to change without notice.
Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 / Nov. 2009 1
H5GQ1H24AFR
1Gb (32Mx32) GDDR5 SGRAM
H5GQ1H24AFR
Rev. 1.0/ Nov. 2009 2
H5GQ1H24AFR
Revision History
Revision No.
History Draft Date Remark
0.1 Defined target spec. Dec. 2008 Preliminary
0.2 Updated tRTPS / tRTW / tFAW / t32AW / Thermal Characteristics Mar. 2009 Preliminary
0.3 Updated tCKE / Pin Cap / CRCWL / CRCRL/ IDD / PLL Value April. 2009 Preliminary
0.4 Updated tRRDL / Revision ID/ Density ID
Removed tFLK / tSTDBYLK
May. 2009 Preliminary
0.5 Updated tCKE / tCKSRE / tCKSRX (@ 6Gbps only) May. 2009 Preliminary
0.6 Updated CRCWL / VREFD Selection Coding
Updated Auto VREFD Training
Updated tCKE & tPD
Updated Leakage Current
Updated x16 Mode IDD Value & 1.35V Timing Parameters
Updated Ordering Information
J uly. 2009 Preliminary
0.7 VREFD Options Figure31 change Sep. 2009 Preliminary
1.0 Revision 1.0 Release Nov. 2009
Rev. 1.0/ Nov. 2009 3
H5GQ1H24AFR
TABLE OF CONTENTS
FEATURES........................................................................................................................................................5
FEATURES..............................................................................................................................................5
FUNCTIONAL DESCRIPTION....................................................................................................................5
DEFINITION OF SINGLE STATE TERMINOLOGY....................................................................................................7
CLOCKING..........................................................................................................................................................8
INITIALIZATION................................................................................................................................................10
POWER UP SEQUENCE...........................................................................................................................10
INITIALIZATION WITH STABLE POWER..................................................................................................11
VENDOR ID...........................................................................................................................................13
ADDRESS.........................................................................................................................................................15
ADDRESSING.........................................................................................................................................15
ADDRESS BUS INVERSION(ABI)..............................................................................................................16
BAND GROUP........................................................................................................................................18
TRAINING........................................................................................................................................................21
INTERFACE TRAINING SEQUENCE..........................................................................................................21
ADDRESS TRAINING..............................................................................................................................22
WCK2CK TRAINING...............................................................................................................................25
READ TRAINING...................................................................................................................................32
WRITE TRAINING.................................................................................................................................38
MODE REGISTER..............................................................................................................................................41
Mode REGISTER 0(MR0).......................................................................................................................42
Mode REGISTER 1(MR1).......................................................................................................................45
Mode REGISTER 2(MR2).......................................................................................................................48
Mode REGISTER 3(MR3).......................................................................................................................50
Mode REGISTER 4(MR4).......................................................................................................................52
Mode REGISTER 5(MR5).......................................................................................................................55
Mode REGISTER 6(MR6).......................................................................................................................57
Mode REGISTER 7(MR7).......................................................................................................................60
Mode REGISTER 15(MR15)....................................................................................................................62
OPERATION......................................................................................................................................................63
COMMAND.............................................................................................................................................63
DESELECT.............................................................................................................................................65
NO OPERATION.....................................................................................................................................65
MODE REGISTER SET.............................................................................................................................65
ACTIVATION..........................................................................................................................................66
BANK RESTRITIONS...............................................................................................................................68
WRITE (WOM).......................................................................................................................................70
WRITE DATA MAS(DM)...........................................................................................................................89
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
Rev. 1.0 / Nov. 2009 4
H5GQ1H24AFR
READ....................................................................................................................................................86
DQ PREAMBLE .....................................................................................................................................95
READ AND WRITE DATA BUS INVERSION (DBI).......................................................................................97
ERROR DETECTION CODE.....................................................................................................................99
PRECHARGE........................................................................................................................................103
AUTO PRECHARGE...............................................................................................................................104
REFRESH.............................................................................................................................................104
SELF REFRESH....................................................................................................................................106
POWER-DOWN....................................................................................................................................109
COMMAND TRUTH TABLE.....................................................................................................................110
RDQS MODE........................................................................................................................................114
CLOCK FREQUENCY CHANGE SEQUENCE..............................................................................................116
DYNAMIC VOLTAGE SWITCHING(DVS).................................................................................................117
TEMPERATURE SENSOR.......................................................................................................................119
DUTY CYCLE CORRECTOR....................................................................................................................120
OPERATING CONDITIONS................................................................................................................................122
Absolute Maximum Ratings...................................................................................................................122
AC & DC Characteristics........................................................................................................................124
CLOCK TO DATA TIMING SENSITIVITY..................................................................................................148
PACKAGE SPECIFICATION................................................................................................................................151
BALL-OUT...............................................................................................................................................151
SIGNALS.................................................................................................................................................153
ON DIE TERMINATION(ODT)....................................................................................................................156
PACKAGE DIMENSIONS...........................................................................................................................157
MIRROR FUNCTION(MF) ENABLE AND X16 MODE ENABLE.................................................................................158
BOUNDARY SCAN............................................................................................................................................163
Rev. 1.0/ Nov. 2009 5
H5GQ1H24AFR
FEATURES
Singleendedinterfacefordata,addressandcommand
QuarterdataratedifferentialclockinputsCK/CK#for
ADR/CMD
TwohalfdataratedifferentialclockinputsWCK/
WCK#,eachassociatedwithtwodatabytes(DQ,DBI#,
EDC)
DoubleDataRate(DDR)data(WCK)
SingleDataRate(SDR)command(CK)
DoubleDataRate(DDR)addressing(CK)
16internalbanks
4bankgroupsfort
CCDL
=3t
CK
8nprefetcharchitecture:256bitperarrayreadorwrite
access
Burstlength:8only
ProgrammableCASlatency:5to20t
CK
ProgrammableWRITElatency:1to7t
CK
WRITEDatamaskfunctionviaaddressbus(single/
doublebytemask)
Databusinversion(DBI)&addressbusinversion
(ABI)
Input/outputPLLon/offmode
Addresstraining:addressinputmonitoringbyDQ
pins
WCK2CKclocktrainingwithphaseinformationby
EDCpins
DatareadandwritetrainingviaREADFIFO
READFIFOpatternpreloadbyLDFFcommand
DirectwritedataloadtoREADFIFObyWRTR
command
ConsecutivereadofREADFIFObyRDTRcommand
Read/Writedatatransmissionintegritysecuredby
cyclicredundancycheck(CRC8)
READ/WRITEEDCon/offmode
ProgrammableEDCholdpatternforCDR
ProgrammableCRCREADlatency=0to3t
CK
ProgrammableCRCWRITElatency=7to14t
CK
LowPowermodes
RDQSmodeonEDCpin
Optionalonchiptemperaturesensorwithreadout
Auto&selfrefreshmodes
Autoprechargeoptionforeachburstaccess
32ms,autorefresh(8kcycles)
Temperaturesensorcontrolledselfrefreshrate
Ondietermination(ODT);nominalvaluesof60ohm
and120ohm
Pseudoopendrain(POD15)compatibleoutputs(40
ohmpulldown,60ohmpullup)
ODTandoutputdrivestrengthautocalibrationwith
externalresistorZQpin(120ohm)
Programmableterminationanddriverstrengthoffsets
SelectableexternalorinternalVREFfordatainputs;
programmableoffsetsforinternalVREF
SeparateexternalVREFforaddress/commandinputs
VendorID,FIFOdepthandDensityinfofieldsfor
identification
x32/x16modeconfigurationsetatpowerupwithEDC
pin
MirrorfunctionwithMFpin
BoundaryscanfunctionwithSENpin
1.6V/1.5V+/0.045Vsupplyfordeviceoperation
(VDD)
1.6V/1.5V+/0.045VsupplyforI/Ointerface(VDDQ)
170ballBGApackage
FUNCTIONAL DESCRIPTION
The GDDR5 SGRAM is a high speed dynamic
randomaccess memory designed for applications
requiring high bandwidth. GDDR5 devices contain
thefollowingnumberofbits:
1Gbhas1,073,741,824bitsandsixteenbanks
The GDDR5 SGRAM uses a 8n prefetch
architecture and DDR interface to achieve high
speed operation. The device can be configured to
operate in x32 mode or x16 (clamshell) mode. The
mode is detected during device initialization. The
GDDR5 interface transfers two 32 bit wide data
words per WCK clock cycle to/from the I/O pins.
Corresponding to the 8nprefetch a single write or
readaccessconsistsofa256bitwide,twoCKclock
cycle data transfer at the internal memory core and
eightcorresponding32bitwideonehalfWCKclock
cycledatatransfersattheI/Opins.
The GDDR5 SGRAM operates from a differential
clock CK and CK#. Commands are registered at
everyrisingedgeofCK.Addressesareregisteredat
every rising edge of CK and every rising edge of
CK#.
GDDR5 replaces the pulsed strobes (WDQS &
RDQS) used in previous DRAMs such as GDDR4
with a free running differential forwarded clock
(WCK/WCK#) with both input and output data
registered and driven respectively at both edges of
theforwardedWCK.
ReadandwriteaccessestotheGDDR5SGRAMare
burstoriented;anaccessstartsataselectedlocation
andconsistsofatotalofeightdatawords.Accesses
beginwiththeregistrationofanACTIVEcommand,
which is then followed by a READ or WRITE
command. The address bits registered coincident
withtheACTIVEcommandandthenextrisingCK#
edge are used to select the bank and the row to be
accessed. The address bits registered coincident
with the READ or WRITE command and the next
risingCK#edgeareusedtoselectthebankandthe
columnlocationfortheburstaccess.
Rev. 1.0 / Nov. 2009 6
H5GQ1H24AFR
ORDERING INFORMATION
Above Hynix P/Ns are Leead-free, RoHS Compliant and Halogen-free.
Note.1)It supports not only 5Gbps @ 1.5V, but also 3.2Gbps @ 1.35V.
PartNo PowerSupply CKFrequency WCKFrequency MaxDataRate Interface
H5GQ1H24AFR-R0C VDD/VDDQ=1.6V 1.50GHz 3.00GHz 6.0Gbps/pin
POD_15
H5GQ1H24AFR-T3C
VDD/VDDQ=1.5V
1.375GHz 2.75GHz 5.5Gbps/pin
H5GQ1H24AFR-T2L (Note1) 1.25GHz 2.50GHz 5.0Gbps/pin
H5GQ1H24AFR-T2C 1.25GHz 2.50GHz 5.0Gbps/pin
Rev. 1.0/ Nov. 2009 7
H5GQ1H24AFR
0.1.DEFINITIONOFSIGNALSTATETERMINOLOGY
GDDR5SGRAMwillbeoperatedinbothODTEnable(terminated)andODTDisable(unterminated)
modes.ForhighestdataratesitisrecommendedtooperateintheODTEnablemode.ODTDisablemode
isdesignedtoreducepowerandmayoperateatreduceddatarates.ThereexistsituationswhereODT
Enablemodecannotbeguaranteedforashortperiodoftime,i.e.duringpowerup.
Followingarefourterminologiesdefinedforthestateofadevice(GDDR5SGRAMorcontroller)pindur
ingoperation.Thestateofthebuswillbedeterminedbythecombinationofthedevicepinsconnectedto
thebusinthesystem.ForexampleinGDDR5itispossiblefortheSGRAMpintobetristatedwhilethe
controllerpinisHighorODT.InbothcasesthebuswouldbeHighiftheODTisenabled.Fordetailson
theGDDR5SGRAMpinsandtheirfunctionseePACKAGESPECIFICATIONonpage 156andSIG
NALSonpage 158inthesectionentitledPACKAGESPECIFICATIONonpage 156.
Devicepinsignallevel:
High:AdevicepinisdrivingtheLogic1state.
Low:AdevicepinisdrivingtheLogic0state.
HiZ:Adevicepinistristate.
ODT:AdevicepinterminateswithODTsetting,whichcouldbeterminatingortristatedependingonMode
Registersetting.
Bussignallevel:
High:OnedeviceonbusisHighandallotherdevicesonbusareeitherODTorHiZ.Thevoltagelevelonthebus
wouldbenominallyVDDQ
Low:OnedeviceonbusisLowandallotherdevicesonbusareeitherODTorHiZ.Thevoltagelevelonthebus
wouldbenominallyVOL(DC)ifODTwasenabled,orVSSQifHiZ.
HiZ:AlldevicesonbusareHiZ.Thevoltagelevelonbusisundefinedasthebusisfloating.
ODT:AtleastonedeviceonbusisODTandallothersareHiZ.Thevoltagelevelonthebuswouldbenominally
VDDQ.
Rev. 1.0 / Nov. 2009 8
H5GQ1H24AFR
0.2.CLOCKING
TheGDDR5SGRAMoperatesfromadifferentialclockCKandCK#.Commandsareregisteredatevery
risingedgeofCK.AddressesareregisteredateveryrisingedgeofCKandeveryrisingedgeofCK#.
GDDR5usesaDDRdatainterfaceandan8nprefetcharchitecture.Thedatainterfaceusestwodifferen
tialforwardedclocks(WCK/WCK#).DDRmeansthatthedataisregisteredateveryrisingedgeofWCK
andrisingedgeofWCK#.WCKandWCK#arecontinuouslyrunningandoperateattwicethefrequency
ofthecommand/addressclock(CK/CK#).
Figure 1:GDDR5ClockingandInterfaceRelationship
CK
CK#
COMMAND
ADDRESS
DQ
*1
WCK
WCK#
Note:Figure.1showstherelationshipbetweenthedatarateofthebusesandtheclocksandisnotatimingdiagram.
Rev. 1.0 / Nov. 2009 9
H5GQ1H24AFR
.
Figure 2:BlockDiagramofanexampleclocksystem
ClockPhase
Oscillator
Q D
CMD/ADD
CMD/ADD DRAM
Q D
QB
DQ[0][7]
D Q
early/late
Receiver
D Q
WCK
int
DQ
DRAM
PLL
Q D
D Q
Phasedetector/
corelogic early/latefrom
For8databits
Controller
GDDR5SGRAM
PLL
clock
DataTx/Rx
WCK/WCK#
(2GHz)
CK/CK#
(1GHz)
CMDsampledbyCK/CK#asSDR
ADDsampledbyCK/CK#asDDR
ADD/CMDcenteredwithCK/CK#
calibrationdata
Phaseaccumulator
Controller
ClockPhase
Controller
(4Gbps)
core
core
(1GHz)
D Q
WCK2CK
Alignment
ToEDCpin
/2
Rev. 1.0 / Nov. 2009 10
H5GQ1H24AFR
1.INITIALIZATION
1.1.POWERUPSEQUENCE
GDDR5 SGRAMs must be powered up and initialized in a predefined manner as shown in <Link>Figure . Operational
procedures other than those specified may result in undefined operation. The Mode Registers do not have RESET
default values, except for ABI#, ADR/CMD termination, and the EDC hold pattern. If the mode registers are not set dur-
ing the initialization sequence, it may lead to unspecified operation.
Step
1 ApplypowertoVDD
2 ApplypowertoVDDQatsametimeorafterpowerisappliedtoVDD
3 ApplyVREFCandVREFDatsametimeorafterpowerisappliedtoVDDQ
4 Afterpowerisstable,providestableclocksignalsCK/CK#
5 AssertandholdRESET#lowtoensurealldriversareinHiZandallactiveterminationsareoff.AssertandholdNOPcommand.
6 Waitaminimumof200s.
7
Ifboundaryscanmodeisnecessary,SENcanbeassertedHIGHtoenterboundaryscanmode.Boundaryscanmodemustbe
entereddirectlyafterpowerupwhileRESET#islow.Onceboundaryscanisexecuted,powerupsequenceshouldbefollowed.
8
SetCKE#forthedesiredADR/CMDODTsettings,thenbringRESET#HightolatchinthelogicstateofCKE#,t
ATS
andt
ATH
must
bemetduringthisprocedure.See<Link>Table1forthevaluesandlogicstatesforCKE#.TherisingedgeofRESET#willdetermine
x32modeorx16modedependingonthestateofEDC1(EDC2whenMF=1).Innormalx32mode,EDC1hastobesustainedHIGH
untilRESET#isHIGH.See<Link>TableforthevaluesandlogicstatesforEDC1(EDC2whenMF=1).
9 BringCKE#Lowaftert
ATH
issatisfied
10 Waitatleast200sreferencedfromthebeginningoft
ATS
11 Issueatleast2NOPcommands
12 IssueaPRECHARGEALLcommandfollowedbyNOPcommandsuntilt
RP
issatisfied
13 IssueMRScommandtoMR15.SetGDDR5SGRAMintoaddresstrainingmode(optional)
14 Completeaddresstraining(optional)
15 IssueMRScommandtoreadtheVendorID
16 IssueMRScommandtosetWCK01/WCK01#andWCK23/WCK23#terminationvalues
17 ProvidestableclocksignalsWCK01/WCK01#andWCK23/WCK23#
18
IssueMRScommandstousePLLornotandselectthepositionofaWCK/CKphasedetector.TheuseofPLLandthepositionofa
phasedetectorshouldbeissuedbeforeWCK2CKtraining.IssueMRScommandsincludingPLLresettothemoderegistersinany
order.t
MRD
mustbemetduringthisprocedure.WLmrs,CLmrs,CRCWLandCRCRLmustbeprogrammedbeforeWCK2CK
training.
19 IssuetwoREFRESHcommandsfollowedbyNOPuntilt
RFC
issatisfied
20
AfteranynecessaryGDDR5trainingsequencessuchasWCK2CKtraining,READtraining(LDFF,RDTR)andWRITEtraining
(WRTR,RDTR),thedeviceisreadyforoperation.
Rev. 1.0 / Nov. 2009 11
H5GQ1H24AFR
Figure 3:GDDR5SGRAMPowerupInitialization
1.2.Initialization with Stable Power
Thefollowingsequenceisrequiredforresetsubsequenttopowerupinitialization.Thisrequiresthatthe
powerhasbeenstablewithinthespecifiedVDDandVDDQrangessincepowerupinitialization(See
Figure 4)
Table 1AddressandCommandTermination
VALUE(OHMS) CKE#atRESET#hightransition
ZQ/2 Low
ZQ High
TRAIN/MRS
TRAIN/MRS
ADR
CKE#
min.200s
CMD
V
DD
V
DDQ
V
REFD/C
RESET#
t
ATS
t
ATH
Voltagesand
CKstable
DQ<31:0>,
DBI#<3:0>
ADR
EDC<3,0>
AllBanks
Precharge
WCK
NOP NOP
CK#
CK
WCK#
PRE NOP
t
RP
Executionofsteps
1321inPowerup
sequence
TRAIN/MRS
TRAIN/MRS
ADR
A.C.
ADR ADR
min.200s
NOP NOP
EDC<2,1>
x32
x16
TRAIN/MRS
A.C.
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Note:A.C.=AnyCommand
Rev. 1.0 / Nov. 2009 12
H5GQ1H24AFR
1)AssertRESET#Lowanytimewhenresetisneeded.
2)HoldRESET#Lowforminimum100ns.AssertandholdNOPcommand.
3)SetCKE#forthedesiredADR/CMDODTsettings,thenbringRESET#Hightolatchinthelogicstateof
CKE#;tATSandtATHmustbemetduringthisprocedure.KeepEDC1(MF=0)/EDC2(MF=1)atthesame
logiclevelasduringpowerupinitializationasdevicefunctionalityisnotguaranteediftheI/Owidthhas
changed.
4)Continuewithstep9ofthepowerupinitializationsequence.
Figure 4:InitializationwithStablePower
TRAIN/MRS
ADR
CKE#
min.100ns
CMD
V
DD
,V
DDQ
V
REFD/C
RESET#
t
ATS
t
ATH
DQ<31:0>,
DBI#<3:0>
ADR
EDC<3:0>
AllBanks
Precharge
WCK
NOP NOP
CK#
CK
WCK#
PRE NOP
t
RP
Executionofsteps
1321inPowerup
sequence
TRAIN/MRS
TRAIN/MRS
ADR
A.C.
ADR ADR
min.200s
NOP NOP
TRAIN/MRS
A.C.
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Notes:1.A.C.=AnyCommand
Rev. 1.0 / Nov. 2009 13
H5GQ1H24AFR
1.2.VENDORID
GDDR5SGRAMsarerequiredtoincludeaVendorIDfeaturethatallowsthecontrollertoreceiveinforma
tionfromtheGDDR5SGRAMtodifferentiatebetweendifferentvendorsanddifferentdevicesusinga
softwarealgorithm.
WhentheVendorIDfunctionisenabledtheGDDR5SGRAMwillprovideitsManufacturersVendorCode
onbits[3:0]asshowninTable2;RevisionIdentificationonbits[7:4];Densityonbits[9:8];FIFODepthon
bits[11:10]asshowninTable3&Table4.Bits[15:12]areRFU.
VendorIDispartoftheINFOfieldofModeRegister3(MR3)andisselectedbyissuingaMODEREGIS
TERSETcommandwithMR3bitA6setto1,andbitA7setto0.MR3bitsA0A5andA8A11aresettothe
desiredvalues.
TheVendorIDwillbedrivenontotheDQbusaftertheMRScommandthatsetsbitsA6to1andA7to0.
TheDQbuswillbecontinuouslydrivenuntilanMRScommandsetsMR3A6andA7backto0todisable
theINFOfieldortoanothervalidstatefortheINFOfieldiftheINFOfieldincludessupportforadditional
vendorspecificinformation.TheDQbuswillbeinODTstateaftert
WRIDOFF
(max).Thecodecanbesam
pledbythecontrollerafterwaitingt
WRIDON
(max)andbeforet
WRIDOFF
(min).DBIisnotenabledor
ignoredduringallVendorIDoperations.Table4showsthemappingoftheVendorIDinfotothephysical
DQs.The16bitsofVendorIDaresentonByte0and2whenMF=0.WhenMF=1the16bitsaresenton
Byte1and3.Optionallythevendormayreplicatethedataontheother2byteswheninx32mode.Byte0
wouldbereplicatedonByte1andByte2wouldbereplicatedonByte3whenMF=0.WhenMF=1,Byte1
wouldbereplicatedonByte0andByte3wouldbereplicatedonByte2.
TABLE2.ManufacturersVendorCode
ManufacturersID Bit3 Bit2 Bit1 Bit0 NameofCompany
0 0 0 0 0 Reserved
1 0 0 0 1 Samsung
2 0 0 1 0 Qimonda
3 0 0 1 1 Elpida
4 0 1 0 0 Etron
5 0 1 0 1 Nanya
6 0 1 1 0 Hynix
7 0 1 1 1 ProMOS
8 1 0 0 0 Winbond
9 1 0 0 1 ESMT
A 1 0 1 0 Reserved
B 1 0 1 1 Reserved
C 1 1 0 0 Reserved
D 1 1 0 1 Reserved
E 1 1 1 0 Reserved
F 1 1 1 1 Micron
Rev. 1.0 / Nov. 2009 14
H5GQ1H24AFR
Figure 5:VendorIDTimingDiagram
Table 3RevisionID&Density&FIFODepth
RevisionID Density FIFO
Bit7 Bit6 Bit6 Bit4 Bit9 Bit8 Bit11 Bit10
0 0 0 1 0 1 1 0
Table 4VendorIDtoDQmapping
Bit 7 6 5 4 3 2 1 0
MF=0 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
Feature RevisionIdentification ManufacturersVendorCode
Bit 15 14 13 12 11 10 9 8
Feature RFU FIFODepth Density
CK#
CK
CMD
BA0BA3
A2A5
A9,A10
A0,A1
A8
A7
A11
A6
MRA MRA
Code
Code
Code Code
Code
Code
Code Code
t
WRIDON
(max)
DQ
t
WRIDOFF
(min)
VendorID+RevCode
MRA=ModeRegisterAddress;Code=Opcodetobeloaded
NOP MRS NOP NOP NOP NOP MRS NOP NOP NOP NOP
DontCare
Code Code
Rev. 1.0 / Nov. 2009 15
H5GQ1H24AFR
2.ADDRESS
2.1.ADDRESSING
GDDR5SGRAMsuseadoubledatarateaddressschemetoreducepinsrequiredontheGDDR5SGRAM
asshowninTable5.TheaddressesshouldbeprovidedtotheGDDR5SGRAMintwoparts;thefirsthalfis
latchedontherisingedgeofCKalongwiththecommandpinssuchasRAS#,CAS#andWE#;thesecond
halfislatchedonthenextrisingedgeofCK#.
TheuseofDDRaddressingallowsalladdressvaluestobelatchedinatthesamerateastheSDRcom
mands.Alladdressesrelatedtocommandaccesshavebeenpositionedforlatchingontheinitialrising
edgeforfasterdecoding.
Note:AddresspinA12isrequiredonlyfor2Gdensity.
GDDR5addressingincludessupportfor1Gdensity.Foralldensitiestwomodesaresupported(x32mode
orx16mode).x32andx16modesdifferonlyinthenumberofvalidcolumnaddresses,asshowninTable6.
Table 5AddressPairs
Clock
RisingCK BA3 BA2 BA1 BA0 (A12) A11 A10 A9 A8
RisingCK# A3 A4 A5 A2 (RFU) A6 A0 A1 A7
Table 6AddressingScheme
1G
x32mode x16mode
Rowaddress A0~A11 A0~A11
Columnaddress A0~A5 A0~A6
Bankaddress BA0~BA3 BA0~BA3
Autoprecharge A8 A8
PageSize 2K 2K
Refresh 8K/32ms 8K/32ms
Refreshperiod 3.9us 3.9us
Rev. 1.0 / Nov. 2009 16
H5GQ1H24AFR
2.2.ADDRESSBUSINVERSION(ABI)
AddressBusInversion(ABI)reducesthepowerrequirementsonaddresspins,astheno.ofaddresslines
drivingalowlevelcanbelimitedto4(incaseA12/RFUisnotwired)or5(incaseA12/RFUiswired).
TheAddressBusInversionfunctionisassociatedwiththeelectricalsignallingontheaddresslines
betweenacontrollerandtheGDDR5SGRAM,regardlessofwhethertheinformationconveyedonthe
addresslinesisaroworcolumnaddress,amoderegisteropcode,adatamask,oranyotherpattern.
TheABI#inputisanactiveLowdoubledatarate(DDR)signalandsampledbytheGDDR5SGRAMatthe
risingedgeofCKandtherisingedgeofCK#alongwiththeaddressinputs.
OnceenabledbythecorrespondingABIModeRegisterbit,theGDDR5SGRAMwillinvertthepattern
receivedontheaddressinputsincaseABI#wassampledLow,orleavethepatternnoninvertedincase
ABI#wassampledHigh,asshowninFigure6.
Figure 6:ExampleofAddressBusInversionLogic
8(9)
8(9)
to
DRAM
core
ABI#
Address
Pins
fromModeRegister:
0=enabled
1=disabled
Note:buswidthis8whenA12/RFUpinisnotpresent,and9whenA12/RFUpinispresent
Rev. 1.0 / Nov. 2009 17
H5GQ1H24AFR
TheflowdiagraminFigure7illustratestheABIoperation.Thecontrollerdecideswhethertoinvertornot
invertthedataconveyedontheaddresslines.TheGDDR5SGRAMhastoperformthereverseoperation
basedontheleveloftheABI#pin.AddressinputtimingparametersareonlyvalidwithABIbeingenabled
andamaximumof4addressinputsdrivenLow.
Figure 7:AddressBusInversion(ABI)FlowDiagram
Datatobesent
onaddresslines
0count
>4?
ABI#=L
Invert
Yes
ABI#=H
Dontinvert
No
Determine0
count
Datareceived
onaddresslines
ABI#=H
Dontinvert
ABI#=L
Invert
Controller
GDDR5
SGRAM
Rev. 1.0 / Nov. 2009 18
H5GQ1H24AFR
2.3.BANKGROUPS
ForGDDR5SGRAMdevicesoperatingatfrequenciesaboveacertainthreshold,theactivitywithinabank
groupmustberestrictedtoensureproperoperationofthedevice.The8or16banksinGDDR5SGRAMs
aredividedintofourbankgroups.ThebankgroupsfeatureiscontrolledbybitsA10andA11inMode
Register3(MR3).TheassignmentofthebankstothebankgroupsisshowninTable7.
Thesebankgroupsallowthespecificationofdifferentcommanddelayparametersdependingonwhether
backtobackaccessesaretobankswithinonebankgrouporacrossbankgroupsasshowninTable8.
Table 7BankGroups
Bank
Addressing 1G
BA3 BA2 BA1 BA0 16banks
0 0 0 0 0
GroupA
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
GroupB
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
GroupC
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
GroupD
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1
Rev. 1.0 / Nov. 2009 19
H5GQ1H24AFR
Note.1:ParameterstRTPSandtRTPLapplyonlywhenREADandPRECHARGEgotothesamebank;usetRTPSwhenBGare
disabled,andtRTPLwhenBGareenabled.
Table 8CommandSequencesAffectedbyBankGroups
CommandSequence
CorrespondingACTimingParameter
Notes
BankGroups
Disabled
BankGroupsEnabled
Accessestodifferentbank
groups
Accesseswithinthesame
bankgroup
ACTIVEtoACTIVE t
RRDS
t
RRDS
t
RRDL
WRITEtoWRITE t
CCDS
t
CCDS
t
CCDL
READtoREAD t
CCDS
t
CCDS
t
CCDL
InternalWRITEtoREAD t
WTRS
t
WTRS
t
WTRL
READtoPRECHARGE t
RTPS
1tck t
RTPL
1
Rev. 1.0 / Nov. 2009 20
H5GQ1H24AFR
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
CLK
CAS
DQ
A0 A1 B0 B1 C0 C1
A0 A1 B0 B1 C1
Example1(BankGroupsdisabled):t
CCDS
=2*t
CK
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
CLK
CAS
DQ
A0 A1 A2 A3
A0 A1 A2
Example2:(BankGroupsenabled):t
CCDL
=4*t
CK
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
CLK
CAS
DQ
A0 B0 A1 B1 C0 D0
A0 B0 A1 B1 C0
Example3:(BankGroupsenabled):t
CCDS
=2*t
CK
T12
T12
T12
D0
A3
C1
T13
T13
T13
C0 D0
D0 C1
Back-to-back column accesses based on t
CCDL
and t
CCDS
parameters.
Notes:
1)Columnaccessesaretoopenbanks,andt
RCD
hasbeenmet.
2)CL=0assumed
3)Ax,Bx,Cx,Dx:accessestobankgroupsA,B,CorD,respectively
4)Withbankgroupsenabled,t
CCDL
is3t
CK
,asprogrammedinMR3.
Rev. 1.0 / Nov. 2009 21
H5GQ1H24AFR
3.TRAINING
3.1.INTERFACETRAININGSEQUENCE
DuetothehighdataratesofGDDR5,itisrecommendedthattheinterfacesbetrainedtooperatewiththe
optimaltimings.GDDR5SGRAMhasfeaturesdefinedwhichallowforcompleteandefficienttrainingof
theI/OinterfacewithouttheuseoftheGDDR5SGRAMarray.Theinterfacetrainingsarerequiredfornor
malDRAMfunctionalityunlessrunninginlowerfrequencymodesasdescribedinthelowfrequencysec
tion.Interfacetimingswillonlybeguaranteedafterallrequiredtrainingshavebeenexecuted.
Arecommendedorderoftrainingsequenceshasbeenchosenbasedonthefollowingcriteria:
TheaddresstrainingmustbedonefirsttoallowfullaccesstotheModeRegisters.(MRSforaddresstrain
ingisaspecialsingledataratemoderegistersetguaranteedtoworkwithouttraining).Addressinputtim
ingshallfunctionwithouttrainingaslongast
AS/H
aremetattheGDDR5SGRAM.
WCK2CKtrainingshouldbedonebeforereadtrainingbecauseashiftinWCKrelativeCKwillcausea
shiftinallREADtimingsrelativetoCK.
READtrainingshouldbedonebeforeWRITEtrainingbecauseoptimalWRITEtrainingdependsoncor
rectREADdata.
Figure 8:InterfaceTrainingSequence
Initialization
AddressTraining(optional)
WCK2CKAlignmentTraining
READTraining
WRITETraining
StartNormalOperation
Rev. 1.0 / Nov. 2009 22
H5GQ1H24AFR
3.2.ADDRESSTRAINING
TheGDDR5SGRAMprovidesmeansforaddressbusinterfacetraining.Thecontrollermayusethe
addresstrainingmodetoimprovethetimingmarginsontheaddressbus.
AddresstrainingmodeisenteredandexitedviatheADTbitinModeRegister15(MR15).ModeRegister
15supportsthesamesetupandholdtimesontheaddresspinsasforcommandstoallowasafeentryinto
addresstrainingmode.
AddresstrainingmodeusesaninternalbridgebetweentheGDDR5SGRAMsaddressinputsandDQ/
DBI#outputs.ItalsousesaspecialREADcommandforaddresscapturethatisencodedusingtheSDR
commandpinsonly(CS#,RAS#,CAS#,WE#=L,H,L,H).Theaddressvaluesnormallyusedtoencodethe
commandswillnotbeinterpreted.Oncetheaddresstrainingmodehasbeenentered,theaddressvalues
registeredcoincidentwiththisspecialREADcommandwillbetransmittedtothecontrollerontheDQ/
DBI#pins.Thecontrolleristhenexpectedtocomparetheaddresspatternreceivedtotheexpectedvalue
andtoadjusttheaddresstransmittimingaccordingly.Theproceduremayberepeatedusingdifferent
addresspatternandinterfacetimings.
NoWCKclockisrequiredforthisspecialREADcommandoperationduringaddresstrainingmode.The
latchedaddressesaredrivenoutasynchronously.
TheonlycommandsallowedduringaddresstrainingmodearethisspecialREAD,MRS(e.g.toexit
addresstrainingmode)andNOP/DESELECT.
WhenenabledbytheABIbitinModeRegister1,addressbusinversion(ABI)iseffectiveduringaddress
trainingmode.ItissuggestedtotraintheABI#pinsinterfacetimingtogetherwiththeotheraddresslines.
ThetimingdiagraminFigure9illustratesthetypicalcommandsequenceinaddresstrainingmode.The
DQ/DBI#outputdriversareenabledaslongastheADTbitisset.Theminimumspacingbetweenconsec
utivespecialREADcommandsis2t
CK.
Rev. 1.0 / Nov. 2009 23
H5GQ1H24AFR
Figure 9:AddressTrainingTiming
Table10definesthecorrespondencebetweenaddressbitsandDQ/DBI#.Devicesconfiguredtox16mode
reflecttheaddressonthetwobytesbeingenabledinthatmode,whicharebytes0and2forMF=0and
bytes1and3forMF=1configurations.Devicesconfiguredtox32modereflecttheaddressonthesameDQ
asinx16mode;inadditiontheyareallowedbutnotrequiredtoreflecttheaddressonthosebytesthatare
disabledinx16mode,thusreflectingeachaddresstwice.
DevicesnotsupportinganA12/RFUpinshalldrivealogicHighontheDBI#pins.
Table 9ACtimingsinAddressTrainingMode
Parameter Symbol Min Max Unit
READcommandtodataoutdelay t
ADR
0.5*tCK+0 0.5*tCK+10 ns
ADTofftoDQ/DBI#inODTstatedelay t
ADZ
0.5*tCK+10 ns
CK#
CK
t
ADR
Even
DQ
Notes:
1)READcommandencoding:CS#=L,RAS#=H,CAS#=L,WE#=H
2)ADRxR=1sthalfofaddressx,sampledonrisingedgeofCK;
ADRxR#=2ndhalfofaddressx,sampledonrisingedgeofCK#
3)AddressessampledonrisingedgeofCKarereturnedonevenDQaftertADR;
addressessampledonrisingedgeofCK#arereturnedonoddDQsimultaneouslywithevenDQ
4)DQsareenabledwhenADTbitinModeRegister15setto1(EnterAddressTrainingMode)
DQsaredisabledaftert
ADZ
whenADTbitinModeRegister15setto0(ExitAddressTrainingMode)
ADRx
R#
CMD
ADDR
ADRy
R
ADRy
R#
Odd
DQ
t
ADR
t
MRD
MR15
A10=1
ADRx
R
DontCare
ADRx
R
ADRy
R
ADRx
R#
ADRy
R#
ADRz
R
ADRz
R
ADRz
R#
t
ADR
MR15
A10=0
t
ADZ
ADRz
R#
MRS NOP READ(*) NOP READ(*) NOP READ(*) NOP MRS NOP NOP NOP NOP
Rev. 1.0 / Nov. 2009 24
H5GQ1H24AFR
Table 10AddresstoDQMappinginAddressTrainingMode
Output
AddressbitsregisteredatrisingedgeofCK
A12 A8 A11 BA1 BA2 BA3 BA0 A9 A10
DQ
DBI0# DQ22 DQ20 DQ18 DQ16 DQ6 DQ4 DQ2 DQ0
Output
AddressbitsregisteredatrisingedgeofCK#
RFU A7 A6 A5 A4 A3 A2 A1 A0
DQ
Rev. 1.0 / Nov. 2009 25
H5GQ1H24AFR
3.3.WCK2CKTRAINING
ThepurposeofWCK2CKtrainingistoalignthedataWCKclockwiththecommandCKclocktoaidinthe
GDDR5SGRAMsinternaldatasynchronizationbetweenthelogicclockedbyCK/CK#andWCK/WCK#.
ThiswillhelptodefinebothReadandWritelatenciesbetweentheGDDR5SGRAMandmemorycontrol
ler.WCK2CKtrainingmodeiscontrolledviaMRS.
BeforestartingWCK2CKtraining,thefollowingconditionsmustbemet:
CK/CK#clockisstableandtoggling
Thetimingofalladdressandcommandpinsmustbeguaranteed
PLLon/off(MR1bitA7)andPLLdelaycompensationenable(MR7bitA2)aresettodesiredmodebeforeWCKto
CKtrainingisstarted
ThedesiredWCK2CKalignmentpoint(MR6,bitA0)isselected
TheEDCholdpattern(MR4,bitsA0A3)mustbeprogrammedto1111
2ModeRegisterbitsforinternalWCK01andWCK23inversion(MR3,bitsA2A3)mustbesettoaknownstate
Allbanksareidleandnoothercommandexecutionisinprogress
WCK2CKtrainingmustbedoneafteranyofthefollowingconditions:
Deviceinitialization
AnyCLmrs,WLmrs,CRCRLorCRCWLlatencychange
CKandWCKfrequencychanges
PLLon/off(MR1bitA7)andPLLdelaycompensationmode(MR7bitA2)changes
ChangeoftheWCK2CKalignmentpoint(MR6,bitA0)
WCKstatechangefromofftotoggling,includingselfrefreshexitorexitfrompowerdownwhenbitA1(LP2)in
MR5isset
Figure10andFigure11showexampleWCK2CKtrainingsequences.WCK2CKtrainingisenteredvia
MRSbysettingbitA4inMR3.ThiswillinitiatetheWCKdivideby2circuitsassociatedwithWCK01and
WCK23clocksintheGDDR5SGRAM.Incasethedivideby2circuitsareatoppositeoutputphases,
whichisindicatedbyoppositeearly/latephasesontheEDCpinsassociatedwithWCK01andWCK23
(seebelow),theymaybeputinphasebyusingtheWCK01andWCK23inversionbits.Alternatively,the
WCKclocksmaybeputintoastableinactivestateforthisinitializationeventtoaidinresettingalldivid
erstothesameoutputphaseasshownin<Link>Figure11.Thechallengeofthismethodistorestartthe
WCKclocksinawaythateventheirfirstclockedgesmeettheWCKclockinputspecification.Otherwise,
divideby2circuitsforbothWCK01andWCK23mightagainhaveoppositephasealignment.
Figure12illustrateshowtheWCKphaseinformationisderived.Thephasedetectors(PD)samplethe
internallydividedby2WCKclocks.Onlyonesamplepointisshowninthefigureforclarity.Inreality,
whenWCK2CKtrainingmodeisenabled,asamplewilloccureveryt
CK
andwillbetranslatedtotheEDC
pinsaccordingly.Ifthedividedby2WCKclockarrivesearly,thentheEDCpinoutputstheEDChold
patternduringthetimeintervalspecifiedinFigure12.Ifthedividedby2WCKclockarriveslate,thenthe
EDCpinoutputstheinvertedEDCholdpatternduringthetimeintervalspecifiedinFigure12.Thisis
showninTable11.
Rev. 1.0 / Nov. 2009 26
H5GQ1H24AFR
Figure 10:ExampleWCK2CKTrainingSequence
Figure 11:ExampleWCK2CKTrainingSequencewithWCKStopping
CK
CK#
NOP NOP MRS NOP NOP NOP NOP MRS MRS CMD A.C.
t
LK
t
MRD
EnterWCK2CKTraining StartWCK2CK
PhaseSearch
PLLReset ExitWCK2CKTraining
(setsdatasynchronizers,
restsFIFOpointers)
WCK
WCK#
(PLLononly)
NOP MRS NOP NOP NOP NOP MRS NOP NOP Valid MRS
CK#
CK
CMD
t
WCK2MRS
WCK
WCK#
t
MRSTWCK
t
WCK2TR
EnterWCK2CK
TrainingbyMRS
WCK
Restart
StartWCK2CK
PhaseSearch
t
LK
t
MRD
ExitWCK2CK
(resetsWCKdivide
by2circuits)
resetsFIFOpointers)
(Setdatasynchronizers,
TrainingbyMRS
PLLReset
(PLLononly)
Rev. 1.0 / Nov. 2009 27
H5GQ1H24AFR
Figure 12:EDCpinBehaviourforWCK2CKTraining(assumes1111asEDCHoldPattern)
Theidealalignmentisindicatedbythephasedetectoroutputtransitioningfromearlytolatewhen
thedelayoftheWCKphaseiscontinuouslyincreased.TheWCKphaserangeforidealalignmentisspeci
fiedbytheparametert
WCK2CKPIN
;thevalue(s)varywiththePLLmode(onoroff)andtheselectedalign
mentpoint.
Ifenabled,thePLLshallnotinterfereinthebehavioroftheWCK2CKtraining.Significantlymovingthe
phaseand/orstoppingtheWCKduringtrainingmaydisturbthePLL.ItisrequiredtoperformaPLLreset
aftertheWCK2CKtraininghasdeterminedandselectedtheproperalignmentbetweenWCKandCK
clocks.ThePLLlocktimet
LK
mustbemetbeforeexitingWCK2CKtrainingtoguaranteethatthePLLisin
locksuchthattheGDDR5SGRAMdatasynchronizersaresetuponWCK2CKtrainingexit.
WCK2CKtrainingisexitedviaMRSbyresettingbitA4inMR3.Forproperresetofthedatasynchronizers
itisrequiredthattheWCKandCKclocksarealignedwithint
WCK2CKSYNC
atthetimeoftheWCK2CK
trainingexit.
Table 11PhaseDetectorandEDCPinbehavior
WCK/2valuesampledbyCK WCK2CKPhase DataonEDCPin Action
1 Early EDChold(1111) IncreaseDelayonWCK
0 Late InvertedEDCHold(0000) DecreaseDelayonWCK
x
EDC0
CK
WCK01/2
WCK23/2
(internal)
x x x x x x x x x x x x x x
EDC2
1
t
WCK2CK
t
WCKTPH
WCKEarly
EDC0
WCK01/2
WCK23/2
(internal)
x x x x x x x x x x x x x x x
EDC2
0
+t
WCK2CK
t
WCKTPH
WCKLate
1
2
1111
0000
EDC0
WCK01/2
WCK23/2
(internal)
x x x x x x x x x x x x x x x
EDC2
t
WCKTPH
3
x x x x
Aligned
Late
Early
~ ~
~ ~
~ ~
Rev. 1.0 / Nov. 2009 28
H5GQ1H24AFR
AfterexitingWCK2CKtrainingmode,theWCKphaseisallowedtofurtherdriftfromtheidealalignment
pointbyamaximumoft
WCK2CK
(e.g.duetovoltageandtemperaturevariation).OncethisWCKphase
driftexceedst
WCK2CK
(min)ort
WCK2CK
(max),itisrequiredtorepeattheWCK2CKtrainingandrealign
theclocks.
WCK2CKalignmentatPINMode
TheWCKandCKphasealignmentpointcanbechangedviaMRSbysettingbitA0inMR6.Innormal
mode,whenMR6A0issetto0,thephasesofCKandWCKarealignedatCKpinsandtheendofWCK
treeasshowninFigure13.Ontheotherhand,whenMR6A0issetto1,thephasesofCKandWCKare
alignedatthepinasshowninFigure14.PINmodeissupporteduptothemaxCKclockfrequencyof
f
CKPIN
,andisanoptiontoreducethetimeofWCK2CKtrainingatlowfrequency.
Figure 13:NormalMode
Figure 14:PinMode
WCK2CKAutoSynchronization
GDDR5SGRAMssupportaWCK2CKautomaticsynchronizationmodethateliminatestheneedfor
WCK2CKtraininguponpowerdownexit.Thismodeiscontrolledbytheautosyncbit(MR7,bitA4),and
iseffectivewhentheLP2bit(MR5,bitA1)issetandtheWCKclocksarestoppedduringpowerdown.
CK
CK#
WCK
WCK#
D Q
CK
EDC
InternalWCK/2
InternalCK
Phase
Detector
CK
CK#
WCK
WCK#
D Q
CK
EDC
InternalWCK/2
InternalCK
Phase
Detector
Rev. 1.0 / Nov. 2009 29
H5GQ1H24AFR
Also,thismodeworksforbothnormalandPINmode.WhenWCK2CKautomaticsynchronizationmode
isenabled,afullWCK2CKtrainingincludingPhasesearchisnotrequiredafterpowerdownexit,
althoughWCK2CKMRSmustbeissuedmomentarilyforsettingthedatasynchronizers.However,WCK
andCKclocksmustmeetthet
WCK2CKSYNC
specificationuponpowerdownexit.Anyallowedcommand
maybeissuedaftert
XPN
oraftert
LK
incasethePLLhadbeenenableduponpowerdownentry.ThePLL
sequenceisnotaffectedbythismode.TheuseofWCK2CKautomaticsynchronizationmodeisrestricted
toloweroperatingfrequenciesuptof
CKAUTOSYNC
asdescribedinthedatasheets.
Table12describesWCK2CKtrainingmethodsfordifferentfrequencyranges.EachFrequencyrangeis
vendorspecific.NormalandPINmodeofWCK2CKtrainingaredescribedinTable12.Eachfrequency
rangeisDRAMvendorspecific.DividerinitializationcanbedonebytrainingwithWCK2CKinversion,
WCK2CKstopping,orWCK2CKautosync.IftheuserwantstouseWCK2CKstopfordividerinitializa
tioninsteadofWCK2CKautosync,theusermustnotsettheWCK2CKautosync.Lowfrequency,the
combineduseofPINandWCK2CKautosyncmodescanminimizeWCK2CKtrainingtime.
*Note:ThedividedWCK/WCK#shouldbealignedCK/CK#byWCK2CKAutoSynchronizationorWCKstopmode
ThefollowingexamplesdescribetheWCK2CKtraininginmoredetail.
Example1:outlineofabasicWCK2CKtrainingsequencewithoutWCKclockstop:
1) EnabletrainingmodeviaMRSandwaitt
MRD
2) SweepandobservethephaseindependentlyforWCK01onEDC0andWCK23onEDC2;incase
theinternaldivideby2circuitsareatoppositephaseuseeithertheWCK01orWCK23inversion
bit
tofliponeoftheWCKdivideby2circuits
3) AdjusttheWCKphaseindependentlyforWCK01andWCK23totheoptimalpoint(ideal
alignment)
4) IssueaPLLresetandwaitfort
LK
(PLLonmodeonly)
5) WhileallWCKandCKarealigned,exitWCK2CKtrainingmodeviaMRS
6) Waitt
MRD
fortheresetofdatasynchronizers
Table 12WCK2CKtrainingsimplifiedforNormalmodeandPINmode
HighFrequency LowFrequency
Frequency
2Gbps
2Gbps
WCK2CKalignmentmode Normal PIN Normal PIN
PhaseSearch Required Required No* No*
Rev. 1.0 / Nov. 2009 30
H5GQ1H24AFR
Example2:outlineofabasicWCK2CKtrainingsequencewithoptionalWCKclockstop:
1) StopWCKclockswithWCK01/WCK23LOWandWCK01#/WCK23#HIGH
2) Waitt
WCK2MRS
forinternalWCKclockstosettle
3) EnabletrainingmodeviaMRSandwaitt
MRD
fordivideby2circuitstoreset
4) StartWCKclockswithoutglitches(bothdivideby2circuitsremaininsync)
5) Waitt
WCK2TR
forinternalWCKclockstostabilize
6) SweepandobservethephaseindependentlyforWCK01onEDC0andWCK23onEDC2;adjust
the
WCKphasetotheoptimalpoint(idealalignment)
7) IssueaPLLresetandwaitt
LK
(PLLonmodeonly)
9) Waitt
MRD
READandWRITElatencytimingsaredefinedrelativetoCK.AnyoffsetinWCKandCKatthepinsand/
orthephasedetectorwillbereflectedinthelatencytimings.Theparametersusedtodefinetherelation
shipbetweenWCKandCKareshowninFigure6.FormoredetailsontheimpactonREADandWRITE
timingsseetheOPERATIONSsection.
Figure 15:WCK2CKTimings
CK
CK#
t
CH
t
CL
t
CK
WCK
WCK#
t
WCK2CKPIN
Case1:Negativet
WCK2CKPIN
;t
WCK2CK
=0(idealWCK2CKalignment)
t
WCK
WCK
WCK#
Case2:Negativet
WCK2CKPIN
;negativet
WCK2CK
WCK
WCK#
t
WCK2CKPIN
Case3:Positivet
WCK2CKPIN
;t
WCK2CK
=0(idealWCK2CKalignment)
t
WCK2CKPIN
+t
WCK2CK
WCK#
WCK
Case4:Positivet
WCK2CKPIN
;positivet
WCK2CK
t
WCK2CKPIN
+t
WCK2CK
Note: t
WCK2CKPIN
andt
WCK2CK
parametervaluescouldbenegativeorpositivenumbers,dependingontheselected
WCK2CKalignmentpoint,PLLonorPLLoffmodeoperationanddesignimplementation.Theyalsovaryacross
PVT.WCK2CKtrainingisrequiredtodeterminethecorrectWCKtoCKphaseforstabledeviceoperation.
t
WCKH
t
WCKL
Rev. 1.0 / Nov. 2009 31
H5GQ1H24AFR
GDDR5WCK2CKTraininginx16mode
ForconfigurationswithWCKclocksnotsharedbetweentwoGDDR5SGRAMsitissuggestedtosetthe
WCKphasetotheidealalignmentpoint.However,forconfigurationswheretwoGDDR5SGRAMs(x16)
sharetheirWCKclocksasinax16clamshell,anoffsetgivenbythemidpointofbothDRAMsidealWCK
positionsmayberequired.Themaximumallowedoffsetinthiscaseisspecifiedbyparameter
t
WCK2CKSYNC
:itdefinestheWCKoffsetrangefromtheidealalignmentwhichstillguaranteesaGDDR5
SGRAMdevicetointernallysynchronizeitsWCKandCKclocksupontrainingexit.
Example:outlineoftrainingsequenceforx32andx16configurationswith2GDDR5SGRAMssharing
theirWCKclocks(e.g.clamshell):
1) EnabletrainingmodeforbothDRAMsviaMRSandwaitt
MRD
2) ForbothDRAMssweepandobservethephaseindependentlyforWCK01onEDC0andWCK23
on
EDC2;incasetheinternaldivideby2circuitsareatoppositephasesuseeithertheWCK01or
WCK23inversionbittofliponeoftheWCKdivideby2circuits;incaseofsharedCS#signalsuse
MREMF0andMREMF1bitsinMR15toexplicitlydirecttheMRScommandforthisphaseflipping
toeitherDRAM1orDRAM2(softchipselect);
3) SweepandobservethephaseonDRAM1independentlyforWCK01onEDC0andWCK23on
EDC2;storethesettingfortheoptimalWCKphase
4) SweepandobservethephaseonDRAM2independentlyforWCK01onEDC0andWCK23on
EDC2;storethesettingfortheoptimalWCKphase
5) SweepWCK01andWCK23phasetomidpointofDRAM1andDRAM2optimalsettings
6) IssueaPLLresetandwaitfort
LK
(PLLonmodeonly)
8) Waitt
MRD
Rev. 1.0 / Nov. 2009 32
H5GQ1H24AFR
3.4.READTRAINING
Readtrainingallowsthememorycontrollertofindthedataeyecenter(symboltraining)andburstframe
location(frametraining)foreachhighspeedoutputoftheGDDR5SGRAM.Eachpin(DQ0DQ31,DBI0#
DBI3#,EDC0EDC3)canbeindividuallytrainedduringthissequence.
ForReadTrainingthefollowingconditionsmustbetrue:
atleastonebankisactive,oranautorefreshmustbeinprogressandbitA2inModeRegister5(MR5)issetto0to
allowtrainingduringautorefresh(todisablethisspecialREFenablingoftheWCKclocktreeanACTcommand
mustbeissued,orthedevicemustbesetintopowerdownorselfrefreshmode)
WCK2CKtrainingmustbecomplete
thePLLmustbelocked,ifenabled
RDBIandWDBImustbeenabledpriortoandduringReadTrainingifthetrainingshallincludetheDBI#pins.
RDCRCandWRCRCmustbeenabledpriortoandduringReadTrainingifthetrainingshallincludetheEDC
pins.
ThefollowingcommandsareassociatedwithReadTraining:
LDFFtopreloadtheReadFIFO;
RDTRtoreadaburstofdatadirectlyoutoftheReadFIFO.
NeitherLDFFnorRDTRaccessthememorycore.NoMRSisrequiredtoenterReadTraining.
Figure16showsanexampleoftheinternaldatapathsusedwithLDFFandRDTR.Table13listsACtiming
parametersassociatedwithReadTraining.
Table 13LDFFandRDTRTIMINGS
PARAMETER SYMBOL
VALUES
UNIT NOTES
MIN MAX
ACTIVEtoLDFFcommanddelay t
RCDLTR
10 ns
ACTIVEtoRDTRcommanddelay t
RCDRTR
10 ns
REFRESHtoRDTRorWRTRcommanddelay t
REFTR
10 ns
RDTRtoRDTRcommanddelay t
CCDS
2 t
CK
LDFFtoLDFFcommandcycletime t
LTLTR
4 t
CK
LDFF(111)toLDFFcommandcycletime t
LTL7TR
4 t
CK
a
a. Themin.valuedoesnotexceed8t
CK
.
LDFF(111)toRDTRcommanddelay t
LTRTR
4 t
CK
READorRDTRtoLDFFcommanddelay t
RDTLT
4 t
CK
Rev. 1.0 / Nov. 2009 33
H5GQ1H24AFR
Figure 16:DataPathsusedforReadandWriteTraining
LDFFCommand
TheLDFFcommand(Figure17)isusedtosecurelyloaddatatotheGDDR5SGRAMReadFIFOsviathe
addressbus.DependingontheGDDR5SGRAMREADFIFOdepthnFIFO6,anybitpatternoflength32
48canbeloadeduniquelytoeveryDQ,DBI#andEDCpinwithinabyte.TheFIFOdepthisfixedby
designandcanbereadviatheVendorIDfunction.
EightLDFFcommandsarerequiredtofilloneFIFOstage;eachLDFFcommandloadsoneburstposition,
andthebankaddressesBA0BA2selecttheburstpositionfrom0to7.
ThedatapatternisconveyedonaddresspinsA0A7forDQ0DQ7,A9forDBI0#,andBA3forEDC0;the
dataareinternallyreplicatedtoall4bytes,asshowninFigure18.
72
WRTRstrobe
(CKdomain)
WRTR
FIFO6 72=432 bitsperbyte
RDTRstrobe
(WCK)
Reverse
DBI
DRAM
Core
64
64
WRTR
output
pointer
input
pointer
DQ0DQ7
DBI0#
EDC0
e.g.500Mbps
DBI
e.g.4Gbps
e.g.
500Mbps
RDTRstrobe
(WCK)
72
LDFF
ADDR
72
8
DEMUX
LDFF
8
10
BA0BA2
Notes:
1)FIFOdepthof5shown;supportedFIFOdepths:4,5or6
2)datapathsshownfor1of4bytes(byte0)
Address
Path
4 3 2 1 0 4 3 2 1 0
output
pointer
input
pointer
4 3 2 1 0 4 3 2 1 0
9
0
8
16
24
32
40
48
56
64
1
9
17
25
33
41
49
57
65
2
10
18
26
34
42
50
58
66
3
11
19
27
35
43
51
59
67
4
12
20
28
36
44
52
60
68
5
13
21
29
37
45
53
61
69
6
14
22
30
38
46
54
62
70
7
15
23
31
39
47
55
63
71
8 8:1 TX
9
ParalleltoSerial
Converter
SerialtoParallel
Converter
72 8:1 RX
8:1
ParalleltoSerial
Converter
CRCstrobe
LDFFstrobe(burst7)
WRTRstrobe
LDFFstrobe(burst7)
M
U
X
M
U
X
72
M
U
X
DQ
72
M
U
X
8
CRC8
RX
DatapathusedwithRDTR
DatapathusedwithWRTR
8
M
U
X
0 1 2 3 4 5 6 7
CRCFIFO6 8=48 bitsper byte
DatapathusedwithLDFF
DatapathusedwithLDFF/WRTR
TX
5
5
Rev. 1.0 / Nov. 2009 34
H5GQ1H24AFR
LDFFloadstheDBIFIFOregardlessoftheWDBIandRDBIModeRegisterbits.ItalsoloadstheEDCFIFO
regardlessoftheWRCRCandRDCRCModeRegisterbits,andnoCRCiscalculated;however,RDBIand
RDCRCmustbeenabledtoreadtheDBIandEDCbits,respectively,withtheRDTRcommand.
Figure 17:LDFFCommand
CS#
WE#
CAS#
RAS#
CKE# LOW
LDFF
CK
CK#
A9,BA3
A1,A3
A8,A10,A11
BA0BA2
A2,A4,A5
0,0,1
A0,A7,A6
DATA DATA
DATA
DATA
DATA=FIFOdata
BP
BP=BurstPosition
Rev. 1.0 / Nov. 2009 35
H5GQ1H24AFR
Figure 18:LDFFCommandAddresstoDQ/DBI#/EDCMapping
Allburstaddresses0to7mustbeloaded;LDFFcommandstoburstaddress0to6maybeissuedinran
domorder;theLDFFcommandtoburstaddress7(LDFF7)mustbethelastof8consecutiveLDFFcom
mands,asiteffectivelyloadsthedataintotheFIFOandresultsinaFIFOpointerincrement.Consecutive
LDFFcommandshavetobespacedbyatleastt
LTLTR
,andatleastt
LTL7TR
cyclesarerequiredaftereach
LDFFcommandtoburstaddress7.
LDFFpatternmayefficientlybereplicatedtothenextFIFOstagesbyissuingconsecutiveLDFFcommands
toburstaddress7(withidenticaldatapattern).ThedatapatterninthescratchmemoryforLDFFwillbe
availableuntilthefirstRDTRcommand.
TheDQ/DBI#outputbuffersremaininODTstateduringLDFF.
AnamountofLDFFcommandstoburstaddress7greaterthantheFIFOdepthisallowedandshallresult
inaloopingoftheFIFOsdatainput.
ThetotalnumberofLDFFcommandstoburstaddress7moduloFIFOdepthmustequalthetotalnumber
ofRDTRcommandsmoduloFIFOdepthwhenusedinconjunctionwithRDTR.NoREADorWRITEcom
mandsareallowedbetweenLDFFandRDTR.
TheEDCholdpatternisdrivenontheEDCpinsduringLDFF(providedRDQSmodeisnotenabled).
A0
A1
A6
A3
A4
A5
A7
A10
A9
A11
BA1
A8
A0
A1
A2
A3
A9
A4
A5
A6
A7
1FIFOSTAGE=1BURST
0 1 2 3 4 5 6 7
7 6 5 4 3 2 1 0
1 1 1 1 0 0 0 0
1 1 0 0 1 1 0 0
1 0 1 0 1 0 1 0
H
L
BurstPosition
BA2
BA1
BA0
CK
LDFFFIFOLoadPulse
L
LDFFCommand
CK#
AddresstoDQMapping
BA3
BA3
DBI0# DBI1# DBI2# DBI3#
EDC0 EDC1 EDC2 EDC3
DQ7 DQ15 DQ23 DQ31
DQ6 DQ14 DQ22 DQ30
DQ5 DQ13 DQ21 DQ29
DQ4 DQ12 DQ20 DQ28
DQ3 DQ11 DQ19 DQ27
DQ2 DQ10 DQ18 DQ26
DQ1 DQ9 DQ17 DQ25
DQ0 DQ8 DQ16 DQ24
Byte0 Byte1 Byte2 Byte3
A2 BA0
BA2
Rev. 1.0 / Nov. 2009 36
H5GQ1H24AFR
RDTRCommand
ARDTRburstisinitiatedwithaRDTRcommandasshowninFigure19.Nobankorcolumnaddressesare
usedasthedataisreadfromtheinternalREADFIFO,notthearray.Thelengthoftheburstinitiatedwith
aRDTRcommandiseight.ThereisnointerruptionnortruncationofRDTRbursts.
Figure 19:RDTRCommand
ARDTRcommandmayonlybeissuedwhenabankisopenorarefreshisinprogressandbitA2inMR5
issetto0toallowtrainingduringrefresh.
RDBIandRDCRCmustbeenabledtoreadtheDBIandEDCbits,respectively,withtheRDTRcommand.
Ifnotset,theDBI#pinswillremaininODTstate,andtheEDCpinswilldrivetheEDCholdpattern.
IncaseoftheRDQSmode,theEDCpinfunctionslikewithanormalREADinthismode.TheDBI#pin
behaveslikeaDQ,andnoencodingwithDBIisperformed.
AnamountofRDTRcommandsgreaterthantheFIFOdepthisallowedandshallresultinaloopingofthe
FIFOsdataoutput.TheFIFOdepthfromwhichtheRDTRdataisreadmustbeanumberbetween46and
mustbespecifiedbytheDRAMvendor.TheFIFOdepthisreadviatheVendorIDfunction.
DuringRDTRbursts,thefirstvaliddataoutelementwillbeavailableaftertheCASlatency(CL).The
latencyisthesameasforREAD.ThedataontheEDCpinscomeswithadditionalCRClatency(t
CRCRD
)
aftertheCL.
Uponcompletionofaburst,assumingnootherRDTRcommandhasbeeninitiated,allDQandDBI#pins
willdriveavalueof1andtheODTwillbeenabledatamaximumof1t
CK
later.Thedrivevalueandter
minationvaluemaybedifferentduetoseparatelydefinedcalibrationoffsets.IftheODTisdisabled,the
pinswilldriveHiZ.
CS#
WE#
CAS#
RAS#
CKE#
A9(A12)
A1
A8,A10,A11
BA0BA3
A2A5
LOW
RDTR
CK
CK#
0,1,1
A7,A0,A6
Rev. 1.0 / Nov. 2009 37
H5GQ1H24AFR
DatafromanyRDTRburstmaybeconcatenatedwithdatafromasubsequentRDTRcommand.Acontin
uousflowofdatacanbemaintained.Thefirstdataelementfromthenewburstfollowsthelastelementof
acompletedburst.ThenewRDTRcommandshouldbeissuedafterthefirstRDTRcommandaccordingto
thet
CCDS
timing.
AWRTRcanbeissuedanytimeafteraRDTRcommandaslongasthebusturnaroundtimet
RTW
ismet.
ThetotalnumberofRDTRcommandsmoduloFIFOdepthmustbeequaltototalnumberofWRTRcom
mandsmoduloFIFOdepthwhenusedinconjunctionwithWRTR.NoREADorWRITEcommandsare
allowedbetweenWRTRandRDTR.
ThetotalnumberofRDTRcommandsmoduloFIFOdepthmustbeequaltothetotalnumberofLDFF
commandstoburstposition7moduloFIFOdepthwhenusedinconjunctionwithLDFF.NoREADor
WRITEcommandsareallowedbetweenLDFFandRDTR.
Rev. 1.0 / Nov. 2009 38
H5GQ1H24AFR
3.5.WRITETRAINING
Writetrainingallowsthememorycontrollertofindthedataeyecenter(symboltraining)andburstframe
location(frametraining)foreachhighspeedinputoftheGDDR5SGRAM.Eachpin(DQ0DQ31,DBI0#
DBI3#)canbeindividuallytrainedduringthissequence.
ForWriteTrainingthefollowingconditionsmustbetrue:
atleastonebankisactive,oranautorefreshmustbeinprogressandbitA2inModeRegister5(MR5)issetto0to
allowtrainingduringautorefresh(todisablethisspecialREFenablingoftheWCKclocktreeanACTcommand
mustbeissued,orthedevicemustbesetintopowerdownorselfrefreshmode)
thePLLmustbelocked,ifenabled.
WCK2CKtrainingshouldbecomplete
Readtrainingshouldbecomplete
RDBIandWDBImustbeenabledpriortoandduringWriteTrainingifthetrainingshallincludetheDBI#pins.
RDCRCandWRCRCmustbeenabledpriortoandduringWriteTrainingifthetrainingshallincludetheEDC
pins.
ThefollowingcommandsareassociatedwithWriteTraining:
WRTRtowriteaburstofdatadirectlyintotheReadFIFO;
RDTRtoreadaburstofdatadirectlyoutoftheReadFIFO.
NeitherWRTRnorRDTRaccessthememorycore.NoMRSisrequiredtoenterWriteTraining.
Figure16showsanexampleoftheinternaldatapathsusedwithWRTRandRDTR.Figure21showsatyp
icalWritetrainingcommandsequenceusingWRTRandRDTR.Table14listsACtimingparametersasso
ciatedwithWRITETraining.
Table 14WRTRandRDTRTimings
PARAMETER SYMBOL
VALUES
UNIT NOTES
MIN MAX
ACTIVEtoWRTRcommanddelay t
RCDWTR
10 ns
ACTIVEtoRDTRcommanddelay t
RCDRTR
10 ns
REFRESHtoRDTRorWRTRcommanddelay t
REFTR
10 ns
RD/WRbankAtoRD/WRbankBcommanddelay
differentbankgroups
t
CCDS
2 t
CK
a
a. t
CCDS
iseitherforgaplessconsecutiveREADorRDTR(anycombination),gaplessconsecutiveWRITE,orgaplessconsecutive
WRTRcommands.
WRTRtoRDTRcommanddelay t
WTRTR
WLtWLmin t
CK
WRITEtoWRTRcommanddelay t
WRWTR
WL+CRCWL+2 t
CK
READorRDTRtoWRITEorWRTRcommanddelay t
RTW
1 ns
b
b. t
RTW
isnotadevicelimitbutdeterminedbythesystembusturnaroundtime.Thedifferencebetweent
WCK2DQO
andt
WCK2DQI
shallbeconsideredinthecalculationofthebusturnaroundtime.
Rev. 1.0 / Nov. 2009 39
H5GQ1H24AFR
WRTRCommand
AWRTRburstisinitiatedwithaWRTRcommandasshowninFigure20.Nobankorcolumnaddresses
areusedasthedataiswrittentotheinternalREADFIFO,notthearray.Thelengthoftheburstinitiated
withaWRTRcommandiseight.ThereisnointerruptionnortruncationofWRTRbursts.
Figure 20:WRTRCommand
AWRTRcommandmayonlybeissuedwhenabankisopenorarefreshisinprogressandbitA2inMR5
issetto0toallowtrainingduringrefresh.
WDBIandWRCRCmustbeenabledtowritetheDBIandEDCbits,respectively,withtheWRTRcom
mand.IfWDBIisnotset,a1willbewrittentotheDBIFIFO,anda1willbeassumedfortheDBI#input
intheCRCcalculation.IncontrasttoanormalWRITE,noCRCisreturnedbytheWRTRcommandand
theEDCpinswilldrivetheEDCholdpattern.
IncaseoftheRDQSmode,theEDCpinfunctionslikewithanormalREADinthismode.Pleasenotethat
RDCRCmustbeenabledtoreadthecalculatedCRCdatawiththeRDTRcommand.
AnamountofWRTRcommandsequaltotheFIFOdepthisrequiredtofullyloadtheFIFO;anynumberof
WRTRcommandsgreaterthantheFIFOdepthisallowedandshallresultinaloopingoftheFIFOsdata
input.TheFIFOdepthtowhichtheWRTRdataiswrittenmustbe6.TheFIFOdepthisreadviatheVen
dorIDfunction.
DuringWRTRbursts,thefirstvaliddatainelementmustbeavailableattheinputlatchaftertheWrite
Latency(WL).TheWriteLatencyisthesameasforWRITE.
Uponcompletionofaburst,assumingnootherWRTRdataisexpectedonthebustheGDDR5SGRAM
DQandDBI#pinswillbedrivenaccordingtotheODTstate.Anyadditionalinputdatawillbeignored.
WRTR
CS#
WE#
CAS#
RAS#
CKE# LOW
CK
CK#
A9(A12)
A1
A8,A10,A11
BA0BA3
A2A5
0,1,1
A7,A0,A6
Rev. 1.0 / Nov. 2009 40
H5GQ1H24AFR
DatafromanyWRTRburstmaybeconcatenatedwithdatafromasubsequentWRTRcommand.Acontin
acompletedburst.ThenewWRTRcommandshouldbeissuedafterthepreviousWRTRcommand
accordingtothet
CCDS
timing.
ARDTRcanbeissuedanytimeafteraWRTRcommandaslongastheinternalbusturnaroundtime
t
RTWTR
ismet.
ThetotalnumberofWRTRcommandsmoduloFIFOdepthmustequalthetotalnumberofRDTRcom
mandsmoduloFIFOdepthwhenusedinconjunctionwithRDTR.NoREADorWRITEcommandsare
allowedbetweenWRTRandRDTR.
Figure 21:WriteTrainingusingWRTRandRDTRCommands
CK#
CK
CMD
WLmrs
DQ
NOP WRTR
1.WLmrs,CLmrsandCRCRLsetto1foreaseofillustration;checkModeRegisterdefinitionforsupportedsettings
WRTR
ADDR
T0 T1 T2 T3 T4 T5 Ta Ta+1 Ta+2 Ta+3 Ta+4
NOP NOP NOP RDTR NOP RDTR NOP NOP
WCK
WCK#
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
EDC
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
EDCHold EDCHold EDCHold EDCHold EDCHold EDCHold EDCHold EDCHold
DontCare
WLmrs
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
0
D
1
CLmrs CRCRL CLmrs CRCRL
t
WTRTR
2.WCKandCKareshownaligned(t
WCK2CKPIN
=0,t
WCK2CK
=0)forillustrationpurposes.WCK2CKtrainingdeterminestheneededoffsetbetweenWCKandCK.
Rev. 1.0 / Nov. 2009 41
H5GQ1H24AFR
4.MODEREGISTERS
GDDR5 specifies 10 Mode Registers to define the specific mode of operation. MR0 to MR7 and MR15 are defined as shown in
the overview in Figure 22. MR8 to MR13 are not defined and may be used by DRAM vendors for vendor specific features. Repro-
gramming the Mode Registers will not alter the contents of the memory array.
All Mode Registers are programmed via the MODE REGISTER SET (MRS) command and will retain the stored information until
they are reprogrammed or the device loses power. Mode Registers must be loaded when all banks are idle and no bursts are in
progress, and the controller must wait the specified time t
MRD
before initiating any subsequent operation. Violating either of these
requirements will result in unspecified operation.
No default states are defined for Mode Registers except when otherwise noted. Users therefore must fully initialize all Mode Reg-
isters to the desired values e.g. upon power-up.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result. RFU bits are
reserved for future use and must be programmed to 0. Bit A12 is not used for any mode register programming as this address input
is not defined for 1G density.
BA3 BA2 BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
MR0 0 0 0 0 0 WriteRecovery(WR) TM CASLatency(CLmrs)
WriteLatency
(WLmrs)
MR1 0 0 0 1 0
PLL
Reset
ABI WDBI RDBI PLL
Cal
Upd
ADR/CMD
Termination
Data
Termination
Driver
Strength
MR2 0 0 1 0 0
ADR/CMD
TerminationOffset
DataandWCK
TerminationOffset
OCDPullup
DriverOffset
OCDPulldown
DriverOffset
MR3 0 0 1 1 0
Bank
Groups
WCK
Termination
Info
RDQS
Mode
WCK
2CK
WCK
23Inv
WCK
01Inv
SelfRefresh
MR4 0 1 0 0 0
EDC
13Inv
WR
CRC
RD
CRC
CRCRead
Latency
(CRCRL)
CRCWriteLatency
(CRCWL)
EDCHoldPattern
MR5 0 1 0 1 0 RFU
PLLBandwidth
(PLLBW)
LP3 LP2 RFU
MR6 0 1 1 0 0
VREFDOffset
Upper2bytes
VREFDOffset
Lower2bytes
VREFD
Auto
VREFD
VREFD
Merge
WCK
PIN
MR7 0 1 1 1 0 DCC RFU
Half
VREFD
Temp
Sense
DQ
PreA
Auto
Sync
LF
Mode
RFU
MR14 RFU
MR15 1 1 1 1 0 RFU ADT
MRE
MF1
MRE
MF0
X X X X X X X X
Figure 22. Mode Registers Overview
Rev. 1.0 / Nov. 2009 42
H5GQ1H24AFR
4.1.MODEREGISTER0(MR0)
ModeRegister0controlsoperatingmodessuchasWriteLatency,CASlatency,WriteRecoveryandTest
ModeasshowninFigure23.
TheregisterisprogrammedviatheMODEREGISTERSET(MRS)commandwithBA0=0,BA1=0,BA2=0
andBA3=0.
0 0 0 0 0 WriteRecovery(WR) TM CASLatency(CLmrs)
WriteLatency
(WLmrs)
A11 A10 A9 A8
WriteRecovery
(WR)
0 0 0 0 4
0 0 0 1 5
0 0 1 0 6
0 0 1 1 7
0 1 0 0 8
0 1 0 1 9
0 1 1 0 10
0 1 1 1 11
1 0 0 0 12
1 0 0 1 13
1 0 1 0 14
1 0 1 1 15
1 1 0 0 16
1 1 0 1 17
1 1 1 0 18
1 1 1 1 19
A7 TestMode
0 Normal
1 TestMode
A2 A1 A0
WriteLatency
(WLmrs)
0 0 0 RFU
0 0 1 1
0 1 0 2
0 1 1 3
1 0 0 4
1 0 1 5
1 1 0 6
1 1 1 7
A6 A5 A4 A3 CASLatency(CLmrs)
0 0 0 0 5
0 0 0 1 6
0 0 1 0 7
0 0 1 1 8
0 1 0 0 9
0 1 0 1 10
0 1 1 0 11
0 1 1 1 12
1 0 0 0 13
1 0 0 1 14
1 0 1 0 15
1 0 1 1 16
1 1 0 0 17
1 1 0 1 18
1 1 1 0 19
1 1 1 1 20
Figure 23. Mode Register 0 (MR0) Definition
Rev. 1.0 / Nov. 2009 43
H5GQ1H24AFR
WRITELatency(WLmrs)
TheWRITElatency(WLmrs)isthedelayinclockcyclesusedinthecalculationofthetotalWRITElatency
(WL) between the registration of a WRITE command and the availability of the first piece of input data.
DRAMvendorspecificationsshouldbecheckedforvalue(s)ofWLmrssupported.ThefullWRITElatency
definitioncanbefoundinthesectionentitledOPERATION.
WhentheWRITElatenciesaresettosmallvalues(i.e.1,2,...clocks),theinputreceiversneverturnoff,in
turn,raisingtheoperatingpower.WhentheWRITElatencyissettohighervalues(i.e...6,7clocks)theinput
receivers turn on when the WRITE command is registered. Refer to vendor datasheets for value(s) of
WLmrswheretheinputreceiversarealwaysonoronlyturnonwhentheWRITEcommandisregistered
Speed
AllowableOperatingFrequency(Gbps)
WL7 WL6 WL5 WL4 WL3 WL2 WL1
6.0Gbps
5.5Gbps
5.0Gbps
4.5Gbps
4.0Gbps
CASLatency(CLmrs)
The CAS latency (CLmrs) is the delay in clock cycles used in the calculation of the total READ latency
(CL)betweentheregistrationofaREADcommandandtheavailabilityofthefirstpieceofoutputdata.
BydefaultCLmrsisspecifiedbybitsA3A6,definingaCLmrsrangeof5to20tCK.
DRAMvendorspecificationsshouldbecheckedforvalue(s)ofCLmrssupported.ThefullREADlatency
definitioncanbefoundinthesectionentitledOPERATION
Speed
RDBI
ON/OFF
CL20 CL19 CL18 CL17 CL16 CL15 CL14 CL13 CL12
6.0Gbps
OFF
ON
5.5Gbps
OFF
ON
5.0Gbps
OFF
ON
4.5Gbps
OFF
ON
4.0Gbps
OFF
ON
Rev. 1.0 / Nov. 2009 44
H5GQ1H24AFR
WRITERecovery(WR)
TheprogrammedWRvalueisusedfortheautoprechargefeaturealongwitht
RP
todeterminet
DAL
.The
WR register bits are not a required function and may be implemented at the discretion of the DRAM
manufacturer.
WRmustbeprogrammedwithavaluegreaterthanorequaltoRU{t
WR
/t
CK
},whereRUstandsforround
up,t
WR
istheanalogvaluefromthevendordatasheetandt
CK
istheoperatingclockcycletime.
BydefaultWRisspecifiedbybitsA8A11,definingaWRrangeof4to19tCK.
TestMode
ThenormaloperatingmodeisselectedbyissuingaMODEREGISTERSETcommandwithbitA7setto
0,andbitsA0A6andA8A11settothedesiredvalues.ProgrammingbitA7to1placesthedeviceintoa
testmodethatisonlytobeusedbytheDRAMmanufacturer.Nofunctionaloperationisspecifiedwithtest
modeenabled.
Rev. 1.0 / Nov. 2009 45
H5GQ1H24AFR
ModeRegister1controlsfunctionslikedrivestrength,datatermination,address/commandtermination,
ReadDBI,WriteDBI,ABI,controlofcalibrationupdatesandPLLasshowninFigure24.
andBA3=0.BitsA0A1,A4A6andA10ofthisregisterareinitializedwith0s.
ImpedanceAutocalibrationofOutputBufferandActiveTerminator
GDDR5SGRAMsofferautocalibratingimpedanceoutputbuffersandondieterminations.Thisenablesa
user to match the driver impedance and terminations to the system within a given range. To adjust the
impedance,anexternalprecisionresistorisconnectedbetweentheZQpinandV
SSQ
.Anominalresistor
A1 A0 DriverStrength
0 0 AutoCalibrationOn
0 1 RFU
1 0 Nominal(60/40)
1 1 RFU
0 0 0 1 0
PLL
Reset
ABI WDBI RDBI PLL
Cal
Upd
ADR/CMD
Termination
Data
Termination
Driver
Strength
A3 A2 DataTermination
0 0 Disabled
0 1 ZQ/2
1 0 ZQ
1 1 RFU
A5 A4 ADD/CMDTermination
0 0 CKE#valueatReset
0 1 ZQ/2
1 0 ZQ
1 1 Disabled
A7 PLL
0 Off
1 On
A11 PLLReset
0 No
1 Yes
A9 WriteDBI
0 On
1 Off
A10 ABI
0 On
1 Off
A8 ReadDBI
0 On
1 Off
A6 CalibrationUpdate
0 On
1 Off
Rev. 1.0 / Nov. 2009 46
H5GQ1H24AFR
valueof120Ohmsis equivalenttothe 40 OhmsPulldownand60OhmsPullupnominalimpedancesof
GDDR5SGRAMs.RESET#,CKandCK#arenotinternallyterminated.CKandCK#shallbeterminatedon
thesystemusingexternal1%resistorstoV
DDQ
.
The output driver and ondie termination impedances are updated during all REFRESH commands to
compensateforvariationsinsupplyvoltageandtemperature.Theimpedanceupdatesaretransparentto
thesystem.
DriverStrength
Bits A0 and A1 define the driver strength. The Auto Calibration setting enables the AutoCalibration
functionality for the Pulldown, Pullup and Termination over process, temperature and voltage changes.
Thedesigntargetforthefactorysettingis40OhmPulldown,60OhmPullupdriverstrengthwithnominal
process,voltageandtemperatureconditions.
ThenominaloptionenablesthefactorysettingforthePulldown,Pullupdriverstrengthandtermination.
With this option enabled, driver strength and termination are expected to change with process, voltage
andtemperature.ACtimingsareonlyguaranteedwithAutoCalibration.
DataTermination
BitsA2andA3definethedataterminationvaluefortheondietermination(ODT)fortheDQandDBI#
pinsincombinationwiththedriverstrengthsetting.
TheterminationcanbesettoavalueofZQ/2whichisintendedforasingleloadedsystem,orZQwhich
is intended for a weaker termination used in a lower power or frequency applications. The data
terminationmayalsobeturnedoff.
ADR/CMDTermination
Bits A4 and A5 define the address/command termination. The default setting (00) provides that the
address/commandterminationisdeterminedbylatchingCKE#ontherisingedgeofRESET#.
The address/command termination can also be set to a value of ZQ/2 which is intended for a single
loaded system, or ZQ which is intended for double loaded configurations with two devices sharing a
commonaddress/commandbus.Theaddress/commandterminationmayalsobeturnedoff.
Rev. 1.0 / Nov. 2009 47
H5GQ1H24AFR
CalibrationUpdate
The Calibration Update setting enables the calibration value to be updated automatically by the auto
calibrationengine.Thefunctionisenableduponpoweruptoreduceupdateinducedjitter.Theusermay
decidetosuppressupdatesfromtheautocalibrationenginebydisablingCalibrationUpdate(A6=1).
ThecalibrationupdatescanoccurwithanyREFRESHcommand.Theupdateisnotcompleteforatime
t
KO
after the latching of the REFRESH command. During this t
KO
time, only NOP or DESELECT
commandsmaybeissued
PLLandPLLReset
IfaPLListobeused,itmustbeenabledfornormaloperationbysettingbitA7to1.
APLLresetisdonebyturningthePLLoffthenon,orbyuseofthePLLResetbitA11.ThePLLResetbit
isselfclearingmeaningthatitreturnsbacktothevalue0afterthePLLresetfunctionhasbeenissued.
RDBIandWDBI
BitA8controlsDataBusInversion(DBI)forREADs(RDBI),andbitA9controlsDataBusInversionfor
WRITEs(WDBI).FormoredetailsonDBIseeREADandWRITEDataBusInversion(DBI)inthesection
entitledOPERATION.
ABI
AddressBusInversion(ABI)isselectedindependentlyfromDBIusingbitA10.Whenenabledanydata
sentovertheaddressbus(whetheropcode,addresses,LDFFdataorDM)isinvertedornotinvertedbased
onthestateofABI#signal.FormoredetailsonABIseeAddressBusInversion(ABI)inthesectionentitled
OPERATION.
Rev. 1.0 / Nov. 2009 48
H5GQ1H24AFR
ModeRegister2definestheoutputdriver(OCD)andterminationoffsetsasshowninFigure25.
Mode Register 2 is programmed via the MODE REGISTER SET (MRS) command with BA0=0, BA1=1,
BA2=0andBA3=0.
ImpedanceOffsets
ThedriverandterminationimpedancesmaybeoffsetindividuallyforPDdriver,PUdriver,DQ/DBI#/
WCK termination and address/command termination. The offset impedance step values may be non
linearandwillvaryacrossPVT.WithnegativeoffsetstepsthedrivestrengthswillbedecreasedandRon
0 0 1 0 0
ADR/CMD
TerminationOffset
DataandWCK
TerminationOffset
OCDPullup
DriverOffset
OCDPulldown
DriverOffset
A2 A1 A0
OCDPulldown
DriverOffset
0 0 0 0
0 0 1 +1
0 1 0 +2
0 1 1 +3
1 0 0 4
1 0 1 3
1 1 0 2
1 1 1 1
A5 A4 A3
OCDPullup
DriverOffset
0 0 0 0
0 0 1 +1
0 1 0 +2
0 1 1 +3
1 0 0 4
1 0 1 3
1 1 0 2
1 1 1 1
A8 A7 A6
DataandWCK
TerminationOffset
0 0 0 0
0 0 1 +1
0 1 0 +2
0 1 1 +3
1 0 0 4
1 0 1 3
1 1 0 2
1 1 1 1
A11 A10 A9
ADR/CMD
TerminationOffset
0 0 0 0
0 0 1 +1
0 1 0 +2
0 1 1 +3
1 0 0 4
1 0 1 3
1 1 0 2
1 1 1 1
Rev. 1.0 / Nov. 2009 49
H5GQ1H24AFR
will be increased. With positive offset steps the drive strengths will be increased and Ron will be
decreased.Withnegative offsetstepsthetermination value will be increased.Withpositive offsetsteps
theterminationvaluewillbedecreased.
IVcurvesandACtimingsareonlyguaranteedwithzerooffset.
Figure 26. Impedance Offsets

Calibration
Engine
120
Ohms
VSSQ
ZQ
Pullup
Impedance
Pulldown
Impedance
Offset
PUDriver
Offset
PDDriver
ADD/CMD
Termination
Impedance
Offset
ADD/CMDTermination
DQ/DBI#/WCK
Termination
Impedance
Offset
DQ/DBI#/WCKTermination
Autocalibrated
Impedance
Note:sumofoffset+auto
calibratedimpedancecannot
exceedmaximum /minimum
availableimpedancesteps
FixedImpedance
nominal(60/40)
Auto/Fixed
Rev. 1.0 / Nov. 2009 50
H5GQ1H24AFR
ModeRegister3controlsfunctionsincludingBankGroups,WCKtermination,selfrefresh,RDQSmode,
DRAMInfoandWCK2CKtrainingasshowninFigure27.
Mode Register 3 is programmed via the MODE REGISTER SET (MRS) command with BA0=1, BA1=1,
BA2=0andBA3=0.
SelfRefresh
Therefreshintervalinselfrefreshmodemaybesetto32ms,16msand8ms.
WCK2CK
Bit A4 (WCK2CK) enables and disables the WCK2CK alignment training. For details on this training
sequence,seethesectiononTRAINING.
A1 A0 SelfRefresh
0 0 32ms
0 1 16ms
1 0 8ms
1 1 RFU
0 0 1 1 0
Bank
Groups
WCK
Termination
Info
RDQS
Mode
WCK
2CK
WCK
23Inv
WCK
01Inv
SelfRefresh
A9 A8 WCKTermination
0 0 Disabled
0 1 ZQ/2
1 0 ZQ
1 1 RFU
A4 WCK2CKTraining
0 Off
1 On
A3 WCK23Invert
0 Off
1 On
A2 WCK01Invert
0 Off
1 On
A7 A6 DRAMInfo
0 0 off
0 1 VendorID
1 0 TemperatureReadout
1 1 RFU
A5
RDQS
Mode
0 Off
1 On
A11 A10 BankGroups
0 X off/tCCDL=2t
CK
1 X on/tCCDL=3t
CK
Rev. 1.0 / Nov. 2009 51
H5GQ1H24AFR
WCK01/WCK23Inversion
BitsA2andA3controlwhethertheinternalphaseoftheWCK01andWCK23clockinputsafterinternal
divideby2shallbeinverted,correspondingtoa2U.I.phaseshift.Thebitsareusedinconjunctionwith
WCK2CKtrainingmode.
RDQSMode
BitA5 enablestheRDQSmode oftheGDDR5SGRAM.In this modethe EDC pins willactasa READ
strobe (RDQS). No CRC is supported in RDQS mode, and all related bits in MR4 will be ignored. A
detaileddescriptionoftheRDQSmodecanbefoundinthesectionentitledOPERATION.
DRAMInfo
BitsA6andA7enabletheDRAMInfomodewhichisprovidedtooutputtheVendorID,orthecurrent
junctiontemperature.
The Vendor ID identifies the manufacturer of the GDDR5 SGRAM, and provides the die revision,
memorydensityandFIFOdepth.
TheTemperatureReadoutprovidestheSGRAMsjunctiontemperature.Theonchiptemperaturesensor
isenabledinadvancebybitA6inMR7.
WCKTermination
BitsA8andA9definetheterminationvaluefortheondietermination(ODT)fortheWCK01,WCK01#,
WCK23andWCK23#pinsincombinationwiththedriverstrengthsetting.
TheterminationcanbesettoavalueofZQ/2whichisintendedforasingleloadedsystem,orZQwhich
is intended for double load configurations with two devices sharing the WCK clocks. The WCK
terminationmayalsobeturnedoff.
BankGroups
Bit A11 enables the bank groups feature. With A11 set to 1, the bank groups feature is enabled and
t
CCDL
is3tCK.
Rev. 1.0 / Nov. 2009 52
H5GQ1H24AFR
Mode Register 4 defines the Error Detection Code (EDC) features of GDDR5 SGRAMs as shown in
Figure28.
andBA3=0.BitsA0A3(EDCHoldPattern)ofthisregisterareinitializedwith1111.
EDCHoldpattern/EDC13Invert
The4bitEDCholdpatternisconsideredabackgroundpatterntransmittedontheEDCpins.Theregister
isinitializedwithall1s.Thepatternisshiftedfromrighttoleftandrepeatedwitheveryclockcycle.The
outputtimingisthesameasofaREADburst.
CRC bursts calculated from WRITEs or READs will replace the EDC hold pattern for the duration of
thosebursts,providedCRCisenabledforthosebursts.
With each MRS command to MR4 that changes bits A0A3 or A9A11, the EDC hold pattern will be
undefinedfort
MRD
.
A3 A2 A1 A0 EDCHoldPattern
0 0 0 0 Pattern
...
1 1 1 1 Pattern
Burst
Pos3
Burst
Pos2
Burst
Pos1
Burst
Pos0
0 1 0 0 0
EDC
13Inv
WR
CRC
RD
CRC
CRCRead
Latency
(CRCRL)
CRCWriteLatency
(CRCWL)
EDCHoldPattern
A6 A5 A4 CRCWriteLatency(CRCWL)
0 0 0 N/A
0 0 1 8
0 1 0 9
0 1 1 10
1 0 0 11
1 0 1 12
1 1 0 13
1 1 1 14
A8 A7 CRCReadLatency(CRCRL)
0 0 0
0 1 1
1 0 2
1 1 3
A10 WRCRC
0 On
1 Off
A9 RDCRC
0 On
1 Off
A11
EDCHoldPatternInvert
forEDC1+EDC3
0
EDCholdpatternnot
inverted
1 EDCholdpatterninverted
Rev. 1.0 / Nov. 2009 53
H5GQ1H24AFR
TheEDCholdpatternwillnotbetransmittedwhenthedeviceisinaddresstrainingmode,inWCK2CK
trainingmode,inRDQSmode,inselfrefreshmode,inresetstate,inpowerdownstatewiththeLP2bit
set,orinscanmode.
WithregisterbitA11setHigh,EDC1andEDC3willtransmittheinvertedEDCholdpattern,resultingin
apseudodifferentialpattern.Pleasenotethatthisfunctionisnotavailableinx16configuration.BitA11is
ignoredforREAD,WRITEandRDTRCRCburstsandtheclockphaseinformationinWCK2CKtraining
mode.
CRCWriteLatency(CRCWL)
The value of the CRC write latency is loaded into register bits A4A6. If the DRAM vendor does not
supporttheModeRegisterdefinitionofCRCWL,theModeRegistersettingswillbeignored.Inthatcase
the valid fixed latency is given with the DRAM vendors specification. The user must set the CRCWL
ModeRegisterbits.
Speed
CRCWL14 CRCWL13 CRCWL12 CRCWL11 CRCWL10 CRCWL9 CRCWL8
6.0Gbps
5.5Gbps
5.0Gbps
4.5Gbps
4.0Gbps
CRCReadLatency(CRCRL)
ThevalueoftheCRCreadlatencyisloadedintoregisterbitsA7A8.IftheDRAMvendordoesnotsupport
theModeRegisterdefinitionofCRCRL,theModeRegistersettingswillbeignored.Inthatcasethevalid
fixedlatencyisgivenwiththeDRAMvendorsspecification.TheusermustsettheCRCRLModeRegister
bits.
Speed
RDBI
ON/OFF
CRCRL3 CRCRL2 CRCRL1 CRCRL0
6.0Gbps
OFF
ON
5.5Gbps
OFF
ON
5.0Gbps
OFF
ON
4.5Gbps
OFF
ON
4.0Gbps
OFF
ON
Rev. 1.0 / Nov. 2009 54
H5GQ1H24AFR
ReadCRC
BitA9controlstheCRCcalculationforREADbursts.Whenenabled,thecalculatedCRCpatternwillbe
transmitted on the EDC pins with the latency as programmed in the CRCRL field of this register. With
Read CRC being off, no CRC will be calculated for READ bursts, and the EDC hold pattern will be
transmittedinstead.
WriteCRC
BitA10controlstheCRCcalculationforWRITEbursts.Whenenabled,thecalculatedCRCpatternwillbe
transmitted on the EDC pins with the latency as programmed in the CRCWL field of this register. With
WriteCRCbeingoff,noCRCwillbecalculatedforWRITEbursts,andtheEDCholdpatternwillbetrans
mittedinstead.
Rev. 1.0 / Nov. 2009 55
H5GQ1H24AFR
ModeRegister5definesdigitalRAS,PLLbandwidthandlowpowermodesasshowninFigure29.
andBA3=0.
A1 LP2
0 Off
1 On
0 1 0 1 0 RFU PLLBandwidth LP3 LP2 RFU
A5 A4 A3
3dB[MHz]
BW
3dBLL
Peak[MHz]
BW
PKLL
Peak[dB]
PK
LL
0 0 0 13 2 1.2
0 0 1 18 4 1.1
0 1 0 22 5 1.1
0 1 1 28 7 1.2
1 0 0 36 10 1.2
1 0 1 44 13 1.2
1 1 0 54 15 1.7
1 1 1 69 20 1.5
A2 LP3
0 Off
1 On
Note 1) PLL BW characteristics is extracted at 4Gbps
Note 2) PLL BW is linearly proportional to the data rate
Rev. 1.0 / Nov. 2009 56
H5GQ1H24AFR
LowPowerModes(LP2,LP3)
BitsA1A2controlseverallowpowermodesoftheGDDR5SGRAM.Themodesareindependentofeach
other.
WhenbitA1(LP2)isset,theWCKreceiversmaybeturnedoffduringpowerdown.
WhenbitA2(LP3)isset,RDTR,WRTRandLDFFcommandsarenotallowedwhileaREFcommandis
beingexecuted.
PLL Bandwidth
ThePLLbandwidthmayoptionallybeconfiguredtomatchsystemcharacteristics.Eachsettingdefinesa
uniquecombinationof3dBcornerfrequency,peakingfrequencyandpeakingmagnitude.
Rev. 1.0 / Nov. 2009 57
H5GQ1H24AFR
Mode Register 6 controls the WCK2CK alignment point and defines VREFD related features such as
source,level,offsets,VREFDMergeandVREFDAutoCalibrationmode,asshowninFigure30.
andBA3=0.
WCK2CKAlignmentPoint(WCKPIN)
BitA0definesthepositionofthealignmentpointbetweenCKandWCK.Whensetto0,thealignment
pointwillbeatthephasedetectorinsidetheGDDR5SGRAM.Whensetto1,thealignmentpointwillbe
attheCKandWCKpins.
InputReferenceVoltageforDQandDBI#Pins
GDDR5SGRAMsoffermultipleoptionsfortheinputreferencevoltage(Vref)fortheDQandDBI#pins,
asshowninFigure31.
A11 A10 A9 A8
VREFD
Offset
0 0 0 0
0/
default
0 0 0 1 +1
0 0 1 0 +2
0 0 1 1 +3
0 1 0 0 +4
0 1 0 1 +5
0 1 1 0 +6
0 1 1 1 +7
1 0 0 0
0/Auto
(opt.)
1 0 0 1 7
1 0 1 0 6
1 0 1 1 5
1 1 0 0 4
1 1 0 1 3
1 1 1 0 2
1 1 1 1 1
0 1 1 0 0
VREFDOffset
BytesinrowsAF
VREFDOffset
BytesinrowsMU
VREFD
Auto
VREFD
VREFD
Merge
WCK
PIN
A3 VREFD
0 externalVREFDpins
1 internallygenerated
A1 VREFDMerge
0 Off
1 On
A7 A6 A5 A4
VREFD
Offset
0 0 0 0
0/
default
0 0 0 1 +1
0 0 1 0 +2
0 0 1 1 +3
0 1 0 0 +4
0 1 0 1 +5
0 1 1 0 +6
0 1 1 1 +7
1 0 0 0
0/Auto
(opt.)
1 0 0 1 7
1 0 1 0 6
1 0 1 1 5
1 1 0 0 4
1 1 0 1 3
1 1 1 0 2
1 1 1 1 1
A0
WCK2CK
AlignmentPt.
0
PDinside
DRAM
1 PDatpins
Rev. 1.0 / Nov. 2009 58
H5GQ1H24AFR
Separate Vref circuits are associated with the bytes in rows A to F and the bytes in rows M to U, with
separateVREFDpinsfortherequiredexternalVref.
The only mandatory mode is that Vref will be supplied externally at the VREFD pins. This mode is
configuredwithbitsA1A3andbitA7inMR7allsetto0.
Figure 31. VREFD Options
VREFDMerge
The VREFD Merge mode is enabled when bit A1 is set to1. The externally supplied VFRED and the
internally generated Vref will be merged, resulting in the average value of both. DRAM vendor
specificationsshouldbecheckedforvaluesofexternalresistorsthatmaybeconnectedtoVREFDpinsin
thisVREFMergemode.
AutoVREFDTraining
When Auto is set for VREFD offsets, the internal Vref generator must be trained. Bit A2 enables this
training; the bit is selfclearing, meaning that it returns back to the value 0 after the training has
completed.
Once the training mode is enabled, the GDDR5 SGRAM drives the EDC pins Low to indicate to the
controllerthatthetraininghasstarted.ThecontrollerisnowexpectedtosendthespecifiedPRBSpattern
totheGDDR5SGRAM.Uponcompletionofthetraining,theGDDR5SGRAMstopsdrivingtheEDCpins
Low,andtheEDCpinswillresumetransmittingtheEDCholdpattern.
But,itisnotsupported.
VREFD
Bit A3 selects between external and internal Vref. The bit is Dont Care when VREF Merge mode is
selected.
VREFDOffsetsandVREFDAutoMode
ItsupportsthecapabilitytooffsetVrefindependentlyfortheupper2bytesandthelower2bytes.The
offsetstepvaluesmaybenonlinearandwillvaryacrossPVT.
VREFD
0.5*VDDQ(opt.)
0.7*VDDQ(opt.)
VREFD
Merge
(opt.)
+
+
Receiver
DQ/DBI#
+
VREFDOffsets
Rev. 1.0 / Nov. 2009 59
H5GQ1H24AFR
ThevendorsmayoptionallysupporttheoffsetcapabilitytobeappliedtotheexternalVref(notshownin
Figure31).
TheoptionalAutosettingforVREFDenablestheGDDR5SGRAMtosearchforitsownoptimalinternal
Vref.Thereisnooffsetfromthisinternallydeterminedvalue(seealsoAutoVREFDTraining).
Rev. 1.0 / Nov. 2009 60
H5GQ1H24AFR
Mode Register 7 controls features like PLL Standby, PLL FastLock, PLL Delay Compensation, Low
Frequency mode, Auto Synchronization, Data Preamble, Temperature Sensor operation, Half VREFD,
VDDRangeandDCCasshowninFigure32.
andBA3=0.
LowFrequencyMode
When Low Frequency Mode is enabled by bit A3, the power consumption of input receivers and clock
treesisreduced.Themaximumoperatingfrequencyforthislowfrequencymodeisgiveninthevendors
datasheet.
WCK2CKAutoSynchronization
GDDR5 SGRAMs support a WCK2CK automatic synchronization mode that eliminates the need for
WCK2CKtraininguponpowerdownexitorforreducingWCK2CKtrainingtimeatlowfrequency.This
modeiscontrolledbybitA4.ForadetaileddescriptionseeWCK2CKAutoSynchronizationinthesection
entitledWCK2CKTraining.
A11 A10 DCC
0 0
noDCC/
DCCofforhold/opt.
0 1 DCCstart
1 0 DCCresetl
1 1 RFU
A3 LowFrequencyMode
0 Off
1 On
A4 WCK2CKAutoSync
0 Off
1 On
A5 DataPreamble
0 Off
1 On
A6 TemperatureSensor
0 Off
1 On
A7 HalfVFRED
0 0.7*VDDQ
1 0.5*VDDQ
0 1 1 1 0 DCC RFU
Half
VREFD
Temp
Sense
DQ
PreA
Auto
Sync
LF
Mode
RFU
Rev. 1.0 / Nov. 2009 61
H5GQ1H24AFR
DataPreamble
WhenenabledbybitA5,nongaplessREADburstswillbeprecededbyafixeddatapreambleontheDQ
and DBI# pins of 4 U.I. duration. The programmed READ latency does not change when the Data
Preambleisenabled.ThepatternisnotencodedwithRDBI,however,ifRDBIisdisabled,theDBI#pins
willnottoggleanddriveaHIGH.
TemperatureSensor
TheonchiptemperaturesensorisenabledbybitA6.
AdetaileddescriptionoftheTemperatureSensorcanbefoundintheVENDORID,TEMPSENSORand
SCANsection.
HalfVREFD
This mode allows users to adjust the Vref level in case the GDDR5 SGRAM is operated without
termination:whenbitA7issetto1,aVreflevelofnominally0.5*VDDQisexpectedattheVREFDpinor
beinggeneratedinternally(seeFigure31).
DutyCycleCorrection(DCC)
BitsA10andA11controltheoperationofthedutycyclecorrector(DCC).TheDCCcanbeusedtocancel
outastaticdutycycleerrorontheWCKclocks.FormoredetailsseeDutyCycleCorrection(DCC)inthe
sectionentitledOPERATION.
VREFDSelectionOptionsSummary
ThefollowingtablesummarizesthecompletesetofVREFDselectionoptions.
Table 15VREFDSelectionOptions
MR6 MR7
Description
A3
InternalVREFD
A7
HalfVREFD
0 0 External
0 1 External
1 0 Internal0.7*VDDQ
1 1 Internal0.5*VDDQ
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Mode Register 15 controls address training mode (ADT) and access to Mode Registers 0 to 14 (MRE) as
showninFigure33.
andBA3=1.
Mode Register 15 is a special register that operates in SDR addressing mode. Increased setup and hold
timesasforcommandinputsareassumedtoensuretheMRScommandtothisregisterissuccessfulwhile
address training (ADT) has not taken place and the integrity of DDR addresses may not be guaranteed.
ThisisindicatedbysettingbitsA0A7toDontCare(X)whicharepairedwiththeusablebits(A8A11)
andtheModeRegisteraddress(BA0BA3).
AddressTraining(ADT)
AddresstrainingmodeisenabledanddisabledwithbitA10.
ModeRegister014Enable
WhendisabledbybitA8(forSGRAMsconfiguredtoMF=0)orbitA9(forSGRAMsconfiguredtoMF=1),
the GDDR5 SGRAM will ignore any MODE REGISTER SET command to Mode Registers 0 to 14. If
enabled, MODE REGISTER SET commands function as normal. MODE REGISTER SET commands to
ModeRegister15(thisregister)arenotaffectedandwillalwaysbeexecuted.
This functional allows for individual configuration of two GDDR5 SGRAMS on a common address bus
withouttheuseofaCS#pin.
A9 MR014EnableMF=1
0 Enabled
1 Disabled
1 1 1 1 0 RFU ADT
MRE
MF1
MRE
MF0
X X X X X X X X
A10 AddressTraining(ADT)
0 Off
1 On
A8 MR014EnableMF=0
0 Enabled
1 Disabled
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5.OPERATION
5.1.COMMANDS
Notes:
1)H=LogicHighLevel;L=LogicLowLevel;X=Dontcare:signalmaybeHorL,butnotfloating
2)Addressesshownarelogicaladdresses;physicaladdressesareinvertedwhenaddressbusinversion(ABI)isactivatedandABI#=L
3)BA0BA3providetheModeRegisteraddress(MRA),A0A11theopcodetobeloaded
4)BA0BA3providethebankaddress(BA),A0A11(A12)providetherowaddress(RA).
5)BA0BA3providethebankaddress,A0A5(A6)providethecolumnaddress(CA);nosubwordaddressingwithinaburstof8.
6)ThecommandisRefreshwhenCKE#(n)=LandSelfRefreshEntrywhenCKE#(n)=H.
7)BA0BA3andCAareusedtoselectburstlocationanddatarespectively
8)DESELECTandNOParefunctionallyinterchangeable
9)InaddresstrainingmodeREADisdecodedfromthecommandspinsonlywithRAS#=H,CAS#=L,WE#=H
Table 16TruthTableCommands
Operation
Symbol
CKE#
CS# RAS# CAS# WE# BA A11 A10 A8
A6,
A7,
A9,
(A12)
A0
A5
(A6) Notes
Previous
cycle
Current
cycle
DESELECT(NOP) DES L X H X X X X X X X X X 1,2,8
NOOPERATION(NOP) NOP L X L H H H X X X X X X 1,2,8
MODEREGISTERSET MRS L L L L L L MRA Opcode 1,2,3
ACTIVE(Selectbank&
activaterow)
ACT L L L L H H BA RA 1,2,4
READ(Selectbankand
column,&startburst)
RD L L L H L H BA L L L X CA 1,2,5,
9
READwithAutoprecharge RDA L L L H L H BA L L H X CA 1,2,5
LoadFIFO LDFF L L L H L H X H L L X X 1,2,7
READTraining RDTR L L L H L H X H H L X X 1,2
WRITEwithoutMask
(Selectbankandcolumn,&
startburst)
WOM L L L H L L BA L L L X CA 1,2,5
WRITEwithoutMaskwith
Autoprecharge
WOMA L L L H L L BA L L H X CA 1,2,5
WRITEwithsinglebyte
mask
WSM L L L H L L BA L H L X CA 1,2,5
WRITEwithsinglebyte
maskwithAutoprecharge
WSMA L L L H L L BA L H H X CA 1,2,5
WRITEwithdoublebyte
mask(WDM)
WDM L L L H L L BA H L L X CA 1,2,5
WRITEwithdoublebyte
maskwithAutoprecharge
WDMA L L L H L L BA H L H X CA 1,2,5
WRITETraining WRTR L L L H L L X H H L X X 1,2
PRECHARGE(Deactivate
rowinbankorbanks)
PRE L L L L H L BA X X L X X 1,2
PRECHARGEALL PREALL L L L L H L X X X H X X 1,2
REFRESH REF L L L L L H X X X X X X 1,6
POWERDOWNENTRY PDE L H
H X X X X X X X X X 1
L H H H X X X X X X 1
POWERDOWNEXIT PDX H L
L H H H
SELFREFRESHENTRY SRE L H L L L H X X X X X X 1,6
SELFREFRESHEXIT SRX H L
L H H H
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Figure34andFigure35illustratethetimingsassociatedwiththeCommandandAddressinputaswellas
Datainput.
Figure 34. Command and Address Input Timings
Figure 35. Data Input Timings
CK#
CK
t
CH
t
CL
t
CK
COMMAND
t
CMDS t
CMDPW
ADDRESS
t
AH
t
CMDH
t
APW
t
APW
t
AS
t
AH
t
AS
DontCare
t
DIPW
t
DIPW
t
DIVW
t
DIVW
t
WCK2DQI
t
WCK2DQI
DQ/DBI#
WCK#
WCK
(1Pin)
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5.2.DESELECT(NOP)
TheDESELECTfunction(CS#HIGH)preventsnewcommandsfrombeingexecutedbytheGDDR5
SGRAM.TheGDDR5SGRAMiseffectivelydeselected.Operationsalreadyinprogressarenotaffected.
5.3.NOOPERATION(NOP)
TheNOOPERATION(NOP)commandisusedtoinstructtheselectedGDDR5SGRAMtoperformaNOP
(CS#LOW).Thispreventsunwantedcommandsfrombeingregisteredduringidleorwaitstates.Opera
tionsalreadyinprogressarenotaffected.
5.4.MODEREGISTERSET
TheMODEREGISTERSETcommandisusedtoloadtheModeRegistersoftheGDDR5SGRAM.Thebank
addressinputsBA0BA3selecttheModeRegister,andaddressputsA0A11(A12)determinetheopcode
tobeloaded.SeeMODEREGISTERforaregisterdefinition.TheMODEREGISTERSETcommandcan
onlybeissuedwhenallbanksareidleandnoburstsareinprogress,andasubsequentexecutablecom
mandcannotbeissueduntilt
MRD
ismet.
Figure 36. MRS Command
LOW
RA=RowAddress
CO=Opcode
BA=BankAddress
ENAP=EnableAutoPrecharge
DISAP=DisableAut oPrecharge
ModeRegisterSet
CO CO
CS#
WE#
CAS#
RAS#
CKE#
CK
CK#
DONTCARE
BA CO
BA0BA3
A2A5
BA0,1,2,3 A2,3,4,5
A8,9,10,11, (12) A0,1,6,7
A8A11(A12)
A0,A1,A6,A7
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Figure 37. Mode Register Set Timings
5.5.ACTIVATION
BeforeanyREADorWRITEcommandscanbeissuedtoabankintheGDDR5SGRAM,arowinthatbank
mustbeopened.ThisisaccomplishedbytheACTIVEcommand(seeFigure38):BA0BA3selectthe
bank,andA0A11(A12)selecttherowtobeactivated.Oncearowisopen,aREADorWRITEcommand
couldbeissuedtothatrow,subjecttothet
RCD
specification.
AsubsequentACTIVEcommandtoanotherrowinthesamebankcanonlybeissuedaftertheprevious
rowhasbeenclosed(precharged).TheminimumtimeintervalbetweentwosuccessiveACTIVEcom
mandsonthesamebankisdefinedbyt
RC
.Aminimumtime,t
RAS
,musthaveelapsedbetweenopening
andclosingarow.
AsubsequentACTIVEcommandtoanotherbankcanbeissuedwhilethefirstbankisbeingaccessed,
whichresultsinareductionoftotalrowaccessoverhead.Theminimumtimeintervalbetweentwosuc
cessiveACTIVEcommandsondifferentbankstodifferentbankgroupsisdefinedbyt
RRDS
.Withbank
groupsenabled,theminimumtimeintervalbetweentwosuccessiveACTIVEcommandstodifferent
banksinthesamebankgroupisdefinedbyt
RRDL
.Inallothercasestheintervalisdefinedbyt
RRDS
.
<Link>Figureshowsthet
RCD
andt
RRD
definition.
CK#
CK
CMD
A.C.=anycommandallowedinbankidlestate
t
RP
t
MRD
UpdatingSetting NewSetting OldSetting
NOP
PRE
ALL
NOP MRS NOP A.C. NOP
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TherowremainsactiveuntilaPRECHARGEcommand(orREADorWRITEcommandwithAutoPre
charge)isissuedtothebank.
Figure 38. Active Command
Figure 39. Bank Activation Command Cycle
A8A11(A12)
A0,A1,A6,A7
LOW
RA=RowAddress
CA=ColumnAddress
BA=BankAddress
RowActivation
RA RA
CS#
WE#
CAS#
RAS#
CKE#
DONTCARE
BA RA
BA0BA3
A2A5
BA0,1,2,3 A2,3,4,5
A8,9,10,11, (12) A0,1,6,7
CK
CK#
CK#
CK
CMD
ADDR
BA
RA
RA BA CA BA
BA
RA
RA
t
RCD
t
RP
t
RAS
t
RC
BA=bankaddress;RA=rowaddress;CA=columnaddress
t
RCD
=t
RCDRD
,t
RCDWR
,t
RCDRTR
,t
RCDWTR
ort
RCDLTR
,dependingoncommand
(*)=couldalsobePREALL
NOP ACT NOP RD/WR NOP PRE* NOP ACT NOP
DontCare
T0 T1 T2 Ta0 Ta1 Tb0 Tb1 Tc1 Tc0
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5.6.BANKRESTRICTIONS
Theremaybeaneedtolimitthenumberofactivatesinarollingwindowtoensurethattheinstantaneous
currentsupplyingcapabilityofthedevicesisnotexceeded.Toreflecttheshorttermcapabilityofthe
GDDR5SGRAMcurrentsupply,theparametert
FAW
(fouractivatewindow)isdefined.Nomorethan4
banksmaybeactivatedinarollingt
FAW
window.Convertingtoclocksisdonebydividingt
FAW
(ns)by
t
CK
(ns)androundinguptonextintegervalue.Asanexampleoftherollingwindow,if(t
FAW
/t
CK
)rounds
upto10clocks,andanactivatecommandisissuedatclockN,nomorethanthreefurtheractivatecom
mandsmaybeissuedatclocksN+1throughN+9asillustratedinFigure40.
ToreflectalongertermGDDR5SGRAMcurrentsupplycapability,theparametert
32AW
(thirtytwoacti
vatewindow)isdefined.Nomorethan32banksmaybeactivatedinarollingt
32AW
window.Converting
toclocksisdonebydividingt
32AW
(ns)byt
CK
(ns)androundinguptonextintegervalue.Theuseofa
shorterandlongerrollingactivationwindowallowstheGDDR5SGRAMdesigntobeoptimizedtohandle
higherinstantaneouscurrentswithinashorterwindowwhilestilllimitingthecurrentstrainoveralonger
periodoftime.Thismeansthatingeneralt
32AW
willbegreaterthanorequalto8*t
FAW
asshownin
Figure41.
ItispreferablethatGDDR5SGRAMshavenorollingactivationwindowrestrictions(t
FAW
=4*t
RRD
).
Figure 40. t
RRD
and t
FAW
ACT
t
RRD
t
RRD
t
RRD
t
RRD
t
RRD
t
RRD
t
FAW
t
FAW
+ 3
*
t
ACT ACT ACT ACT ACT ACT ACT
RRD
CK
CK#
CMD
t
RRD
=t
RRDL
ort
RRDS
dependingonBankGroupson/offsettingandaccessedbanks
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Figure 41. t
32AW
t
FAW
A.)t
32AW
>8*t
FAW
B.)t
32AW
=8*t
FAW
t
FAW
t
FAW
t
FAW
t
FAW
t
FAW
t
FAW
t
FAW
t
FAW
t
FAW
t
FAW
t
FAW
t
FAW
t
FAW
t
FAW
t
FAW
t
FAW
t
FAW
t
32AW
t
32AW
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5.7.WRITE(WOM)
WRITEburstsareinitiatedwithaWRITEcommandasshowninFigure42.Thebankandcolumn
addressesareprovidedwiththeWRITEcommandandautoprechargeiseitherenabledordisabledfor
thataccesswiththeA8pin.Ifautoprechargeisenabled,therowbeingaccessedisprechargedatthecom
pletionoftheburstaftert
RAS
(min)hasbeenmet.ThelengthoftheburstinitiatedwithaWRITEcommand
iseightandthecolumnaddressisuniqueforthisburstofeight.Thereisnointerruptionnortruncationof
WRITEbursts.
Figure 42. WRITE Command
DuringWRITEbursts,thefirstvaliddatainelementmustbeavailableattheinputlatchaftertheWrite
Latency(WL).TheWriteLatencyisdefinedasWLmrs*t
CK
+t
WCK2CKPIN
+t
WCK2CK
+t
WCK2DQI
,where
WLmrsisthenumberofclockcyclesprogramedinMR0,t
WCK2CKPIN
isthephaseoffsetbetweenWCK
andCKatthepinswhenphasealignedatphasedetector,t
WCK2CK
isthealignmenterrorbetweenWCK
andCKattheGDDR5SGRAMphasedetector,andt
WCK2DQI
istheWCKtoDQ/DBI#offsetasmeasured
attheDRAMpinstoensureconcurrentarrivalatthelatch.Thetotaldelayisrelativetothedataeyecenter
averagedoveronedoublebyte.Themaximumskewwithinadoublebyteisdefinedbyt
DQDQI
.
Thedatainputvalidwindow,t
DIVW
,definesthetimeregionwheninputdatamustbevalidforreliable
datacaptureatthereceiverforanyoneworstcasechannel.Itaccountsforjitterbetweendataandclockat
thelatchingpointintroducedinthepathbetweentheDRAMpadsandthelatchingpoint.Anyadditional
jitterintroducedintothesourcesignals(i.e.withinthesystembeforetheDRAMpad)mustbeaccounted
forinthefinaltimingbudgettogetherwiththechosenPLLmodeandbandwidth.t
DIVW
ismeasuredat
thepins.t
DIVW
isdefinedforthePLLoffandonmodeseparately.InthecaseofPLLon,t
DIVW
mustbe
specifiedforeachsupportedbandwidth.Ingeneralt
DIVW
issmallerthant
DIPW
.
A10,A11
0,0
CS#
WE#
CAS#
RAS#
CKE#
A9(A12)
A1
A8
LOW
WRITE
CK
CK#
CA
A0,A6
BA0BA3
A2A5
CA BA
A7
ENAP
DISAP
BA=BankAddress;CA=ColumnAddress
ENAP=EnableAutoPrecharge;DISAP=DisableAutoPrecharge
0,0 CA
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Thedatainputpulsewidth,t
DIPW
,definestheminimumpositiveornegativeinputpulsewidthforany
oneworstcasechannelrequiredforproperpropagationofanexternalsignaltothereceiver.t
DIPW
ismea
suredatthepins.t
DIPW
isindependentofthePLLmode.Ingeneralt
DIPW
islargerthant
DIVW
.
Uponcompletionofaburst,assumingnootherWRITEdataisexpectedonthebustheGDDR5SGRAM
DQandDBI#pinswillbedrivenaccordingtotheODTstate.Anyadditionalinputdatawillbeignored.
DataforanyWRITEburstmaynotbetruncatedwithasubsequentWRITEcommand.
DatafromanyWRITEburstmaybeconcatenatedwithdatafromasubsequentWRITEcommand.Acon
tinuousflowofdatacanbemaintained.Thefirstdataelementfromthenewburstfollowsthelastelement
ofacompletedburst.ThenewWRITEcommandshouldbeissuedafterthepreviousWRITEcommand
accordingtothet
CCD
timing.IfthatWRITEcommandistoanotherbankthenanACTIVEcommandmust
precedetheWRITEcommandandt
RCDWR
alsomustbemet.
AREADcanbeissuedanytimeafteraWRITEcommandaslongastheinternalturnaroundtimet
WTR
is
met.IfthatREADcommandistoanotherbank,thenanACTIVEcommandmustprecedetheREADcom
mandandt
RCDRD
alsomustbemet.
APRECHARGEcanalsobeissuedtotheGDDR5SGRAMwiththesametimingrestrictionasthenew
WRITEcommandift
RAS
ismet.AfterthePRECHARGEcommand,asubsequentcommandtothesame
bankcannotbeissueduntilt
RP
ismet.
ThedatainversionflagisreceivedontheDBI#pintoidentifywhethertostorethetrueorinverteddata.If
DBI#isLOW,thedatawillbestoredafterinversioninsidetheGDDR5SGRAMandnotinvertedifDBI#is
HIGH.WRITEDataInversioncanbeenabled(A9=0)ordisabled(A9=1)usingWDBIinMR1.
WhenenabledbytheWRCRCflaginMR4,EDCdataarereturnedtothecontrollerwithalatencyof
(WLmrs+CRCWL)*t
CK
+t
WCK2CKPIN
+t
WCK2CK
+t
WCK2DQO
,whereCRCWListheCRCWritelatency
programmedinMR4andt
WCK2DQO
istheWCKtoDQ/DBI#/EDCphaseoffsetattheDRAMpins.
Rev. 1.0 / Nov. 2009 72
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Figure 43. WRITE Timings
CK
CK#
t
CH
t
CL
t
CK WLmrs
DQ/DBI#
(mean)
WCK#
WCK
t
WCK2CKPIN
+t
WCK2CK
t
WCK2DQI
DQ/DBI#
(firstbit)
DQ/DBI#
(lastbit)
t
DQDQI
(min)
t
DQDQI
(max)
1) WLmrsistheWRITElatencyprogrammedinModeRegisterMR0.
2) Timingsareshownwithpositivet
WCK2CKPIN
andt
WCK2CK
values.SeeWCK2CKtimingsfor
t
WCK2CKPIN
andt
WCK2CK
ranges.
3) t
WCK2DQI
parametervaluescouldbenegativeorpositivenumbers,dependingonPLLonorPLLoffmode
operationanddesignimplementation.TheyalsovaryacrossPVT.Datatrainingisrequiredtodetermine
theactualt
WCK2DQI
valueforstableWRITEoperation.
4) t
DQDQI
definestheminimumtomaximumvariationoft
WCK2DQI
withinadoublebyte(x32mode)or
asinglebyte(x16mode).
5) DataReadtimingsareusedforCRCreturntimingfromWRITEcommandswithCRCenabled.
D1 D2 D3 D4 D5 D6 D7 D0
D1 D2 D3 D4 D5 D6 D7 D0
D1 D2 D3 D4 D5 D6 D7 D0
Case1:Negativet
WCK2DQI
DQ/DBI#
(mean)
t
WCK2DQI
DQ/DBI#
(firstbit)
DQ/DBI#
(lastbit)
t
DQDQI
(min)
t
DQDQI
(max)
D1 D2 D3 D4 D5 D6 D7 D0
D1 D2 D3 D4 D5 D6 D7 D0
D1 D2 D3 D4 D5 D6 D7 D0
Case2:Positivet
WCK2DQI
DontCare
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Figure 44. Single WRITE without EDC
CK
CK#
ADDRESS
DQ
DBI#
WCK#
WCK
DO DO
DBI DBI
n+7
n+7
n
n
Banka,
Coln
Coln
WL=WLmrs=3
T1 T2 T0 T3 T4 T5 T6 T7 T8 T3n T4n
EDCHoldPattern EDC
3.ForWRITEoperationsitisimportantthatthelatchingpointmeetthedatavalidwindowrequirements,whichmayormaynotbecenteralignedatthepins.
4.BeforetheWRITEcommands,anACTIVE(ACT)commandisrequiredtobeissuedtotheGDDR5SGRAMandt
RCDWR
mustbemet.
1.WLmrs=3isshownasanexample.ActualsupportedvalueswillbefoundintheMRandACtimingssections.
WCK2CKPIN
=0,t
WCK2CK
Notes:
5.t
WCK2DQI
=0isshownforillustrationpurposes.
DONTCARE TRANSITIONINGDATA
NOP WRITE COMMAND NOP NOP NOP NOP NOP NOP NOP
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Figure 45. Single WRITE with EDC
WCK2CKPIN
=0,t
WCK2CK
RCDWR
mustbemet.
WL=WLmrs=3
T1 T2 T0 T3 T4 T5 T11 T12 T13 T3n T4n
Banka,
Coln
Coln
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
CRCWL=8
EDCHoldPattern
EDCHold
Pattern
(
)
(
)
(
)
(
)
DO DO
DBI DBI
n+7
n+7
n
n
CK
CK#
DQ
DBI#
WCK#
WCK
EDC
(
)
(
)
(
)
(
)
EDC EDC
n+7 n
1.WLmrs=3andCRCWL=8isshownasanexample.ActualsupportedvalueswillbefoundintheMRandACtimingssections.
5.t
WCK2DQI
,t
WCKDQO
Notes:
NOP WRITE NOP NOP NOP NOP NOP NOP NOP
ADDRESS
COMMAND
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
Rev. 1.0 / Nov. 2009 75
H5GQ1H24AFR
Figure 46. Non-Gapless WRITEs
WCK2CKPIN
=0,t
WCK2CK
RCDWR
mustbemet.
DBI DBI
n+7 n
DO DO
n+7 n
DO DO
m+7 m
DBI DBI
m+7 m
Banka,
Colm
Colm
WL=WLmrs=5
T7 T11 T12 T0 T1 T2 T5 T5n T6 T6n T11n T10 T10n
Bankb,
Coln
Coln
WL=WLmrs=5
t
RCDWR
Bankb,
Row
Row
1.WLmrs=5andt
RCDWR
=3isshownasanexample.ActualsupportedvalueswillbefoundintheMRandACtimingssections.
3.EDCmaybeonoroff.SeeFigure4forEDCTiming.
Notes:
6.t
WCK2DQI
NOP WRITE ACT WRITE NOP NOP NOP NOP NOP
CK
CK#
COMMAND
ADDRESS
DQ
DBI#
WCK#
WCK
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
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H5GQ1H24AFR
Figure 47. Gapless WRITEs
NOP WRITE WRITE NOP NOP NOP NOP NOP NOP
WCK2CKPIN
=0,t
WCK2CK
WL=WLmrs=2
Banka,
Colm
Colm
CK
CK#
COMMAND
DQ
DBI#
WCK#
WCK
RCDWR
mustbemet.
Banka,
Coln
Coln
DO DO
DBI DBI
m+7
m+7
m
m
t
CCD
DO DO
n+7 n
DBI DBI
n+7 n
WL=WLmrs=2
4.t
CCD
=t
CCDS
whenbankgroupsisdisabledorthesecondWRITEistoadifferentbankgroup,otherwiset
CCD
=t
CCDL
.
Notes:
7.t
WCK2DQI
ADDRESS
Rev. 1.0 / Nov. 2009 77
H5GQ1H24AFR
Figure 48. WRITE to READ
WCK2CKPIN
=0,t
WCK2CK
DO DO
m+7 m
CL=CLmrs=6
WL=WLmrs=3
DBI DBI
n+7 n
Banka,
Colm
Colm
Ta0 Ta7 Ta8 T0 T1 T3 T4 T4n T5 Ta6 Ta6n
DO DO
n+7 n
Bankb,
Coln
Coln
t
WTR
respectivelymustbemet.
DBI DBI
m+7 m
T3n
1.WLmrs=3andCLmrs=6isshownasanexample.ActualsupportedvalueswillbefoundintheMRandACtimingssections.
6.BeforetheREADandWRITEcommands,anACTIVE(ACT)commandisrequiredtobeissuedtotheGDDR5SGRAMandt
RCDRD
ort
RCDWR
4.t
WTR
=t
WTRL
whenbankgroupsisenabledandbothWRITEandREADaccessbanksinthesamebankgroup,otherwiset
WTR
=t
WTRS
.
Notes:
7.t
WCK2DQI
,t
WCKDQO
NOP WRITE NOP NOP NOP READ NOP NOP NOP
CK
CK#
ADDRESS
DQ
DBI#
WCK#
WCK
COMMAND
(
)
(
)
(
)
(
)
(
)
(
)
(
)
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Rev. 1.0 / Nov. 2009 78
H5GQ1H24AFR
Figure 49. WRITE to PRECHARGE
WCK2CKPIN
=0,t
WCK2CK
Banka,
Coln
Coln
CK
CK#
DQ
DBI#
WL=WLmrs=3
WCK#
WCK
T5 Ta0 Ta1 T0 T1 T2 T3 T3n T4 T4n T6
t
WR
Banka,
orall
t
RP
DO DO
DBI DBI
n+7
n+7
n
n
5.BeforetheWRITEcommand,anACTIVE(ACT)commandisrequiredtobeissuedtotheGDDR5SGRAMandt
RCDWR
mustbemet.
Notes:
6.t
WCK2DQI
NOP WRITE NOP NOP NOP NOP NOP PRE NOP
ADDRESS
COMMAND
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Rev. 1.0 / Nov. 2009 79
H5GQ1H24AFR
5.8.WRITEDATAMASK(DM)
ThetraditionalmethodofusingaDMpinforWRITEdatamaskmustbeabandonedforanewmethod.
DuetothehighdatarateofGDDR5SGRAMs,biterrorsareexpectedontheinterfaceandarenotrecover
ablewhentheyoccuronthetraditionalDMpin.
InGDDR5theDMissenttotheSGRAMovertheaddressfollowingthebank/columnaddresscycleassoci
atedwiththecommand,duringtheNOP/DESELECTcommandsbetweentheWRITEcommandandthe
nextcommand.TheDMisusedtomaskthecorrespondingdataaccordingtothefollowingtable.
TwoadditionalWRITEcommandsthataugmentthetraditionalWRITEWithoutMask(WOM)are
requiredforproperDMsupport:
WDM:WRITEWithDoublebyteMask:
2cyclecommandwherethe1stcyclecarriesaddressinformationandthe2ndcyclecarriesdatamask
information(2bytegranularity);
Table17:DMState
FUNCTION
DM
Value
DQ
WriteEnable 0 Valid
WriteInhibit 1 X
Rev. 1.0 / Nov. 2009 80
H5GQ1H24AFR
Figure 50. WRITE-With-Doublebyte-Mask Command
CS#
WE#
CAS#
RAS#
CKE#
A9(A12)
A1
A10,A11
A8
A7
LOW
WDM
CK
CK#
0,1
BA0BA3
A2A5
A0,A6
DM
DM
DM
DM DM
DM
DM
DM
ENAP
DISAP
CA
BA
CA
CA
BA=BankAddress;CA=ColumnAddress;DM=DataMask
Note:NOPshownasanexampleonly
Rev. 1.0 / Nov. 2009 81
H5GQ1H24AFR
Figure 51. WDM Timing
NOP WDM WDM NOP NOP NOP NOP NOP NOP
WCK2CKPIN
=0,t
WCK2CK
WL=WLmrs=2
Banka,
Colm
Colm
CK
CK#
COMMAND
DQ
DBI#
WCK#
WCK
RCDWR
mustbemet.
Banka,
Coln
Coln
DO DO
DBI DBI
m+7
m+7
m
m
t
CCD
DO DO
n+7 n
DBI DBI
n+7 n
WL=WLmrs=2
4.t
CCD
=t
CCDS
whenbankgroupsisdisabledorthesecondWRITEistoadifferentbankgroup,otherwiset
CCD
=t
CCDL
.
Notes:
7.t
WCK2DQI
ADDRESS DMm DMm DMn DMn
Rev. 1.0 / Nov. 2009 82
H5GQ1H24AFR
WSM:WRITEWithSinglebyteMask:
3cyclecommandwherethe1stcyclecarriesaddressinformation,the2ndand3rdcyclecarrydatamask
information
Figure 52. WRITE-With-Singlebyte-Mask Command
CS#
WE#
CAS#
RAS#
CKE#
A9(A12)
A1
A10,A11
A8
A7
LOW
WSM
CK
CK#
0,1
BA0BA3
A2A5
A0,A6
DM
DM
DM
DM DM
DM
DM
DM
ENAP
DISAP
CA
BA
CA
CA
BA=BankAddress;CA=ColumnAddress;DM=DataMask
DM
DM
DM
DM DM
DM
DM
DM
Note:NOPshownasanexampleonly
Rev. 1.0 / Nov. 2009 83
H5GQ1H24AFR
Figure 53. WSM Timing
WCK2CKPIN
=0,t
WCK2CK
RCDWR
mustbemet.
DBI DBI
n+7 n
DO DO
n+7 n
DO DO
m+7 m
DBI DBI
m+7 m
Banka,
Colm
Colm
WL=WLmrs=5
Bankb,
Coln
Coln
WL=WLmrs=5
DMm
1.WLmrs=5andt
RCDWR
=3isshownasanexample.ActualsupportedvalueswillbefoundintheMRandACtimingssections.
Notes:
6.t
WCK2DQI
NOP WSM NOP WSM NOP NOP NOP NOP NOP
CK
CK#
COMMAND
ADDRESS
DQ
DBI#
WCK#
WCK
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DMm DMm DMm DMn DMn DMn DMn
Rev. 1.0 / Nov. 2009 84
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Table 18WDMMappingformirrored&nonmirroredx32Mode
ByteandBurstPositionMaskedduringWDM
ADR ADRCKRisingEdge ADR ADRCK#RisingEdge
Byte Burst Byte Burst
A10 DQ[15:0] 0 A0 DQ[15:0] 4
A9 DQ[15:0] 1 A1 DQ[15:0] 5
BA0 DQ[15:0] 2 A2 DQ[15:0] 6
BA3 DQ[15:0] 3 A3 DQ[15:0] 7
BA2 DQ[31:16] 0 A4 DQ[31:16] 4
BA1 DQ[31:16] 1 A5 DQ[31:16] 5
A11 DQ[31:16] 2 A6 DQ[31:16] 6
A8 DQ[31:16] 3 A7 DQ[31:16] 7
Table 19WDMMappingfornonmirroredx16Mode
ADRCKRisingEdge ADR ADRCK#RisingEdge
ADR Byte Burst Byte Burst
A10 DQ[7:0] 0 A0 DQ[7:0] 4
A9 DQ[7:0] 1 A1 DQ[7:0] 5
BA0 DQ[7:0] 2 A2 DQ[7:0] 6
BA3 DQ[7:0] 3 A3 DQ[7:0] 7
BA2 DQ[23:16] 0 A4 DQ[23:16] 4
BA1 DQ[23:16] 1 A5 DQ[23:16] 5
A11 DQ[23:16] 2 A6 DQ[23:16] 6
A8 DQ[23:16] 3 A7 DQ[23:16] 7
Table 20WDMMappingformirroredx16Mode
ADRCKRisingEdge ADR ADRCK#RisingEdge
ADR Byte Burst Byte Burst
A10 DQ[15:8] 0 A0 DQ[15:8] 4
A9 DQ[15:8] 1 A1 DQ[15:8] 5
BA0 DQ[15:8] 2 A2 DQ[15:8] 6
BA3 DQ[15:8] 3 A3 DQ[15:8] 7
BA2 DQ[31:24] 0 A4 DQ[31:24] 4
BA1 DQ[31:24] 1 A5 DQ[31:24] 5
A11 DQ[31:24] 2 A6 DQ[31:24] 6
A8 DQ[31:24] 3 A7 DQ[31:24] 7
Rev. 1.0 / Nov. 2009 85
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Table 21WSMMappingformirroredandnonmirroredx32Mode
ByteandBurstPositionMaskedDuringWSM
ADRCK1strisingEdge ADRCK#1strisingEdge ADRCK2ndrisingEdge ADRCK#2ndrisingEdge
ADR Byte Burst ADR Byte Burst ADR Byte Burst ADR Byte Burst
A10 DQ[7:0] 0 A0 DQ[7:0] 4 A10 DQ[15:8] 0 A0 DQ[15:8] 4
A9 DQ[7:0] 1 A1 DQ[7:0] 5 A9 DQ[15:8] 1 A1 DQ[15:8] 5
BA0 DQ[7:0] 2 A2 DQ[7:0] 6 BA0 DQ[15:8] 2 A2 DQ[15:8] 6
BA3 DQ[7:0] 3 A3 DQ[7:0] 7 BA3 DQ[15:8] 3 A3 DQ[15:8] 7
BA2 DQ[23:16] 0 A4 DQ[23:16] 4 BA2 DQ[31:24] 0 A4 DQ[31:24] 4
BA1 DQ[23:16] 1 A5 DQ[23:16] 5 BA1 DQ[31:24] 1 A5 DQ[31:24] 5
A11 DQ[23:16] 2 A6 DQ[23:16] 6 A11 DQ[31:24] 2 A6 DQ[31:24] 6
A8 DQ[23:16] 3 A7 DQ[23:16] 7 A8 DQ[31:24] 3 A7 DQ[31:24] 7
Table 22WSMMappingfornonmirroredx16Mode
ADR Byte Burst ADR Byte Burst Byte Burst Byte Burst
A10 DQ[7:0] 0 A0 DQ[7:0] 4 0 4
A9 DQ[7:0] 1 A1 DQ[7:0] 5 1 5
BA0 DQ[7:0] 2 A2 DQ[7:0] 6 2 6
BA3 DQ[7:0] 3 A3 DQ[7:0] 7 3 7
BA2 DQ[23:16] 0 A4 DQ[23:16] 4 0 4
BA1 DQ[23:16] 1 A5 DQ[23:16] 5 1 5
A11 DQ[23:16] 2 A6 DQ[23:16] 6 2 6
A8 DQ[23:16] 3 A7 DQ[23:16] 7 3 7
Table 23WSMMappingformirroredx16Mode
Byte Burst Byte Burst ADR Byte Burst ADR Byte Burst
0 4 A10 DQ[15:8] 0 A0 DQ[15:8] 4
1 5 A9 DQ[15:8] 1 A1 DQ[15:8] 5
2 6 BA0 DQ[15:8] 2 A2 DQ[15:8] 6
3 7 BA3 DQ[15:8] 3 A3 DQ[15:8] 7
0 4 BA2 DQ[31:24] 0 A4 DQ[31:24] 4
1 5 BA1 DQ[31:24] 1 A5 DQ[31:24] 5
2 6 A11 DQ[31:24] 2 A6 DQ[31:24] 6
3 7 A8 DQ[31:24] 3 A7 DQ[31:24] 7
Rev. 1.0 / Nov. 2009 86
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5.9.READ
AREADburstisinitiatedwithaREADcommandasshowninFigure54.Thebankandcolumnaddresses
areprovidedwiththeREADcommandandautoprechargeiseitherenabledordisabledforthataccess
withtheA8address.Ifautoprechargeisenabled,therowbeingaccessedisprechargedatthecompletion
oftheburstaftert
RAS
(min)hasbeenmet.ThelengthoftheburstinitiatedwithaREADcommandiseight
andthecolumnaddressisuniqueforthisburstofeight.ThereisnointerruptionnortruncationofREAD
bursts.
Figure 54. READ Command
DuringREADbursts,thefirstvaliddataoutelementwillbeavailableaftertheCASlatency(CL).TheCAS
LatencyisdefinedasCLmrs*t
CK
+t
WCK2CKPIN
+t
WCK2CK
+t
WCK2DQO
,whereCLmrsisthenumberof
clockcyclesprogramedinMR0,t
WCK2CKPIN
isthephaseoffsetbetweenWCKandCKatthepinswhen
phasealignedatphasedetector,t
WCK2CK
isthealignmenterrorbetweenWCKandCKattheGDDR5
SGRAMphasedetector,andt
WCK2DQO
istheWCKtoDQ/DBI#/EDCoffsetasmeasuredattheDRAM
pins.Thetotaldelayisrelativetothedataeyeinitialedgeaveragedoveronedoublebyte.Themaximum
skewwithinadoublebyteisdefinedbyt
DQDQO
.
Uponcompletionofaburst,assumingnootherREADcommandhasbeeninitiated,allDQandDBI#pins
willdriveavalueof1andtheODTwillbeenabledatamaximumof1t
CK
later.Thedrivevalueandter
minationvaluemaybedifferentduetoseparatelydefinedcalibrationoffsets.IftheODTisdisabled,the
pinswilldriveHiZ.
DatafromanyREADburstmaybeconcatenatedwithdatafromasubsequentREADcommand.Acontin
acompletedburst.ThenewREADcommandshouldbeissuedafterthepreviousREADcommandaccord
ingtothet
CCD
timing.IfthatREADcommandistoanotherbankthenanACTIVEcommandmustpre
cedetheREADcommandandt
RCDRD
alsomustbemet.
WE#
A10,A11
0,0
CS#
CAS#
RAS#
CKE#
A9(A12)
A1
A8
LOW
READ
CK
CK#
CA
A0,A6
BA0BA3
A2A5
CA BA
A7
ENAP
DIS AP
BA=BankAddress; CA=ColumnAddress
0,0 CA
Rev. 1.0 / Nov. 2009 87
H5GQ1H24AFR
AWRITEcanbeissuedanytimeafteraREADcommandaslongasthebusturnaroundtimet
RTW
ismet.
IfthatWRITEcommandistoanotherbank,thenanACTIVEcommandmustprecedethesecondWRITE
commandandt
RCDWR
alsomustbemet.
APRECHARGEcanalsobeissuedtotheGDDR5SGRAMwiththesametimingrestrictionasthenew
READcommandift
RAS
ismet.AfterthePRECHARGEcommand,asubsequentcommandtothesame
bankcannotbeissueduntilt
RP
ismet.
ThedatainversionflagisdrivenontheDBI#pintoidentifywhetherthedataistrueorinverteddata.If
DBI#isHIGH,thedataisnotinverted,andifLOWitisinverted.READDataInversioncanbeenabled
(A8=0)ordisabled(A8=1)usingRDBIinMR1.
Rev. 1.0 / Nov. 2009 88
H5GQ1H24AFR
WhenenabledbytheRDCRCflaginMR4,EDCdataisreturnedtothecontrollerwithalatencyof(CLmrs
+CRCRL)*t
CK
+t
WCK2CKPIN
+t
WCK2CK
+t
WCK2DQO
,whereCRCRListheCRCReadlatencypro
grammedinMR4.
Figure 55. READ Word Lane Timing
CK
CK#
t
CH
t
CL
t
CK CLmrs
DQ/DBI#/EDC
(mean)
WCK#
WCK
t
WCK2CKPIN
+t
WCK2CK
t
WCK2DQO
DQ/DBI#/EDC
(firstbit)
DQ/DBI#/EDC
(lastbit)
t
DQDQO
(min)
t
DQDQO
(max)
1) CLmrsistheCASlatencyprogrammedinModeRegisterMR0.
2) Timingsareshownwithpositivet
WCK2CKPIN
andt
WCK2CK
values.SeeWCK2CKtimingsfor
t
WCK2CKPIN
andt
WCK2CK
ranges.
3) t
WCK2DQO
parametervaluescouldbenegativeorpositivenumbers,dependingonPLLonorPLLoffmode
operationanddesignimplementation.TheyalsovaryacrossPVT.Datatrainingisrequiredtodetermine
theactualt
WCK2DQO
valueforstableREADoperation.
4) t
DQDQO
definestheminimumtomaximumvariationoft
WCK2DQO
withinadoublebyte(x32mode)or
asinglebyte(x16mode).
5) t
DQDQO
alsoappliesforCRCdatafromWRITEandREADcommandswithCRCenabled,theEDChold
D1 D2 D3 D4 D5 D6 D7 D0
D1 D2 D3 D4 D5 D6 D7 D0
D1 D2 D3 D4 D5 D6 D7 D0
Case1:Negativet
WCK2DQO
DQ/DBI#/EDC
(mean)
t
WCK2DQO
DQ/DBI#/EDC
(firstbit)
DQ/DBI#/EDC
(lastbit)
t
DQDQO
(min)
t
DQDQO
(max)
D1 D2 D3 D4 D5 D6 D7 D0
D1 D2 D3 D4 D5 D6 D7 D0
D1 D2 D3 D4 D5 D6 D7 D0
Case2:Positivet
WCK2DQO
DontCare
pattern,andthedatastrobeinRDQSmode.
Rev. 1.0 / Nov. 2009 89
H5GQ1H24AFR
Figure 56. Single READ without EDC
3.BeforetheREADcommand,anACTIVE(ACT)commandisrequiredtobeissuedtotheGDDR5SGRAMandt
RCDRD
mustbemet.
4.t
WCK2DQO
DBI
CL=CLmrs=6
Banka,
Coln
Coln
CK
CK#
DQ
DBI#
T0 T1 T2 T5 T6n T6 T7n T8 T9 T10 T7
WCK#
DO DO
DBI
n+7
n+7
n
n
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
ODTDisabled ODTEnabled ODTEnabled ODT
(
)
(
)
(
)
(
)
1.CLmrs=6isshownasanexample.ActualsupportedvalueswillbefoundintheMRandACtimingssections.
WCK2CKPIN
=0,t
WCK2CK
Notes:
EDCHoldPattern EDC
WCK
ADDRESS
NOP READ NOP NOP NOP NOP NOP NOP NOP COMMAND
(
)
(
)
(
)
(
)
(
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(
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(
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(
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(
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(
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(
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(
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(
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(
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(
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(
)
Rev. 1.0 / Nov. 2009 90
H5GQ1H24AFR
Figure 57. Single READ with EDC
EDCHoldPattern
EDCHold
Pattern
EDC EDC
n+7 n
Banka,
Coln
Coln
CK
CK#
DQ
DBI#
CL=CLmrs=6
T0 T1 T6 T7 T7n T6n T8 T10 T11 T12 T9
EDC
WCK#
CRCRL=4
DO DO
DBI DBI
n+7
n+7
n
n
WCK
RCDRD
mustbemet.
4.t
WCK2DQO
1.CLmrs=6andCRCRL=4areshownasexamples.ActualsupportedvalueswillbefoundintheMRandACtimingssections.
WCK2CKPIN
=0,t
WCK2CK
Notes:
ADDRESS
NOP READ NOP NOP NOP NOP NOP NOP NOP
(
)
(
)
(
)
(
)
(
)
(
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(
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(
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(
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(
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(
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(
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(
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(
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(
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(
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(
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(
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(
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(
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(
)
(
)
(
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(
)
COMMAND
T10n T11n
Rev. 1.0 / Nov. 2009 91
H5GQ1H24AFR
Figure 58. Non-Gapless READs
DBI DBI
n+7 n
Banka,
Colm
Colm
CL=CLmrs=6
DO DO
DBI DBI
m+7
m+7
m
m
DO DO
n+7 n
Bankb,
Coln
Coln
t
CCD
CL=CLmrs=6
WCK2CKPIN
=0,t
WCK2CK
4.t
CCD
=t
CCDL
whenbankgroupsareenabledandbothREADsaccessbanksinthesamebankgroup;otherwiset
CCD
=t
CCDS
.
5.BeforetheREADcommands,anACTIVE(ACT)commandisrequiredtobeissuedtotheGDDR5SGRAMandt
RCDRD
mustbemet.
Notes:
6.t
WCK2DQI
NOP READ READ NOP NOP NOP NOP NOP NOP
CK
CK#
COMMAND
DQ
DBI#
WCK#
WCK
ADDRESS
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
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(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
Rev. 1.0 / Nov. 2009 92
H5GQ1H24AFR
Figure 59. Gapless READs
CL=CLmrs=6
Banka,
Colm
Colm
CK
CK#
DQ
DBI#
WCK#
WCK
Bankb,
Coln
Coln
DO DO
DBI DBI
m+7
m+7
m
m
t
CCD
DO DO
n+7 n
DBI DBI
n+7 n
WCK2CKPIN
=0,t
WCK2CK
4.t
CCD
=t
CCDS
whenbankgroupsaredisabledorthesecondREADistoadifferentbankgroup;otherwiset
CCD
=t
CCDL
.
RCDRD
mustbemet.
Notes:
6.t
WCK2DQI
NOP READ READ NOP NOP NOP NOP NOP NOP COMMAND
ADDRESS
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
Rev. 1.0 / Nov. 2009 93
H5GQ1H24AFR
Figure 60. READ to WRITE
DBI DBI
n+7 n
DO DO
n+7 n
DO DO
DBI DBI
m+7
m+7
m
m
WL=WLmrs=3
CL=CLmrs=6
Banka,
Colm
Colm
T9 T11 T12 T0 T1 T6 T7 T7n T8 T6n T10 T10n
Bankb,
Coln
Coln
t
RTW
T11n
WCK2CKPIN
=0,t
WCK2CK
respectivelymustbemet.
1.WLmrs=3andCLmrs=6isshownasanexample.ActualsupportedvalueswillbefoundintheMRandACtimingssections.
6.BeforetheREADandWRITEcommands,anACTIVE(ACT)commandisrequiredtobeissuedtotheGDDR5SGRAMandt
RCDRD
ort
RCDWR
4.t
WTR
=t
WTRL
whenbankgroupsisenabledandbothWRITEandREADaccessbanksinthesamebankgroup,otherwiset
WTR
=t
WTRS
.
Notes:
7.t
WCK2DQI
,t
WCKDQO
NOP READ NOP WRITE NOP NOP NOP NOP NOP
CK
CK#
COMMAND
ADDRESS
DQ
DBI#
WCK#
WCK
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
Rev. 1.0 / Nov. 2009 94
H5GQ1H24AFR
Figure 61. READ to PRECHARGE
DO DO
DBI DBI
n+7
n+7
n
n
Banka,
Coln
Coln
CK
CK#
DQ
DBI#
CL=CLmrs=6
WCK#
WCK
T5 T7 T8 T0 T1 T2 T3 T4 T7n T6 T6n
t
RTP
Banka,
orall
t
RP
WCK2CKPIN
=0,t
WCK2CK
4.t
RTP
=t
RTPL
whenbankgroupsareenabledandthePRECHARGEcommandaccessesthesamebank;otherwiset
RTP
=t
RTPS
.
RCDRD
mustbemet.
Notes:
6.t
WCK2DQO
NOP READ PRE NOP NOP NOP NOP NOP NOP
ADDRESS
COMMAND
Rev. 1.0 / Nov. 2009 95
H5GQ1H24AFR
5.10.DQPREAMBLE
DQpreambleisafeatureforGDDR5SGRAMsthatisusedforREADdata.DQpreambleconditionsthe
DQsforbettersignalintegrityontheinitialdataofaburst.
Onceenabledbybit5inMR7,theDQpreamblewillprecedeallREADbursts,includingnonconsecutive
READburstswithaminimumgapof1t
CK
,asshowninFigure58.Whenenabled,theDQpreamblepat
ternappliestoallDQandDBI#pinsinabyte,andthesamepatternisusedforallbytesasshownin
Figure62.DQpreambleisenabledordisabledforallbytes.TheEDCpinineachbyteisnotincludedinthe
DQpreamble.IfODTisenabled,theODTisdisabled1t
CK
beforethestartofthepreamblepatternas
showninFigure63.
ThepreamblepatternontheDBI#pinisonlyenablediftheMRforRDBIisenabled(MR1A8bit).During
thepreambletheDBI#pinistreatedasanotherDQpinandthepreamblepatternontheDQsisnot
encodedwithRDBI.IfRDBIisdisabled,thentheDBI#pindrivesODT.
Notes:
1)ThenumberofMax0sintheburstis4onlyifRDBIisenabled.Max0sisonaperbytebasisanddoesnotincludetheEDCpin.
2)x=ValidData
Figure 62. DQ Preamble Pattern
Byte0 Byte1 Byte2 Byte3 Idle Preamble Burst
DQ7 DQ15 DQ23 DQ31 1 1 1 1 0 1 0 1 x x x x x x x x
DBI0# DBI1# DBI2# DBI3# 1 1 1 1 0 1 0 1 x x x x x x x x
Max0s 0 0 0 0 5 4 5 4 4 4 4 4 4 4 4 4
Time
Rev. 1.0 / Nov. 2009 96
H5GQ1H24AFR
Figure 63. Preamble Timing Diagram
DBI
DO DO
DBI
n+7
n+7
n
n
DO DO
n+7 n
CL=CLmrs=6
Banka,
Coln
Coln
CK
CK#
DQ6
DBI#
T0 T1 T4 T5 T5n T6n T6 T7n T8 T9 T10 T7
WCK#
DQ7
WCK
ODTDisabled ODTEnabled ODTEnabled ODT
WCK2CKPIN
=0,t
WCK2CK
4.DQ6,DQ7andtheDBI#pinareshowntoillustratetheDQpreamblepattern.RDBIisEnabled(MR1A8=0).
RCDRD
mustbemet.
Notes:
6.t
WCK2DQO
NOP READ NOP NOP NOP NOP NOP NOP NOP
ADDRESS
COMMAND
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
Rev. 1.0 / Nov. 2009 97
H5GQ1H24AFR
5.11.READandWRITEDATABUSINVERSION(DBI)
TheGDDR5SGRAMDataBusInversion(DBIdc)reducestheDCpowerconsumptionondatapins,asthe
numberofDQlinesdrivingalowlevelcanbelimitedto4withinabyte.DBIdcisevaluatedperbyte.
ThereisoneDBI#pinperbyte:DBI0#isassociatedwithDQ0DQ7,DBI1#withDQ8DQ15,DBI2#with
DQ16DQ23andDBI3#withDQ24DQ31.
TheDBI#pinsarebidirectionalactiveLowdoubledatarate(DDR)signals.ForWrites,theyaresampled
bytheGDDR5SGRAMalongwiththeDQofthesamebyte.ForReads,theyaredrivenbytheGDDR5
SGRAMalongwiththeDQofthesamebyte.
OnceenabledbythecorrespondingRDBIModeRegisterbit,theGDDR5SGRAMinvertsreaddataand
setsDBI#Low,whenthenumberof0databitswithinabyteisgreaterthan4;otherwisetheGDDR5
SGRAMdoesnotinvertthereaddataandsetsDBI#High,asshowninFigure64.
OnceenabledbythecorrespondingWDBIModeRegisterbit,theGDDR5SGRAMinvertswritedata
receivedontheDQinputsincaseDBI#wassampledLow,orleavesthedatanoninvertedincaseDBI#
wassampledHigh,asshowninFigure65.
Figure 64. Example of Data Bus Inversion Logic for READs
Figure 65. Example of Data Bus Inversion Logic for WRITEs
TheflowdiagraminFigure66illustratestheDBIdcoperation.Inanycase,thetransmitter(thecontroller
forWRITEs,theGDDR5SGRAMforREADs)decideswhethertoinvertornotinvertthedataconveyedon
theDQs.Thereceiver(theGDDR5SGRAMforWRITEs,thecontrollerforREADs)hastoperformthe
reverseoperationbasedonthelevelontheDBI#pin.Datainputandoutputtimingparametersareonly
validwithDBIbeingenabledandamaximumof4datalinesperbytedrivenLow.
8
8
from
DRAM
core
DQ
fromModeRegister:
0=enabled
1=disabled
DBI#
0
count
>4
8
8
to
DRAM
core
DBI#
DQ
fromModeRegister:
0=enabled
1=disabled
Rev. 1.0 / Nov. 2009 98
H5GQ1H24AFR
Figure 66. DBI Flow Diagram
DBI#PinSpecialFunctionOverview
TheDBI#pinhasspecialbehaviorcomparedtoDQpinsbecauseoftheabilitytoenableanddisableitvia
MRS.ForeitherWRITEorREADDBI#pintraining,bothDBIREADandDBIWRITEinMRSmustbe
enabled.ThebehavioroftheDBI#pininvariousmoderegistersettingsissummarizedbelow:
IfbothDBIREADandDBIWRITEareenabled:
PindrivesDBIFIFOdatawithRDTRcommand
DBI#pinFIFOacceptsWRTRdatawiththeWRTRcommand
IfonlyDBIREADisenabled:
DBI#pindrivesODTwhennotREADorRDTR
IfonlyDBIWRITEisenabled:
PinalwaysdrivesODT(unlessRESET)
IfbothDBIREADandDBIWRITEaredisabled:
DBI#pindrivesODT(unlessRESET)
No Yes
Logical
outputdata
0count
>4?
DBI#=L
Invert
databyte
DBI#=H
Dontinvert
databyte
Determine0count
indatabyte
Logical
inputdata
DBI#=H
Dontinvert
databyte
DBI#=L
Invert
databyte
Transmitter
Receiver
Rev. 1.0 / Nov. 2009 99
H5GQ1H24AFR
5.12.ERRORDETECTIONCODE(EDC)
TheGDDR5SGRAMprovideserrordetectiononthedatabustoimprovesystemreliability.Thedevice
generatesachecksumperbytelaneforbothREADandWRITEdataandreturnsthechecksumtothecon
troller.Basedonthechecksum,thecontrollercandecideifthedata(orthereturnedCRC)wastransmitted
inerrorandretrytheREADorWRITEcommand.TheGDDR5SGRAMitselfdoesnotperformanyerror
correction.ThefeaturesoftheEDCare:
8bitchecksumon72bits(9channelsx8bitburst)
dedicatedEDCtransferpinper9channels(4xperGDDR5SGRAM)
asymmetricallatenciesonEDCtransferforReadsandWrites
TheCRCpolynomialusedbytheGDDR5SGRAMisanATM8HEC,X^8+X^2+X^1+1.Thestartingseed
valueissetinhardwareatzero.Table24showstheerrortypesthataredetectableandthedetectionrate.
ThebitorderingcalculationfortheCRCerrordetectionisoptimizedforerrorsinthetimeburstdirection.
Figure67showsthebitorientationonabytelanebasis.
Table 24ErrorCorrectionDetails
ErrorType DetectionRate
RandomSingleBit 100%
RandomDoubleBit 100%
RandomOddCount 100%
Burst<=8 100%
Rev. 1.0 / Nov. 2009 100
H5GQ1H24AFR
Figure 67. EDC Calculation matrix
TheCRCcalculationisembeddedintotheWRITEandREADdatastreamasshowninFigure16:
forWRITEs,theCRCchecksumiscalculatedontheDQandDBI#inputdatabeforedecodingwithDBI
forREADs,theCRCchecksumiscalculatedontheDQandDBI#outputdataafterencodingwithDBI
Thebitorderingisoptimizedforerrorsinthetimeburstdirection.Figure67showsthebitorientationona
bytelanebasis.All1sareassumedinthecalculationfortheDBI#inburstincaseDBIisdisabledfor
WRITEsorREADsintheModeRegister.
TheCRCcalculationisalsonotaffectedbyanydatamasksentalongwithWDM,WDMA,WSMorWSMA
commands.
TheEDClatencyisbasedontheCASlatencyforREADdataandtheWRITElatencyforWRITEdata.
Table25showsthe2timingparametersassociatedwiththeEDCscheme.
ModeRegister4isusedtodeterminethefunctionalityoftheEDCpin.RegisterbitsA9andA10controlthe
GDDR5SGRAMsCRCcalculationindependentlyforREADsandWRITEs.WithEDCoff,thecalculated
CRCpatternwillbereplacedbytheEDCholdpatterndefinedinModeRegisterbitsA0A3.SeeMode
Registersonpage39sectionformoredetails.
DQ0 0 1 2 3 4 5 6 7
8 9 10 11 12 13 14 15
16 17 18 19 20 21 22 23
24 25 26 27 28 29 30 31
32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47
48 49 50 51 52 53 54 55
56 57 58 59 60 61 62 63
64 65 66 67 68 69 70 71
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DBI0#
Burst8Ordering(2t
CK
)
CRCDataInput
DQ/DBI#bitordering
0 1 2 3 4 5 6 7
CRCPolynomial
T0+8U.I. T0
CRCDataOutput
EDCbitordering
Burst8Ordering(2t
CK
)
X0 X1 X2 X3 X4 X5 X6 X7
T0+8U.I. T0
X
8
+X
2
+X+1=0x83=(X+1)(X
7
+X
6
+X
5
+X
4
+X
3
+X
2
+1)
Rev. 1.0 / Nov. 2009 101
H5GQ1H24AFR
Table 25EDCTiming
Description Parameter Value Units
EDCREADLatency t
EDCRL
CL+CRCRL t
CK
EDCWRITELatency t
EDCWL
WL+CRCWL t
CK
Rev. 1.0 / Nov. 2009 102
H5GQ1H24AFR
EDCPinSpecialFunctionOverview
TheEDCpinisusedformanydifferentfunctions.ThebehavioroftheEDCpininvariousmodesissum
marizedinTable26.
Table 26EDCPinBehavior
DeviceStatus Condition EDC0EDC3PinStatus
DevicePowerup
RESET#=LOW HiZ
RESET#=HIGH;noWCKclocks High
RESET#=HIGH;stableWCKclocks EDCholdpattern(default=1111)
WCK2CKTraining
WCKissampledHigh EDCholdpattern(1111)
WCKissampledLow InvertedEDCholdpattern(0000)
Idle
EDC13invMR4A11=0 EDCholdpattern
EDC13invMR4A11=1
EDC0,EDC2:EDCholdpattern
EDC1,EDC3:invertedEDCholdpattern
WRITEBurst
WRCRCon CRCdata
WRCRCoff EDCholdpattern
READorRDTRburst
RDCRCon CRCdata
RDCRCoff EDCholdpattern
LDFF WRCRC+RDCRCbothonorbothoff EDCholdpattern
WRTRburst EDCholdpattern
PowerDown
WCKenabled(MR5A1=0) EDCholdpattern
WCKdisabledduringPowerDown
usingMR5A1=1
High
SelfRefresh High
ReadBurstinRDQSMode MR3A5=1
Fixed1010strobepatternwith4U.I.
preamble
READburstinRDQSModewith
RDQSpseudodifferential
MR3A5=1;EDC13invMR4A11=1
EDC0,EDC2:Fixed1010strobepattern
with4U.I.preamble
EDC1,EDC3:Fixed0101strobepattern
with4U.I.preamble
Rev. 1.0 / Nov. 2009 103
H5GQ1H24AFR
5.13.PRECHARGE
ThePRECHARGEcommand(seeFigure68)isusedtodeactivatetheopenrowinaparticularbank(PRE)
ortheopenrowinallbanks(PREALL).Thebank(s)willbeavailableforasubsequentrowaccessaspeci
fiedtime(t
RP
)afterthePRECHARGEcommandisissuedasillustratedinFigure39.
InputA8determineswhetheroneorallbanksaretobeprecharged.Incasewhereonlyonebankistobe
precharged,inputsBA0BA3selectthebank.OtherwiseBA0BA3aretreatedasDontCare.
Onceabankhasbeenprecharged,itisintheidlestateandmustbeactivatedpriortoanyREADorWRITE
commandbeingissued.APRECHARGEcommandwillbetreatedasaNOPifthereisnoopenrowinthat
bank,orifthepreviouslyopenrowisalreadyintheprocessofprecharging.SequencesofPRECHARGE
commandsmustbespacedbyatleastt
PPD
asshowninFigure69.
Figure 68. PRECHARGE command
Figure 69. Precharge to Precharge Timings
BA=BankAddress(ifA8isLOW;
otherwiseDontCare)
CS#
WE#
CAS#
RAS#
CKE#
A9A11(A12)
A0,A1,A6,A7
A8
BA0BA3
A2A5
LOW
PREALL
PRE
BA
Precharge
CK
CK#
A7
CK#
CK
CMD NOP
BAx,y=bankaddressx,y
ADDR
PRE NOP PRE NOP
BAy
t
PPD
BAx
t
RAS
t
RP
T0 T1 T2 T3 T4
DontCare
Rev. 1.0 / Nov. 2009 104
H5GQ1H24AFR
5.14.AUTOPRECHARGE
AutoPrechargeisafeaturewhichperformsthesameindividualbankprechargefunctionasdescribed
above,butwithoutrequiringanexplicitcommand.ThisisaccomplishedbyusingA8(A8=High),to
enableAutoPrechargeinconjunctionwithaspecificREADorWRITEcommand.Aprechargeofthebank
/rowthatisaddressedwiththeREADorWRITEcommandisautomaticallyperformeduponcompletion
ofthereadorwriteburst.AutoPrechargeisnonpersistentinthatitiseitherenabledordisabledforeach
individualREADorWRITEcommand.
AutoPrechargeensuresthataprechargeisinitiatedattheearliestvalidstagewithinaburst.Theuser
mustnotissueanothercommandtothesamebankuntiltheprechargetime(t
RP
)iscompleted.Thisis
determinedasifanexplicitPRECHARGEcommandwasissuedattheearliestpossibletime,asdescribed
foreachbursttypeintheOPERATIONsectionofthisspecification.
5.15.REFRESH
TheREFRESHcommandisusedduringnormaloperationoftheGDDR5SGRAM.Thecommandisnon
persistent,soitmustbeissuedeachtimearefreshisrequired.Aminimumtimet
RFC
isrequiredbetween
twoREFRESHcommands.Thesameruleappliestoanyaccesscommandaftertherefreshoperation.All
banksmustbeprechargedpriortotheREFRESHcommand.
Therefreshaddressingisgeneratedbytheinternalrefreshcontroller.ThismakestheaddressbitsDont
CareduringaREFRESHcommand.TheGDDR5SGRAMrequiresREFRESHcyclesatanaverageperi
odicintervaloft
REFI
(max).Thevaluesoft
REFI
fordifferentdensitiesarelistedinTable6.Toallowfor
improvedefficiencyinschedulingandswitchingbetweentasks,someflexibilityintheabsoluterefresh
intervalisprovided.AmaximumofeightREFRESHcommandscanbepostedtotheGDDR5SGRAM,and
themaximumabsoluteintervalbetweenanyREFRESHcommandandthenextREFRESHcommandis9*
t
REFI
.
DuringREFRESH,andwhenbitA2inMR5issetto0,WRTR,RDTR,andLDFFcommandsareallowedat
timet
REFTR
aftertheREFRESHcommand,whichenable(incremental)datatrainingtooccurinparallel
withtheinternalrefreshoperationandthuswithoutlossofperformanceontheinterface.SeeREADTrain
ingandWRITETrainingfordetails.
AsimpedanceupdatesfromtheautocalibrationenginemayoccurwithanyREFRESHcommand,itissafe
toonlyissueNOPcommandsduringt
KO
periodtopreventfalsecommand,addressordatalatching
resultingfromimpedanceupdates.
Rev. 1.0 / Nov. 2009 105
H5GQ1H24AFR
Figure 70. REFRESH command
Figure 71. Refresh Timings
CS#
WE#
CAS#
RAS#
CKE#
A9A11(A12)
A0,A1,A6
A8
BA0BA3
A2A5
LOW
Refresh
CK
CK#
A7
CK#
CK
CMD
t
KO
DQ
NOP
PRE
ALL
BA=bankaddress;RA=rowaddress
WRTRandRDTRcommandsareallowedduringrefreshunlessdisabledintheModeRegister
REF
ADDR
T0 T1 Ta0 Ta1 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tc0
NOP WRTR NOP NOP NOP NOP NOP ACT
WCK
WCK#
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
WL=3
t
RP
t
RFC
t
REFTR
DontCare
BA
RA
WCKandCKareshownaligned(t
WCK2CKPIN
=0,t
WCK2CK
=0)forillustrationpurposes.WCK2CKtrainingdetermines
theneededoffsetbetweenWCKandCK.
Rev. 1.0 / Nov. 2009 106
H5GQ1H24AFR
5.16.SELFREFRESH
SelfRefreshcanbeusedtoretaindataintheGDDR5SGRAM,eveniftherestofthesystemispowered
down.WhenintheSelfRefreshmode,theGDDR5SGRAMretainsdatawithoutexternalclocking.The
SELFREFRESHENTRYcommand(seeFigure72)isinitiatedlikeaREFRESHcommandexceptthatCKE#
ispulledHIGH.SELFREFRESHENTRYisonlyallowedwhenallbanksareprechargedwitht
RP
satisfied,
andwhenthelastdataelementorCRCdataelementfromaprecedingREADorWRITEcommandhave
beenpushedout(t
RDSRE
).NOPcommandsarerequireduntilt
CKSRE
ismetaftertheenteringSelfRefresh.
ThePLLisautomaticallydisableduponenteringSelfRefreshandisautomaticallyenabledandresetupon
exitingSelfRefresh.IftheGDDR5SGRAMentersSelfRefreshwiththePLLdisabled,itwillexitSelf
RefreshwiththePLLdisabled.
OncetheSELFREFRESHENTRYcommandisregistered,CKE#mustbeheldHIGHtokeepthedevicein
SelfRefreshmode.WhenthedevicehasenteredtheSelfRefreshmode,allexternalcontrolsignals,except
CKE#andRESET#areDontcare.ForproperSelfRefreshoperation,allpowersupplyandreference
pins(VDD,VDDQ,VSS,VSSQ,VREFC,VREFD)mustbeatvalidlevels.TheGDDR5SGRAMinitiatesa
minimumofoneinternalrefreshwithint
CKE
periodonceitentersSelfRefreshmode.Theaddress,com
mand,dataandWCKpinsareinODTstate,andtheEDCpinsdriveaHIGH.
TheclockisinternallydisabledduringSelfRefreshoperationtosavepower.Theminimumtimethatthe
GDDR5SGRAMmustremaininSelfRefreshmodeist
CKE
.Theusermaychangetheexternalclockfre
quencyorhalttheexternalCKandWCKclockst
CKSRE
afterSelfRefreshentryisregistered.However,the
clocksmustberestartedandstablet
CKSRX
beforethedevicecanexitSelfRefreshoperation.
TheprocedureforexitingSelfRefreshrequiresasequenceofevents.First,theCKandWCKclocksmust
bestablepriortoCKE#goingbackLOW.Adelayofatleastt
XSNRW
mustbesatisfiedbeforeavalidcom
mandnotrequiringalockedPLLcanbeissuedtothedevicetoallowforcompletionofanyinternal
refreshinprogress.BeforeacommandrequiringalockedPLLcanbeapplied,adelayofatleastt
XSRW
mustbesatisfied.
DuringSelfRefreshtheondietermination(ODT)anddriverwillnotbeautocalibrated.Therefore,itis
recommendedthattheODTanddriverberecalibratedbythecontrolleruponexitingSelfRefresh.Alter
natively,ifchangesinvoltageandtemperaturearetrackedorknowntobeboundedthentheprovided
VoltageandTemperatureVariationtablesmaybeconsultedtodetermineifrecalibrationisnecessary.
UponexitfromSelfRefresh,theGDDR5SGRAMcanbeputbackintoSelfRefreshmodeafterwaitingat
leastt
XSNRW
periodandissuingoneextraREFRESHcommand.
Rev. 1.0 / Nov. 2009 107
H5GQ1H24AFR
Figure 72. SELF REFRESH Entry Command
Figure 73. Self Refresh Entry and Exit
Note:
1.Clock(CKandCK#)mustbestablebeforeexitingselfrefreshmode.
2.Devicemustbeintheallbanksidlestatepriortoenteringselfrefreshmode.
3.t
XSNRW
isrequiredbeforeanynonREADorWRITEcommandcanbeapplied,andt
XSRW
isrequiredbeforeaREADorWRITEcommandcanbe
applied.
4.REF=REFRESHcommand.
CS#
WE#
CAS#
RAS#
CKE#
A9A11(A12)
A0,A1,A6
A8
BA0BA3
A2A5
HIGH
SelfRefresh
CK
CK#
A7
CK#
CK
CMD
DQ
SRE NOP
ADDR
T0 T1 T2 Ta0 Tb2 Tb0 Tb1 Td0
SRX PREA Valid NOP
t
CPDED
CKE#
NOP
t
CKSRE
t
CKSRX
t
RP
Tc0
EnterSelfRefreshMode ExitSelfRefreshMode
t
XSNRW
t
XSRW
t
RDSRE
ort
WRSRE
SelfrefreshexitrequiresWCK2CKtrainingpriortoanyWRITEorREADoperation
AtleastoneREFRESHcommandshallbeissuedaftert
XSNRW
foroutputdriverandterminationimpedanceupdates.
NOP
DontCare
t
CMDS
Rev. 1.0 / Nov. 2009 108
H5GQ1H24AFR
Table 27PinStatesDuringSelfRefresh
Pin State
EDC High
DQ/DBI# ODT
ADR/CMD ODT
CKE# ODT(DrivenHighbyController)
WCK/WCK# ODT
Rev. 1.0 / Nov. 2009 109
H5GQ1H24AFR
5.17.POWERDOWN
GDDR5SGRAMsrequiresCKE#tobeLOWatalltimesanaccessisinprogress:fromtheissuingofa
READorWRITEcommanduntilcompletionoftheburst.ForREADs,aburstcompletionisdefinedas
whenthelastdataelementincludingCRChasbeentransmittedontheDQoutputs,forWRITEs,aburst
completionisdefinedaswhenthelastdataelementhasbeenwrittentothememoryarrayandCRCdata
hasbeenreturnedtothecontroller.
POWERDOWNisenteredwhenCKE#isregisteredHIGH.IfPOWERDOWNoccurswhenallbanksare
idle,thismodeisreferredtoasprechargePOWERDOWN;ifPOWERDOWNoccurswhenthereisarow
activeinanybank,thismodeisreferredtoasactivePOWERDOWN.EnteringPOWERDOWNdeacti
vatestheinputandoutputbuffers,excludingCK,CK#,WCK,WCK#,EDCpinsandCKE#.
Formaximumpowersavings,theuserhastheoptionofdisablingthePLLpriortoenteringPOWER
DOWN.Inthatcase,onexitingPOWERDOWN,WCK2CKtrainingisrequiredtosettheinternalsynchro
nizerswhichwillincludetheenablingofthePLL,PLLreset,andt
LK
clockcyclesmustoccurbeforeany
READorWRITEcommandcanbeissued.
Whileinpowerdown,CKE#HIGHandstableCKandWCKsignalsmustbemaintainedatthedevice
inputs.TheEDCpinscontinuouslydrivetheEDCholdpattern;ifthecontrollerdoesnotrequireCDR,
usersmayprogramtheEDCholdpatternto1111priortoenteringpowerdownmode.POWERDOWN
durationislimitedbytherefreshrequirementsofthedevice.
ThePOWERDOWNstateissynchronouslyexitedwhenCKE#isregisteredLOW(inconjunctionwitha
NOPorDESELECTcommand).Avalidexecutablecommandmaybeappliedt
XPN
cycleslater.Themin.
powerdowndurationisspecifiedbyt
PD
.
Figure 74. Power-Down Entry and Exit
Note:
1.MinimumCKE#pulsewidthmustsatisfyt
CKE
.
2.AfterissuingPowerDowncommand,twomoreNOPsshouldbeissued.
CK#
CK
CMD PDE NOP
T0 T1 T2 T3 Tb0 Ta1 Ta2
PDX Valid NOP
t
CPDED
CKE#
NOP
t
PD
EnterPowerDownMode ExitPowerDownMode
t
XPN
t
RDSRE
ort
WRSRE
WCK
WCK#
NOP
T4 Ta0
DontCare
Rev. 1.0 / Nov. 2009 110
H5GQ1H24AFR
5.18.COMMANDTRUTHTABLES
Notes:
1.CKE#nisthelogicstateofCKE#atclockedgen;CKE#n1wasthestateofCKE#atthepreviousclockedge.
2.CurrentstateisthestateoftheGDDR5SGRAMimmediatelypriortoclockedgen.
3.COMMANDnisthecommandregisteredatclockedgen,andACTIONnisaresultofCOMMANDn.
4.Allstatesandsequencesnotshownareillegalorreserved.
5.DESELECTorNOPcommandsshouldbeissuedonanyclockedgesoccurringduringthet
XSRW
period.Aminimumoft
LK
is
neededforthePLLtolockbeforeapplyingaREADorWRITEcommandifthePLLwasdisabled.
Table 28PinStatesDuringPowerDown
Pin LP2 State
EDC
WCK Hold
noWCK High
DQ/DBI# x ODT
ADR/CMD x ODT
CKE# x ODT(DrivenHighbyController)
WCK/WCK# x ODT
Table 29TruthTableCKE#
CKE#n1 CKE#n
CURRENT
STATE
COMMANDn ACTIONn NOTES
H H PowerDown X MaintainPowerDown
H H SelfRefresh X MaintainSelfRefresh
H L PowerDown DESELECTorNOP ExitPowerDown
H L SelfRefresh DESELECTorNOP ExitSelfRefresh 5
L H AllBanksIdle DESELECTorNOP PrechargePowerDownEntry
L H Bank(s)Active DESELECTorNOP ActivePowerDownEntry
L H AllBanksIdle REFRESH SelfRefreshEntry
L L
See<Link>Table30and
<Link>Table31
1,2,3
Rev. 1.0 / Nov. 2009 111
H5GQ1H24AFR
Notes
1.ThistableapplieswhenCKE#n1wasLOWandCKE#nisLOW(see<Link>Table29)andaftert
XSNR
hasbeenmet(iftheprevious
statewasselfrefresh).
2.Thistableisbankspecific,exceptwherenoted(i.e.,thecurrentstateisforaspecificbankandthecommandsshownarethose
allowedtobeissuedtothatbankwheninthatstate).Exceptionsarecoveredinthenotesbelow.
3.Currentstatedefinitions:
Idle:Thebankhasbeenprecharged,andt
RP
hasbeenmet.
RowActive:Arowinthebankhasbeenactivated,andt
RCD
hasbeenmet.Nodatabursts/accessesandnoregisteraccessesare
inprogress.
Read:AREADbursthasbeeninitiated,withautoprechargedisabled.
Write:AWRITEbursthasbeeninitiated,withautoprechargedisabled.
4.Thefollowingstatesmustnotbeinterruptedbyacommandissuedtothesamebank.DESELECTorNOPcommands,orallowable
commandstotheotherbankshouldbeissuedonanyclockedgeoccurringduringthesestates.Allowablecommandstotheother
bankaredeterminedbyitscurrentstateand<Link>Table30,andaccordingto<Link>Table31.
Precharging:StartswithregistrationofaPRECHARGEcommandandendswhent
RP
ismet.Oncet
RP
ismet,thebankwillbein
theidlestate.
RowActivating:StartswithregistrationofanACTIVEcommandandendswhent
RCD
ismet.Oncet
RCD
ismet,thebankwillbe
intherowactivestate.
Readw/AutoPrechargeEnabled:StartswithregistrationofaREADcommandwithautoprechargeenabledandendswhent
RP
hasbeenmet.Oncet
RP
ismet,thebankwillbeintheidlestate.
Writew/AutoPrechargeEnabled:StartswithregistrationofaWRITEcommandwithautoprechargeenabledandendswhent
RP
hasbeenmet.Oncet
RP
ismet,thebankwillbeintheidlestate.
5.Thefollowingstatesmustnotbeinterruptedbyanyexecutablecommand;DESELECTorNOPcommandsmustbeappliedoneach
positiveclockedgeduringthesestates.
Refreshing:StartswithregistrationofaREFRESHcommandandendswhent
RC
ismet.Oncet
RC
ismet,theGDDR5SGRAMwill
beintheallbanksidlestate.
AccessingModeRegister:StartswithregistrationofaMODEREGISTERSETcommandandendswhent
MRD
hasbeenmet.Once
t
MRD
ismet,theGDDR5SGRAMwillbeintheallbanksidlestate.
PrechargingAll:StartswithregistrationofaPRECHARGEALLcommandandendswhent
RP
ismet.Oncet
RP
ismet,allbanks
willbeintheidlestate.
READorWRITE:StartswiththeregistrationoftheACTIVEcommandandendsthelastvaliddatanibble.
7.Notbankspecific;requiresthatallbanksareidle,andburstsarenotinprogress.
8.Mayormaynotbebankspecific;ifmultiplebanksaretobeprecharged,eachmustbeinavalidstateforprecharging.
Table 30TruthTableCurrentStateBanknCommandToBankn
CURRENT
STATE
CS# RAS# CAS# WE# COMMAND/ACTION NOTES
Any
H X X X DESELECT(NOP/continuepreviousoperation)
L H H H NOOPERATION(NOP/continuepreviousoperation)
Idle
L L H H ACTIVE(selectandactivaterow)
L L L H REFRESH 4
L L L L MODEREGISTERSET 4
RowActive
L H L H READ(selectcolumnandstartREADburst) 6
L H L L
WRITE(selectcolumnandstartWRITEburst)
(WOM,WSMorWDM)
6
L L H L PRECHARGE(deactivaterowinbankorbanks) 5
Read
(Auto
Precharge
Disabled)
L H L H READ(selectcolumnandstartnewREADburst) 6
L H L L
WRITE(selectcolumnandstartWRITEburst)
(WOM,WSMorWDM)
6,8
L L H L PRECHARGE(onlyaftertheREADburstiscomplete 5
Write
(Auto
Precharge
Disabled)
(WOM,WSM
orWDM)
L H L H READ(selectcolumnandstartREADburst) 6,7
L H L L
WRITE(selectcolumnandstartnewWRITEburst)
(WOM,WSMorWDM)
6
L L H L PRECHARGE(onlyaftertheWRITEburstiscomplete) 5,7
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9.ReadsorWriteslistedintheCommand/ActioncolumnincludeReadsorWriteswithautoprechargeenabledandReadsorWrites
withautoprechargedisabled.
10.AWRITEcommandmaybeappliedafterthecompletionoftheREADburst
Notes
1.ThistableapplieswhenCKE#n1wasLOWandCKE#nisLOW(see<Link>Table30)andaftert
XSNR
hasbeenmet(iftheprevious
statewasselfrefresh).
2.WRITEinthistablereferstobothWOM/WOMA,WSM/WSMAandWDM/WDMAcommands
3.Thistabledescribesalternatebankoperation,exceptwherenoted(i.e.,thecurrentstateisforbanknandthecommandsshownare
thoseallowedtobeissuedtobankm,assumingthatbankmisinsuchastatethatthegivencommandisallowable).Exceptions
arecoveredinthenotesbelow.
4.Currentstatedefinitions:
Idle:Thebankhasbeenprecharged,andt
RP
hasbeenmet.
RowActive:Arowinthebankhasbeenactivated,andt
RCD
hasbeenmet.Nodatabursts/accessesandnoregisteraccessesare
inprogress.
Read:AREADbursthasbeeninitiated,withautoprechargedisabled.
Write:AWRITEbursthasbeeninitiated,withautoprechargedisabled.
ReadwithAutoPrechargeEnabled:Seefollowingtext
WritewithAutoPrechargeEnabled:Seefollowingtext
4a.Thereadwithautoprechargeenabledorwritewithautoprechargeenabledstatescaneachbebrokenintotwoparts:theaccess
periodandtheprechargeperiod.Forreadwithautoprecharge,theprechargeperiodisdefinedasifthesameburstwas
Table 31TruthTableCurrentStateBanknCommandToBankm
CURRENT
STATE
CS# RAS# CAS# WE# COMMAND/ACTION NOTES
Any H X X X DESELECT(NOP/continuepreviousoperation)
L H H H NOOPERATION(NOP/continuepreviousoperation)
Idle X X X X AnyCommandOtherwiseAllowedtoBankm
RowActivating,
Active,or
Precharging
L H L L WRITE(selectcolumnandstartWRITEburst)
(WOM,WSMorWDM)
6
L L H L PRECHARGE
Read
(AutoPrecharge
Disabled)
(WOM,WSMorWDM)
6
L L H L PRECHARGE
Write
(AutoPrecharge
Disabled)
L H L H READ(selectcolumnandstartREADburst) 6,7
L H L L WRITE(selectcolumnandstartnewWRITEburst)
(WOM,WSMorWDM)
6
L L H L PRECHARGE
Read
(WithAuto
Precharge)
(WOM,WSMorWDM)
6
L L H L PRECHARGE
Write
(WithAuto
Precharge)
L H L L WRITE(selectcolumnandstartnewWRITEburst)
(WOM,WSMorWDM)
6
L L H L PRECHARGE
Rev. 1.0 / Nov. 2009 113
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executedwithautoprechargedisabledandthenfollowedwiththeearliestpossiblePRECHARGEcommandthatstillaccesses
allofthedataintheburst.Forwritewithautoprecharge,theprechargeperiodbeginswhent
WR
ends,witht
WR
measuredasif
autoprechargewasdisabled.Theaccessperiodstartswithregistrationofthecommandandendswheretheprechargeperiod
(ort
RP
)begins.Duringtheprechargeperiodofthereadwithautoprechargeenabledorwritewithautoprechargeenabled
states,ACTIVE,PRECHARGE,READandWRITEcommandstotheotherbankmaybeapplied.Ineithercase,allotherrelated
limitationsapply(e.g.,contentionbetweenreaddataandwritedatamustbeavoided).
4b.TheminimumdelayfromaREADorWRITEcommandwithautoprechargeenabled,toacommandtoadifferentbankis
summarizedbelow.
5.REFRESHandMODEREGISTERSETcommandsmayonlybeissuedwhenallbanksareidle.
7.READsorWRITEslistedintheCommand/ActioncolumnincludeREADsorWRITEswithautoprechargeenabledandREADsor
WRITEswithautoprechargedisabled.
*** CL=CASlatency(CL)
BL=Burstlength
WL=WRITElatency
t
WTR
=t
WTRL
ifBankGroupsenabledandaccesstothesamebankotherwiset
WTR
=t
WTRS
Table 32MinimumDelayBetweenCommandstoDifferentBankswithAutoPrechargeEnabled
FromCommand ToCommand Minimumdelay
(withconcurrentautoprecharge)
WRITE
withAUTO
PRECHARGE
(WOMA)
READorREADwithAUTOPRECHARGE [WLmrs+(BL/4)]t
CK
+t
WTRL
***
WRITEorWRITEwithAUTOPRECHARGE
(WOM/WOMA,WSM/WSMAorWDM/WDMA)
2*t
CK
PRECHARGE 1t
CK
ACTIVE 1t
CK
WRITE
withAUTO
PRECHARGE
(WDMA)
READorREADwithAUTOPRECHARGE [WL+(BL/4)]t
CK
+t
WTR
***
2*t
CK
PRECHARGE 2t
CK
ACTIVE 2t
CK
WRITE
withAUTO
PRECHARGE
(WSMA)
READorREADwithAUTOPRECHARGE [WL+(BL/4)]t
CK
+t
WTR
***
3*t
CK
PRECHARGE 3t
CK
ACTIVE 3t
CK
READ
withAUTO
PRECHARGE
READorREADwithAUTOPRECHARGE 2*t
CK
[CLmrs+(BL/4)+2WL]*t
CK
***
PRECHARGE 1t
CK
ACTIVE 1t
CK
Rev. 1.0 / Nov. 2009 114
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5.19.RDQSMODE
FordeviceoperationatlowerclockfrequenciestheGDDR5SGRAMmaybesetintoRDQSmodeinwhich
aREADDATASTROBE(RDQS)inthestyleofGDDR4willbesentontheEDCpinsalongwiththeREAD
data.ThecontrollerwillusetheRDQStolatchtheREADdata.
RDQSmodeisenteredbysettingtheRDQSModebitA5inModeRegister3(MR3).Whenthebitisset,the
GDDR5SGRAMwillasynchronouslyterminateanyEDCholdpatternanddrivealogicHIGHaftert
MRD
atthelatest.AllfeaturescontrolledbyMR4areignoredbyRDQSmode.
READcommandsareexecutedasinnormalmoderegardingcommandtodataoutdelayandpro
grammedREADlatencies.AfixedclocklikepatternasshowninFigure75isdrivenonEDCpinsinphase
(edgealigned)withtheDQ.Priortothefirstvaliddataelement,thisfixedclocklikepatternorREADpre
ambleisdrivenfor2t
WCK
.
NoCRCiscalculatedinRDQSmode,neitherforREADsnorforWRITEs.TheCRCengineiseffectively
disabled,andthecorrespondingWRCRCandRDCRCModeRegisterbitsareignored.ThePLLmaybeon
oroffwithRDQSmode,dependingonsystemconsiderationsandthePLLsminimumclockfrequency.
ThereisnoequivalentWDQSmode;WRITEcommandstotheGDDR5SGRAMarenotaffectedbyRDQS
mode.
RDQSmodeisexitedbyresettingtheRDQSModebit.InthiscasetheGDDR5SGRAMwillasynchro
nouslystartdrivingtheEDCholdpatternaftert
MRD
.
Rev. 1.0 / Nov. 2009 115
H5GQ1H24AFR
TheWCK2CKtrainingshouldbeperformedpriortoenteringRDQSmode.NoWCK2CKtrainingcanbe
donewhentheRDQSmodeisactive.
Figure 75. RDQS Mode Timings
EDC1andEDC3canbetreatedaspseudodifferentialtoEDC0andEDC2respectively,bysettingthe
EDC13Invfield,bitA11inMR4,asshowninTable34.
Table 33EDCpinbehaviorinRDQSmodeincludingpseudodifferentialRDQS
MRSSet READ/RDTR
NOP
(except
RD/RDTR/
PDN/SRF)
POWER
DOWN/SELF
REFRESH
RDQSMode
WCK2CK
Training
EDC13Invert
EDC02
Output
EDC13
Output
EDC0123
Output
EDC0123
Output
On Off
Off RDQS RDQS 1111 High
On RDQS
Inverted
RDQS
1111 High
CK#
CK
CMD
DQ
NOP MRS
1.MRA=ModeRegisteraddressandopcode;BA=bankaddress;CA=columnaddress
READ
ADDR MRAMRA
NOP NOP NOP NOP MRS NOP NOP
WCK
WCK#
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
EDC
CLmrs
BA CA MRAMRA
t
MRD
EDC
Hold
NOP
t
MRD
EDC
Hold
EnterRDQSMode ExitRDQSMode
T0 T1 Ta0 Ta1 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tc0
DontCare
RCDRD
mustbemet.
4.t
WCK2DQO
WCK2CKPIN
=0,t
WCK2CK
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5.20.CLOCKFREQUENCYCHANGESEQUENCE
Step1)Waituntilallcommandshavefinished,allbanksareidle.
Step2)SendNOPorDESELECT(mustmeetsetup/holdrelativetoclockwhileclockischanging)to
GDDR5SGRAMfortheentiresequenceunlessstatedtodootherwise.Theusermusttakecareofrefresh
requirements.
Step3)IfthenewdesiredclockfrequencyisbelowtheminfrequencysupportedbyPLLonmode,turnthe
PLLoffviaanMRScommand.
Step4)Changetheclockfrequencyandwaituntilclockisstabilized.
Step5)IfthenewclockfrequencyiswithinthePLLonrangeandthePLLonstateisdesired,enablethe
PLLviaanMRSCommandifitisnotalreadyenabled.
Step6)Performaddresstrainingifrequired.
Step7)PerformWCK2CKtraining.AsdefinedintheWCK2CKtrainingprocess,ifthePLLisenabled,
thencompletesteps7aand7b:
7a)ResetthePLLbywritingtotheMRSregister.
7b)Waitt
LK
clockcyclesbeforeissuinganycommandstotheGDDR5SGRAM.
Step8)ExitWCK2CKtraining.
Step9)PerformREADandWRITEtraining,ifrequired.
Step10)GDDR5SGRAMisreadyfornormaloperationafteranynecessaryinterfacetraining.
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5.21.DYNAMICVOLTAGESWITCHING(DVS)
GDDR5SGRAMsallowthesupplyvoltagetobechangedduringthecourseofnormaloperationusingthe
GDDR5DynamicVoltageSwitching(DVS)feature.ByusingDVStheGDDR5SGRAMspowerconsump
tioncanbereducedwheneveronlyafractionofthemaximumavailablebandwidthisrequiredbythecur
rentworkload.
DVSrequirestheGDDR5SGRAMtobeproperlyplacedintoselfrefreshbeforethevoltageischanged
fromtheexisingstablevoltage,V
original
tothenewdesiredvoltageV
new
.TheDVSproceduremayalso
requirechangestotheVDDRangemoderegisterusingMR7bitsA8andA9,dependingonwhetherthe
featureissupported.ThedatasheetshallbeconsultedregardingthesupportedsupplyvoltagesforDVS,
andanydependenciesofACtimingparametersontheselectedsupplyvoltage.
Clockfrequencychangescanalsotakeplacebeforeorafterenteringselfrefreshmodeusingthestandard
ClockFrequencyChangeprocedure.AclockfrequencychangeinconjunctionwithDVSisrequiredift
CK
islessthant
CK
minsupportedbyV
new
.Inthiscasenormaldeviceoperationincludingselfrefreshexitis
notguaranteedwithoutafrequencychange.Changingthefrequencywhileinselfrefreshisthemostsafe
procedure.
Onceselfrefreshisentered,t
CKSRE
mustbemetbeforethesupplyvoltageisallowedtotransitionfrom
V
original
toV
new
.AfterVDDandVDDQarestableatV
new
,t
VS
mustbemettoallowforinternalvoltages
intheGDDR5SGRAMtostabilizebeforeselfrefreshmodemaybeexited.Duringthevoltagetransition
thevoltagemustnotgobelowV
min
ofthelowervoltageofeitherV
original
orV
new
inordertopreventfalse
chipreset.V
min
istheminimumvoltageallowedbyVDDorVDDQintheDCoperatingconditionstable.
VREFshallcontinuetotrackVDDQ.
DVSProcedure
Step1)Completealloperationsandprechargeallbanks.
Step2)IssueanMRScommandtosetVDDRangetopropervaluesforV
new
.ThisstepisonlyrequiredwhentheVDD
RangemoderegisterfieldissupportedbytheGDDR5SGRAM.
Step3)Enterselfrefreshmode.Selfrefreshentryproceduremustbemet.
Step4)Waitrequiredtimet
CKSRE
beforechangingvoltagetoV
new
.
Step5)ChangeVDDandVDDQtoV
new
.
Step6)Waitrequiredtimet
VS
forvoltagestabilization.
Step7)Exitselfrefresh.Theselfrefreshexitproceduremustbemet.
Step8)IssueMRScommandstoadjustmoderegistersettingsasdesired(e.g.latencies,PLLon/off,CRCon/off,RDQS
modeon/off).
Step9)Performanyinterfacetrainingasrequired.
Step10)Continuenormaloperation.
Rev. 1.0 / Nov. 2009 118
H5GQ1H24AFR
Figure 76. DVS Sequence
CK#
CK
CMD SRE NOP
T0 T1 T2 Ta0 Tb2 Tb0 Tb1 Td0
SRX PREA Valid NOP
t
CPDED
CKE#
NOP
t
CKSRE
t
CKSRX
t
RP
Tc0
EnterSelfRefreshMode ExitSelfRefreshMode
t
XSNRW
t
XSRW
t
RDSRE
ort
WRSRE
SelfrefreshexitrequiresWCK2CKtrainingpriortoanyWRITEorREADoperation
AtleastoneREFRESHcommandshallbeissuedaftert
XSNRW
foroutputdriverandterminationimpedanceupdates
NOP
DontCare
Voltageramp
t
VS
VDD,
VDDQ
V
original
V
new
VSS,VSSQ
V
original
>V
new
shownasanexampleofavoltagechange
Rev. 1.0 / Nov. 2009 119
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5.22.TEMPERATURESENSOR
GDDR5SGRAMsincorporateatemperaturesensorwithdigitaltemperaturereadoutfunction.Thisfunc
tionallowsthecontrollertomonitortheGDDR5SGRAMdiesjunctiontemperatureandusethisinforma
tiontomakesurethedeviceisoperatedwithinthespecifiedtemperaturerangeortoadjustinterface
timingsrelativetotemperaturechangesovertime.
ThetemperaturesensorisenabledbybitA6inModeRegister7(MR7).Inthiscasethetemperatureread
outisvalidaftert
TSEN
.Hynixapplies10ustot
TSEN
.
ThetemperaturereadoutusestheDRAMInfomodefeature.Thedigitalvalueisdrivenasynchronously
ontheDQbusfollowingtheMRScommandtoModeRegister3(MR3)thatsetsbitA7to1andbitA6to0.
ThetemperaturereadoutwillbecontinuouslydrivenuntilanMRScommandsetsbothbitsto0.
TheGDDR5SGRAMsjunctiontemperatureislinearlyencodedasshowninTable35.Hynixhastheread
outtoasubsetofsixdigitalcodesoutofTable35,correspondingtosixtemperaturethresholds.
Table 34TemperatureSensorReadoutPattern
Temperature[C]
BinaryTemperatureReadout
MF=0:
MF=1:
DQ[5:0]
DQ[31:26]
45 000000
55 000001
65 000011
75 000111
85 001111
95 011111
95 111111
Rev. 1.0 / Nov. 2009 120
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5.23.DUTYCYCLECORRECTOR(DCC)
AsGDDR5SGRAMscanoperatewiththePLLoffduringnormaloperation,theuseofaDutyCycleCor
rector(DCC)cancorrectforthedutycycleoftheWCK.DCCcanbeusedatanytime,however,risingand
fallingedgesofWCKcanbeshiftedaccordingtotheDCCtype.TheDCCshouldbeenabledbeforeWCK
trainingandshouldberunfort
DCC
inordertoeffectivelycorrectanyerror.
DCCcancorrectthedutycycleerrorwithintherangeof 100ps.
Figure 77. Timing Diagram of DCC Control Signals
DCCcontrolsignals
DCCreset:TheDCCresetisusedtoinitializetheDCCcodeandshouldbeissuedanytimebeforetheWCK
enables(MRS7A11:1,A10:0)
DCCstart:TheDCCstartisusedtoupdatetheDCCcodeandshouldbeissuedanytimeaftertheWCKisstable
(MRS7A11:0,A10:1)
DCCstop:TheDCCstopisusedtomakeitstoptoupdatetheDCCcodewhiletheDCCcodeisheld.Thisshould
beissuedafterenoughtimefromDCCstartifneeds(MRS7A11:0,A10:0)
Table 35DCCTimings
Parameter Symbol Min Max Unit
Requiredtimefordutycyclecorrector t
DCC
150 tCK
Training
PLLReset
DCCstart
DCCstopornot
DCCreset
EnterWCK2CK
Training(resetWCK
dividebycircuits)
EnterWCK2CK
Training(setsdata
synchronizers,resets
FIFOpointers)
WCK#
WCK
CK#
CK
CMD NOP NOP MRS NOP NOP MRS NOP NOP MRS A.C.
t
WCKTMRS t
MRD
t
WCKTTR t
DCC
t
LK
t
MRD
StartWCK2CKPhase
Rev. 1.0 / Nov. 2009 121
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Table 36DCCControlSignals
A11 A10 DCC
0 0 noDCC&DCCstop
0 1 DCCstart
1 0 DCCreset
1 1 RFU
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6.OPERATINGCONDITIONS
6.1.ABSOLUTEMAXIMUMRATINGS
VoltageonVddSupply
RelativetoVss...................................................0.5Vto+2.0V
VoltageonVddQSupply
RelativetoVss..................................................0.5Vto+2.0V
VoltageonVrefandInputs
RelativetoVss..................................................0.5Vto+2.0V
VoltageonI/OPins
RelativetoVss..................................................0.5VtoVddQ+0.5V
StorageTemperature(plastic)............................55Cto+150C
ShortCircuitOutputCurrent.............................50mA
*Stressesgreaterthanthoselistedmaycausepermanentdamagetothedevice.Thisisastressratingonly,andfunctionaloperationof
thedeviceattheseoranyotherconditionsabovethoseindicatedintheoperationalsectionsofthisspecificationisnotimplied.
Exposuretoabsolutemaximumratingconditionsforextendedperiodsmayaffectreliability.
Notes:
1.MeasurementproceduresforeachparametermustfollowstandardproceduresdefinedinthecurrentJEDECJESD51standard.
2.Theta_JAmeasuredwiththelowandhighthermalconductivitytestboarddefinedinJESD519
Table 37Capacitance
PARAMETER SYMBOL MIN MAX UNITS NOTES
DeltaInput/OutputCapacitance:DQs,DBI#,EDC,
WCK,WCK#
DCio 0 0.5 pF
DeltaInputCapacitance:CommandandAddress DCi1 0 0.5 pF
DeltaInputCapacitance:CK,CK# DCi2 0 0.3 pF
Input/OutputCapacitance:DQs,DBI#,EDC,WCK,
WCK#
Cio 1.2 1.9 pF
InputCapacitance:CommandandAddress Ci1 0.9 1.6 pF
InputCapacitance:CK,CK#,WCK,WCK# Ci2 0.9 1.6 pF
InputCapacitance:CKE# Ci3 0.9 1.6 pF
Table 38ThermalCharacteristics
Parameter Description Value Units Notes
Theta_J A
1s
Thermalresistancejunctiontoambient
45
o
C/W 1,2,4,5
33
o
C/W 1,4,5(atTc115
o
C)
2s2p 30
o
C/W 1,2,4,5
Theta_J B Thermalresistancejunctiontoboard 12
o
C/W 1,3
Theta_J C Thermalresistancejunctiontocase 3
o
C/W 1,6
Rev. 1.0 / Nov. 2009 123
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3.Theta_JBmeasuredwiththespecialboundaryconditiondefinedinJESD518
4.Theta_JAshouldonlybeusedforcomparingthethermalperformanceofsinglepackageandnotforsystemrelatedjunction.
5.Theta_JAisthenaturalconvectionjunctiontoambientairthermalresistancemeasuredinonecubicfootsealedenclosure
asdecribedinJESD512.
Theenvironmentissometimesreferedtoasstillairalthoughnaturalconvectioncausestheairtomove.
6.Theta_JCcasesurfaceisdefinedastheoutsidesurfaceofthepackage(case)closesttothechipmountingareawhenthat
samesurfaceisproperlyhearsunksoastominimizetemperaturevariationacrossthatsurface.
Rev. 1.0 / Nov. 2009 124
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6.2.AC&DCCHARACTERISTICS
AllGDDR5SGRAMsaredesignedfor1.5Vtypicalvoltagesupplies.TheinterfaceofGDDR5with1.5V
VDDQwillfollowthePOD15specification.AllACandDCvaluesaremeasuredattheball.
Notes:
1.VDD/VDDQ1.6Visfor6Gbps
2.GDDR5SGRAMsaredesignedtotoleratePCBdesignswithseparateVDDandVDDQpowerregulators.
3.ACnoiseinthesystemisestimatedat50mVpkpkforthepurposeofDRAMdesign.
4.SourceofReferenceVoltageandcontrolofReferenceVoltageforDQandDBI#pinsisdeterminedbyVREFD,HalfVREFD,Auto
VREFD,VREFDMERGEandVREFDOffsetsmoderegisters.
5.VREFDOffsetsarenotsupportedwithVREFD2.
6.ExternalVREFCistobeprovidedbythecontrollerasthereisnootheralternativesupply.
7.DQ/DBI#inputslewratemustbegreaterthanorequalto3V/ns.TheslewrateismeasuredbetweenVREFDcrossingandVIHD(AC)
orVILD(AC)orVREFD2crossingandVIHD2(AC)orVILD2(AC).
8.ADR/CMDinputslewratemustbegreaterthanorequalto3V/ns.TheslewrateismeasuredbetweenVREFCcrossingand
VIHA(AC)orVILA(AC).
9.VIHXandVILXdefinethevoltagelevelsforthereceiverthatdetectsx32orx16modewithRESET#goingHigh.
Table 39DCOperatingConditions
Parameter Symbol Min Typ Max Unit Note
DeviceSupplyVoltage VDD 1.452 1.6 1.648 V 1
OutputSupplyVoltage VDDQ 1.452 1.6 1.648 V 1
DeviceSupplyVoltage VDD 1.455 1.5 1.545 V 2
OutputSupplyVoltage VDDQ 1.455 1.5 1.545 V 2
ReferenceVoltageforDQandDBI#pins VREFD 0.69*VDDQ 0.71*VDDQ V 3,4
ReferenceVoltageforDQandDBI#pins VREFD2 0.49*VDDQ 0.51*VDDQ V 3,4,5
ExternalReferenceVoltageforaddressand
command
VREFC 0.69*VDDQ 0.71*VDDQ V 6
DCInputLogicHIGHVoltageforaddressand
command
VIHA(DC) VREFC+0.15 V
DCInputLogicLOWVoltageforaddressand
command
VILA(DC) VREFC0.15 V
DCInputLogicHIGHVoltageforDQandDBI#
pinswithVREFD
VIHD(DC) VREFD+0.10 V
DCInputLogicLOWVoltageforDQandDBI#
pinswithVREFD
VILD(DC) VREFD0.10 V
DCInputLogicHIGHVoltageforDQandDBI#
pinswithVREFD2
VIHD2
(DC)
VREFD2+0.30 V
DCInputLogicLOWVoltageforDQandDBI#
pinswithVREFD2
VILD2(DC) VREFD20.30 V
InputLogicHIGHVoltageforRESET#,SEN,MF VIHR VDDQ0.50 V
InputLogicLOWVoltageforRESET#,SEN,MF VILR 0.30 V
InputlogicHIGHvoltagefor
EDC1/2(x16modedetect)
VIHX VDDQ0.3 V 9
InputlogicLOWvoltagefor
EDC1/2(x16modedetect)
VILX 0.30 V 9
InputLeakageCurrent
AnyInput0V<=V
IN
<=VDDQ
(Allotherpinsnotundertest=0V)
Il 10 A
OutputLeakageCurrent
(DQsaredisabled;0V<=Vout<=VDDQ)
Ioz 10 A
OutputLogicLOWVoltage VOL(DC) 0.62 V
Rev. 1.0 / Nov. 2009 125
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Figure 78. Voltage Waveform
Table 40ACOperatingConditions
POD15
Parameter Symbol Min Typ Max Unit Note
ACInputLogicHIGHVoltagefor
addressandcommand
VIHA(AC) VREFC+0.20 V
ACInputLogicLOWVoltagefor
addressandcommand
VILA(AC) VREFC0.20 V
DQandDBI#pinswithVREFD
VIHD(AC) VREFD+0.15 V
DQandDBI#pinswithVREFD
VILD(AC) VREFD0.15 V
DQandDBI#pinswithVREFD2
VIHD2(AC) VREFD2+0.40 V
DQandDBI#pinswithVREFD2
VILD2(AC) VREFD20.40 V
VIL(AC)
VIL(DC)
VREFACNoise
VREFDCNoise
VREF+DCNoise
VREF+ACNoise
VIH(DC)
VIH(AC)
VOH
VIN(AC)Providesmargin
betweenVOL(MAX)and
VIL(AC)
VDDQ
VOL(MAX)
SystemNoiseMargin(Power/Ground,
Crosstalk,SignalIntegrityAttenuation)
Note:VREF,VIH,VILreferto
whicheverVREFxx(VREFD,
VREFD2,orVREFC)isbeingused.
Output
Input
Rev. 1.0 / Nov. 2009 126
H5GQ1H24AFR
Notes:
1.Thisprovidesaminimumof0.9Vtoamaximumof1.2V,andisnominally70%ofVDDQwithPOD15.DRAMtimingsrelativeto
CKcannotbeguaranteediftheselimitsareexceeded.
2.ForACoperations,allDCclockrequirementsmustbesatisfiedaswell.
3.ThevalueofVIXCKandVIXWCKisexpectedtoequal70%VDDQforthetransmittingdeviceandmusttrackvariationsintheDC
levelofthesame.
4.VIDCKisthemagnitudeofthedifferencebetweentheinputlevelinCKandtheinputlevelonCK#.Theinputreferencelevelfor
signalsotherthanCKandCK#isVREFC.
5.VIDWCKisthemagnitudeofthedifferencebetweentheinputlevelinWCKandtheinputlevelonWCK#.Theinputreferencelevel
forsignalsotherthanWCKandWCK#iseitherVREFD,VREFD2ortheinternalVREFD.
6.TheCKandCK#inputreferencelevel(fortimingreferencedtoCKandCK#)isthepointatwhichCKandCK#cross.Pleaserefer
totheapplicabletimingsintheACtimingstable(Table44).
7.TheWCKandWCK#inputreferencelevel(fortimingreferencedtoWCKandWCK#)isthepointatwhichWCKandWCK#cross.
PleaserefertotheapplicabletimingsintheACTimingstable(Table44).
8.VREFDiseitherVREFD,VREFD2ortheinternalVREFD.
9.TheslewrateismeasuredbetweenVREFCcrossingandVIXCK(AC).
10.TheslewrateismeasuredbetweenVREFDcrossingandVIXWCK(AC).
11.Figure illustratestheexactrelationshipbetween(CKCK#)or(WCKWCK#)andVID(AC),VID(DC)andtDVAC
12.RingbackbelowVID(DC)isnotallowed.
13.t
DVAC
isnotmeasuredinandofitselfasacompliancespecification,butisrelieduponinmeasurementofclockoperating
conditionsandclockrelatedparameters.
Table 41ClockInputOperatingConditions
POD15
Parameter Symbol Min Max Unit Note
ClockInputMidPointVoltage;CKandCK# VMP(DC) VREFC0.10 VREFC+0.10 V 1,6
ClockInputDifferentialVoltage;CKandCK# VIDCK(DC) 0.22 V 4,6
ClockInputDifferentialVoltage;CKandCK# VIDCK(AC) 0.40 V 2,4,6
ClockInputDifferentialVoltage;WCKandWCK# VIDWCK(DC) 0.20 V 5,7
ClockInputDifferentialVoltage;WCKandWCK# VIDWCK(AC) 0.30 2,5,7
ClockInputVoltageLevel;CK,CK#,WCKandWCK#
singleended
VIN 0.30 VDDQ+0.30
CK/CK#Singleendedslewrate CKslew 3 V/ns 9
WCK/WCK#Singleendedslewrate WCKslew 3 V/ns 10
ClockInputCrossingPointVoltage;CKandCK# VIXCK(AC) VREFC0.12 VREFC+0.12 V 2,3,6
ClockInputCrossingPointVoltage;WCKandWCK# VIXWCK(AC) VREFD0.10 VREFD+0.10 V
2,3,7,
8
AllowedtimebeforeringbackofCK/WCKbelow
VIDCK/WCK(AC)
t
DVAC
ps
11,12,
13
Rev. 1.0 / Nov. 2009 127
H5GQ1H24AFR
Figure 79. Clock Waveform
VIX(AC)
CK#
CK
MaximumClockLevel
MinimumClockLevel
VID(AC)
VID(DC) VMP(DC)
Rev. 1.0 / Nov. 2009 128
H5GQ1H24AFR
Figure 80. Definition of differential ac-swing and time above ac-level t
DVAC
0
V
ID(AC)MIN
tDVAC
t
DVAC
halfcycle
time
D
i
f
f
e
r
e
n
t
i
a
l
I
n
p
u
t
V
o
l
t
a
g
e
(
i
.
e
.
W
C
K
W
C
K
#
,
C
K
C
K
#
)
V
ID(DC)MIN
(V
ID(DC)MIN
)
(V
ID(AC)MIN
)
Rev. 1.0 / Nov. 2009 129
H5GQ1H24AFR
NOTE: Mint
RC
ort
RFC
forIDDmeasurementsisthesmallestmultipleoft
CK
thatmeetstheminimumoftheabsolutevalueforthe
respectiveparameter.
CommonTestconditions:
1) Deviceisconfiguredtox32mode
2) ABIandDBIareenabled
3) AllODTsareenabledwithZQ/2
4) PLLsareenabledunlessotherwisenoted
5) CRCisenabledforREADsandWRITEs,andtheEDCholdpatternisprogrammedto1010
6) Bankgroupsareenabledifrequiredfordeviceoperationatt
CK
(min)
7) AddressinputsincludeABI#pin
8) EachdatabyteconsistsofeightDQsandoneDBI#pin
9) DESELECTconditionduringidlecommandcycles
Table 42IDDSpecificationsandTestConditions
PARAMETER/CONDITION SYMBOL NOTES
OneBankActivatePrechargeCurrent:t
CK
=t
CK
(min);t
WCK
=t
WCK
(min);t
RC
=t
RC
(min);CKE#=
LOW;DQ,DBI#areHIGH;randombankandrowaddresses(4addressinputssetLOW)withACT
command
IDD0 1
OneBankActivateReadPrechargeCurrent:t
CK
=t
CK
(min);t
WCK
=t
WCK
(min);
t
RC
=t
RC
(min);CKE#=LOW;onebankactivated;singlereadburstwith50%datatoggleoneachdata
transfer,with4outputsperdatabytedrivenLOW;otherwiseDQ,DBI#areHIGH;randombank,row
andcolumnaddresses(4addressinputssetLOW)withACTandREADcommands;I
OUT
=0mA
IDD1 1
PrechargePowerdownCurrent:t
CK
=t
CK
(min);t
WCK
=t
WCK
(min);allbanksidle;
CKE#=HIGH;allotherinputsareHIGH;PLLsareoff
IDD2P
PrechargeStandbyCurrent:t
CK
=t
CK
(min);t
WCK
=t
WCK
(min);allbanksidle;
CKE#=LOW;allotherinputsareHIGH
IDD2N
ActivePowerdownCurrent:t
CK
=t
CK
(min);t
WCK
=t
WCK
(min);onebankactive;
CKE#=HIGH;allotherinputsareHIGH
IDD3P
ActiveStandbyCurrent:t
CK
=t
CK
(min);t
WCK
=t
WCK
(min);onebankactive;
CKE#=LOW;allotherinputsareHIGH
IDD3N
ReadBurstCurrent:t
CK
=t
CK
(min);t
WCK
=t
WCK
(min);CKE#=LOW;onebankineachofthe4bank
groupsactivated;continuousreadburstacrossbankgroupswith50%datatoggleoneachdata
transfer,with4outputsperdatabytedrivenLOW;randombankandcolumnaddresses(4address
inputssetLOW)withREADcommand;I
OUT
=0mA
IDD4R
WriteBurstCurrent:t
CK
=t
CK
(min);t
WCK
=t
WCK
(min);CKE#=LOW;onebankineachofthe4bank
groupsactivated;continuouswriteburstacrossbankgroupswith50%datatoggleoneachdata
transfer,with4inputsperdatabytesetLOW;randombankandcolumnaddresses(4addressinputs
setLOW)withWRITEcommand;nodatamask
IDD4W
RefreshCurrent:t
CK
=t
CK
(min);t
WCK
=t
WCK
(min);t
RFC
=t
RFC
(min);CKE#=LOW;
DQ,DBI#areHIGH;addressinputsareHIGH
IDD5 1
SelfRefreshCurrent:CKE#=HIGH;allotherinputsareHIGH IDD6
FourBankInterleaveReadCurrent:t
CK
=t
CK
(min);t
WCK
=t
WCK
(min);CKE#=LOW;
onebankineachofthe4bankgroupsactivatedandprechargedatt
RC
(min);continuousreadburst
acrossbankgroupswith50%datatoggleoneachdatatransfer,with4outputsperdatabytedriven
LOW;randombank,rowandcolumnaddresses(4addressinputssetLOW)withACTandREAD/
READAcommands;I
OUT
=0mA
IDD7
Rev. 1.0 / Nov. 2009 130
H5GQ1H24AFR
Table 43. IDD SPECIFICATIONS AND CONDITIONS
Symbol 4.0Gbps 4.5Gbps 5.0Gbps 5.5Gbps 6.0Gbps Units
IDD0 550 590 630 670 710 mA
IDD1 590 630 670 710 750 mA
IDD2P 240 260 280 300 320 mA
IDD2N 260 280 300 320 340 mA
IDD3P 385 405 425 445 465 mA
IDD3N 540 580 620 660 700 mA
IDD4W 1300 1430 1560 1690 1820 mA
IDD4R 1370 1500 1630 1760 1890 mA
IDD5 545 580 615 650 685 mA
IDD6 60 60 60 60 60 mA
IDD7 900 1000 1100 1200 1300 mA
Symbol 4.0Gbps 4.5Gbps 5.0Gbps 5.5Gbps 6.0Gbps Units
IDD0 370 400 420 450 490 mA
IDD1 390 420 450 480 520 mA
IDD2P 170 175 185 195 210 mA
IDD2N 190 200 210 230 250 mA
IDD3P 250 260 275 290 310 mA
IDD3N 350 370 390 420 450 mA
IDD4W 830 910 990 1070 1160 mA
IDD4R 850 930 1010 1090 1080 mA
IDD5 350 370 390 420 450 mA
IDD6 60 60 60 60 60 mA
IDD7 660 710 770 840 910 mA
1. 32 Mode IDD
2. 16 Mode IDD
Rev. 1.0 / Nov. 2009 131
H5GQ1H24AFR
PARAMETER a, b SYMBOL
6.0Gbps 5.5Gbps
UNIT NOTES
MIN MAX MIN MAX
CK and WCK Timings
CK Clock cycle time
PLL on
tCK
0.667 2 0.727 2
ns
PLL off 0.667 20 0.727 20
CK Clock high-level width tCH 0.470 0.530 0.470 0.530 tCK C
CK Clock low-level width tCL 0.470 0.530 0.470 0.530 tCK C
Min CK Clock half period tHP 0.470 - 0.470 - tCK
Max CK Clock frequency with bank groups disabled fCKBG - 1500 - 1375 MHz d
Max CK Clock frequency with bank groups enabled
and tCCDL=3tCK
fCKBG4 - 1500 - 1375 MHz d
Max CK Clock frequency with WCK2CK alignment
at pins
fCKPIN - 1500 - 1375 MHz e
Max CK Clock frequency in RDQS Mode fCKRDQS - TBD - TBD MHz f
Max CK Clock frequency for device operation with
VREFD2
fCKVREFD2 - TBD - TBD MHz g
Max CK Clock frequency for WCK-to-CK
auto synchronization in WCK2CK training mode
fCKAUTOSYNC - 1500 - 1375 MHz h
Low Frequency Mode enabled
fCKLF - 900 - 900 MHz i
WCK Clock cycle time
PLL on
tWCK
0.333 1 0.364 1
ns j
PLL off 0.333 10 0.364 10
WCK Clock high-level width tWCKH 0.470 0.530 0.470 0.530 tWCK k,l
WCK Clock low-level width tWCKL 0.470 0.530 0.470 0.530 tWCK k,l
Min WCK Clock half period tWCKHP 0.470 - 0.470 - tWCK
Command and Address Input Timings
Command input setup time tCMDS 0.25 - 0.25 - ns m,n
Command input hold time tCMDH 0.25 - 0.25 - ns m,n
Command input pulse width tCMDPW 0.60 - 0.65 - ns m,n,o
Address input setup time tAS 0.1 - 0.1 - ns m,n,p
Address input hold time tAH 0.1 - 0.1 - ns m,n,p
Address input pulsewidth tAPW 0.3 - 0.32 - ns m,n,o,p
Table 44. AC Timings (@1.5V)
Rev. 1.0 / Nov. 2009 132
H5GQ1H24AFR
6.0Gbps 5.5Gbps
UNIT NOTES
MIN MAX MIN MAX
WCK2CK Timings
WCK stop to MRS delay for entering WCK2CK
training
tWCK2MRS 3 - 3 - ns
MRS to WCK restart delay after entering WCK2CK
training
tMRSTWCK 10 - 10 - ns q
WCK start to WCK phase movement delay tWCK2TR 10 - 10 - tCK
WCK phase change to phase detector out delay tWCK2PH 5 - 5 - ns
WCK Clock high-level width during WCK2CK
training
tWCKHTR 0.42 0.58 0.42 0.58 tWCK k,l,r
WCK Clock low-level width during WCK2CK
training
tWCKLTR 0.42 0.58 0.42 0.58 tWCK k,l,r
WCK2CK offset when zero
offset at phase detector or at
pins
PLL on;MR6A0=0
(at phasedetector)
tWCK2CKPIN
-0.2 0.2 -0.2 0.2
ns s
PLL on;MR6A0=1
(at pins)
-0.2 0.2 -0.2 0.2
PLL off;MR6A0=0
(at phasedetector)
-0.2 0.2 -0.2 0.2
PLL off;MR6A0=1
(at pins)
-0.2 0.2 -0.2 0.2
WCK2CK phase offset upon
WCK2CK training exit
MR6A0=0
(at phasedetector)
tWCK2CKSYNC
-0.25 0.25 -0.25 0.25 tCK
t
MR6A0=1
(at pins)
-0.25 0.25 -0.25 0.25 ns
WCK2CK phase offset
MR6A0=0
(at phasedetector)
tWCK2CK
-0.4 0.4 -0.4 0.4 tCK
u
MR6A0=1
(at pins)
-0.4 0.4 -0.4 0.4 ns
PLL Input and Output Timings
WCK to DQ/DBI#offset for
input data
PLL on
tWCK2DQI
0.7 1.7 0.7 1.7
ns v
PLL off 0.7 1.7 0.7 1.7
WCK to DQ/DBI#/EDC/
offset for output data
PLL on
tWCK2DQO
1.1 2.2 1.1 2.2
ns w,x
PLL off 1.1 2.2 1.1 2.2
DQ/DBI#input pulse width tDIPW 0.15 - 0.164 - ns y,z,aa
Rev. 1.0 / Nov. 2009 133
H5GQ1H24AFR
6.0Gbps 5.5Gbps
UNIT NOTES
MIN MAX MIN MAX
DQ/DBI#data input valid
window
PLL on
tDIVW
0.1 - 0.11 -
ns y,z,ab
PLL off 0.1 - 0.11 -
DQ/DBI#input skew within double byte tDQDQI -0.1 0.1 -0.1 0.1 ns ac
DQ/DBI#/EDC output skew within double byte tDQDQO -0.125 0.125 -0.125 0.125 ns ad
Row Access Timings
Active to Active command period tRC 40 - 40 - ns
Active to PRECHARGE command period tRAS 28 9*tREFI 28 9*tREFI ns ae
Active to READ command delay tRCDRD 12 - 12 - ns
Active to WRITE command delay tRCDWR 10 - 10 - ns
Active to RDTR command delay tRCDRTR 10 - 10 - ns
Active to WRTR command delay tRCDWTR 10 - 10 - ns
Active to LDFF command delay tRCDLTR 10 - 10 - ns
REFRESH to RDTR or WRTR command delay tREFTR 10 - 10 - ns
Active bank A to Active bank B command delay same
bank group
tRRDL 5.5 - 5.5 - ns af
Active bank A to Active bank B command delay
different bank groups
tRRDS 5.5 - 5.5 - ns ag
Four bank activate window tFAW 23 - 23 - ns ah
Thirty two bank activate window t32AW 184 - 184 - ns ai
READ to PRECHARGE command delay same bank
with bank groups enabled
tRTPL 2 - 2 - tCK aj
with bank groups disabled
tRTPS 2 - 2 - tCK ak
PRECHARGE to PRECHARGE command delay tPPD 1 - 1 - ns
PRECHARGE command period tRP 12 - 12 - ns
WRITE recovery time tWR 12 - 12 - ns
Auto precharge write recovery +precharge time tDAL 24 - 24 - tCK al
Column Access Timings
RD/WR bank A to RD/WR bank B command delay
same bank group
tCCDL 3 - 3 - tCK af,am
tCCDS 2 - 2 - tCK ag,an
Rev. 1.0 / Nov. 2009 134
H5GQ1H24AFR
6.0Gbps 5.5Gbps
UNIT NOTES
MIN MAX MIN MAX
LDFF to LDFF command cycle time tLTLTR 4 - 4 - tCK
LDFF(111) to LDFF command cycle time tLTL7TR 4 - 4 - tCK ao
LDFF(111) to RDTR command cycle delay tLTRTR 4 - 4 - tCK
READ or RDTR to LDFF command delay tRDTLT 4 - 4 - tCK
WRITE to LDFF command delay tWRTLT WL+5 - WL+5 - tCK
WRTR to RDTR command delay tWTRTR
WL-
tWLmin
-
WL-
tWLmin
- tCK
WRITE to WRTR command delay tWRWTR
WL+tCR
CWL+2
-
WL+tCR
CWL+2
- tCK
Internal WRITE to READ command delay same bank
group
tWTRL 5 - 5 - ns af
Internal WRITE to READ command delay different
bank groups
tWTRS 5 - 5 - ns ag
READ or RDTR to WRITE or WRTR command
delay
tRTW
[CLmrs+(BL
/4)+2-
WLmrs]*tC
K
-
[CLmrs+(BL
/4)+2-
WLmrs]*tC
K
- tCK ap
Write Latency tWL 4 7 4 7 tCK aq
Power-Down and Refresh Timings
CKE#min high and low pulse width tCKE 16 - 14 - tCK
Valid CK Clock required after self refresh entry tCKSRE 16 - 14 - tCK
Valid CK Clock required before self refresh exit tCKSRX 16 - 14 - tCK
READ to SELF REFRESH ENTRY or POWER
DOWN ENTRY command delay
tRDSRE CL+2tCK - CL+2tCK - tCK ar
WRITE to SELF REFRESH ENTRY or POWER
tWRSRE TBD - TBD - tCK as
REFRESH command period tRFC 65 - 65 - ns
Exit self refresh to non-READ/WRITE command
delay
tXSNRW tRFC - tRFC - ns
Exit self refresh to READ/WRITE command delay tXSRW
tRFC+
tRCD
-
tRFC+
tRCD
- tCK at
Refresh period tREF - 32 - 32 ms
Average periodic refresh
interval
8k rows
tREFI
- 3.9 - 3.9
us au
16k rows - 1.9 - 1.9
Min Power down entry to exit time tPD 16 14 tCK
Rev. 1.0 / Nov. 2009 135
H5GQ1H24AFR
6.0Gbps 5.5Gbps
UNIT NOTES
MIN MAX MIN MAX
NOP/DESELECT commands required upon power-
down and self refresh entry
tCPDED 4 - 3 - tCK
Power down exit time tXPN 17 - 15 - tCK
Miscellaneous Timings
MODE REGISTER SET command period tMRD 4 - 4 - tCK
PLL enabled to PLL lock delay tLK - 5000 - 5000 tCK
PLL standby time tSTDBTY - TBD - TBD us ax
DVS voltage stabilization time tVS TBD - TBD - us
REFRESH to calibration update complete delay tKO - 40 - 40 ns
Active termination setup time tATS 10 - 10 - ns
Active termination hold time tATH 10 - 10 - ns
READ to data out delay in address training mode tADR
0.5*tCK+
0
0.5*tCK+
10
0.5*tCK+
0
0.5*tCK+
10
tCK q
Address training exit to DQ in ODT state delay tADZ -
0.5*tCK+
10
-
0.5*tCK+
10
ns
Vendor ID on tWRIDON - 11 - 11 ns
Venodr ID off tWRIDOFF - 11 - 11 ns
Temperature sensor enable delay tTSEN 10 - 10 - us
Rev. 1.0 / Nov. 2009 136
H5GQ1H24AFR
5.0Gbps 4.5Gbps
UNIT NOTES
MIN MAX MIN MAX
CK and WCK Timings
CK Clock cycle time
PLL on
tCK
0.8 2 0.89 2
ns
PLL off 0.8 20 0.89 20
CK Clock high-level width tCH 0.470 0.530 0.470 0.530 tCK C
CK Clock low-level width tCL 0.470 0.530 0.470 0.530 tCK C
Min CK Clock half period tHP 0.470 - 0.470 - tCK
Max CK Clock frequency with bank groups disabled fCKBG - 1250 - 1125 MHz d
and tCCDL=3tCK
fCKBG4 - 1250 - 1125 MHz d
at pins
fCKPIN - 1250 - 1125 MHz e
Max CK Clock frequency in RDQS Mode fCKRDQS - TBD - TBD MHz f
VREFD2
fCKVREFD2 - TBD - TBD MHz g
fCKAUTOSYNC - 1250 - 1125 MHz h
fCKLF - 900 - 900 MHz i
PLL on
tWCK
0.4 1 0.444 1
ns j
PLL off 0.4 10 0.444 10
WCK Clock high-level width tWCKH 0.470 0.530 0.470 0.530 tWCK k,l
WCK Clock low-level width tWCKL 0.470 0.530 0.470 0.530 tWCK k,l
Min WCK Clock half period tWCKHP 0.470 - 0.470 - tWCK
Command input setup time tCMDS 0.25 - 0.25 - ns m,n
Command input hold time tCMDH 0.25 - 0.25 - ns m,n
Command input pulsewidth tCMDPW 0.7 - 0.7 - ns m,n,o
Address input setup time tAS 0.1 - 0.125 - ns m,n,p
Address input hold time tAH 0.1 - 0.125 - ns m,n,p
Address input pulsewidth tAPW 0.36 - 0.4 - ns m,n,o,p
Rev. 1.0 / Nov. 2009 137
H5GQ1H24AFR
5.0Gbps 4.5Gbps
UNIT NOTES
MIN MAX MIN MAX
WCK2CK Timings
training
tWCK2MRS 3 - 3 - ns
training
tMRSTWCK 10 - 10 - ns q
WCK start to WCK phase movement delay tWCK2TR 10 - 10 - tCK
WCK phase change to phase detector out delay tWCK2PH 5 - 5 - ns
training
tWCKHTR 0.42 0.58 0.42 0.58 tWCK k,l,r
training
tWCKLTR 0.42 0.58 0.42 0.58 tWCK k,l,r
pins
PLL on;MR6A0=0
(at phasedetector)
tWCK2CKPIN
-0.2 0.2 -0.2 0.2
ns s
PLL on;MR6A0=1
(at pins)
-0.2 0.2 -0.2 0.2
PLL off;MR6A0=0
(at phasedetector)
-0.2 0.2 -0.2 0.2
PLL off;MR6A0=1
(at pins)
-0.2 0.2 -0.2 0.2
MR6A0=0
(at phasedetector)
tWCK2CKSYNC
-0.25 0.25 -0.25 0.25 tCK
t
MR6A0=1
(at pins)
-0.25 0.25 -0.25 0.25 ns
WCK2CK phase offset
MR6A0=0
(at phasedetector)
tWCK2CK
-0.4 0.4 -0.4 0.4 tCK
u
MR6A0=1
(at pins)
-0.4 0.4 -0.4 0.4 ns
input data
PLL on
tWCK2DQI
0.7 1.7 0.7 1.7
ns v
PLL off 0.7 1.7 0.7 1.7
WCK to DQ/DBI#/EDC/
PLL on
tWCK2DQO
1.1 2.2 1.1 2.2
ns w,x
PLL off 1.1 2.2 1.1 2.2
DQ/DBI#input pulse width tDIPW 0.18 - 0.197 - ns y,z,aa
Rev. 1.0 / Nov. 2009 138
H5GQ1H24AFR
5.0Gbps 4.5Gbps
UNIT NOTES
MIN MAX MIN MAX
window
PLL on
tDIVW
0.12 - 0.13 -
ns y,z,ab
PLL off 0.12 - 0.13 -
DQ/DBI#input skew within double byte tDQDQI -0.1 0.1 -0.1 0.1 ns ac
DQ/DBI#/EDC output skew within double byte tDQDQO -0.125 0.125 -0.125 0.125 ns ad
Row Access Timings
Active to Active command period tRC 40 - 40 - ns
Active to PRECHARGE command period tRAS 28 9*tREFI 28 9*tREFI ns ae
Active to READ command delay tRCDRD 12 - 12 - ns
Active to WRITE command delay tRCDWR 10 - 10 - ns
Active to RDTR command delay tRCDRTR 10 - 10 - ns
Active to WRTR command delay tRCDWTR 10 - 10 - ns
Active to LDFF command delay tRCDLTR 10 - 10 - ns
REFRESH to RDTR or WRTR command delay tREFTR 10 - 10 - ns
bank group
tRRDL 5.5 - 5.5 - ns af
tRRDS 5.5 - 5.5 - ns ag
Four bank activate window tFAW 23 - 23 - ns ah
Thirty two bank activate window t32AW 184 - 184 - ns ai
tRTPL 2 - 2 - tCK aj
tRTPS 2 - 2 - tCK ak
PRECHARGE to PRECHARGE command delay tPPD 1 - 1 - ns
PRECHARGE command period tRP 12 - 12 - ns
WRITE recovery time tWR 12 - 12 - ns
Auto precharge write recovery +precharge time tDAL 24 - 24 - tCK al
same bank group
tCCDL 3 - 3 - tCK af,am
tCCDS 2 - 2 - tCK ag,an
Rev. 1.0 / Nov. 2009 139
H5GQ1H24AFR
5.0Gbps 4.5Gbps
UNIT NOTES
MIN MAX MIN MAX
LDFF to LDFF command cycle time tLTLTR 4 - 4 - tCK
LDFF(111) to LDFF command cycle time tLTL7TR 4 - 4 - tCK ao
LDFF(111) to RDTR command cycle delay tLTRTR 4 - 4 - tCK
READ or RDTR to LDFF command delay tRDTLT 4 - 4 - tCK
WRITE to LDFF command delay tWRTLT WL+5 - WL+5 - tCK
WL-
tWLmin
-
WL-
tWLmin
- tCK
WL+tCR
CWL+2
-
WL+tCR
CWL+2
- tCK
group
tWTRL 5 - 5 - ns af
bank groups
tWTRS 5 - 5 - ns ag
delay
tRTW
[CLmrs+(BL
/4)+2-
WLmrs]*tC
K
-
[CLmrs+(BL
/4)+2-
WLmrs]*tC
K
- tCK ap
Write Latency tWL 3 7 3 7 tCK aq
CKE#min high and low pulse width tCKE 12 - 11 - tCK
Valid CK Clock required after self refresh entry tCKSRE 12 - 11 - tCK
Valid CK Clock required before self refresh exit tCKSRX 12 - 11 - tCK
tRDSRE CL+2tCK - CL+2tCK - tCK ar
tWRSRE TBD - TBD - tCK as
REFRESH command period tRFC 65 - 65 - ns
delay
tXSNRW tRFC - tRFC - ns
tRFC+
tRCD
-
tRFC+
tRCD
- tCK at
Refresh period tREF - 32 - 32 ms
interval
8k rows
tREFI
- 3.9 - 3.9
us au
16k rows - 1.9 - 1.9
Min Power down entry to exit time tPD 12 11 tCK
Rev. 1.0 / Nov. 2009 140
H5GQ1H24AFR
5.0Gbps 4.5Gbps
UNIT NOTES
MIN MAX MIN MAX
tCPDED 3 - 3 - tCK
Power down exit time tXPN 13 - 11 - tCK
MODE REGISTER SET command period tMRD 4 - 4 - tCK
PLL enabled to PLL lock delay tLK - 5000 - 5000 tCK
PLL standby time tSTDBTY - TBD - TBD us ax
DVS voltage stabilization time tVS TBD - TBD - us
REFRESH to calibration update complete delay tKO - 40 - 40 ns
Active termination setup time tATS 10 - 10 - ns
Active termination hold time tATH 10 - 10 - ns
0.5*tCK+
0
0.5*tCK+
10
0.5*tCK+
0
0.5*tCK+
10
tCK q
0.5*tCK+
10
-
0.5*tCK+
10
ns
Vendor ID on tWRIDON - 11 - 11 ns
Venodr ID off tWRIDOFF - 11 - 11 ns
Temperature sensor enable delay tTSEN 10 - 10 - us
Rev. 1.0 / Nov. 2009 141
H5GQ1H24AFR
4.0Gbps -
UNIT NOTES
MIN MAX MIN MAX
CK and WCK Timings
CK Clock cycle time
PLL on
tCK
1 2
ns
PLL off 1 20
CK Clock high-level width tCH 0.470 0.530 tCK C
CK Clock low-level width tCL 0.470 0.530 tCK C
Min CK Clock half period tHP 0.470 - tCK
Max CK Clock frequency with bank groups disabled fCKBG - 1000 MHz d
and tCCDL=3tCK
fCKBG4 - 1000 MHz d
at pins
fCKPIN - 1000 MHz e
Max CK Clock frequency in RDQS Mode fCKRDQS - TBD MHz f
VREFD2
fCKVREFD2 - TBD MHz g
fCKAUTOSYNC - 100 MHz h
fCKLF - 800 MHz i
PLL on
tWCK
0.5 1
ns j
PLL off 0.5 10
WCK Clock high-level width tWCKH 0.470 0.530 tWCK k,l
WCK Clock low-level width tWCKL 0.470 0.530 tWCK k,l
Min WCK Clock half period tWCKHP 0.470 - tWCK
Command input setup time tCMDS 0.25 - ns m,n
Command input hold time tCMDH 0.25 - ns m,n
Command input pulsewidth tCMDPW 0.7 - ns m,n,o
Address input setup time tAS 0.125 - ns m,n,p
Address input hold time tAH 0.125 - ns m,n,p
Address input pulsewidth tAPW 0.45 - ns m,n,o,p
Rev. 1.0 / Nov. 2009 142
H5GQ1H24AFR
4.0Gbps -
UNIT NOTES
MIN MAX MIN MAX
WCK2CK Timings
training
tWCK2MRS 3 - ns
training
tMRSTWCK 10 - ns q
WCK start to WCK phase movement delay tWCK2TR 10 - tCK
WCK phase change to phase detector out delay tWCK2PH 5 - ns
training
tWCKHTR 0.42 0.58 tWCK k,l,r
training
tWCKLTR 0.42 0.58 tWCK k,l,r
pins
PLL on;MR6A0=0
(at phasedetector)
tWCK2CKPIN
-0.2 0.2
ns s
PLL on;MR6A0=1
(at pins)
-0.2 0.2
PLL off;MR6A0=0
(at phasedetector)
-0.2 0.2
PLL off;MR6A0=1
(at pins)
-0.2 0.2
MR6A0=0
(at phasedetector)
tWCK2CKSYNC
-0.25 0.25 tCK
t
MR6A0=1
(at pins)
-0.25 0.25 ns
WCK2CK phase offset
MR6A0=0
(at phasedetector)
tWCK2CK
-0.4 0.4 tCK
u
MR6A0=1
(at pins)
-0.4 0.4 ns
input data
PLL on
tWCK2DQI
0.7 1.7
ns v
PLL off 0.7 1.7
WCK to DQ/DBI#/EDC/
PLL on
tWCK2DQO
1.1 2.2
ns w,x
PLL off 1.1 2.2
DQ/DBI#input pulse width tDIPW 0.225 - ns y,z,aa
Rev. 1.0 / Nov. 2009 143
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4.0Gbps -
UNIT NOTES
MIN MAX MIN MAX
window
PLL on
tDIVW
0.15 -
ns y,z,ab
PLL off 0.15 -
DQ/DBI#input skew within double byte tDQDQI -0.1 0.1 ns ac
DQ/DBI#/EDC output skew within double byte tDQDQO -0.125 0.125 ns ad
Row Access Timings
Active to Active command period tRC 40 - ns
Active to PRECHARGE command period tRAS 28 9*tREFI ns ae
Active to READ command delay tRCDRD 12 - ns
Active to WRITE command delay tRCDWR 10 - ns
Active to RDTR command delay tRCDRTR 10 - ns
Active to WRTR command delay tRCDWTR 10 - ns
Active to LDFF command delay tRCDLTR 10 - ns
REFRESH to RDTR or WRTR command delay tREFTR 10 - ns
bank group
tRRDL 5.5 - ns af
tRRDS 5.5 - ns ag
Four bank activate window tFAW 23 - ns ah
Thirty two bank activate window t32AW 184 - ns ai
tRTPL 2 - tCK aj
tRTPS 2 - tCK ak
PRECHARGE to PRECHARGE command delay tPPD 1 - ns
PRECHARGE command period tRP 12 - ns
WRITE recovery time tWR 12 - ns
Auto precharge write recovery +precharge time tDAL 24 - tCK al
same bank group
tCCDL 3 - tCK af,am
tCCDS 2 - tCK ag,an
Rev. 1.0 / Nov. 2009 144
H5GQ1H24AFR
4.0Gbps -
UNIT NOTES
MIN MAX MIN MAX
LDFF to LDFF command cycle time tLTLTR 4 - tCK
LDFF(111) to LDFF command cycle time tLTL7TR 4 - tCK ao
LDFF(111) to RDTR command cycle delay tLTRTR 4 - tCK
READ or RDTR to LDFF command delay tRDTLT 4 - tCK
WRITE to LDFF command delay tWRTLT WL+5 - tCK
WL-
tWLmin
- tCK
WL+tCR
CWL+2
- tCK
group
tWTRL 5 - ns af
bank groups
tWTRS 5 - ns ag
delay
tRTW
[CLmrs+(BL
/4)+2-
WLmrs]*tC
K
- tCK ap
Write Latency tWL 3 7 tCK aq
CKE#min high and low pulse width tCKE 10 - tCK
Valid CK Clock required after self refresh entry tCKSRE 10 - tCK
Valid CK Clock required before self refresh exit tCKSRX 10 - tCK
tRDSRE CL+2tCK - tCK ar
tWRSRE TBD - tCK as
REFRESH command period tRFC 65 - ns
delay
tXSNRW tRFC - ns
tRFC+
tRCD
- tCK at
Refresh period tREF - 32 ms
interval
8k rows
tREFI
- 3.9
us au
16k rows - 1.9
Min Power down entry to exit time tPD 10 tCK
Rev. 1.0 / Nov. 2009 145
H5GQ1H24AFR
4.0Gbps -
UNIT NOTES
MIN MAX MIN MAX
tCPDED 2 - tCK
Power down exit time tXPN 10 - tCK
MODE REGISTER SET command period tMRD 4 - tCK
PLL enabled to PLL lock delay tLK - 5000 tCK
PLL standby time tSTDBTY - TBD us ax
DVS voltage stabilization time tVS TBD - us
REFRESH to calibration update complete delay tKO - 40 ns
Active termination setup time tATS 10 - ns
Active termination hold time tATH 10 - ns
0.5*tCK+
0
0.5*tCK+
10
tCK q
0.5*tCK+
10
ns
Vendor ID on tWRIDON - 11 ns
Venodr ID off tWRIDOFF - 11 ns
Temperature sensor enable delay tTSEN 10 - us
Rev. 1.0/ Nov. 2009 146
H5GQ1H24AFR
3.2Gbps -
UNIT NOTES
MIN MAX MIN MAX
CK and WCK Timings
CK Clock cycle time
PLL on
tCK
1.25 2
ns
PLL off 1.25 20
CK Clock high-level width tCH 0.470 0.530 tCK C
CK Clock low-level width tCL 0.470 0.530 tCK C
Min CK Clock half period tHP 0.470 - tCK
Max CK Clock frequency with bank groups disabled fCKBG - 800 MHz d
and tCCDL=3tCK
fCKBG4 - 800 MHz d
at pins
fCKPIN - 800 MHz e
Max CK Clock frequency in RDQS Mode fCKRDQS - TBD MHz f
VREFD2
fCKVREFD2 - TBD MHz g
fCKAUTOSYNC - 800 MHz h
fCKLF - 700 MHz i
PLL on
tWCK
0.625 1
ns j
PLL off 0.625 10
WCK Clock high-level width tWCKH 0.470 0.530 tWCK k,l
WCK Clock low-level width tWCKL 0.470 0.530 tWCK k,l
Min WCK Clock half period tWCKHP 0.470 - tWCK
Command input setup time tCMDS 0.3 - ns m,n
Command input hold time tCMDH 0.3 - ns m,n
Command input pulsewidth tCMDPW 1.0 - ns m,n,o
Address input setup time tAS 0.15 - ns m,n,p
Address input hold time tAH 0.15 - ns m,n,p
Address input pulsewidth tAPW 0.55 - ns m,n,o,p
Rev. 1.0/ Nov. 2009 147
H5GQ1H24AFR
3.2Gbps -
UNIT NOTES
MIN MAX MIN MAX
WCK2CK Timings
training
tWCK2MRS 3 - ns
training
tMRSTWCK 10 - ns q
WCK start to WCK phase movement delay tWCK2TR 10 - tCK
WCK phase change to phase detector out delay tWCK2PH 5 - ns
training
tWCKHTR 0.42 0.58 tWCK k,l,r
training
tWCKLTR 0.42 0.58 tWCK k,l,r
pins
PLL on;MR6A0=0
(at phasedetector)
tWCK2CKPIN
-0.2 0.2
ns s
PLL on;MR6A0=1
(at pins)
-0.2 0.2
PLL off;MR6A0=0
(at phasedetector)
-0.2 0.2
PLL off;MR6A0=1
(at pins)
-0.2 0.2
MR6A0=0
(at phasedetector)
tWCK2CKSYNC
-0.25 0.25 tCK
t
MR6A0=1
(at pins)
-0.25 0.25 ns
WCK2CK phase offset
MR6A0=0
(at phasedetector)
tWCK2CK
-0.4 0.4 tCK
u
MR6A0=1
(at pins)
-0.4 0.4 ns
input data
PLL on
tWCK2DQI
0.7 1.7
ns v
PLL off 0.7 1.7
WCK to DQ/DBI#/EDC/
PLL on
tWCK2DQO
1.1 2.2
ns w,x
PLL off 1.1 2.2
DQ/DBI#input pulse width tDIPW 0.295 - ns y,z,aa
Rev. 1.0/ Nov. 2009 148
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3.2Gbps -
UNIT NOTES
MIN MAX MIN MAX
window
PLL on
tDIVW
0.19 -
ns y,z,ab
PLL off 0.19 -
DQ/DBI#input skew within double byte tDQDQI -0.1 0.1 ns ac
DQ/DBI#/EDC output skew within double byte tDQDQO -0.125 0.125 ns ad
Row Access Timings
Active to Active command period tRC 48 - ns
Active to PRECHARGE command period tRAS 32 9*tREFI ns ae
Active to READ command delay tRCDRD 16 - ns
Active to WRITE command delay tRCDWR 14 - ns
Active to RDTR command delay tRCDRTR 16 - ns
Active to WRTR command delay tRCDWTR 14 - ns
Active to LDFF command delay tRCDLTR 14 - ns
REFRESH to RDTR or WRTR command delay tREFTR 14 - ns
bank group
tRRDL 12 - ns af
tRRDS 7 - ns ag
Four bank activate window tFAW 30 - ns ah
Thirty two bank activate window t32AW 245 - ns ai
tRTPL 2 - tCK aj
tRTPS 2 - tCK ak
PRECHARGE to PRECHARGE command delay tPPD 1 - ns
PRECHARGE command period tRP 16 - ns
WRITE recovery time tWR 16 - ns
Auto precharge write recovery +precharge time tDAL 32 - tCK al
same bank group
tCCDL 3 - tCK af,am
tCCDS 2 - tCK ag,an
Rev. 1.0/ Nov. 2009 149
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3.2Gbps -
UNIT NOTES
MIN MAX MIN MAX
LDFF to LDFF command cycle time tLTLTR 4 - tCK
LDFF(111) to LDFF command cycle time tLTL7TR 4 - tCK ao
LDFF(111) to RDTR command cycle delay tLTRTR 4 - tCK
READ or RDTR to LDFF command delay tRDTLT 4 - tCK
WRITE to LDFF command delay tWRTLT WL+5 - tCK
WL-
tWLmin
- tCK
WL+tCR
CWL+2
- tCK
group
tWTRL 5 - ns af
bank groups
tWTRS 5 - ns ag
delay
tRTW
[CLmrs+(BL
/4)+2-
WLmrs]*tC
K
- tCK ap
Write Latency tWL 3 7 tCK aq
CKE#min high and low pulse width tCKE 11 - tCK
Valid CK Clock required after self refresh entry tCKSRE 11 - tCK
Valid CK Clock required before self refresh exit tCKSRX 11 - tCK
tRDSRE CL+2tCK - tCK ar
tWRSRE TBD - tCK as
REFRESH command period tRFC 120 - ns
delay
tXSNRW tRFC - ns
tRFC+
tRCD
- tCK at
Refresh period tREF - 32 ms
interval
8k rows
tREFI
- 3.9
us au
16k rows - 1.9
Min Power down entry to exit time tPD 11 tCK
Rev. 1.0/ Nov. 2009 150
H5GQ1H24AFR
3.2Gbps -
UNIT NOTES
MIN MAX MIN MAX
tCPDED 2 - tCK
Power down exit time tXPN 10 - tCK
MODE REGISTER SET command period tMRD 4 - tCK
PLL enabled to PLL lock delay tLK - 5000 tCK
PLL standby time tSTDBTY - TBD us ax
DVS voltage stabilization time tVS TBD - us
REFRESH to calibration update complete delay tKO - 40 ns
Active termination setup time tATS 10 - ns
Active termination hold time tATH 10 - ns
0.5*tCK+
0
0.5*tCK+
10
tCK q
0.5*tCK+
10
ns
Vendor ID on tWRIDON - 11 ns
Venodr ID off tWRIDOFF - 11 ns
Temperature sensor enable delay tTSEN 10 - us
a. All parameters assume proper device initialization.
b. Tests for AC timing may be considered at norminal supply voltage levels, but the related specification and device operation are guaranteed for the full
voltage and temperature range specified.
c. CK and CK#single-ended input slew rate must be greater than or equal to 3V/ns. The slew rate is measured between VREFC crossing and VIXCK(AC)
d. Parameter fCKBG4 is required for those devices supporting both 3*tCK and 4*tCK setting for bank groups. Devices supporting only 3*tCK or 4*tCK
need only to specify fCKBG.
e. Parameter fCKPIN applies when the alignment point in MR6, bit A0 is set to at pins, the phase difference between the WCK and CK clocks at the
DRAM pins is within tWCK2CKSYNC or tWCK2CK for pin mode and no phase search in WCK2CK training is performed.
f. Parameter fCKRDQS applies when RDQS mode is enabled in AR3, bit A5.
g. Parameter fCKBREFD2 applies when the data input reference voltage in MR7, bit A7 (Half VREFD) is set to VREFD2.
h. Parameter fCKAUTOSYNC applies when WCK2CK Auto Synchronization is enabled in MR7, bit A4.
i. Parameter fCKLF applies when Low Frequency Mode is enabled in MR7, bit A3.
j. By definition the norminal WCK clock cycle time always is 1/2 of the CK clock cycle time (not including jitter).
k. WCK and WCK#single-ended input slew rate must be greater than or equal to 3V/ns. The slew rate is measured between VREFD crossing and
VIXWCK(AC).
Rev. 1.0 / Nov. 2009 151
H5GQ1H24AFR
l. The phase relationship between WCK/WCK#and CK/CK#clocks must meet the tWCK2CK specification.
m. Command and address input timings are referenced to VREFC.
n. Command and address input slew rate must be greater than or equal to 3V/ns. The slew rate is measured between VREFC crossing and VIHA(AC)
or VILA(AC).
o. Command and address input pulse widths are design targets. The value will be characterized but not tested on each device.
p. Address input timings are only valid with ABI beging enabled and a maximumof 4 address input driven LOW.
q. Parameter may be specified as a combination of tCK and ns.
r. Parameters tWCKHTR and tWCKLTR specify the max. allowed WCK clock-to-clock phase shift during WCK2CK training. For READ and WRITE
bursts use tWCKH and tWCKL.
s. Parameter tWCK2CKPIN defines the WCK2CK phase offset range at the CK and WCK pins for ideal (phase=0 ) clock alignment at the
GDDR5 SGRAMs phase detector (when the alignment point in MR6, bit A0 is set to at phase detector), or at the WCK and CK pins (when the
alignment in MR6, bit A0 is set to at pins). The minimumand maximumvalues could be negative or positive numbers, depending on the selected
WCK2CK alignment point, PLL-on or PLL-off mode and design implementation.
t. Parameter tWCK2CKSYNC defines the max. phase offset fromthe ideal (phase =0 ) clock alignment at the GDDR5 SGRAMs phase
detector (when the alignment point in MR6, bit A0 is set to at the phase detector), or at the WCK and CK pins (when the alignment point
in MR6, bit A0 is set to at pins), where the internal logic synchronizes the CK and WCK clocks; it is expected to be a fraction of tWCK2CK.
u. Parameter tWCK2CK defines the max. phase offset fromthe ideal (phase =0 ) clock alignment at the GDDR5 SGRAMs phase detector
(when the alignment point in MR6, bit A0 is set to at phase detector) or at the WCK and CK pins (when the alignment point in MR6, bit A0 is set to
at pins), for stable device operation.
v. Parameter tWCK2DQI defines the WCK to DQ/DBI#time delay range for WRITEs for PLL-on and PLL-off mode. The minimumand maximumvalues
could be negative or positive numbers, depending on design implementation and PLL-on or PLL-off mode. They also vary across PVT.
Data training is required to determine the actual tWCK2DQI value for reliable WRITE operation.
w. Parameter tWCK2DQO defines the WCK to DQ/DBI#time delay range for READs for PLL-on and PLL-off mode. The minimumand maxiumvalues
could be negative or positive numbers, depending on design implementation and PLL-on or PLL-off mode. They also vary across PVT.
Data training is required to determind the actual tWCK2DQO value for reliable READ operation.
x. Outputs measured with equivalent load terminated with 60 Ohms to VDDQ
y. DQ/DBI#input timings are valid only with DBI being enabled and a maximumof 4 data inputs per byte driven LOW.
z. Data input slew rate must be greater than or equal to 3V/ns. The slew rate is measured between VREFD crossing and VIHD(AC) or VILD(AC).
aa. The data input pulse width, tDIPW, defines the minimumpositive or negative input pulse width for any worst-case channel required for proper
propagation of an external signal to the receiver. tDIPW is measured at the pins. tDIPW is independent of the PLL mode.
In general tDIPW is larger than tDIVW
ab. The data input valid width, tDIVW, defines the time region where input data must be valid for reliable data capture at the receiver for any one worst
case channel. It accounts for jitter between data and clock at the latching point introduced in the path between DARM pads and the latching point.
Any additional jitter introduced into the source signals (e.g. within the systembefore the DRAM pad) must be accounted for in thefinal timing
budget together with the chosen PLL mode and bandwidth. tDIVW is measured at the pins. tDIVW is defined for PLL off and on mode separately.
In the case of PLL on, tDIVW must be specified for each supported bandwidth. In general, tDIVW is smaller than tDIPW.
ac. tDQDQI defines the maximumskew among all DQ/DBI#inputs of a double byte (when configured to 32 mode) or a single byte (when
configured to 16 mode) under worst case conditions. Parameter tWCK2DQI defines the mean value of the earliest and latest DQ/DBI#pin,
tDQDQI(min) the negative offset to tWCK2DQI for the earliest DQ/DBI#pin and tDQDQI(max) the positive offset to tWCK2DQI for the latest
DQ/DBI#pin.
ad. tDQDQO defines the maximumskew among all DQ/DBI#outputs of a double byte (when configured to 32mode) or a single byte (when
configured to 16 mode) under worst case conditions. Parameter tWCK2DQO defines the mean value of of the earliest and latest DQ/DBI#
/EDC pin, tDQDQO(min) the negative offset to tWCK2DQO for earliest DQ/DBI#/EDC pin and tDQDQO(max) the positive offset to tWCK2DQO
for the latest DQ/DBI#/EDC pin.
ae. For READs and WRITEs with AUTO PRECHARGE enabled the device will hold off the internal PRECHARGE until tRAS(min) has been satisfied.
af. Parameter applies when bank groups are enabled and consecutive commands access the same bank group.
ag. Parameter applies when bank groups are disabled or consecutive commands access different bank group.
ah. Not more than 4 ACTIVE commands are allowed within period.
ai. Not more than 32 ACTIVE commands are allowed within t32AW period. The parameter need not to be specified in case t32AW(min) would not be
greater than 8*tFAW(min).
aj. Parameter applies when bank groups are enabled and READ and PRECHARGE commands access the same bank.
ak. Parameter applies when bank groups are disabled or READ and PRECHARGE commands access the same bank.
al. tDAL =(tWR/tCK) +( tRP/tCK). For each of the terms, if not already an integer, round up to the next integer.
am. tCCDL is either for gapless consecutive READ or gapless consecutive WRITE commands
an. tCCDS is either for gapless consecutive READ or RDTR (any combination), gapless consecutive WRITE, or gapless consecutive WRTR commands.
ao. The min. value does not exceed 8 tCK
ap. tRTW is not a device limit but determined by the systembus turnaround time. The difference between tWCK2DQO and tWCK2DQI shall be considered
in the calculation of the bus turnaround time.

Rev. 1.0 / Nov. 2009 152
H5GQ1H24AFR
aq. The WRITE latency WLmrs cna be set to 3 to 7 clocks. When the WRITE latency is set to small values (3 ~4 clocks), the input buffers are always on,
reducing the latency but adding power. When the WRITE latency is set to larger values (5 ~7 clocks), the input buffers are turned on with the WRITE
command, thus saving power.
ar. Read data including CRC data must have been clocked out before entering self refresh or power down mode.
as. Write data must have been written to the memory core and CRC data must have been clocked out before entering self refresh or power down mode.
at. Time for WCK2CK training and data training not included.
au. A maximumof 8 consecutive REFRESH commands can be posted to a GDDR5 SGRAM device, meaning that the maximumabsolute interval
between any REFRESH command and the next REFRESH command is 9*tREFI.
av. Replaces parameter tLK when PLL Fast Lock has been neabled prior to the PLL enable or reset.
aw. Replaces parameter tLK when PLL Standby has been enabed and the WCK clock frequency has not charged while in standby mode.
ax. The PLL standby time tSTDBY ismeasured fromself refresh entry until after self refresh exit a subsequent PLL reset is given (with PLL Standby
enabled)
Rev. 1.0 / Nov. 2009 153
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Theavailabilityofclocktodata(WCK2DQ)timingsensitivityinformationprovidesthecontrollerthe
opportunitytoanticipatetheimpacttotimingsfromvariationsinenvironmentalconditions(suchas
changesinvoltageortemperature)allowingthecontrollertotakecorrectiveactionifnecessary(e.g.
realigningWCKandDQ).
VariationsinrelativetimingbetweenWCKanddataarereportedforREADandWRITEpaths.Thisspeci
ficationcallsoutonezoneeachforVDDQ,VDD,andTcasetemperatureoveraspecifiedrange.Vendors
maychoosetoprovideinformationforadditionalzonescovering,intotal,awiderrangeorafinergranu
larityorboth.
However,withinagivenzoneifanapproximatedvalue(i.e.thespecifiedslope)deviatesfromthecharac
terizedslopetosuchadegreethattheapproximatedWCKtoDQtimedelaywouldbeinerrorbymore
than5%ofoneUIrelativetothecharacterizeddelaythenthesplittingofthiszoneintomorethanonezone
isrequired.
Allzonesandtheirassociatedspecifiedslopesmustformacontinuouspiecewiselinearcurvesuchthat,
aftercalibrationduringnormaloperation,traversingtheapproximatedcurve(i.e.thesetofspecified
slopes)doesnotleadtotimedelayerrorsinexcessofthe5%ofoneUI.
Tables45,46,and47belowdescribetheminimumsetofdefinedzones.
6.3 CLOCK-TO-DATA TIMING SENSITIVITY
VDDQHigh VDDQLow Notes
Zone_VQ1
VDDQmax
VDDQmin
a
a.VDDQ(max)isthemaximumspecifiedoperatingvoltage.VDDQ(min)istheminimumspecifiedoperating
voltage.
Table 45. VDDQ Voltage Zone
VDDHigh VDDLow Notes
Zone_VD1 VDDmax VDDmin
a
a. VDD(max) is the maximum specified operating voltage. VDD(min) is the minimum specified operating
voltage.
Table 46. VDD Voltage Zone
TcaseHigh TcaseLow Notes
Zone_T1 Tcasemax 10C
a
a.Tcase(max)isthemaximumspecifiedoperatingtemperature.
Table 47. Tcase Temperature Zone
Asnoted,variationsinrelativetimingarereportedforREADandWRITEpaths.Tables48,49and50below
provideinformationforREADtimingswhileTables51,52and53provideinformationforWRITEtimings
Rev. 1.0 / Nov. 2009 154
H5GQ1H24AFR
Table 48. WCK-to-Data READ Timing Sensitivity to VDDQ
Parameter Symbol Values Units Notes
WCK2DQOSensitivitytovariationsinVDDQfor
zone_VQ1
PLLon
t
O2VQSensZ1
TBD
ps/V
a
,
b
a.CalculationoftO2VQSensZ1isperformedasfollows:
tO2VQSensZ1equalsthequantity(tWCK2DQO(Zone_VQ1(max))tWCK2DQO(Zone_VQ1(min)))
dividedby(VDDQ(Zone_VQ1(max))VDDQ(Zone_VQ1(min)))
=(tWCK2DQO(VDDQ(max))tWCK2DQO(VDDQ(min)))/(VDDQ(max)VDDQ(min)).
b.VDD(typ),Tcase=85C,worstcaseprocesscorner.
PLLoff TBD
Table 49. WCK-to-Data READ Timing Sensitivity to VDD
WCK2DQOSensitivitytovariationsinVDDforzone_VD1
PLLon
t
O2VDSensZ1
TBD
ps/V
a
,
b
a.CalculationoftO2VDSensZ1isperformedasfollows:
tO2VDSensZ1equalsthequantity(tWCK2DQO(Zone_VD1(max))tWCK2DQO(Zone_VD1(min)))
dividedby(VDD(Zone_VD1(max))VDD(Zone_VD1(min)))
=(tWCK2DQO(VDD(max))tWCK2DQO(VDD(min)))/(VDD(max)VDD(min)).
b.VDDQ(typ),Tcase=85C,worstcaseprocesscorner.
PLLoff TBD
Table 50. WCK-to-Data READ Timing Sensitivity to Tcase
WCK2DQOSensitivitytovariationsinTcaseforzone_T1
PLLon
t
O2TSensZ1
TBD
ps/C
a
,
b
a.CalculationoftO2TSensZ1isperformedasfollows:
tO2TSensZ1equalsthequantity(tWCK2DQO(Zone_T1(max))tWCK2DQO(Zone_T1(min)))
dividedby(Tcase(Zone_T1(max))Tcase(Zone_T1(min)))
=(tWCK2DQO(Tcase(max))tWCK2DQO(Tcase(min)))/(Tcase(max)Tcase(min)).
b.VDDQ(typ),VDD(typ),worstcaseprocesscorner.
PLLoff TBD
Rev. 1.0 / Nov. 2009 155
H5GQ1H24AFR
Tables51,52and53belowprovideinformationforWRITEtimings.
.
Table 51. WCK-to-Data WRITE Timing Sensitivity to VDDQ
WCK2DQISensitivitytovariationsinVDDQforzone_VQ1
PLLon
t
I2VQSensZ1
TBD
ps/V
a
,
b
a.CalculationoftI2VQSensZ1isperformedasfollows:
tI2VQSensZ1equalsthequantity(tWCK2DQI(Zone_VQ1(max))tWCK2DQI(Zone_VQ1(min)))
dividedby(VDDQ(Zone_VQ1(max))VDDQ(Zone_VQ1(min)))
=(tWCK2DQI(VDDQ(max))tWCK2DQI(VDDQ(min)))/(VDDQ(max)VDDQ(min)).
b.VDD(typ),Tcase=85C,worstcaseprocesscorner.
PLLoff TBD
Table 52. WCK-to-Data WRITE Timing Sensitivity to VDD
WCK2DQISensitivitytovariationsinVDDforzone_VD1
PLLon
t
I2VDSensZ1
TBD
ps/V
a
,
b
a.CalculationoftO2VDSensZ1isperformedasfollows:
tI2VDSensZ1equalsthequantity(tWCK2DQI(Zone_VD1(max))tWCK2DQI(Zone_VD1(min)))
dividedby(VDD(Zone_VD1(max))VDD(Zone_VD1(min)))
=(tWCK2DQI(VDD(max))tWCK2DQI(VDD(min)))/(VDD(max)VDD(min)).
b.VDDQ(typ),Tcase=85C,worstcaseprocesscorner.
PLLoff TBD
Table 53. WCK-to-Data WRITE Timing Sensitivity to Tcase
WCK2DQISensitivitytovariationsinTcaseforzone_T1
PLLon
t
I2TSensZ1
TBD
ps/C
a
,
b
a.CalculationoftI2TSensZ1isperformedasfollows:
tI2TSensZ1equalsthequantity(tWCK2DQI(Zone_T1(max))tWCK2DQI(Zone_T1(min)))
dividedby(Tcase(Zone_T1(max))Tcase(Zone_T1(min)))
=(tWCK2DQI(Tcase(max))tWCK2DQI(Tcase(min)))/(Tcase(max)Tcase(min)).
b.VDDQ(typ),VDD(typ),worstcaseprocesscorner.
PLLoff TBD
Rev. 1.0 / Nov. 2009 156
H5GQ1H24AFR
7.PACKAGESPECIFICATION
Note) Top View (as seen thru package), MF =LOW (MF =0)
1 2 3 7 8 9 4 5 6 10 11 12 13 14
V
SSQ
V
SSQ
V
DDQ
V
DD
V
SS
DQ22
DQ20
DQ16
DQ18
V
DDQ
V
DDQ
V
SSQ
V
SSQ
V
SSQ
V
DDQ DQ23
DQ21
DBI2#
EDC2
DQ19
DQ17
V
DDQ
V
DDQ
V
SSQ
V
SSQ
V
SSQ
V
DDQ
VREFD
V
SS
V
DD
CKE#
V
SS
CAS#
DQ31
DQ4 DQ5
DQ7 DQ6
V
DDQ
V
SSQ
V
DDQ
RAS#
A10
A0
WCK01
DQ0
MF
DQ3 DQ2
V
SSQ
EDC0
V
DDQ
DBI0#
V
SSQ
V
DD
V
SS
DQ30
DQ29
DQ28
V
DDQ
DBI3#
V
SSQ
EDC3
DQ24
V
DDQ
DQ27
DQ26
SEN RESET#
A
B
C
D
F
G
H
J
E
L
M
K
N
P
T
U
R
VREFC
VREFD
V
DD
V
SSQ
V
SSQ
V
SSQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SSQ
V
SSQ
V
DDQ
V
SSQ
V
DD
V
DDQ
V
DDQ
V
SSQ
V
SSQ
V
SSQ
V
DDQ
V
DDQ
ABI#
DQ1
V
SSQ
V
SSQ
DQ25
V
DDQ
V
DDQ
V
SSQ
A8
A7
V
DD
WCK23
V
DDQ
V
SSQ
V
SS
V
DD
BA1
A5
V
SS
DQ12
DQ14
BA0
A2
DQ8
DQ10
V
DD
CK#
V
SSQ
V
DD
WE#
CS#
V
DDQ
V
SSQ
V
SSQ
V
DDQ
V
SSQ
V
DDQ
V
DDQ
DQ13
DQ15
V
DDQ
DQ11
EDC1
DBI1#
ZQ
V
DDQ
DQ9
V
SSQ
V
SSQ
V
SS
V
DDQ
V
SSQ
V
SSQ
V
DDQ
V
SSQ
V
DD
V
SS
V
DD
V
DDQ
V
SS
V
DD
BA2
A4
BA3
A3
BYTE0 BYTE1
BYTE3 x32mode:ON
x16mode:OFF
x32mode:ON
x16mode:ON
V
PP,
V
DDQ
V
SSQ
V
DDQ
V
DD
V
SS
V
SSQ
A9
A1
V
SS
V
SS
V
DD
NC
V
PP,
NC
WCK01#
A12
RFU,
NC
A11
A6
V
SS
WCK23#
CK
V
SS
DBI0#
V
DDQ
BYTE2
Figure 81. GDDR5 SGRAM 170ball BGA Ball-out MF=0
Rev. 1.0 / Nov. 2009 157
H5GQ1H24AFR
Note)TopView(asseenthrupackage),MF=HIGH(MF=1)
1 2 3 7 8 9 4 5 6 10 11 12 13 14
V
SSQ
V
SSQ
V
DDQ
V
DD
V
SS
DQ14
DQ12
DQ8
DQ10
V
DDQ
V
DDQ
V
SSQ
V
SSQ
V
SSQ
V
DDQ DQ15
DQ13
DBI1#
EDC1
DQ11
DQ9
V
DDQ
V
DDQ
V
SSQ
V
SSQ
V
SSQ
V
DDQ
VREFD
V
SS
V
DD
CKE#
V
SS
RAS#
DQ7
DQ28 DQ29
DQ31 DQ30
V
DDQ
V
SSQ
V
DDQ
CAS#
A10
A0
WCK23
DQ24
MF
DQ27 DQ26
V
SSQ
EDC3
V
DDQ
DBI3#
V
SSQ
V
DD
V
SS
DQ6
DQ5
DQ4
V
DDQ
DBI0#
V
SSQ
EDC0
DQ0
V
DDQ
DQ3
DQ2
SEN RESET#
A
B
C
D
F
G
H
J
E
L
M
K
N
P
T
U
R
VREFC
VREFD
V
DD
V
SSQ
V
SSQ
V
SSQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SSQ
V
SSQ
V
DDQ
V
SSQ
V
DD
V
DDQ
V
DDQ
V
SSQ
V
SSQ
V
SSQ
V
DDQ
V
DDQ
ABI#
DQ25
V
SSQ
V
SSQ
DQ1
V
DDQ
V
DDQ
V
SSQ
A8
A7
V
DD
WCK01
V
DDQ
V
SSQ
V
SS
V
DD
BA3
A3
V
SS
DQ20
DQ22
BA2
A4
DQ16
DQ18
V
DD
CK#
V
SSQ
V
DD
CS#
WE#
V
DDQ
V
SSQ
V
SSQ
V
DDQ
V
SSQ
V
DDQ
V
DDQ
V
DDQ
DQ21
DQ23
V
DDQ
DQ19
EDC2
DBI2#
ZQ
V
DDQ
DQ17
V
SSQ
V
SSQ
V
SS
V
DDQ
V
SSQ
V
SSQ
V
DDQ
V
SSQ
V
DD
V
SS
V
DD
V
DDQ
V
SS
V
DD
BA0
A2
BA1
A5
BYTE3 BYTE2
BYTE0 BYTE1
x32mode:ON
x16mode:OFF
x32mode:ON
x16mode:ON
V
PP,
V
DDQ
V
SSQ
V
DDQ
V
DD
V
SS
V
SSQ
A9
A1
V
SS
V
SS
V
DD
NC
V
PP,
NC
WCK23#
A12
RFU,
NC
A11
A6
V
SS
WCK01#
CK
V
SS
Figure 82. GDDR5 SGRAM 170ball BGA Ball-out MF=1
Rev. 1.0 / Nov. 2009 158
H5GQ1H24AFR
7.1.SIGNALS
Table 54. Ball-out Description
SYMBOL TYPE DESCRIPTION
CK,CK# Input Clock:CKandCK#aredifferentialclockinputs.Commandinputsarelatchedontherising
edgeofCK.AddressinputsarelatchedontherisingedgeofCKandtherisingedgeofCK#.
AlllatenciesarereferencedtoCK.CKandCK#areexternallyterminated.
WCK01,
WCK01#,
WCK23,
WCK23#
Input WriteClocks:WCKandWCK#aredifferentialclocksusedforWRITEdatacaptureandREAD
dataoutput.WCK01/WCK01#isassociatedwithDQ0DQ15,DBI0#,DBI1#,EDC0andEDC1.
WCK23/WCK23#isassociatedwithDQ16DQ31,DBI2#,DBI3#,EDC2andEDC3.
CKE# Input ClockEnable:CKE#LOWactivatesandCKE#HIGHdeactivatestheinternalclock,device
inputbuffers,andoutputdrivers.TakingCKE#HIGHprovidesPRECHARGEPOWER
DOWNandSELFREFRESHoperations(allbanksidle),orACTIVEPOWERDOWN(row
ACTIVEinanybank).CKE#mustbemaintainedLOWthroughoutreadandwriteaccesses.
ThevalueofCKE#latchedatpowerupwithRESET#goingHighdeterminesthetermination
valueoftheaddressandcommandinputs.
CS# Input ChipSelect:CS#LOWenablesandCS#HIGHdisablesthecommanddecoder.Allcommands
aremaskedwhenCS#isregisteredHIGH.CS#providesforexternalrankselectiononsystems
withmultipleranks.CS#isconsideredpartofthecommandcode.
RAS#,
CAS#,WE#
Input CommandInputs:RAS#,CAS#,andWE#(alongwithCS#)definethecommandbeing
entered.
BA0BA3 Input BankAddressInputs:BA0BA3definetowhichbankanACTIVE,READ,WRITE,or
PRECHARGEcommandisbeingapplied.BA0BA3alsodeterminewhichModeRegisteris
accessedwithanMODEREGISTERSETcommand.BA0BA3aresampledwiththerising
edgeofCK.
A0A11
(A12)
Input AddressInputs:A0A11(A12)providetherowaddressforACTIVEcommands,A0A5(A6)
providethecolumnaddressandA8definestheautoprechargefunctionforREAD/WRITE
commands,toselectonelocationoutofthememoryarrayintherespectivebank.A8sampled
duringaPRECHARGEcommanddetermineswhetherthePRECHARGEappliestoonebank
(A8LOW,bankselectedbyBA0BA3)orallbanks(A8HIGH).Theaddressinputsalso
providetheopcodeduringaMODEREGISTERSETcommandandthedatabitsduringa
LDFFcommand.A8A11(A12)aresampledwiththerisingedgeofCKandA0A7are
sampledwiththerisingedgeofCK#.
DQ031 I/O DataInput/Output:32bitdatabus
DBI#03 I/O DataBusInversion.DBI#0isassociatedwithDQ0DQ7,DBI#1isassociatedwithDQ8DQ15,
DBI#2isassociatedwithDQ16DQ23,DBI#3isassociatedwithDQ24DQ31.
EDC03 Output ErrorDetectionCode.ThecalculatedCRCdataistransmittedonthesepins.Inadditionthese
pinsdriveaholdpatternwhenidleandcanbeusedasanRDQSfunction.EDC0is
associatedwithDQ0DQ7,EDC1isassociatedwithDQ8DQ15,EDC2isassociatedwith
DQ16DQ23,EDC3isassociatedwithDQ24DQ31.
ABI# Input AddressBusInversion
VddQ Supply I/OPowerSupply.Isolatedonthedieforimprovednoiseimmunity.
VssQ Supply I/OGround:Isolatedonthedieforimprovednoiseimmunity.
Vdd Supply PowerSupply
Vss Supply Ground
Vrefd Supply ReferenceVoltageforDQ,DBI#,andEDCpins.
Vrefc Supply ReferenceVoltageforaddressandcommandpins.
Vpp Supply PumpVoltage
MF Reference MirrorFunction:VDDQCMOSinput.Mustbetiedtopowerorground.
ZQ Reference ExternalReferencePinforautocalibration
Rev. 1.0 / Nov. 2009 159
H5GQ1H24AFR
Figure clarifiestheuseoftheMF=0andMF=1balloutsinx16modeandwhythebytesarerenumberedto
givethecontrollertheviewofthesamebytesthatacontrollerseeswithasinglex32device.Thisisimpor
tantforAddressTraining,DMandEDCfunctionality.Formoredetailsseethex16enableandMFenable
section.
RFU ReservedforFutureUse
NC Notconnected
SEN Input Scanenable.VDDQCMOSinput.Mustbetiedtothegroundwhennotinuse.
RESET# Input ResetPin.VDDQCMOSinput.RESET#Lowasynchronouslyinitiatesafullchipreset.With
RESET#LowallODTsaredisabled.
Table 54. Ball-out Description
SYMBOL TYPE DESCRIPTION
Rev. 1.0 / Nov. 2009 160
H5GQ1H24AFR
Figure 83. Byte Orientation in Clamshell Topology
x16MF=0 x16MF=0
x16MF=1 x16MF=1
0
2
1
3
0 1
2 3
+
=
TopviewthruPCB
(PCBabove)
Controllerview Topviewthrupackage
(PCBbelow)
DQ
ADDRESS/COMMAND(exceptCS#)
Legend:
CS#
Rev. 1.0 / Nov. 2009 161
H5GQ1H24AFR
7.2.ONDIETERMINATION(ODT)
GDDR5SGRAMssupportmultipleterminationmodesforitshighspeedinputsignals.Whenthetermina
tionisenabledforareceiver,animpedancedefinedforthatterminationmodeisappliedbetweenthat
inputreceiverandtheVDDQsupplyrail.ThisiscommonlyreferredtoasVDDQtermination.Registers
havebeendefinedtocontroltheterminationmodes.ADD/CMDTerminationiscontrolledusingMR1bits
A4andA5.DataterminationiscontrolledusingMR1bitsA2andA3.WCKterminationiscontrolled
usingMR3bitsA8andA9.
Table55includesallthehighspeedGDDR5SGRAMsignalswhosereceiversincludeondieterminationto
VDDQandwhethertheirterminationcanbedisabledbyADD/CMDTerm,DQTerm,orWCKTerm.A
Yesindicateswhetherthemoderegisterfieldcontrolsterminationforthesignal.
Table 55. Signals Affected by Termination Control Registers
ADD/CMDTerm
MR1(A4,A5)
DQTerm
MR1(A2,A3)
WCKTerm
MR3(A8,A9)
Signal x32 x16 x32 x16 x32 x16
RAS#,CAS#,WE,CS#,CKE# Yes Yes No No No No
A10/A0,A9/A1,BA0/A2,BA3/A3,
BA2/A4,BA1/A5,A11/A6,A8/A7,
A12/RFU/(NC),ABI#
Yes Yes No No No No
DQ[7:0],DBI0# No No Yes Yes No No
DQ[15:8],DBI1# No Disabled Yes Disabled No Disabled
DQ[23:16],DBI2# No No Yes Yes No No
DQ[31:24],DBI3# No Disabled Yes Disabled No Disabled
WCK01,WCK01#,WCK23,WCK23# No No No No Yes Yes
Rev. 1.0 / Nov. 2009 162
H5GQ1H24AFR
7.3.PACKAGEOUTLINE
Figure 84. Package Dimensions
Notes:
1)GDDR5packageheightspecificationiscomplianttoMO207RevL,variationDAAz
Table 56. Package Height Parameters
Nominal Variation
pkg
standoff
0.350 +/0.050
pkg
height
1.100 +/0.100
TOPVIEW SIDEVIEW
pkg
standoff
pkg
height
BOTTOMVIEW
(170ball)
13x0.8=10.4
5x0.8=4.0 0.8
12
1
6
0
.
8
1
2
.
8
1
4
0
.
8
p
k
g
Y
pkg
x
U
T
R
p
N
M
L
K
J
H
G
F
E
D
C
B
A
Rev. 1.0 / Nov. 2009 163
H5GQ1H24AFR
7.4.MIRRORFUNCTION(MF)ENABLEandx16MODEENABLE
TheGDDR5SGRAMprovidesamirrorfunction(MF)pintochangethephysicallocationofthecommand,
address,data,andWCKpinsassistinginroutingdevicesbacktoback.TheMFballshouldbetieddirectly
toVSSQorVDDQdependingonthecontrollineorientationdesired.
TheGDDR5SGRAMcanoperateinax32modeorax16modetoallowaclamshellconfigurationwitha
pointtopointconnectiononthehighspeeddatasignal.Thedisabledpinsinx16modeshouldallbeina
HiZstate,nonterminating.
Thex16modeisdetectedatpoweruponthepinatlocationC13whichisEDC1whenconfiguredtoMF=0
andEDC2whenconfiguredtoMF=1.Forx16modethispinistiedtoVSSQ;thepinispartofthetwobytes
thataredisabledinthismodeandthereforenotneededforEDCfunctionality.Forx32modethispinis
activeandalwaysterminatedtoVDDQinthesystemorbythecontroller.Theconfigurationissetwith
RESET#goingHigh.Oncetheconfigurationhasbeenset,itcannotbechangedduringnormaloperation.
Usuallytheconfigurationisfixedinthesystem.Detailsofthex16modedetectionaredepictedinFigure .
Acomparisonofx32modeandx16modesystemsisshowninFigure .
Rev. 1.0 / Nov. 2009 164
H5GQ1H24AFR
Figure 85. Enabling x16 mode
RESET#
RESET#
RESET#
RESET#
RESET# RESET#
RESET#
RESET# RESET#
VSSQ
VSSQ
VSSQ
1=x32
0=x16
0=x16
EDC1
EDC
EDC1
RX
enable
Termination
Controller
EDCdatafrom
otherDRAM
VDDQ
VDDQ
VDDQ
RX
RX
Controller
Controller
enable
Termination
EDC2
EDC
EDCdatafrom
otherDRAM
RX
TX
EN
RX D
EDC2
EDC1
EDC
EDC1
TX
EN
RX D
enable
Termination
x16
EDCData
EDCData
x32
EDCData
D
TX
EN
x16
GDDR5
inx16mode
MF=1
GDDR5
inx16mode
MF=0
GDDR5
inx32mode
MF=0or1
Rev. 1.0 / Nov. 2009 165
H5GQ1H24AFR
Figure 86. System view for x32 mode vs. x16 mode
Figure86andFigure87showexamplesoftheboardchannelsandtopologiesthataresupportedin
GDDR5inordertoillustratetheexpectedusageofx16modeandtheMFpin.
Table 57. x16 mode and MF
MODE MF EDC1(MF=0)orEDC2(MF=1)
x16nonmirrored VSSQ VSSQ
x32nonmirrored VSSQ VDDQ(terminatedbythesystemorcontroller)
x16mirrored VDDQ VSSQ
x32mirrored VDDQ VDDQ(terminatedbythesystemorcontroller)
Byte1
Byte3
Byte2
Byte0
ADD/
CMD
ADD/
CMD
Byte1
Byte3
Byte2
Byte0 DQ0DQ7,DBI0#
EDC0
DQ8DQ15,DBI1#
EDC1
DQ16DQ23,DBI2#
EDC2
DQ24DQ31,DBI3#
EDC3
WCK01,WCK01#
WCK23,WCK23#
AddressBus
CommandBus
CK,CK#
GDDR5
x32
CK,CK#
EDC2 EDC1
RESET RESET#
MF MF
VDDQ VSSQ
MF
VSSQ
GDDR5
x16
GDDR5
x16
AddressBus
CommandBus
DQ0DQ7,DBI0#
EDC0
DQ8DQ15,DBI1#
EDC1
DQ16DQ23,DBI2#
EDC2
DQ24DQ31,DBI3#
EDC3
WCK01,WCK01#
WCK23,WCK23#
C
o
n
t
r
o
l
l
e
r
C
o
n
t
r
o
l
l
e
r
Rev. 1.0 / Nov. 2009 166
H5GQ1H24AFR
Figure 87. Example Channel Topologies
ForflexibilityofPCBroutingGDDR5SGRAMdevices,theballoutincludesdefinitionofbothMF=0and
MF=1.ThefollowingsimpleblockdiagramsinFigure88demonstratesomeoftheflexibilityofPCBrout
ing.
(P2P)
32DQ
(P2P)
32DQ
(P22P)
ADD/CMD
16DQ
(P2P)
(P22P)
ADD/CMD
16DQ
64bitchannel
32DQ
32bitchannel
(P2P)
ADD/CMD
(P2P)
(P2P)
Rev. 1.0 / Nov. 2009 167
H5GQ1H24AFR
Clamshellconfigurations
Singlesideconfigurations
x32MF=0
x32MF=1
DQ
ADDRESS/COMMAND(exceptCS#)
Legend:
CS#
x16MF=1
x16MF=0
x16MF=0 x16MF=1
x32MF=0 x32MF=0
x16MF=0
x16MF=1
x32MF=0 x32MF=0
Note1:32bitchannelisshownasanexample.
Alsoapplieswithx16ona16bitchannel.
1
1
x32MF=1
x32MF=1
1
x32MF=0
x32MF=0
1
x32MF=0 x32MF=1
x32MF=1 x32MF=1
x32MF=0 x32MF=1
1
x32MF=1 x32MF=1
1
Figure 88. Example GDDR5 PCB Layout Topologies
Rev. 1.0 / Nov. 2009 168
H5GQ1H24AFR
BOUNDARY SCAN
TheGDDR5SGRAMincorporatesamodifiedboundaryscantestmode.Thismodedoesnotoperatein
accordancewithIEEEStandard1149.11990.TosavethecurrentGDDR5SGRAMsballout,thismodewill
scantheparalleldatainputandoutputthescanneddataonEDC0locatedatC2controlledbyanaddon
pin,SENwhichislocatedatJ10ofthe170ballpackage.
Scanmodeisentereddirectlyafterpowerupwhilethedeviceisinresetstate.Thisensuresthatno
unwantedaccesscommandsarebeingexecutedpriortoscanmode.
Boundaryscandoesnotdistinguishbetweenx16andx32modes,anddataiscapturedonallpins.Theuser
hastomakesuretomaskthosebitsinthetestprogramwhicharenotwiredinthesystem.
Fornormaldeviceoperation,i.e.afterscanmodeoperation,itisrequiredthatdevicereinitialization
occursthroughdevicepowerdownandthenpowerup.
ItispossibletooperatetheGDDR5SGRAMwithoutusingtheboundaryscanfeature.SENshouldbetied
Lowtopreventthedevicefromenteringtheboundaryscanmode.Theotherpinswhichareusedforscan
mode(RESET#,MF,EDC0andCS#)willbeoperatingasnormalwhenSENisdeasserted.
Note:Whenthedeviceisinscanmode,mirrorfunctionisdisabled(MF=0)andnoneofthepinsareremapped.
Table 58. Boundary Scan Exit Order
BIT# BALL BIT# BALL BIT# BALL BIT# BALL BIT# BALL
1 D5 13 J3 25 T2 37 M11 49 E13
2 D4 14 K4 26 T4 38 M13 50 E11
3 D2 15 K5 27 U2 39 L12 51 D13
4 E4 16 L3 28 U4 40 K10 52 C13
5 E2 17 M2 29 U11 41 K11 53 B13
6 F4 18 M4 30 U13 42 J13 54 B11
7 F2 19 N2 31 T11 43 J12 55 A13
8 G3 20 N4 32 T13 44 J11 56 A11
9 H5 21 P2 33 R13 45 H11 57 A4
10 H4 22 P4 34 P13 46 H10 58 A2
11 J5 23 P5 35 N11 47 F13 59 B4
12 J4 24 R2 36 N13 48 F11 60 B2
Rev. 1.0 / Nov. 2009 169
H5GQ1H24AFR
Notes:
1. WhenSENisasserted,nocommandsaretobeexecutedbytheGDDR5SGRAM.Thisappliestobothuser
commandsandmanufacturingcommandswhichmayexistwhileRESET#isdeasserted.
2. Allscanfunctionalityisvalidonlyaftertheappropriatepowerup(Steps14ofinitializationsequence).
3. Inscanmode,allODTwillbedisabled.
Table 59. Scan Pin Description
PACKAGE
BALL
SYMBOL
NORMAL
FUNCTION
TYPE DESCRIPTION
J2 SSH RESET# Input
ScanShift:capturethedatainputfromthepadatlogicLOW
andshiftthedataonthechainatlogicHIGH.
G12 SCK CS# Input
ScanClock.Notatrueclock,couldbeasinglepulseorseriesof
pulses.Allscaninputswillbereferencedtotherisingedgeof
thescanclock.
C2 SOUT EDC0 Output ScanOutput.
J10 SEN RFU Input
ScanEnable:logicHIGHenablesscanmode.Scanmodeis
disabledatlogicLOW.MustbetiedtoVSSQwhennotinuse.
J1 SOE# MF Input
ScanOutputEnable:enables(registeredLOW)anddisables
(registeredHIGH)SOUTdata.ThispinwillbetiedtoVDDQor
GNDthrougharesistor(typically1KOhm)fornormal
operation.Testerneedstooverdrivethispintoguaranteethe
requiredinputlogiclevelinscanmode.
Table 60. Scan AC Electrical Characteristics
PARAMETER/CONDITION SYMBOL MIN MAX
UNIT
S
NOTES
Clock
Clockcycletime t
SCK
40 ns 1
ScanCommandTime
Scanenablesetuptime t
SES
20 ns 1
Scanenableholdtime t
SEH
20 ns 1
ScancommandsetuptimeforSSH,SOE#andSOUT t
SCS
14 ns 1
ScancommandholdtimeforSSH,SOE#andSOUT t
SCH
14 ns 1
ScanCaptureTime
Scancapturesetuptime t
SDS
10 ns 1
Scancaptureholdtime t
SDH
10 ns 1
Rev. 1.0 / Nov. 2009 170
H5GQ1H24AFR
Notes:
1. TheparameterappliesonlywhenSENisasserted.
Figure. 89 Scan Capture Timing
ScanShiftTime
Scanclocktovalidscanoutput t
SAC
6 ns 1
Scanclocktoscanoutputhold t
SOH
1.5 ns 1
Table 60. Scan AC Electrical Characteristics
PARAMETER/CONDITION SYMBOL MIN MAX
UNIT
S
NOTES
SCK
SEN
t
SDS
t
SDH
Pins
under
Test
VALID
t
SES
SSH
SOE#
t
SCS
(Low)
Notatrueclock,butasinglepulse
oraseriesofpulses
Rev. 1.0 / Nov. 2009 171
H5GQ1H24AFR
Figure. 90 Scan Shift Timing
t
SES
t
SCS
t
SCS
t
SAC
ScanOut
bit1
ScanOut
bit2
ScanOut
bit3
ScanOut
bit4
t
SOH
SCK
SEN
SOUT
SSH
SOE#
Rev. 1.0 / Nov. 2009 172
H5GQ1H24AFR
VDD
VDDQ
VREF
RESET#
(SSHin
ScanMode)
SEN
tSES
SCK
SOE#
tSAC
SOUT
Pins
under
Test
VALID
tSDS tSDH
ScanOut
bit1
t
SCK
200us
Powerup
VDDstable DontCare
t
SCS
tSCS
tSCS
BoundaryScanMode RESETatpowerup
Figure 91. Scan Initialization Sequence
Rev. 1.0 / Nov. 2009 173
H5GQ1H24AFR
Figure. 92 Internal Block Diagram
DQ2
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
DQ1
DQ3
WCK01#
SSH,ScanShiftPinRESET#
SCK,ScanClockPinCS#
SOUT,ScanOutPinEDC0
SEN,ScanEnablePinSEN
SOE#,ScanOutputEnablePinMF
Pinsundertest
DedicatedScanDFFpersignalundertest
Signalsinscanchain:
DQ[31:0],EDC[3:1],DBI#[3:0],
WCK01,WCK01#,WCK23,WCK23#,
RAS#,CAS#,WE#,CKE#,ABI#,
A[7:0]***,CK,CK#,ZQ
Note:A[7:0]***aremultiplexedpinsand
representA[12:8]andBA[3:0]
Signalsnotinthescanchain:
VDDQ,VSSQ,VDD,VSS,VREFx

H5GQ1H24AFR (Rev1 0)

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Figure 26. Impedance Offsets

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