Two sided PWM control of switching power factor

correction ac-dc converter

M Mahesh* IEEE Student Member Prof. Anup Kumar Panda†
Department of Electrical Engineering
National Institute of Technology
Rourkela – 769008, Orissa, India
matadamahesh1@rediffmail.com* anuppanda64@gmail.com†

Abstract- A novel PWM technique in active power factor

correction converter for power supplies with a 1-phase front end
diode rectifier is proposed and analyzed. Regarding PFC
converters as highly non-linear plants with inherence parameter
uncertainties, the deleterious effects due to large disturbances in
line voltage and load resistance are tackled by two sided latched
PWM technique with sophisticated feedback control loops. Two
sided latched PWM control approach which owns merits in both
fast response and cost-effectiveness. The performance of the
power factor correction converter for variable input voltage is
observed by simulating in PSIM. The resulting input voltage
and current waveforms show that design is successful.

Key words: Pulse Width Modulation (PWM), Power Factor

Correction (PFC), Continuous Conduction Mode (CCM).
I. INTRODUCTION
The power factor correction techniques in switch-mode
supplies have been improving, due to the increasing demand
for improved power quality. In addition to unity power
factor, fast response, high efficiency, high power density &
size also are important. Many new topologies have been
discussed in recent literature for achieving the required unity
power factor. Most switching power supplies always use
closed-loop negative feed-back systems with PWM technique
to achieve objectives for line and load regulation. Most
PWM controllers use a clock-edge to set one edge of the
PWM signal and feed-back to set the other edge of the PWM
signal. But, one edge available for control remains unused.
This direct duty cycle control has disadvantages like slow
response to sudden input changes, poor audio susceptibility
and poor open loop line regulation [1]. In both current mode
and voltage mode control [1-3] of PWM is restricted that it
uses one of two edges available for control.
Controller with hysteresis based of power converters makes
use of both edges but the switching frequency is allowed to
vary and control scheme is sensitive to commutation noises
[4-7]. Variation in the switching frequency makes it difficult
to filter the ripple components in the input and output
waveforms of the converters [3]. Therefore, it is essential to
have constant switching frequency to obtain unity power
factor in power supplies to increase the efficiency of the
electrical power grid and to meet the specifications of
Fig. 1 Two Sided Latched PWM Schematic for PFC ac-dc Converter.
International standards. Employing two sided PWM to active
PFC converter is not known to be present in the literature. [4-
7, 10-15].
Saw-tooth ramp generator is required in PFC ac-dc
converters to stabilize fixed frequency PWM control. Many
commercial PWM controller ICs are available with/without
saw-tooth generator. ICs with a saw-tooth generator are
limited in switching frequency and ICs that do not include the
saw-tooth ramp generator are available that operate at much
higher switching frequency. Still there exists a challenging
task for power supply design engineers in generation of the
high frequency saw-tooth ramp with the fast reset.
Employing two sided PWM technique improves the dynamic
response of the power factor correction circuit & it is most
suitable for high frequency applications [7].
II. OPERATION OF TWO SIDED PWM:
The two sided latched PWM [8] proposed scheme
for active PFC ac-dc converter is shown in figure1 which
achieves modulation of both edges while maintaining fully
latched operation. In this PWM scheme two comparators are
used instead of one to set and to reset the switch. One
comparator is used for the comparison between the feedback
signal Sign and ramp to set the switch while another
comparison between an offset feed-back signal and ramp is
used to reset the switch.
The ramp is not a saw-tooth, which is hard to
generate at high frequencies, but a triangular ramp wave with
equal rising and falling slopes is used to stabilize the duty
ratio of the switch and to set the switching frequency. The
ramp amplitude is chosen to meet the equal ramp slope
criteria for optimal current mode control. Fig1 shows a
sensor-less current mode control implementation, in an inner
current mode control of active PFC ac-dc converter.
Fig 2 shows the timing diagram of the signals in this
proposed PWM scheme for active PFC ac-dc converter.
There is a triangular ramp with equal rising and falling
slopes. This ramp is compared to the feedback signal with an
appropriate offset. The resulting pulse width modulation
signal is shown below. Note that the delay between
consecutive rising and falling edges are Tsw. The ramp slope
is chosen to be equal to the feedback signal at duty ratio of
half. This is a design choice and depends on the nominal
duty ratio.
III. TIME DOMAIN ANALYSIS:
A Assuming the continuous mode of operation and using the
switch set and reset criteria, the following analysis is made [8,
9]. Fig 2 shows the timing diagram for the two sided PWM
technique.
During the nth switching cycle, the crossing point of
the signal+0.5 current feedback and rising ramp signals
causes the switch transition to occur at time tsw =
(2n+Dr(n))Tsw.
Therefore, the nominal duty ratio is given by Dn =
Dr (n) +Dl (n). Where Dr (n) is the duty ratio provided from
the control loop by rising ramp only in the nth cycle and Dl
(n) is the duty ratio provided from the control loop by falling
ramp in the nth cycle.
Fig 2 Timing Diagram
The magnitudes of two signals at transition are given by
Sign1 (tsw) = Dr (n) Tsw mramp
Sign2 (tsw) = Dl (n) Tsw mramp
Where mramp = V (pk) ramp/Tsw. (slope of ramp).
The signal Sign is obtained as the integral of the difference of
the Iref and the actual boost inductor current waveform. The
gain of the integral is obtained using the equal slope criteria
when the reference is the half the input voltage.
IV. Control Circuit Considerations
Generally, active power factor correction (APFC) systems
are designed at high frequency converters that are controlled
by two feedback loops. Voltage loop is the outer loop which
regulates the output voltage with slow-response and the inner
loop that shapes the input current, is a much faster loop.
Average current mode control method is employed to achieve
high power factor. Bode plots of the transfer functions
discussed below are obtained in MATLAB.
(a) Current Loop Compensator
Excellent references exist on current loop design [1, 10-
12]. The objective of this loop is to track a reference
waveform (Iref) whose frequency is twice the line frequency.
The bandwidth of the current loop needs to be much greater
than twice the line frequency. This reference signal has a
high dv/dt around the zero crossings of the line. Therefore
the loop needs gain at frequencies corresponding to the higher
order Fourier coefficients needed to recreate the reference
waveform. This implies high bandwidth for the current loop.
In this case, a 10 kHz bandwidth is considered which is
usually adequate. In order to design a compensator loop
properly, the model of the converter is needed. A small signal
model of the converter based on the PWM switch model is
shown in Figure 3.
Fig. 3 Model of Boost Converter
The transfer function of the exact model of boost PFC is
. . ω
. -- (1)
.
ω . ω
 2 1
ω ,ω , 1
√

The simplified current loop transfer function is give by

V .RSENSE
G s -- (2)
.L .VSE

Where VSE is the triangular voltage peak to peak. Fig. 4 Current Loop error amplifier

The Bode plot of (1) is plotted in Fig. 5 for high line and
low line input voltages. At higher frequencies the plot
converges to the simplified model as shown in fig.5 (a). The
simplified model approach is easier to use and is adequate to
design the current loop. The exact model is shown to explain
what is seen if one measures the loop.
Its Bode plot is developed in MATLAB the same is shown
in Fig. 5.
(b) Voltage Loop Compensator:
There are some trade-offs inherent in the voltage
loop design that are particular to PFC applications. The
fundamental requirement of power balance, on the line
frequency time scale requires that the voltage loop’s
bandwidth must be less than the half the line frequency.
Otherwise, the voltage loop will distort the line current in
order to regulate the output voltage. 10Hz is considered in
this case. The proportional integrator is considered which
suits for PFC applications. The feedback loop PI
compensator is shown in below Fig. & its transfer function is
Av.

Vout

(a)

Fig. 6 Gm amplifier configuration

(b)
Fig. 5 Gain & Phase Plots of Exact Model at high & low line voltages,
Simplified Model & Current Error Amplifier. ---- (3)
||
The current loop error amplifier is shown in fig 4 and its
transfer function is V Design Criteria

The design criteria of PFC ac-dc converter follow

1 SR C those of the corresponding single-phase boost PFC’s
AV
sR CP CZ 1 R CP ||C operating in CCM. The only difference is in the way switch
is driven by two sided PWM technique which results in the
fast dynamic response compare to PWM technique. In the
current loop controller, IMO (reference current) is obtained
from multiplier whose equation is (4)
 simulator is
i shown in fig. 6 and the inputt & output voltaages, input
1 line currentt waveforms aree shown in fig. 7.
2 -- (4)

Where KM is i the multiplieer constant.

i is the current
AC c proporrtional to the rectified inpuut
volttage.
VFF is the feed forw
ward voltage.

All param meters are con

nstant except multiplier
m inpuut
currrent iAC. It can be shown usinng (4) that VEA
A remains fixeed
for a given load d (power) irrespective of thhe line voltagge
variiations.
i is derrived from a unit amplitude rectifier sinne
AC

wavve generated by b the separatte source of unitu magnitudde

whiich is perfectlyy synchronizedd with the inpuut instantaneouus
volttage. The feeed forward volltage is usuallly corrupted by b
Elecctro Magnetic Interference (EMI) noise if i it is deriveed
direectly from the rectified inpu ut voltage [13
3], so that it iis Fig. 6 S
Schematic of 1- Phasse Active PFC modell in PSIM
imppossible to obtaain pure sinuso
oidal.

Thee main design n criteria for the

t voltage looop are usuallly
reduuction of the 100Hz
1 ripple component
c beiing fed back tto
the multiplier. This is due to the t fact that thhe ripple at thhe
outpput of the voltaage error ampllifier is a majoor contributor tto
3rd order
o harmonics in the line current [12-133]. The issue iis
the dc regulation of the output voltage is prop portional to thhe
loopp gain. With th he voltage loopp gain set relattively low (witth
prop portional gain)), the output voltage
v will vaary widely witth
the line and load. Since the load d of a PFC cirrcuit is typicallly
anotther converter,, dc regulation may not an isssue, and start upu
trannsient responsee can be morre of a conceern (due to thhe
volttage stress on the
t output capaacitor).
Fig. 7 Innput and output voltaages & Input current..
VI Details of the Boost
B Convertter:
Simulation
S resullts are obtained for
f an input of 270Vrms &
A sy
ystem has the follow
wing specification
ns: the following
fo table summarizes the t Harmonic Distortion
Summmary:
Vin = 85-270 Vrms – 50H; V0 = 400V.
4
Poutt =100W, fs = 200
2 KHz. PF LINE THD VOUT
T (Vo) EFFIC
CIENCY
(Vrms) (%) (
(%)
Booost Converter Element
E Valuess: 0.9955 270 8.29 4000.1 93.55
0.9966 230 7.13 4000 94.13
Lboosst = 2.2mH, C0 = 110uF, RLoad = 1600 ohm;
0.9999 150 6.1 399.97 95.28
0.9988 90 4.9 399.86 94.69
MOOSFET: On-staate resistance – 0.015ohm, Diode voltagge
drop
p 0.8.
Booost Diode: Fasst recovery dioode is taken too minimize thhe
swittching losses inn the MOSFET
T.
V CONCLUS
VIII SION:

VII Simulatiion Results A two sided PW

WM in active PFC C ac-dc converteer has been
describ
ibed. Frequenccy responses of o exact model of boost
Simulations weere carried out on
o the boost PFC
C circuit, togetheer conveerter and curreent loop erro or amplifier have been
withh the compensattors and two sidded PWM. Pow wer-Sim simulatoor repressented. The twwo side PWM technique in acctive PFC
is used for the Acttive PFC circuitt. The schemattic entry into thhe increaases the dynamicc response of thhe whole system
m compare
to connventional PWWM technique. The design criteria c of
feedback current & voltage loops are discussed. The whole
system has been tested by means of simulation using Power-
Sim Power Electronics & Drives simulation package. Even
though the simulator restricted the implementation of the
control law, the results are encouraging. Reduced Total
Harmonic Distortion (THD) over the conventional boost
converter is significant at low line. Better regulated dc voltage
on constant power load is observed. Here the results are
encouraging; there is indication that if a practical system is
realized with the freedom of practical hardware, excellent
results will be achieved.

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