Boundary-Scan Speech

Electronic subject
Second course, Degree in
Electrical Engineering
Angel Moises Galvany Menor
01/12/2011

Page 1 of 3
Angel Mosies Galvany Menor






Work about Boundary Scan Language and The Joint Test Action
Group
1



On the following text, I will try to expose a brief explanation about the general idea that
we got at the speech about Boundary-Scan method and what it is for. This explanation
will be based in the speech we received the last day from the hand of Jouko Kotkansalo,
teacher in JYVSKYLN AMMATTIKORKEAKOULU.
The talk was quite interesting and extensive, and it was made in a foreign language so
maybe I couldnt have caught some ideas or specific information.



1
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Boundary-Scan Speech
Electronic subject
Second course, Degree in
Electrical Engineering
Angel Moises Galvany Menor
01/12/2011

Page 2 of 3
Angel Mosies Galvany Menor


-What is it? And what is it for?
As Jouko explained us, Boundary scan is a method for testing interconnects printed on boards or
sub-blocks inside integrated circuits. Its also used as debugging method to watch integrated
circuit pin states, measure its voltage, or analyze sub-blocks inside an integrated circuit. And its
language (Boundary-Scan Description Language BSDL) describes the interface of the chip, so
this creates an interface between the unit under test and the test software.
This doesnt mean the BSDL describe on the chip system logic. It describes the properties of the
Boundary-Scan register with its terminal connections. It is with VHDL where we can describe
the logic functions of the chip.
And the Joint Test Action Group (JTAG) is something like the method for testing printed circuit
board in industrial production using the Boundary-Scan stuff. It follows a debugging system
applied on the whole board.
For this purpose, its absolutely necessary that the board take all the pins connected as
electronic logic, linked together in a set called the Boundary Scan chain.


Boundary-Scan Speech
Electronic subject
Second course, Degree in
Electrical Engineering
Angel Moises Galvany Menor
01/12/2011

Page 3 of 3
Angel Mosies Galvany Menor

-How is it structured?
This is structured such that each boundary-scan memory element could capture data on tis
parallel input, update data onto its parallel output, to have a serially scan data to its neighbor and
behave transparently. It has pins for Test data In, Test Clock, Test Mode Select and Test Data
Out.
When you connect it to one another, the signal Out have to be connected to the following in,
forming a chain. Sometimes you need Vcc and Ground pins, it depends on the download wire. It
forms a whole cell which makes four basic operations; transparent mode, update capture and
serial shift mode.

As the Professor said, the machine to carry out a full test in all circuit board produced is very
expensive. But its necessary to expect the product works as we expect it to, to fulfill the
customers needs and expectations and to ensure compatibility and quality.
And Using Boundary-scan and self-tests has great advantages such as reducing test debugging
time (it only uses 4 pins instead of thousand that it has), so the number of test connections are
reduced. And this contributes to reduce testing costs.