Beruflich Dokumente
Kultur Dokumente
ME1402
UNIT-3
1!hat are the characteristics o" ne#ati$e "eed %ack&'n(d-
200)*200+,
1 -educe the noise and distortion*etc
2 1.0de#ree /hase shi" t to %e /ro$ided
2write the ana0o#ous e0ectrica0 e0ements in "orce $o0ta#e
ana0o#1 "or the e0ements o" mechanica0 trans0ationa0
s1stem& 'n(d-200)*200+,
It re/resents the t1/es o" "orces e2/erienced when
o%3ect is mo$ed a#ainst "rictiona0 "orces or when the
o%3ect is /ushed throu#h a "0uid
34eri$e the equation "or a trans0ationa0 mechanica0
s1stem mode0 with s/rin# and mass'N(4-200.,
It re/resents the sti""ness o" a s1stemThe sti""ness is
#i$en %1 the re0eationshi/ %etween the "orce '5,used to
e2tend or com/ress a s/rin# and the resu0tin# e2tension or
com/ression'6,
572* 5892
4:i$e an e2am/0e "or two ste/ mode contro0 unit 'N(4-
200.,
-oom ;eatin# s1stem is an e2am/0e "or two ste/ mode
contro0 unit
<!hat are the $arious contro0 modes used in
mechatronics contro0 s1stem&'=(M-2010,
>ro/otiona0 contro0 mode
Inte#ra0 contro0 mode
4eri$ati$e contro0 mode
?N-?55 Mode
>ro/otiona0 Inte#ra0 deri$ati$e contro0 mode'>I4,
6!hat are the %ui0din# %0ocks in e0ectrica0 s1stem&'N(4-
2010,
-esistor
Inductor
@a/acitor
):i$e some e2am/0es "or e0ectro mechanica0 s1stems&
' N(4-2010,
>otentiometers*motors*#enerators
. !hat are the %ui0din# %0ocks in mechanica0 or
trans0ationa0 s1stem&'N(4-2011,
A/rin#s
4ash/ots and
Masses
+4e"ine ada/ti$e contro0'N(4-2011,
The contro0 s1stem which can ada/t chan#es and it can
chan#e its /arameters de/endin# on the situation is known
as ada/ti$e conto0 s1stem and the method is ca00ed
ada/ti$e contro0
10!hat is stack /oint re#ister&'M(B-2012,
It is a reser$ed area o" the memor1 in the -=M whose
tem/orar1 in"ormation ma1 %e stored= 16 CIT Atack
/ointer is used to ho0d the addresso" the most recent stack
entr1
Unit 4
1what are the criteria that need to %e considered "or
se0ectin# a >D@&
=nsE The criteria that need to %e considered "or se0ectin# a
>D@ is
is1stem de"inition*
iichoosin# the in/ut and out/ut hardware*
iiiana0o# in/ut(out/ut modu0e*
i$ in/ut and out/ut timin# consideration
2draw the 0adder run#s to re/resent E two switches are
norma001 o/en and %oth ha$e to %e c0osed "or a motor to
o/erate
------F G--------------F G----------------' ,
9e1 Awitch 1 9e1 Awitch 2 4oor Motor
The a%o$e rea0iHes the "unctionE 4oor Motor 8 9e1
Awitch 1 =N4 9e1 Awitch 2
This circuit shows two ke1 switches that securit1 #uards
mi#ht use to acti$ate an e0ectric motor on a %ank $au0t
door !hen the norma001 o/en contacts o" %oth switches
c0ose* e0ectricit1 is a%0e to "0ow to the motor which o/ens
the door
3desi#n a >D@ timin# circuit that wi00 switch a out/ut on
"or 10 seconds and then switch it o""
IN4UAT-I=D AT?>(AT=-TFE4IT G
In common industria0 0atchin# start(sto/ 0o#ic we ha$e a
IstartI %utton to turn on a motor contactor* and a Isto/I
%utton to turn o"" the contactor
!hen the IstartI %utton is /ushed the in/ut #oes true* $ia
the Isto/I %utton N@ contact !hen the IrunI in/ut
%ecomes true the sea0-in IrunI N? contact in /ara00e0 with
the IstartI N? contact wi00 c0ose maintainin# the in/ut
0o#ic true '0atched or sea0ed-in, ="ter the circuit is
0atched the Isto/I %utton ma1 %e /ushed causin# its N@
contact to o/en and consequent01 the in/ut to #o "a0se
The IrunI N? contact then o/ens and the circuit 0o#ic
returns to its quiescent state
--J----F G--J----FKG----' ,
L start L sto/ run
L L
J----F G--J
run
-------F G--------------' ,
run motor
The a%o$e rea0iHes the "unctionE run 8 ' start ?- run ,
=N4 ' N?T sto/ ,
Note the use o" /arenthesis to #rou/ the 0o#ica0 ?-
"unction %e"ore e$a0uatin# the 0o#ica0 =N4 "unction
'which has a hi#her order o" o/eration /riorit1, =0so
note the use o" NOT to re/resent the Isto/I N@
contact 0o#ic
This 0atch con"i#uration is a common idiom in 0adder
0o#ic In 0adder 0o#ic it is re"erred to as sea0-in 0o#ic The
ke1 to understandin# the 0atch is in reco#niHin# that
IstartI switch is a momentar1 switch 'once the user
re0eases the %utton* the switch is o/en a#ain, =s soon as
the IrunI so0enoid en#a#es* it c0oses the IrunI N?
contact* which 0atches the so0enoid on The IstartI switch
o/enin# u/ then has no e""ect
4what are the 0o#ic "unctions that can %e o%tained %1
usin# switches in series&
=nsE The 0o#ic "unctions that can %e o%tained %1 usin#
switches in series =N4 *N?T* N=N4
<what do 1ou mean %1 e0ectronic counter&
=ns E E$er since e0ectronics ha$e %een used in %att0e in an
attem/t to #ain su/eriorit1 o$er the enem1* e""ort has
%een s/ent on techniques to reduce the e""ecti$eness o"
those e0ectronics More recent01* sensors and wea/ons are
%ein# modi"ied to dea0 with this threat ?ne o" the most
common t1/es o" E@M is radar 3ammin# or s/oo"in#
6wh1 are >D@Ms considered suita%0e "or sho/ "0oor&
= Programmable Logic Controller* PLC or
Programmable Controller is a di#ita0 com/uter used "or
automation o" e0ectromechanica0 /rocesses* such as
contro0 o" machiner1 on "actor1 assem%01 0ines*
amusement rides* or 0i#ht "i2tures The a%%re$iation
I>D@I and the term I>ro#ramma%0e Do#ic @ontro00erI are
re#istered trademarks o" the =00en-Crad0e1 @om/an1
'-ockwe00 =utomation, >D@s are used in man1
industries and machines Un0ike #enera0-/ur/ose
com/uters* the >D@ is desi#ned "or mu0ti/0e in/uts and
out/ut arran#ements* e2tended tem/erature ran#es*
immunit1 to e0ectrica0 noise* and resistance to $i%ration
and im/act >ro#rams to contro0 machine o/eration are
t1/ica001 stored in %atter1-%acked-u/ or non-$o0ati0e
memor1 = >D@ is an e2am/0e o" a hard rea0 time s1stem
since out/ut resu0ts must %e /roduced in res/onse to in/ut
conditions within a 0imited time* otherwise unintended
o/eration wi00 resu0t
11 what is shi"t re#ister& ;ow man1 data is required "or
a shi"t re#ister&
Ahi"t re#ister can %e used where sequence o" o/erations is
required or mo$ement or track the "0ow o" /arts and
in"ormation
It requires 3 in/utsE 'i, "i0e address o" the %it arra1
'ii, @ontro0 =ddress o" contro0
structure
'iii, Cid address - =ddress o" source
%it
'i$, Den#th Num%er o" %its in %it
arra1
Ahi"t re#ister c
124raw the 0adder run#s to re/resent the "o00owin#E a
motor is switched on %1 /ressin# s/rin# return /ush
%utton switch*and the mortor remains on unti0 another
s/rin# return /ush %utton switch is /ressed
I N
---- ---- M
M
M
M
M
INNN NNNNNNNNNNNI INNNNNNNNN MNNNNNNNI
INNNI(I-----------------I N-
I
13o%tain a N?- 0o#ic "unction usin# 0adder /ro#ram&
=ns EI" we ha$e an ?- #ate %1 a N?T #ate wi00 in$ert the
out/uts o" the ?- #ate as i00ustrated in the truth ta%0e
there"ore the com%ination o" ?- and not #ates is termed
a N?- #ate
14 what is meant %1 0adder dia#ram&
=ns E0adder dia#rams is the most common01 used
/ro#rammin# method e$o0$ed "rom e0ectrica0 re0a1
circuits and is in the "orm o" #ra/hica0 0an#ua#e
?r
Dadder dia#ram is a network o" contacts and coi0s are
arran#ed on run#s %etween two $ertica0 0ines ca00ed rai0s
used
1<what are the ad$anta#e o" /ro#ramma%0e 0o#ic
contro00er o$er their re0a1 s1stem&
'i, -ewirin# shou0d %e easi01 done in >D@
'ii, No $ertica0 connections are a00owed
'iii, In >D@ *there must a0wa1s %e one out/ut on each
0ine
1)#i$e t1/ica0 s/eci"ication o" /ro#ramma%0e 0o#ic
contro00er
'i, @entra0 /rocessin# unit
'ii, In/ut ( out/ut modu0es
'iii, >ro#rammer ( Monitor
1.draw the 0adder dia#ram "or de0a1 o"" timer
!hen the contact IN1 is c0osed* the contact wi00
ener#ise the timer T1 and ho0ds the out/ut 0am/ ?N "or
s/eci"ied set $a0ue o" 10 sec The action o" an ?55 de0a1
timer is to de0a1 settin# the 0am/ ?55
1+%rie" on EE>-?M
20write short notes on %asic arran#ement o" >D@ s1stem
'i, @entra0 /rocessin# unit
'ii, In/ut ( out/ut modu0es
'iii, >ro#rammer ( Monitor
Unit <E
1di""erntiate %etween traditiona0 and mechatronics
desi#ns with e2am/0e
A0 no Traditiona0
desi#n
Mechatronics desi#n
1 It is %ased on
the traditiona0
mechanica0
e0ements such
as #ears
*s/rin#
*0e$ers*etcO
It is %ased on the
mechanica0*e0ectronics*com/uter
techno0o#1 contro0 en#ineerin#
2 It in$o0$es
more
com/0icated
mechanisms
and mo$in#
com/onents
It in$o0$es 0ess com/0icated
mechanisms and mo$in#
com/onents
2how a o/erated switch is re/0aced with >D@& Ahow the
0adder dia#ram
In >D@ s1stem*the time duration can %e easi01
ad3usted %1 chan#in# the timer /reset $a0ues in the
/ro#ram whereas the trationa0 s1stem requires $arious
siHe o" cams
3 0ist down the $arious mechatronics e0ements in an
automatic camera
i, auto "oucssin# mechanism contro0
ii, =/erture dri$e
iii, Ahutter dri$e
i$, mirror dri$e
< mention an1 "our statements in /ro%0em de"inition o"
mechatronics s1stem desi#n
i, Need "or desi#n
ii, =na01sis o" /ro%0em
iii, >re/aration o" s/eci"ication
i$, :erneration o" /ossi/0e so0ution
6what are the $arious mo$ements o" ro%ots&
i, cw and acw rotation o" the ro%ot on its %ase
ii, 0inear mo$ement o" the arm horiHonta001
iii, u/ and down mo$ement o" the arm
i$, o/en and c0ose mo$ement o" the #ri//er
)identi"1 the sensor * si#na0 conditioner and dis/0a1
e0ements in the %ourden /reasure #au#e
Aensor Curdon tu%e actin# as sensor
Ai#na0 conditioner ratchet P /inion mechanism is
actin# as si#na0 conditioner
4is/0a1 e0ements >ointer is the dis/0a1 e0ement
.0ist the ad$anta#es o" mecharonics desi#n o$er
traditiona0 desi#n
i, Mechatronics s1stem ser$es the /ur/ose e""ecti$e01
with hi#h dimensiona0 accurac1 requirements
ii, It /ro$ides increased /roducti$it1 in the industr1
iii, it "aci0itation automation in the /roduction
*assem%01 and qua0it1 contro0
+ what are the %asic /rinci/0e in$o0$ed in mechatronics
desi#n&
Need o" desi#n*ana01sis o" /ro%0ems*/re/aration o"
s/eci"ication*#eneration o" /ossi%0e so0ution*se0ection o"
suita%0e so0ution*/roduction o" detai0ed
so0ution*/roduction o" workin# drawin#*im/0ementation
o" desi#n
10what are em%edded s1stems&
The hardware which is desi#ned "or /articu0ar
a//0ications is known as em%edded s1stem
11what is timed switch&
It is a de$ice which is used to switch on a motor "or
some /rescri%ed time
120ist the se$en modu0es o" mechatronics desi#n
a//roach
Need o" desi#n*ana01sis o" /ro%0ems*/re/aration o"
s/eci"ication*#eneration o" /ossi%0e so0ution*se0ection o"
suita%0e so0ution*/roduction o" detai0ed
so0ution*/roduction o" workin# drawin#*im/0ementation
o" desi#n
16what are the "actors to %e considered in the desi#n o"
mechatronics s1stem&
?%3ects to %e hand0ed*actuators*/ower source*ran#e
o" #ri//in#
"orce*/ositionin#*maintenance*en$ironment*tem/
/rotection*materia0s
1.name an1 "our im/artant sensor used in the /ick and
/0ace ro%ot
T-I=@*DE4*Ao0enoid*M6.;@11
1+mention the %asic com/onents o" an1 industria0 ro%ot
Docomotion*sensors*/erce/tion*know0ed#e*/0annin#*auto
nom1*co00a%oration
20denote on inte00i#ent mechatronics s1stem
Mechanica0 0inka#es*dri$es
;1drau0ic and /neumatic actuators
E0ectrica0 motors*switches
16 marks
Unit 3
1aihow does a microcontro00er di""er "rom a
micro/rosser&
Difference between microprocessor and
microcontroller
Micro/rocessor is an I@ which has on01 the @>U inside
them ie on01 the /rocessin# /owers such as Inte0Ms
>entium 1*2*3*4* core 2 duo* i3* i< etc These
micro/rocessors donMt ha$e -=M* -?M* and other
/eri/hera0 on the chi/ = s1stem desi#ner has to add them
e2terna001 to make them "unctiona0 =//0ication o"
micro/rocessor inc0udes 4eskto/ >@Ms* Da/to/s* note/ads
etc
Cut this is not the case with Microcontro00ers
Microcontro00er has a @>U* in addition with a "i2ed
amount o" -=M* -?M and other /eri/hera0s a00
em%edded on a sin#0e chi/ =t times it is a0so termed as a
mini com/uter or a com/uter on a sin#0e chi/ Toda1
di""erent manu"acturers /roduce microcontro00ers with a
wide ran#e o" "eatures a$ai0a%0e in di""erent $ersions
Aome manu"acturers are =TMED* Microchi/* TI*
5reesca0e* >hi0i/s* Motoro0a etc
Microcontro00ers are desi#ned to /er"orm s/eci"ic tasks
A/eci"ic means a//0ications where the re0ationshi/ o"
in/ut and out/ut is de"ined 4e/endin# on the in/ut* some
/rocessin# needs to %e done and out/ut is de0i$ered 5or
e2am/0e* ke1%oards* mouse* washin# machine* di#icam*
/endri$e* remote* microwa$e* cars* %ikes* te0e/hone*
mo%i0es* watches* etc Aince the a//0ications are $er1
s/eci"ic* the1 need sma00 resources 0ike -=M* -?M* I(?
/orts etc and hence can %e em%edded on a sin#0e chi/
This in turn reduces the siHe and the cost
Micro/rocessor "ind a//0ications where tasks are
uns/eci"ic 0ike de$e0o/in# so"tware* #ames* we%sites*
/hoto editin#* creatin# documents etc In such cases the
re0ationshi/ %etween in/ut and out/ut is not de"ined The1
need hi#h amount o" resources 0ike -=M* -?M* I(?
/orts etc
The c0ock s/eed o" the Micro/rocessor is quite hi#h as
com/ared to the microcontro00er !hereas the
microcontro00ers o/erate "rom a "ew M;H to 30 to <0
M;H* toda1Ms micro/rocessor o/erate a%o$e 1:;H as
the1 /er"orm com/0e2 tasks -ead more a%out what is
microcontro00er
Comparing microcontroller and microprocessor in
terms o" cost is not 3usti"ied Undou%ted01 a
microcontro00er is "ar chea/er than a micro/rocessor
;owe$er microcontro00er cannot %e used in /0ace o"
micro/rocessor and usin# a micro/rocessor is not ad$ised
in /0ace o" a microcontro00er as it makes the a//0ication
quite cost01 Micro/rocessor cannot %e used stand a0one
The1 need other /eri/hera0s 0ike -=M* -?M* %u""er* I(?
/orts etc and hence a s1stem desi#ned around a
micro/rocessor is quite cost01
iidraw a %0ock dia#ram o" a %asic microcontro00er and
e2/0ain the "unction o" each su%s1stem
D?@9 4I=:-=M ?5 .0<1 MI@-?@?NT-?DDE-E
Microcontro00er .0<1 %0ock dia#ram is shown %e0ow
DetMs ha$e a c0oser 0ook at each P e$er1 "raction or %0ock
o" this desi#nE
.0<1 MI@-?@?NT-?DDE- CD?@9 4I=:-=M
E6>D=N=TI?NE
@>U '@ENT-=D >-?@EAA?- UNIT,E
=s 1ou ma1 %e "ami0iar that @entra0 >rocessor Unit or
@>U is the mind o" an1 /rocessin# machine It scrutiniHes
and mana#es a00 /rocesses that are carried out in the
Microcontro00er User has no /ower o$er the "unctionin#
o" @>U It inter/rets /ro#ram /rinted in stora#e s/ace
'-?M, and carries out a00 o" them and do the /ro3ected
dut1
INTE--U>TAE
=s the headin# /ut "orward* Interru/t is a su%-routine ca00
that reads the Microcontro00erMs ke1 "unction or 3o% and
he0/s it to /er"orm some other /ro#ram which is e2tra
im/ortant at that /oint o" time The characteristic o"
Interru/t is e2treme01 constructi$e as it aids in emer#enc1
cases Interru/ts /ro$ides us a method to /ost/one or
de0a1 the current /rocess* carr1 out a su%-routine task and
then a00 o$er a#ain restart standard /ro#ram
im/0ementation
The Micro-contro00er .0<1 can %e assem%0ed in such a
manner that it momentari01 sto/s or %reak the core
/ro#ram at the ha//enin# o" interru/t !hen su%-routine
task is "inished then the im/0ementation o" core /ro#ram
initiates automatica001 as usua0 There are < interru/t
su//0ies in .0<1 Microcontro00er* two out o" "i$e are
/eri/hera0 interru/ts* two are timer interru/ts and one is
seria0 /ort interru/t
MEM?-QE
Micro-contro00er needs a /ro#ram which is a set o"
commands This /ro#ram en0i#htens Microcontro00er to
/er"orm /recise tasks These /ro#rams need a stora#e
s/ace on which the1 can %e accumu0ated and inter/ret %1
Microcontro00er to act u/on an1 s/eci"ic /rocess The
memor1 which is %rou#ht into /0a1 to accumu0ate the
/ro#ram o" Microcontro00er is reco#niHed as >ro#ram
memor1 or code memor1 In common 0an#ua#e itMs a0so
known as -ead ?n01 Memor1 or -?M
Micro-contro00er a0so needs a memor1 to amass data or
o/erands "or the short term The stora#e s/ace which is
em/0o1ed to momentari01 data stora#e "or "unctionin# is
acknow0ed#ed as 4ata Memor1 and we em/0o1 -andom
=ccess Memor1 or -=M "or this /rinci/0e reason
Microcontro00er .0<1 contains code memor1 or /ro#ram
memor1 49 so that is has 49C -om and it a0so com/rise
o" data memor1 '-=M, o" 12. %1tes
CUAE
5undamenta001 Cus is a #rou/ o" wires which "unctions as
a communication cana0 or mean "or the trans"er 4ata
These %uses com/rise o" .* 16 or more ca%0es =s a resu0t*
a %us can %ear . %its* 16 %its a00 to#ether There are two
t1/es o" %usesE
1. Address Bus: Microcontro00er .0<1 consists o" 16 %it
address %us It is %rou#ht into /0a1 to address
memor1 /ositions It is a0so uti0iHed to transmit the
address "rom @entra0 >rocessin# Unit to Memor1
2. Data Bus: Microcontro00er .0<1 com/rise o" . %its
data %us It is em/0o1ed to cart data
?A@IDD=T?-E
=s we a00 make out that Microcontro00er is a di#ita0 circuit
/iece o" equi/ment* thus it needs timer "or its "unction
5or this "unction* Microcontro00er .0<1 consists o" an on-
chi/ osci00ator which toi0s as a time source "or @>U
'@entra0 >rocessin# Unit, =s the /roducti$it1 thum/s o"
osci00ator are stead1 as a resu0t* it "aci0itates harmoniHed
em/0o1ment o" a00 /ieces o" .0<1 Microcontro00er
In/ut(out/ut >ortE =s we are acquainted with that
Microcontro00er is em/0o1ed in em%edded s1stems to
mana#e the "unctions o" de$ices Thus to #ather it to other
machiner1* #ad#ets or /eri/hera0s we need I(?
'in/ut(out/ut, inter"acin# /orts in Micro-contro00er 5or
this "unction Micro-contro00er .0<1 consists o" 4
in/ut(out/ut /orts to unite it to other /eri/hera0s
Timers(@ountersE Micro-contro00er .0<1 is incor/orated
with two 16 %it counters P timers The counters are
se/arated into . %it re#isters The timers are uti0iHed "or
measurin# the inter$a0s* to "ind out /u0se width etc
E6>D=N=TI?N ?N .0<1 >IN 4I=:-=ME
5or e2/0ainin# the /in dia#ram and /in con"i#uration o"
microcontro00er .0<1* we are takin# into de0i%eration a 40
/in 4ua0 in0ine /acka#e '4I>, Now 0etMs stud1 throu#h
/in con"i#uration in %rie"E-
Pins 1 :! reco#niHed as >ort 1 4i""erent "rom other
/orts* this /ort doesnMt /ro$ide an1 other /ur/ose >ort 1
is a domestica001 /u00ed u/* quasi %i directiona0
In/ut(out/ut /ort
Pin ":! =s made c0ear /re$ious01 -EAET /in is uti0iHed to
set the micro-contro00er .0<1 to its /rimar1 $a0ues*
whereas the micro-contro00er is "unctionin# or at the ear01
%e#innin# o" a//0ication The -EAET /in has to %e set
e0e$ated "or two machine rotations
Pins 1# 1$:! reco#niHed as >ort 3 This /ort a0so
su//0ies a num%er o" other "unctions such as timer in/ut*
interru/ts* seria0 communication indicators T24 P -24*
contro0 indicators "or outside memor1 inter"acin# !- P
-4* etc This is a domestic /u00 u/ /ort with quasi %i
directiona0 /ort within
Pins 1 and 1":! These are em/0o1ed "or inter"acin# an
outer cr1sta0 to #i$e s1stem c0ock
Pin %#:! Tit0ed as Rss it s1m%o0iHes #round '0 R,
association
Pins! %1!%:! reco#niHed as >ort 2 '> 20 > 2), other
than ser$in# as In/ut(out/ut /ort* senior order address %us
indicators are mu0ti/0e2ed with this quasi %i directiona0
/ort
Pin! %":! >ro#ram Atore Ena%0e or >AEN is em/0o1ed to
inter/ret si#n "rom outer /ro#ram memor1
Pin!&#:! E2terna0 =ccess or E= in/ut is em/0o1ed to
/ermit or /rohi%it outer memor1 inter"acin# I" there is no
outer memor1 need* this /in is dra##ed hi#h %1 0inkin# it
to Rcc
Pin!&1:! =ka =ddress Datch Ena%0e or =DE is %rou#ht
into /0a1 to de-mu0ti/0e2 the address data indication o"
/ort 0 '"or outer memor1 inter"acin#, Two =DE thro%s
are o%taina%0e "or e$er1 machine rotation
Pins &%!&": reco#niHed as >ort 0 '>00 to >0), other
than ser$in# as In/ut(out/ut /ort* 0ow order data P
address %us si#na0s are mu0ti/0e2ed with this /ort 'to
/ro$ide the use o" outer memor1 inter"acin#, This /in is
a %i directiona0 In/ut(out/ut /ort 'the sin#0e one in
microcontro00er .0<1, and outer /u00 u/ resistors are
necessar1 to uti0iHe this /ort as In/ut(out/ut
Pin!'#: termed as Rcc is the chie" /ower su//01 C1 and
0ar#e it is J<R 4@
?r
%draw the %0ock dia#ram o" .0.< micro/roccesor and
e2/0ain the "unction o" each e0ement
A(C)*T+C)T,(+ or -,NCT*ONAL BLOC.
D*A/(A0 O- #1
T2e functional bloc3 diagram or arc2itec2ture of #1
0icroprocessor is 4er5 important as it gi4es t2e
complete details about a 0icroprocessor6 -ig6 s2ows
t2e Bloc3 diagram of a 0icroprocessor6
#1 Bus 7tructure:
Address Bus:
T2e address bus is a group of 18 lines generall5
identified as A# to A116
T2e address bus is unidirectional: bits flow in one
direction!from t2e 0P, to perip2eral de4ices6
T2e 0P, uses t2e address bus to perform t2e first
function: identif5ing a perip2eral or a memor5
location6
Data Bus:
T2e data bus is a group of eig2t lines used for data
flow6
T2ese lines are bi!directional ! data flow in bot2
directions between t2e 0P, and memor5 and
perip2eral de4ices6
T2e 0P, uses t2e data bus to perform t2e second
function: transferring binar5 information6
T2e eig2t data lines enable t2e 0P, to
manipulate !bit data ranging from ## to -- 9% :
%18 numbers;6
T2e largest number t2at can appear on t2e data
bus is 111111116
Control Bus:
T2e control bus carries s5nc2roni<ation signals
and pro4iding timing signals6
T2e 0P, generates specific control signals for
e4er5 operation it performs6 T2ese signals are
used to identif5 a de4ice t5pe wit2 w2ic2 t2e 0P,
wants to communicate6
(egisters of #1:
T2e #1 2a4e si= general!purpose registers to
store !bit data during program e=ecution6
T2ese registers are identified as B> C> D> +> )> and
L6
T2e5 can be combined as register pairs!BC> D+>
and )L!to perform some 18!bit operations6
Accumulator 9A;:
T2e accumulator is an !bit register t2at is part of
t2e arit2metic?logic unit 9AL,;6
T2is register is used to store !bit data and to
perform arit2metic and logical operations6
T2e result of an operation is stored in t2e
accumulator6
-lags:
T2e AL, includes fi4e flip!flops t2at are set or
reset according to t2e result of an operation6
T2e microprocessor uses t2e flags for testing t2e
data conditions6
T2e5 are @ero 9@;> Carr5 9CA;> 7ign 97;> Parit5
9P;> and Au=iliar5 Carr5 9AC; flags6 T2e most
commonl5 used flags are 7ign> @ero> and Carr56
T2e bit position for t2e flags in flag register is>
167ign -lag 97;:
After e=ecution of an5 arit2metic and logical
operation> if D$ of t2e result is 1> t2e sign flag
is set6 Ot2erwise it is reset6
D$ is reser4ed for indicating t2e signB t2e
remaining is t2e magnitude of number6
*f D$ is 1> t2e number will be 4iewed as negati4e
number6 *f D$ is #> t2e number will be 4iewed
as positi4e number6
%6@ero -lag 9<;:
*f t2e result of arit2metic and logical operation is
<ero> t2en <ero flag is set ot2erwise it is reset6
&6Au=iliar5 Carr5 -lag 9AC;:
*f D& generates an5 carr5 w2en doing an5
arit2metic and logical operation> t2is flag is set6
Ot2erwise it is reset6
'6Parit5 -lag 9P;:
*f t2e result of arit2metic and logical operation
contains e4en number of 1Cs t2en t2is flag will be
set and if it is odd number of 1Cs it will be reset6
16Carr5 -lag 9CA;:
*f an5 arit2metic and logical operation result an5
carr5 t2en carr5 flag is set ot2erwise it is
reset6
2aideri$e the mathematica0 mode0 "or a machine
mounted on the #round to stud1 the e""ects o" #round
distur%ances on the machine %ed dis/0acement
iicom/are the contro0 s1stem /er"ormance "or a s1stem
with /ro/ortiona0 contro0 and a s1stem with inte#ra0
contro0
?"ten contro0 s1stems are desi#ned usin# >ro/ortiona0
@ontro0 In this contro0 method* the contro0 s1stem acts in
a wa1 that the contro0 e""ort is /ro/ortiona0 to the error
Qou shou0d not "or#et that /hrase The contro0 e""ort is
/ro/ortiona0 to the error in a /ro/ortiona0 contro0 s1stem*
and thatSs what makes it a /ro/ortiona0 contro0 s1stem I"
it doesnSt ha$e that /ro/ert1* it isnSt a /ro/ortiona0 contro0
s1stems
;ereMs a %0ock dia#ram o" such a s1stem In this
0esson we wi00 e2amine how a /ro/ortiona0 contro0 s1stem
works
=n inte#ra0 contro00er has one $er1 #ood qua0it1 =n
inte#ra0 contro00er wi00 norma001 ensure Hero AAE in a
contro0 s1stem - "or ste/ 'constant, in/uts
=n inte#ra0 contro00er is not /articu0ar01 di""icu0t to
im/0ement
In an ana0o# s1stem* an inte#ra0 contro0 s1stem
inte#rates the error si#na0 to #enerate the contro0
si#na0 I" the error si#na0 is a $o0ta#e* and the contro0
si#na0 is a0so a $o0ta#e* then a /ro/ortiona0 contro00er
is 3ust an ana0o# inte#rator
In a di#ita0 contro0 s1stem* an inte#ra0 contro0 s1stem
com/utes the error "rom measured out/ut and user
in/ut to a /ro#ram* and inte#rates the error usin#
some standard inte#ration a0#orithm* then #enerates
an out/ut(contro0 si#na0 "rom that inte#ration
Inte#ra0 contro00ers ha$e these /ro/erties
The contro00er inte#rates the error as shown in the
%0ock dia#ram o" an e2am/0e s1stem %e0ow
o The inte#ra0 contro00er has a trans"er "unction o"
9
i
(s
Ao* the actuatin# si#na0 'the in/ut to the s1stem %ein#
contro00ed, is /ro/ortiona0 to the inte#ra0 o" the error
!e can e2amine some o" the "eatures o" inte#ra0
contro0 usin# an inte#ra0 contro00er
?r
%ideri$e the di""erentia0 equation #o$ernin# the
mechanica0 s1stem o" an e0ectric motor
iie2/0ain the charecteristics o" >I4 contro00er
= proportional!integral!deri4ati4e controller 'P*D
controller, is a #eneric contro0 0oo/ "eed%ack mechanism
'contro00er, wide01 used in industria0 contro0 s1stems =
>I4 contro00er ca0cu0ates an IerrorI $a0ue as the
di""erence %etween a measured /rocess $aria%0e and a
desired set/oint The contro00er attem/ts to minimiHe the
error %1 ad3ustin# the /rocess contro0 in/uts
The >I4 contro00er ca0cu0ation a0#orithm in$o0$es three
se/arate constant /arameters* and is accordin#01
sometimes ca00ed t2ree!term controlE the /ro/ortiona0*
the inte#ra0 and deri$ati$e $a0ues* denoted P, I, and D.
Aim/01 /ut* these $a0ues can %e inter/reted in terms o"
timeE P de/ends on the present error* I on the
accumu0ation o" past errors* and D is a /rediction o"
future errors* %ased on current rate o" chan#e
F1G
The
wei#hted sum o" these three actions is used to ad3ust the
/rocess $ia a contro0 e0ement such as the /osition o" a
contro0 $a0$e* a dam/er* or the /ower su//0ied to a
heatin# e0ement
In the a%sence o" know0ed#e o" the under01in# /rocess* a
>I4 contro00er has historica001 %een considered to %e the
%est contro00er
F2G
C1 tunin# the three /arameters in the
>I4 contro00er a0#orithm* the contro00er can /ro$ide
contro0 action desi#ned "or s/eci"ic /rocess requirements
The res/onse o" the contro00er can %e descri%ed in terms
o" the res/onsi$eness o" the contro00er to an error* the
de#ree to which the contro00er o$ershoots the set/oint*
and the de#ree o" s1stem osci00ation Note that the use o"
the >I4 a0#orithm "or contro0 does not #uarantee o/tima0
contro0 o" the s1stem or s1stem sta%i0it1
Aome a//0ications ma1 require usin# on01 one or two
actions to /ro$ide the a//ro/riate s1stem contro0 This is
achie$ed %1 settin# the other /arameters to Hero = >I4
contro00er wi00 %e ca00ed a >I* >4* > or I contro00er in the
a%sence o" the res/ecti$e contro0 actions >I contro00ers
are "air01 common* since deri$ati$e action is sensiti$e to
measurement noise* whereas the a%sence o" an inte#ra0
term ma1 /re$ent the s1stem "rom reachin# its tar#et
$a0ue due to the contro0 action
3aiwith a %0ock dia#ram*e2/0ain the use o"
microcontro00er "or the house ho0d a//0ication
ii0ist $arious a//0ications o" microcontro00er
=>>DI@=TI?NA ?5 MI@-?@?NT-?DDE-AE
Microcontro00ers are most01 used in "o00owin# e0ectronic
equi/ments E
Mo%i0e >hones
=uto Mo%i0es
@4(4R4 >0a1ers
!ashin# Machines
@ameras
In @om/uters-T Modems and 9e1%oard @ontro00ers
Aecurit1 =0arms
E0ectronic Measurement Instruments
Microwa$e ?$en
- Aee more atE
htt/E((wwwwiki"orucom(2012(10(a//0ications-o"-
microcontro00erhtm0Usthash-t;M2s#id/u"
?r
%iwrite the /ro#ram to di$ide two .-%it num%ers and to
store resu0t in memor1 a#ain %1 micro/rocessor usin#
.0.<
MI@-?>-?@EAA?- - >-?:-=M T? 4IRI4E T!?
NUMCE-A ?5 . CIT 4=T=
=IME To write an assem%01 0an#ua#e /ro#ram to di$ide
two num%ers o" . %it data
=>>=-=TUA -EVUI-E4E Micro/rocessor .0.< Trainer
9it
>-?@E4U-EE
>-?CDEM =N=DQAIAE
WThe di$ision in .0.< is /er"ormed as re/eated
su%traction The di$idend is stored in = re#ister and
di$isor in C-re#ister
WThe initia0 $a0ue o" quotient is assumed as Xero
WAu%traction shou0d %e /er"ormed on01 when the di$idend
is #reater than di$isor
WAu%traction is continued unti0 di$idend is 0esser than the
di$isor
W5or each su%traction quotient is incremented %1 one
WThen store the quotient and remainder in memor1
=D:?-IT;ME
1Doad the di$isor in the accumu0ator and mo$e it to C
re#ister
2Doad the di$idend in accumu0ator
3@0ear @ re#ister to account "or quotient
4@heck whether di$isor is 0ess than di$idend
<I" di$isor is 0ess than the di$idend #o to ste/ .*
otherwise #o to ne2t ste/
6Increment the contents o" @ re#ister' quotient,
):o to ste/ 4
.Atore the content o" accumu0ator 'remainder, in
memor1
+Mo$e the content o" @ re#ister 'quotient, to
accumu0ator and store in memor1
10Ato/
T=CUD=TI?NE
IN>UT IN>UT ?UT>UT
4ecima0;e2a4ecima0;e2aVuotient-emainder
=AAEMCDQ D=N:U=:E >-?:-=ME 4IRI4E T!?
NUMCE-A ?5 . CIT 4=T=
=44-EAA?>@?4EMNEM?NI@A 4EA@-I>TI?N
.100 3= D4= .201; D?=4 T;E
.101 01 =@@UMUD=T?-
.102 .2
.103 4) M?R =*C
:ET T;E
4IRIA?- IN C
-E:IATE-
.104 3= D4= .200;
:ET T;E
4IRI4EN4 IN =
.10< 00 -E:IATE-
.106 .2
.10) 0E MRI @*00;
@DE=- @
-E:IATE- 5?-
.10. 00 VU?TIENT
.10+ C.
=:=INE @M>
C
@?M>=-E
.10= 4= B@ AT?-E
I5 T;E 4IRIA?-
IA DEAA
.10C 12
T;=N T;E
4IRI4EN4 :?
.10@ .1 T? AT?-E
.104 +0 AUC C
AUCT-=@T T;E
4IRIA?-
5-?M T;E
4IRI4EN4
.10E 0@ IN- @
IN@-EMENT
VU?TIENT
CQ ?NE 5?-
E=@;
AUCT-=@TI?N
.105 @3 BM> =:=IN :? T? =:=IN
.110 0+
.111 .1
.112 32
AT?-EE AT=
.203;
AT?-E T;E
-EM=IN4E-
.113 03 IN MEM?-Q
.114 .2
.11< )+ M?R =* @
M?RE T;E
@?NTENTA ?5
@ -E:IATE- T?
=@@UMUD=T?-
.116 32 AT= .202; AT?-E T;E
VU?TIENT IN
.11) 02 MEM?-Q
.11. .2
.11+ )6 ;DT EN4
A=M>DE 4=T=E
4=T= -EAUDT
.200 @+ '4i$idend,.202 14 'Vuotient,
.201 0= '4i$isor, .203 01 '-emainder,
-EAUDTE The Micro/rocessor 4i$ision /ro#ram is
$eri"ied usin# .0.< Trainer 9it
iidiscuss the workin# o" micro/rocessor contro00er tra""ic
si#na0 s1stem
Casic /rinci/0e o" tra""ic 0i#ht contro0 s1stem
Aome 0i#hts donSt ha$e an1 sort o" detectors 5or e2am/0e*
in a 0ar#e cit1* the tra""ic 0i#hts ma1 sim/01o/erate on
timers -- no matter what time o" da1 it is* there is #oin# to
%e a 0ot o" tra""ic In the su%ur%sand on countr1 roads*
howe$er* detectors are common The1 ma1 detect when a
car arri$es at anintersection* when too man1 cars are
stacked u/ at an intersection 'to contro0 the 0en#th o" the
0i#ht,*or when cars ha$e entered a turn 0ane 'in order to
acti$ate the arrow 0i#ht,There are a00 sorts o"
techno0o#ies "or detectin# cars -- e$er1thin# "rom 0asers
to ru%%er hoses "i00edwith airY C1 "ar the most common
technique is the inducti$e 0oo/ =n inducti$e 0oo/ is
sim/01 a coi0o" wire em%edded in the roadSs sur"ace To
insta00 the 0oo/* the1 0a1 the as/ha0t and then come
%ack and cut a #roo$e in the as/ha0t with a saw The wire
is /0aced in the #roo$e and sea0ed with a
ru%%er1com/ound Qou can o"ten see these %i#
rectan#u0ar 0oo/s cut in the /a$ement %ecause the
com/oundis o%$ious
Inducti$e 0oo/s work %1 detectin# a chan#e o" inductance
To understand the /rocess* 0etSs "irst 0ook atwhat
inductance is This "i#ure is he0/"u0E!e see here is a
%atter1* a 0i#ht %u0%* a coi0 o" wire around a /iece o" iron
'1e00ow,* and a switch Thecoi0 o" wire is an inductor I"
we ha$e read ;ow E0ectroma#nets !ork* we wi00 a0so
reco#niHe thatthe inductor is an e0ectroma#net I" we were
to take the inductor out o" this circuit* then what weha$e
is a norma0 "0ash0i#ht !e c0ose the switch and the %u0%
0i#hts u/ !ith the inductor in the circuitas shown* the
%eha$ior is com/0ete01 di""erent The 0i#ht %u0% is a
resistor 'the resistance creates heatto make the "i0ament in
the %u0% #0ow, The wire in the coi0 has much 0ower
resistance 'itSs 3ust wire,*so what 1ou wou0d e2/ect when
1ou turn on the switch is "or the %u0% to #0ow $er1 dim01
Most o" thecurrent shou0d "o00ow the 0ow-resistance /ath
throu#h the 0oo/ !hat ha//ens instead is that when1ou
c0ose the switch* the %u0% %urns %ri#ht01 and then #ets
dimmer !hen we o/en the switch* the %u0% %urns $er1
%ri#ht01 and then quick01 #oes out
Micro/rocessor as tra""ic 0i#ht contro0 s1stemE
= tra""ic 0i#ht contro0 and in"ormation transmission
de$ice com/risin#E a micro/rocessor 0ocatedinside the
tra""ic contro0 %o2 and to contro0 a00 the circuitriesZ a
tra""ic 0i#ht contro00er connected toand contro00ed %1 said
micro/rocessor to send out the sto/* #o and direction
si#na0sZ an e0ectronicdis/0a1 %oard connected to and
contro00ed %1 said micro/rocessor to dis/0a1 characters*
/atterns and#ra/hic ima#esZ a $ideo camera connected to
and contro00ed %1 said micro/rocessor to monitor
thetra""ic "0owZ a com/ression circuitr1 connected to said
micro/rocessor and said $ideo camera* saidcom/ression
circuitr1 com/resses the ima#e data ca/tured %1 said
$ideo camera and sends the data tosaid micro/rocessorZ
an I(? inter"ace connected to said micro/rocessor to
recei$e* transmit data andcontro0 si#na0sZ a tra""ic "0ow
detector connected to said I(? inter"ace and #atherin# the
tra""ic "0owin"ormationZ the tra""ic "0ow in"ormation is
in/ut to said micro/rocessorZ a 4AD connected to said
I(?inter"ace 6 and recei$in#* transmittin# data and contro0
si#na0sZ a %road%and network 0inkin# sai
4aa hot o%3ect with ca/acitance @ and tem/erature T*
coo0s in a 0ar#e room at a tem/erature T
a
i" the therma0
s1stem has a resistance -*deri$e an equation descri%in#
how the tem/erature o" the hot o%3ect chan#es with the
time and #i$e an e0ectrica0 ana0o#ue o" the s1stem
?r
%i/ro/ose a mode0 "or a ste//ed sha"t used to rotate a
mass and deri$e an equation re0atin# the in/ut torque and
the an#u0ar rotation ne#0ect dam/in# e""ect
iidescri%e and com/are the charecteristics o"
1, /ro/ortiona0 contro00er
2, /ro/ortiona0 /0us inte#ra0 contro00er
<aie2/0ain the mathematica0 mode0 "or rotatin# mass on
the end o" a sha"t and "or torsiona0 s/rin# mass s1stem
iidistin#uish %etween continous and discreet /rocess
contro00ers
?r
%idiscuss the /rinci/0e and o/eration o" a >I4 contro00er
ii e2/0ain the /rinci/0e and o/eration o" se0"-tunin#
circuit
6 aie2/0ain the mathematica0 mode0 "or resistor*
inductor* ca/acitor s1stem usin# kircho""sMs 0aw
iicom/are the contro0 s1stem /er"ormance "or a s1stem
with /ro/ortiona0 contro0 and a s1stem with inte#ra0
contro0
or
Cia motor is used to rotate a 0oad 4esi#n a
mathematica0 mode0 and draw a mechanica0 mode0 and
equi$a0ent mode0 "or the same
iienumerate the essentia0 charecteristics o" the >I4
contro00er
PID CONTROLLER THEORY
This section describes the parallel or non-interacting form of the PID controller. For other
forms please see the section Alternative nomenclature and PID forms.
The >I4 contro0 scheme is named a"ter its three correctin# terms* whose sum constitutes the
mani/u0ated $aria%0e 'MR, The /ro/ortiona0* inte#ra0* and deri$ati$e terms are summed to
ca0cu0ate the out/ut o" the >I4 contro00er 4e"inin# as the contro00er out/ut* the "ina0 "orm
o" the >I4 a0#orithm isE
where
: Proportional gain, a tuning parameter
: Integral gain, a tuning parameter
: Deriatie gain, a tuning parameter
: Error
: Time or in!tantaneou! time "t#e pre!ent$
: %aria&le o' integration( ta)e! on alue! 'rom time * to t#e pre!ent .
PROPORTION+L TERM
Plot o' P% ! time, 'or t#ree alue! o' ,p ",i an- ,- #el- .on!tant$
The /ro/ortiona0 term /roduces an out/ut $a0ue that is /ro/ortiona0 to the current error $a0ue
The /ro/ortiona0 res/onse can %e ad3usted %1 mu0ti/01in# the error %1 a constant K
p
* ca00ed the
/ro/ortiona0 #ain constant
The /ro/ortiona0 term is #i$en %1E
= hi#h /ro/ortiona0 #ain resu0ts in a 0ar#e chan#e in the out/ut "or a #i$en chan#e in the error I"
the /ro/ortiona0 #ain is too hi#h* the s1stem can %ecome unsta%0e 'see the section on 0oo/
tunin#, In contrast* a sma00 #ain resu0ts in a sma00 out/ut res/onse to a 0ar#e in/ut error* and a
0ess res/onsi$e or 0ess sensiti$e contro00er I" the /ro/ortiona0 #ain is too 0ow* the contro0 action
ma1 %e too sma00 when res/ondin# to s1stem distur%ances Tunin# theor1 and industria0 /ractice
indicate that the /ro/ortiona0 term shou0d contri%ute the %u0k o" the out/ut chan#e
Fcitation neededG
DROOP
Cecause a non-Hero error is required to dri$e it* a /ro/ortiona0 contro00er #enera001 o/erates with
a stead1-state error* re"erred to as droop
Fnote 1G
4roo/ is /ro/ortiona0 to the /rocess #ain and
in$erse01 /ro/ortiona0 to /ro/ortiona0 #ain 4roo/ ma1 %e miti#ated %1 addin# a com/ensatin#
%ias term to the set/oint or out/ut* or corrected d1namica001 %1 addin# an inte#ra0 term
INTE/R+L TERM
Plot o' P% ! time, 'or t#ree alue! o' ,i ",p an- ,- #el- .on!tant$
The contri%ution "rom the inte#ra0 term is /ro/ortiona0 to %oth the ma#nitude o" the error and the
duration o" the error The inte#ra0 in a >I4 contro00er is the sum o" the instantaneous error o$er
time and #i$es the accumu0ated o""set that shou0d ha$e %een corrected /re$ious01 The
accumu0ated error is then mu0ti/0ied %1 the inte#ra0 #ain ' , and added to the contro00er out/ut
The inte#ra0 term is #i$en %1E
The inte#ra0 term acce0erates the mo$ement o" the /rocess towards set/oint and e0iminates the
residua0 stead1-state error that occurs with a /ure /ro/ortiona0 contro00er ;owe$er* since the
inte#ra0 term res/onds to accumu0ated errors "rom the /ast* it can cause the /resent $a0ue to
o$ershoot the set/oint $a0ue 'see the section on 0oo/ tunin#,
DERI%+TI%E TERM
Plot o' P% ! time, 'or t#ree alue! o' ,- ",p an- ,i #el- .on!tant$
The deri$ati$e o" the /rocess error is ca0cu0ated %1 determinin# the s0o/e o" the error o$er time
and mu0ti/01in# this rate o" chan#e %1 the deri$ati$e #ain K
d
The ma#nitude o" the contri%ution
o" the deri$ati$e term to the o$era00 contro0 action is termed the deri$ati$e #ain* K
d