2011 M 25 Shvaichenko

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IHP Im Technologiepark 25 15236 Frankfurt (Oder) Germany www.ihp-microelectronics.com 2011 - All rights reserved
Elena Shvaichenko
METHODS OF DESIGNING
ANALOG-TO-DIGITAL
CONVERTERS
Masters Thesis Presentation
Author: Olena Shvaichenko
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Elena Shvaichenko
The purpose is to investigate the design of
14-bit resolution ADC with sampling
frequency 2 MHz in 0.13 um technology.
Purpose
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Elena Shvaichenko
Architecture Speed
Conversion
time
Resolution Area
Power
consumption
Flash ADC High Constant
Low (up till
8 bits)
Increases
exponentially
withresolution
Veryhigh
Pipelined
ADC
Medium
-high
Increases with
resolution
Medium-
high (up till
12-bits)
Increases
linearly with
resolution
Medium
Sigma-Delta
ADC
Medium
Trade off with
resolution
High (up till
24-bits)
Constant; no
change with
increase in
resolution
Medium-low
SAR ADC
Medium
-low
Increases with
resolution
High (up till
18-bits)
Increases
linearly with
resolution
Medium-low
Spec
Resolution
14 bit
Frequency
2 MHz
Technology
SG13S
Power supply
1.2 V
ADC architectures
Comparison table
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Elena Shvaichenko
Advantages
Low power consumption,
Low circuit complexity
Mostly digital circuitry.
Limitations
Lower sampling rates
Accuracy of the system
depends of the accuracy of the
DAC and the comparator.
Successive approximation ADC
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Elena Shvaichenko
Principle of operation
Successive approximation ADC
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Elena Shvaichenko
Mathematical model
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Elena Shvaichenko
Mathematical model
SAR
ADC
Input
Output
Ideal
DAC
Histogram
method
FFT
ramp
>10 samples per
transition level
sine-wave
coherent sampling
Static:
Gain error,
Offset, INL, DNL.
Dynamic:
THD, SFDR,
SINAD, ENOB.
Mismatches
Offset voltage
Settling time limitations
Imperfections
Parasitic capacitance
Thermal noise
Clock
feedthrough
Jitter
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Modeling of Capacitor array
mismatch effect
Common centroid structure
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Elena Shvaichenko
Simulation results of modeling
Capacitor array mismatch effect
0 2000 4000 6000 8000 10000 12000 14000 16000 18000
-0.5
0
0.5
Digital code
I
N
L

(
L
S
B
)

0 2000 4000 6000 8000 10000 12000 14000 16000 18000
-0.4
-0.2
0
0.2
0.4
0.6
Digital code
D
N
L

(
L
S
B
)

ADC W1=2um, L1=2um, kp=10nm
Ideal ADC
ADC W1=2um, L1=2um, kp=10nm
Ideal ADC
0 5 10 15
x 10
-14
75
80
85 X: 6.248e-015
Y: 83.45
SINAD versus value of unit capacitor
C
u
, (F)
S
I
N
A
D
,

(
d
B
)
Mismatch Cu = 6.5 fF
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Elena Shvaichenko
Modeling of Settling time effect
Sampling frequency Switches sizing.
~
Sampling phase
0 0.5 1 1.5 2 2.5 3 3.5
55
60
65
70
75
80
85
90
X: 2.167
Y: 83.43
SINAD versus time constant
, (ns)
S
I
N
A
D
,

(
d
B
)
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Elena Shvaichenko
Behavioural model
Differential triple reference charge-redistribution
SAR ADC with monotonic switching procedure
Reduces Ctot by a factor of 4 compared to conventional
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Elena Shvaichenko
SAR Logic
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Elena Shvaichenko
Behavioural model test bench
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Elena Shvaichenko
Simulation results of behavioral
model
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Elena Shvaichenko
Simulation results of behavioral
model
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Transistor level model
Comparator architecture
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Comparator schematic
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Simulation results
Input and output waveforms
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Conclusion
Analysis of ADC architectures was done.
SAR architecture was chosen as most appropriate architecture to meet
given specification.
Development of program for modeling successive-approximation analog-to-digital
conversion in MATLAB was done.
Analysis of nonideal effects in SAR ADC was done.
Modeling of mismatch, input referred dc offset and settling time effects was done.
Simulation of modeling mismatch effect shows that for SG013S IHP technology it is
possible to get DNL 0.5 LSB, INL < 0.5 LSB, THD = -95.07 dB, SFDR =
85.75 dB, SINAD =84.84 dB, ENOB = 13.8 bit with probability 99.7%.
Simulation of modeling comparator offset voltage effect shows that for SG013S IHP
technology with 3.2 mV input referred dc offset it is possible to get THD = -84.33 dB,
SFDR = 76.10 dB, SINAD =74.95 dB, ENOB = 12.16 bit with probability 99.7%.
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Elena Shvaichenko
Conclusion
Simulation of modeling settling time effect shows that for SG013S
IHP technology with 2.1 ns time constant it is possible to get
SFDR = 83.97 dB, SINAD =83.7 dB, ENOB = 13.61 bit with probability 99.7%.
VerilogA behavioral model of 14-bit differential chargeredistribution SAR ADC with
monotonic switching procedure was developed.
Simulation of proposed high-speed comparator with resolution 40uV, clock
frequency 100 MHz, supply voltage 1.2 V in SG013S IHP technology was done.
Analysis of more than 45 scientific sources up to 2011 year in the field of analog-to-
digital conversion has been conducted.
Results of investigation have been published at the International conference on system
analysis and information technologies.
The investigation was carried out for IHP - Innovations for High Performance
Microelectronics company.
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Elena Shvaichenko
Thank You!!!
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Elena Shvaichenko
General concept in designing ADC
Design flow for ADC
Mathematical model
Algorithm is examined
Functional description
Behavioural model
Architecture is verified
Behavioural description
of the blocks
Schematic is verified
Transistor level of the blocks
Layout level
Abstract model in Matlab, C/C++
Verilog/VHDL model of the digital part;
Verilog-A/VHDL- AMS model for the analog
Synthesis to get gate level Verilog or VHDL
Schematic design of the analog
Mixed verification
Analog layout
Place&Rout of the digital
Post-layout simulation
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Elena Shvaichenko
Modeling of Capacitor array
mismatch effect
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Elena Shvaichenko
Simulation results of modeling
Settling time effect
0 0.5 1 1.5 2
x 10
6
-200
-150
-100
-50
0
Power spectral density
Frequency (Hz)
P
o
w
e
r
/
f
r
e
q
u
e
n
c
y
,

(
d
B
/
H
z
)
THD = -98.90 dB
TSD = -86.98 dB
SFDR = 83.97 dB
SINAD = 83.70 dB
ENOB = 13.61 bits

ADC with = 2.1ns
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Elena Shvaichenko
Waveforms of conventional and
monotonic switching procedure
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Elena Shvaichenko
Waveforms of conventional and
monotonic switching procedure
Waveform of monotonic
switching procedure
Reduces Switching power in a factor of 5
Waveform of conventional
switching procedure
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Elena Shvaichenko
Preamplifiers
Preamplifier with diode connected pMOSload and its gain
Preamplifier with resistor load and its gain
Modified Bultspreamplifier and its gain
Songs preamplifier and its gain
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Elena Shvaichenko
Preamplifier
Amplifier architecture Gain, dB Bandwidth, Hz
Differential pair with resistive load 13.88 565.7
Differential pair with pmos diode
connected load
4.86 465.2
Modified Builts preamplifier 20.13 201.3
Songs preamplifier 20.42 178.1
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Elena Shvaichenko
Latch
Dynamic latch
Advantages
zero dc current in reset mode,
full logic levels after
regeneration,
outputs are both reset to supply
voltage so they are well defined

2011 M 25 Shvaichenko

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