1

Nano-Electro-Mechanical Switches








J une 9
th
, 2008









Authors:

Ecole Polytechnique Fdrale Lausanne: D. Tsamados, A.M. Ionescu
Stanford University: K. Akarvardar, H.-S. Philip Wong
University of California at Berkeley: E. Alon, T.-J. King Liu

2

Table of Contents



1. Introduction: The CMOS Power Crisis ............................................................ 3

2. Nano-Electro-Mechanical (NEM) Switches

2.1 NEM Relays for Ultra-Low-Power Logic................................................ 4
2.1.1 Device structure and operation
2.1.2 NEM relay scaling
2.1.3 Relay technology challenges and limits
2.1.4 NEM relay summary

2.2 NEM-FET for Ultra-Low-Standby-Power Applications.......................... 7
2.2.1 Device structure, fabrication and operation
2.2.2 NEM-FET scaling
2.2.3 NEM-FET performance: opportunities and limits
2.2.4 NEM-FET summary

3. Integrated NEM Systems Roadmap................................................................ 11

4. References .......................................................................................................... 13

5. Appendix: ........................................................................................................... 15
Table with basic figures of merit of NEM relay
Table with basic figures of merit of NEM-FET
3
1. Introduction: The CMOS Power Crisis

In past decades, the focus of the semiconductor industry has been on transistor
miniaturization to improve performance in terms of speed (C
gg
V
dd
/I
on
) as well as to reduce die
area and hence cost per operation. This has been an extremely successful approach in the
simple scaling era, but as the transistors have been scaled to lateral dimensions much below
100nm, new challenges have emerged. Most notably, off-state leakage current (I
off
) has
increased exponentially as the transistor threshold voltage (V
th
) was reduced in order to
achieve these increases in transistor speed. Now that static (leakage) power dissipation
comprises a large fraction (~1/3) of the total power consumption of a chip, further decreases
in V
th
would only cause the chip to consume additional power without increasing circuit
performance.

This power issue is due fundamentally to the non-ideal switching behavior of a transistor.
An ideal switch exhibits an abrupt transition between the on (high-conductance) state and the
off (low-conductance) state as the control voltage is varied, i.e. it has zero sub-threshold
swing defined as S =(d(logI
D
)/dV
GS
)
-1
. Such an ideal switch would allow for a very low
operating voltage (i.e. a low supply voltage V
dd
of ~0.1V) and hence very low dynamic power
consumption. Furthermore, an ideal switch has zero I
off
and hence zero standby power
consumption. Unfortunately, the sub-threshold swing of a MOSFET is limited by Boltzmann
statistics to be no less than 60mV/dec at room temperature, and so V
dd
must be much larger
than 60 mV in order to allow for reasonably large I
on
/I
off
ratios. (For conventional MOSFET
structures in the sub-100nm gate length regime, the value of S is often considerably larger
than this limit. Multiple-gate MOSFET structures offer improved electrostatic control of the
channel potential and therefore can achieve S values close to the limit of 60mV/dec.) Also, I
off

per unit device width has been increasing with MOSFET scaling due to V
th
reduction and
increases in quantum-mechanical tunnelling currents (e.g. gate-induced drain leakage, band-
to-band tunnelling). Therefore, more ideal switching devices based on other physical
mechanisms are needed to overcome the power issue.

Two such devices are the nano-electro-mechanical (NEM) switch, or relay, and the hybrid
NEM field-effect transistor (NEM-FET). In a relay, an air-gap separates the conductive
electrodes (which are analogous to the source and drain electrodes of a MOSFET) in the
off state, which naturally provides for zero I
off
(zero conductance). As the electrodes are
brought into physical contact via electrostatic actuation of the source electrode induced by
the voltage applied to the gate electrode, the conductance increases abruptly, providing for
near-zero sub-threshold swing. In a NEM-FET, the effective gate-dielectric thickness (hence
V
th
) is dynamically modulated with the gate voltage in order to achieve a higher I
on
/I
off
ratio
than that achievable by a conventional MOSFET. Recent progress in surface-micromachining
process technology including nanometer-scale control of gap-formation processes and the
exploitation of nanowire and nanotube growth technologies makes such NEM switches
compelling to consider as a credible alternative to MOSFETs for future ultra-low-power
applications. It is worth noting that NEM switch technologies can be fabricated in a CMOS
compatible fashion in order to facilitate hybrid CMOS/NEM high-performance and low-
power system designs.
4
2.1 NEM Relays for Ultra-Low-Power Logic

2.1.1 Device structure and operation

NEM relays are devices where the operation is based on the displacement of a solid beam
under the influence of electrostatic force in order to create a conducting path between two
electrodes. NEM relays feature two desirable properties for logic computation which are
unavailable in MOSFETs: zero leakage and zero subthreshold swing [1]. The first property
indicates zero standby energy dissipation, while the second suggests the potential to scale V
DD

aggressively (without degrading the on-current to off-current ratio) and hence reduce
significantly the dynamic energy consumption as well. Moreover, features such as
electromechanical hysteresis and sticking induced by surface forces make NEM relays
attractive for non-volatile memory applications [2]. Additional motivations for NEM logic
include high-temperature and radiation-hard operation [3] and the possibility of using cheap
substrates such as plastic or glass for their fabrication. NEM relays can be processed at low
temperatures, allowing their co-integration with CMOS. Possible applications of a hybrid
NEMS-CMOS technology consist of power gating high-performance CMOS circuits [4] and
configuration of CMOS FPGAs [5] using NEM relays.

The cross-section of the simplest, three-terminal NEM relay is shown in Fig. 1a [1]. The
cantilever, which can be comprised of a semiconductor, metal, or even a carbon nanotube
(CNT) or nanowire, is connected to the source electrode and separated from the gate and drain
electrodes by an air gap. Device operation is based on electrostatic actuation, and the current-
voltage characteristics usually include hysteresis characterized by a pull-in voltage, V
pi
, which
is larger than the pull-out voltage, V
po
(Fig. 1b). Note that for this relay of supply voltage V
dd

is limited to be no smaller than V
pi
-V
po
. The actuation direction can be out-of-plane (as shown
in Fig. 1a) or in-plane. NEM relays can be interconnected as are MOSFETs, and can be used
to implement logic families such as fully static logic (Fig. 1c) or pass-gate logic.



2.1.2 NEM relay scaling

As for MOSFETs, performance is improved by constant-field scaling for NEM relays,
which increases speed while decreasing dynamic energy dissipation and area [1]. The ultimate
device density achievable with NEM relays can in principle be competitive with CMOS due
to the simplicity of the NEM relay structure [1]. The main advantage of NEM relays in terms
of scaling resides in their improved energy efficiency as well as in their potential for 3-D
integration (due to low-temperature process-ability), both of which may allow increased
functional density for a given substrate real-estate [6]. This is especially true for memory
applications [2] where hysteresis and sticking lead to an even better functional density.
V
in
V
out
P-relay
N-relay
V
DD
C
L
Fig. 1. (a) Cross-section of the conventional NEM relay, (b) transfer characteristic, (c) CMOS-based CNEM inverter [1].
S
D G
air gap
cantilever beam
S
insulating substrate
D
r
a
i
n

C
u
r
r
e
n
t
Gate to Source Voltage, V
GS
Zero
off-current
"Infinite"
subth.
slope
(a)
(b) (c)
Zero
subth.
swing
5
NEM relays can be fabricated by top-down approaches using conventional lithography
techniques or bottom-up approaches using CNT or nanowire beams. There are many
successful demonstrations using top-down approaches at the micron scale with reliable
operation up to 10
8

cycles [7]. In NEM relay fabrication, the most critical process step is the
beam release (gap formation), which is realized by the etching of a sacrificial material, such
as oxide, polyimide, or silicon.

The smallest actuation gap demonstrated so far for a functional NEM structure fabricated
using a top-down approach is 15 nm [8]. The device consists of a vertically actuated 2-
terminal NEM switch featuring a 35-nm-thick TiN cantilever beam that is 300 nm long and
200 nm wide. The pull-in voltage is approximately 13 V. As expected, the off-state current is
virtually zero and the sub-threshold swing is practically zero. An endurance of several
hundred switching cycles in air ambient is reported. The smallest actuation gap demonstrated
to date for a CNT-based structure fabricated using a bottom-up approach is 40-60 nm [9]. The
structure is a laterally-actuated 3-terminal relay. The clamped-clamped CNT is 800 nm long
with a diameter that varies between 20 nm and 40 nm. The pull-in voltage is approximately
3.5 V. 2- and 3-terminal relays based on LPCVD-grown Si nanowires with ~100 nm diameter
were also demonstrated in [10]. Pull-in voltage was 3.8 V for the 2-terminal NEM switch
featuring a 200 nm gap, while leakage was virtually zero. The use of CNT wafers rather
than individual CNTs has recently been demonstrated as a very promising approach for
fabricating high-density, highly controllable CNT-based NEM relays and logic circuits [11].

The main advantage of NEM relays is their zero off-state leakage (which becomes
increasingly important in high-density circuits featuring relatively long idle times) and
potential for low dynamic energy dissipation, which can be reduced down to the aJ range.
Their main weakness is switching speed: a realistic lower limit for the delay related to beam
movement from the off position to the on position is ~1 ns [1]. It should be further noted that
this turn-on delay can vary depending upon the initial conditions of the beam; the initial
conditions may vary since the settling time required for the beam to return to its nominal
position may be significantly longer than the turn-on time. Essentially, in the on state the
cantilever beam stores elastic energy due to bending (Fig. 1a). Consequently, when V
GS
is
reduced to zero, the cantilever returns to its nominal position at a rate set by the resonant
frequency of the beam, and may even oscillate around its equilibrium position until it
dissipates the potential elastic energy by damping. Thus, the effective turn-on delay of the
relays should be based on the worst-case initial condition.

2.1.3 Relay technology challenges and limits

Many issues remain to be solved in order to apply NEM relays to logic applications. The
most important issue is nanoscale contact reliability, since logic circuits would require the
relays to operate correctly over ~10
16
hot switching cycles where the drain voltage is as
high as the gate voltage. High impact velocity at the end of pull-in and the resultant tip
bouncing (which also increases the effective switching delay) can aggravate the problem [1].
Another significant issue for NEM relays is the presence of surface forces (van der Waals or
Casimir) that can cause sticking if the restoring elastic force is not sufficiently high [1].
Stiction is typically overcome by stiffening the beam at the expense of increasing the pull-in
voltage (and hence the current density at the on-state), and thus these surface forces often set
the minimum energy required to switch a NEM relay. In order to minimize stiction and
maintain clean contact spots, NEM relays should be hermetically sealed.
6
There are several factors which will eventually impact the dimensional scaling of NEM
relays. To maintain zero off-state leakage, the gap between the cantilever tip and the drain
electrode of a NEM relay should remain larger than ~2 nm. At gaps of a few nm, the
subthreshold swing is already expected to degrade due to the onset of tunneling current before
the unstable beam position is reached at ~2/3 of the nominal gap. With sufficiently small
dimensions and gaps, the effect of Brownian beam motion may become significant; however,
stiffening of the beam (e.g. by changing the beam material) can allow for further scaling. In
relays with gaps near the limit set by tunneling (~2 nm), the long turn-off settling time could
cause a significant risk for short-circuit current [12]. This can occur if a new input is
applied to the NEM relay logic gate (turning on the complimentary device) before the beam
has settled to more than ~1nm away from the drain electrode. However, innovative device and
mechanical solutions for the long settling time (as well as for the high impact velocity and tip
bouncing) exist in the RF MEMS domain and can be applied to NEM logic circuits. These
solutions include the optimization of the contact bump (limit stop) height in the conventional
relays and the utilization of symmetrical relays featuring two gate electrodes [13].

Experimental comparisons of NEM logic to other ultra-low power technologies such as
subthreshold CMOS have yet to be conducted. As compared to other emerging devices (SETs,
molecular devices, etc.), mechanical relays are a relatively mature technology at the micron
scale, and have been shown to be scalable to the nanometer scale [8]. It is important to
mention that, because of the relatively slow switching speed of mechanical switches, the main
initial driver for the development of NEM relays will be LSTP and LOP applications.

2.1.4 NEM relay summary

In conclusion, NEM relay technology is a strong candidate for beyond CMOS
technology for LSTP applications because NEM relays exhibit virtually zero leakage. If the
influence of surface forces can be reduced, the steep subthreshold swing of the NEM relay
can be exploited to significantly decrease V
DD
and hence the active power as well. This would
lead to a truly low-power (LSTP and LOP) technology beyond the capability of CMOS. In
this context, controlling and minimizing surface forces as well as guaranteeing contact
reliability are the key requirements and warrant fundamental research. The potential
advantages of NEM relay technology make a compelling case for the development of a
detailed technology roadmap and accelerated engineering development.

7
2.2 NEM-FET for Ultra-Low-Standby-Power Applications

2.2.1 Device structure, fabrication and operation

Nathanson first proposed a movable (resonant) gate transistor in 1967 [14]. However, at
that time, Micro-Electro-Mechanical-Systems (MEMS) technology was only in a very
primitive stage and so follow-up reports were very limited and rather dedicated to applications
in gas sensing. Recent interest [15-18] in so-called suspended-gate FET (SG-FET) devices has
been motivated by their ability to offer solutions for ultra-low power logic, power
management and capacitor-less memory devices by taking advantage of MEMS technology
and properties. Today, MEMS technology has achieved a certain level of maturity and
applications of RF MEM switches and resonators are foreseen in mobile communications and
airborne or space electronics. Moreover, MEMS devices can be integrated monolithically with
conventional CMOS devices using top-down surface micromachining processes, enabling
novel functionality and performance together with low power consumption (based on
electrostatic or piezoelectric actuation). MEMS passive elements, switches, and resonators are
some of the most successful examples in the field.

A Micro- or Nano-Electro-Mechanical Field Effect Transistor (MEM- or NEM-FET)
combines features of a pure NEM relay and a MOSFET: it has a movable part and a solid-
state semiconductor part that operate to couple the mechanical movement with the formation
of the inversion/accumulation channel at the gate-insulator/semiconductor interface. The
device architectures discussed herein are illustrated in Fig. 2 and have an in-plane or out-of-
plane movable gate or body. Note that the current path is always in the semiconductor part, so
that this device is not subject to contact reliability issues specific to purely mechanical relays.
The movable part determines the state of the gate capacitance C
gg
(either low or high), which
determines V
th
; thus the NEM-FET is a dynamic threshold device, with a high V
th
in the off
state and a low V
th
in the on state. As can be seen from Fig. 3, an abrupt transition (with a
swing as low as 2 mV/decade, reported in [16]) occurs as the gate voltage is increased beyond
the point when an imbalance between the electrostatic and mechanical spring-restoring forces
is reached so that pull-in (to the high-C
gg
) occurs. A similarly abrupt transition from the
low-V
th
state to the high-V
th
state occurs as the gate voltage is decreased back to 0 V, when
the electrostatic force is reduced to be equal to the spring restoring force so that pull-out (to
the low C
gg
state) occurs. Note that for switching applications, pull-in should occur at a gate
voltage less than the (high) off-state V
th
, to achieve substantial sub-threshold leakage power
savings for a given on-state current (I
on
) specification. Furthermore, pull-out should occur at
a gate voltage greater than 0 V for proper circuit operation. (If pull-out occurs at a gate
voltage less than 0 V, the NEM-FET can be used for memory applications [16, 18].)
Comprehensive analytical models to predict NEM-FET device characteristics and to enable
NEM-FET circuit simulations have been proposed in [19, 20].

MEM-FETs with movable gate-electrode dimensions on the order of 10 microns, or
movable body dimensions on the order of 1 micron, and air-gaps in the range from 100nm to
200nm and actuation voltages in the range of a few Volts have been successfully
demonstrated [16, 21-23]. The experimental results have fully confirmed the abrupt pull-in
and pull-out behavior and hysteresis in the I-V characteristics (Fig. 3a).
8

(a)

(b)

(c)

(d)
Fig. 2. (a) classical MEM-FET with out-of-plane movable gate. (b) MEM-FET with in-plane movable gate and
auxiliary gate electrode. (c) MEM-FET with out-of-plane movable body and double-gate configuration.(d) MEM-
FET with in-plane movable body and double-gate configuration.



0 2 4 6 8 10 12 14
Gate voltage, V
G
(V)
D
r
a
i
n

c
u
r
r
e
n
t
,

I

D

(
A
)
Pull-in
Pull-out
10
-12
10
-6
10
-7
10
-8
10
-9
10
-10
10
-11


(a) (b)
Fig. 3. (a) Measured I
D
-V
G
characteristics of a fabricated MEM-FET with movable metal gate; abrupt pull-in,
pull-out with very abrupt transition swing and inherent electro-mechanical hysteresis are demonstrated. (b)
Validation of an analytical SG-FET model using data generated by finite element analysis for a device compliant
to the 90 nm ITRS node. The EKV-based analytical model matches well the numerical simulation. Device
parameters: k
beam
=3.9 N/m, t
ox
=3nm, t
gap0
=17nm,
m
=4.4eV, channel doping N
ch
=1x10
18
cm
-3
.



9
In principle, NEM-FET devices can be integrated with CMOS devices by making
relatively small process modifications in the front-end-of-line (FEOL) and back-end-of-
line (BEOL). A movable gate electrode can be made from a thin conductive metal layer or
doped silicon or polycrystalline-silicon, while the gate dielectric can be silicon dioxide or any
other gate dielectric available in the CMOS technology. The mechanical elements require the
selective etching of a sacrificial layer in order to be released; polyimide, silicon dioxide,
amorphous silicon, and silicon-germanium are frequently reported sacrificial materials. The
resulting air-gap can range from a few micrometers down to ~10nm in thickness, dictating
(together with the mechanical properties of the movable part) the NEM-FET actuation
voltages. As is the case for all MEMS devices, the NEM-FET requires special packaging for
mechanical protection, with a controlled dry environment (and, in some cases, vacuum). It is
expected that wafer-level (and perhaps eventually 0-level) packaging technology will be able
to fulfill these requirements.

2.2.2 NEM-FET scaling

Scaling of the NEM-FET into the deca-nanometer regime is one of the key requirements
for its future success. Both the lateral (photolithographically defined) device dimensions and
the thicknesses of the different layers, including the actuation air-gap, must be reduced
together. Air-gaps on the order of 10 nm are feasible today; the smallest air-gap reported to
date is 2-3nm between two gold lines, formed by depositing gold over a patterned resist
trench [24].

The benefits of scaling include reduced layout area for denser memory or logic functions
(to be competitive with other technologies), lower actuation voltage (enabled by nanometer-
scale air-gaps) and higher operation frequency (as the device resonance frequency increases).
Exploitation of suspended nanowire and nanotube technologies could enable NEM-FETs to
operate at near-GHz frequency with negligible standby power consumption. The NEM-FET is
particularly attractive as a power-gating device for high-performance CMOS platforms,
because of its very high I
on
/I
off
ratio (3-4 decades larger than that for a MOSFET). Fig. 3b
shows the simulated I-V characteristics of a NEM-FET compatible with the 90nm CMOS
node, operating at less than 2V and with significantly reduced I
off
.

NEM-FET scaling requires careful consideration of surface forces (e.g. van der Waals and
Casimir) that can significantly influence the pull-in and pull-out voltages, depending on the
device materials and dimensions (in particular the air-gap thickness). Moreover, the numerical
simulation of this hybrid device requires multi-physics analysis [25] to consistently solve the
coupled equations of solid-state physics and mechanical motion. For device dimensions down
to ~10nm, a mechanical model based on classical continuum theory (for material properties
and surface effects) can be used; on the other hand, semi-classical or quantum-mechanical
models should be used to simulate the (semiconductor) electrical behavior.

2.2.3 NEM-FET performance: opportunities and limits

Although truly nanometer-scale NEM-FETs have not been experimentally demonstrated
to date, successful demonstrations of micron-scale devices together with simulations of scaled
NEM-FETs with calibrated models indicate that NEM-FETs are promising for LSTP
applications. In a first phase, NEM-FETs potentially could be an add-on to CMOS platforms
for power management. In a later stage, after full assessment of their long-term reliability
(including variability), they may become candidates for logic and/or memory functions. Based
10
on experimental demonstrations to date, one could envision the NEM-FET as a three- or four-
terminal binary switch (using charge or voltage as the state variable) which provides for 3-4
decades reduction in standby power as compared to the MOSFET. Its intrinsic speed could be
of the order of GHz, with operating voltage below 1 V and switching energy on the order of
aJ . Very recent reports on energy-reversible complementary NEM logic gates [26],
demonstrate that for the same delay, energy-reversible architectures can operate at
significantly lower supply voltage, which is beneficial for better reliability.

Beyond these applications, the NEM-FET can offer unique analog/RF on-chip functions;
as reported in [23], they can be used to efficiently transduce mechanical motion (e.g. a
vibrating body) into an electrical signal (varying drain current), due to built-in gain. Low
motional resistance (as low as 250 Ohms reported in [23]) is required to enable ultra-scaled,
low-power on-chip oscillators and RF blocks.

The following are open issues and challenges for NEM-FET applications:
Thermal drift This is especially important if metallic mechanical beams anchored on
an insulator layer are used; thermal drift of pull-in and pull-out voltages can be
compensated by appropriate anchor design, but at the substantial cost of (increased)
layout area. Compensation at the circuit level will result in additional power
consumption or supplementary hardware area. Perhaps the best solution today is to use
oxidized silicon as a locally compensated movable structure.
Packaging and reliability These have been considered for a long time as the great
generic challenges for MEMS adoption into industrial applications. Hermetic
packaging (preserving a dry controlled ambient) is critical for reliable NEM-FET
operation, and can be achieved by a combination of (local) 0-level protective
packaging and wafer-level packaging. An issue for NEM-FET operation is gate-oxide
charging, which can induce an undesirable V
th
shift and thereby increase the required
operating voltage range. This issue is identical to oxide charging in capacitive RF
MEM switches, and can be solved by improving the quality of the gate insulator and
passivating its interfaces, and by appropriate device design to minimize the transverse
electric field and injection of hot carriers into the gate insulator. Control of the
contacting surface roughness is also expected to improve performance and reliability.
Control of variability NEM-FET variability could be a more complex issue than for
the MOSFET because it involves additional process control of nanoscale air-gap
thickness and uniformity of suspended structure dimensions (e.g. line-edge
roughness), as well as tight control and uniformity of mechanical properties. Top-
down fabrication is presently foreseen to be the likely approach for the NEM-FET;
however, a combination of top-down and bottom-up approaches should be considered
for ultra-scaled NEM-FETs to potentially reduce variability.

2.1.4 NEM-FET summary

The NEM-FET is a true hybrid mechanical-solid-state switch that is attractive for low-I
off

power management switches with near-zero point subthreshold swing, capacitor-less memory
(D-RAM, S-RAM and NVM with appropriate storage layers) and new analog/RF
functionality (in the resonant-gate configuration). Its fabrication exploits the compatibility of
surface micromachining with CMOS processing. In contrast with a NEM relay, the NEM-
FET does not use mechanical contacts in the path of current flow (operation is based on
capacitive switching), so that its long-term reliability should be at least comparable to that of
capacitive RF MEMS switches, being limited by oxide charging.
11
3. Integrated NEM Systems Roadmap

The monolithic integration of M/NEM devices and CMOS electronics is beneficial for
many applications, some of which are noted in Fig. 4. By adding new functionality to
integrated circuits, M/NEM devices have enabled applications in sensing and actuating. In the
future, they can enhance the performance of analog and digital integrated circuits by
providing for dramatic reductions in power consumption.

The earliest integrated microsystem products were pressure sensors [27, 28] followed by
inertial sensors such as the Analog Devices ADXL50 accelerometer [29], with only 1 to 3 on-
chip MEM structures of lateral dimensions on the order of 100 m. More recently, products
with much higher levels of MEM device integration, such as the digital micromirror device
(DMD) developed by Texas Instruments for projection displays [30] and the photonic
switching systems developed by OMM for communication networks, have been successfully
commercialized. Recent success of Radio-Frequency MEMS (RF-MEMS) [32] such as
tunable micromachined capacitors, integrated high-Q inductors, micromachined low-loss
microwave and millimeter-wave filters, low-loss micromechanical switches, microscale
vibrating mechanical resonators with Qs in the tens of thousands, and miniature antennas for
millimeter-wave applications, have offered miniaturization, MEMS-CMOS co-integration and
unique performance enhancement of existing and future wireless transceivers.

As the need for more energy-efficient chips grows, applications for M/NEM devices will
expand to include integrated NEM switches for CMOS power management, and eventually
logic and memory applications. This is because a relatively small number of NEM-FET
switches (<10
3
) can be used to effectively manage CMOS power consumption, whereas a
very large number (up to 10
7
) would be desirable for embedded memory (DRAM/pseudo-
SRAM). As mechanical contact reliability issues are resolved, NEM relays will find
application in ultra-low-power logic, perhaps in stand-alone (purely mechanical) systems first
and then in hybrid CMOS/NEM systems. This is because post-CMOS integration imposes a
thermal budget limit for NEM relay fabrication, which makes it more difficult to form
mechanical elements with good structural properties. Although it is not emphasized in this
whitepaper, NEM structures are generally attractive for high-density non-volatile memory
applications (which have less stringent reliability requirements) because they can be
programmed with much lower energy than conventional semiconductor memory devices [2].

It is important to note that the development of standardized NEM device process flows is
necessary to make integrated NEM systems economically viable. In other words, a single
fabrication process flow should support multiple integrated NEM device products; otherwise,
without economies of scale, it is unlikely that integrated NEM systems will be cost effective.
Since NEM-FET integration will require FEOL and BEOL modifications, semiconductor
foundries will need to develop fully integrated process flows. In contrast, it may not be
necessary to have the CMOS and NEM processing done in a single foundry for integrated
NEM relays, because they can be fabricated post-CMOS. For example, two foundries can be
used: first a conventional CMOS foundry, then a MEMS foundry. However, wafer
compatibility may be a practical issue, because modern MEMS foundries are configured to
handle 150mm-diameter wafers. In any case, standardized processes will be necessary to
allow for development of standard compact (SPICE) models for circuit design and analysis, as
well as computer-aided design tools for synthesis and verification.


12

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r
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,

N
T
Number of Mechanical Components, NM
10
0
10
1
10
2
10
3
10
4
10
5
10
6
10
7
10
8
10
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0
10
1
10
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10
3
10
4
10
5
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6
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9
Early MEMS
(sensing applications)
M/NEMS
Integration Levels
Enabled Applications
RF MEMS
ADXL
More MEMS devices
thantransistors
NT/NM=1
OMM 32x32
NEM-FET Power Gating
and Embedded D/SRAM
Ultra-low-power
NEM-based
Embedded NVM
Integrated
Actuator
Systems
Ultra-low-power
NEM Relay
Logic
Adaptive
Optics
Optical Switches
& Aligners
Digital Micromirror
Device (DMD)
CPUs
i
n
c
r
e
a
s
i
n
g

p
o
w
e
r

c
o
n
s
u
m
p
t
i
o
n
i
n
c
r
e
a
s
i
n
g

p
o
w
e
r

c
o
n
s
u
m
p
t
i
o
n
More transistors
thanMEMS devices
N
u
m
b
e
r

o
f

T
r
a
n
s
i
s
t
o
r
s
,

N
T
Number of Mechanical Components, NM
10
0
10
1
10
2
10
3
10
4
10
5
10
6
10
7
10
8
10
9
10
0
10
1
10
2
10
3
10
4
10
5
10
6
10
7
10
8
10
9
Early MEMS
(sensing applications)
M/NEMS
Integration Levels
Enabled Applications
RF MEMS
ADXL
More MEMS devices
thantransistors
NT/NM=1
OMM 32x32
NEM-FET Power Gating
and Embedded D/SRAM
Ultra-low-power
NEM-based
Embedded NVM
Integrated
Actuator
Systems
Ultra-low-power
NEM Relay
Logic
Adaptive
Optics
Optical Switches
& Aligners
Digital Micromirror
Device (DMD)
CPUs
More transistors
thanMEMS devices
N
u
m
b
e
r

o
f

T
r
a
n
s
i
s
t
o
r
s
,

N
T
Number of Mechanical Components, NM
10
0
10
1
10
2
10
3
10
4
10
5
10
6
10
7
10
8
10
9
10
0
10
1
10
2
10
3
10
4
10
5
10
6
10
7
10
8
10
9
Early MEMS
(sensing applications)
M/NEMS
Integration Levels
Enabled Applications
M/NEMS
Integration Levels
Enabled Applications
RF MEMS
ADXL
More MEMS devices
thantransistors
NT/NM=1
OMM 32x32
NEM-FET Power Gating
and Embedded D/SRAM
Ultra-low-power
NEM-based
Embedded NVM
Integrated
Actuator
Systems
Ultra-low-power
NEM Relay
Logic
Adaptive
Optics
Optical Switches
& Aligners
Digital Micromirror
Device (DMD)
CPUs


Fig. 4. MEMS/NEMS application roadmap. As the number of NEM components increases, the average power
per function will decrease -- and the (diversity of) functionality of the chip will increase.
13
References:

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H.S. P. Wong, Design considerations for complementary nanoelectromechanical logic
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J .-B. Yoon, M.-S. Kim, J .-M. Lee, S.-M. Kim, K.-H. Cho, D.-W.
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Integrated three-dimensional microelectromechanical devices from processable carbon
nanotube wafers, Nature Nanotechnology 3, 289 - 294, 2008.
12. J . Rabaey, A. Chandrakasan, B. Nikolic, Digital Integrated Circuits: A Design
Perspective, 2
nd
edition (Prentice Hall), 2003.
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operating voltage and high speed, 14th MicroMechanics Europe Workshop, pp. 33-36,
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14. H. C. Nathanson, W. E. Newell, R. A. Wickstrom, J . R. Davis, The resonant gate
transistor, IEEE Trans. Electron Devices, ED-14(3), pp. 117133, Mar. 1967.
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Fluckiger, G.A. Racine, Modeling and design of a low-voltage SOI suspended-gate
MOSFET (SG-MOSFET) with a metal-over-gate architecture, International Symposium
on Quality Electronic Design Proceedings, pp. 496 501, 2002.
16. N. Abele, R. Fritschi, K. Boucart, F. Casset, P. Ancey, A. M. Ionescu, Suspended-gate
MOSFET: bringing new MEMS functionality into solid-state MOS transistor, IEEE
International Electron Devices Meeting Technical Digest, pp. 479-481, 2005.
17. H. Kam, D. Lee, R. Howe, T.-J . King, A new nano-electro-mechanical field-effect
transistor (NEMFET) design for low-power electronics, IEEE International Electron
Devices Meeting Technical Digest, pp. 463-466, 2005.
14
18. B. Pruvost, H. Mizuta, S. Oda, 3-D design and analysis of functional NEMS-gate
MOSFETs and SETs, IEEE Transactions on Nanotechnology 6(2), pp. 218-224, 2007.
19. K. Akarvardar, C. Eggimann, D. Tsamados, Y. Chauhan, G.C. Wan, A.M. Ionescu, R.T.
Howe, H.-S.P. Wong, Analytical Modeling of the Suspended-Gate FET and Design
Insights for Low-Power Logic, IEEE Transactions on Electron Devices, 55(1), pp. 48
59, 2008.
20. Y. S. Chauhan, D. Tsamados, N. Abele, C. Eggimann, M. Declercq, A. M. Ionescu,
"Compact modeling of suspended gate FET, IEEE Conference on VLSI Design
(Hyderabad, India), J an. 2008.
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Casset, P. Ancey, L. Buchaillot, A. M. Ionescu, Measurement of nano displacement
based on in-plane suspended gate MOSFET detection compatible with front-end CMOS
process, IEEE International Conference Solid-State Circuits Digest, pp. 332-333, 2008.
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A.M. Ionescu, L. Buchaillot, In-plane Silicon-On-Nothing nanometer-scale resonant
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Laterally vibrating-body double gate MOSFET with improved signal detection, Annual
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15
5. Appendix


Table with basic figures of merit of NEM relay

Principle of Operation Control mechanism Electrostatic actuation
Materials Base Si, SiC, TiN, metals used in CMOS (top-
down); CNT or NW (bottom-up)
Geometry Device or Circuit element Mechanical relay, 3 or 4 terminal
Patterning Lithography for top-down, self-assembly
for bottom-up
Device density as a function of feature size F ~1/(F^2 x R), where F =gap =beam
thickness. Lateral technology is assumed.
R is the beam aspect ratio.
Size in units of feature size F of a gate equivalent
to a 2-input NAND gate, including contacts and
isolation and necessary peripheral circuitry
>~10F^2xR (same assumptions as
above, NAND =2x inverter area)
Functonal Density in terms of "gate equivalents"
per cm
2
using the primitive cell size defined above
and an appropriate value of F.
Operating Parameters Operating temperature compatible with high-T electronics
Output sensing device Relay
Self gain N/A
Switching Energy per gate or gate equivalent @
proposed clock rate 0.5*(Cgap +Cload)*Vdd^2
Static Power Dissipation per gate or gate
equivalent
zero
Binary throughput (Gbits/nsec-cm
2
-joule)
Logic Family
Information processing basis
Universal set comprising NAND, NOR,
NOT logic gates, also pass gates
Interconnects Wire
Compatible memory SRAM (fast) , DRAM (dense), also NV
memory
Clock or its equivalent Relay based clock circuits
CMOS compatible Yes
Performance Potential
Switching speed and energy
Intrinsic speed of single element
Delay ~ns range, VDD ~a few 100 mV,
Energy ~ aJ range
Self Gain N/A
Interconnect Interconnect delay per micron RC
Interconnect energy as a function of distance at
proposed clock rate
CV^2
Limitations
Materials and Geometry Sources of variability gap, thickness, material properties, vdW
forces
External parasitics fringe capacitance
State variables and control Noise margin better or comparable with CMOS
QM limit Tunneling
This section comprises a list of known limiting factors for performance and
manufacturing
This section comprises an extrapolation of the technology to about the year 2020,
stipulating F=14 nm. Provide best estimate numerical values.






16

Table with basic figures of merit of NEM-FET

Major Categories Subcategories NEMFET
Basic description
Device Proposed Primitive Unit Cell or Device Field-Effect Transistor with movable gate
or movable body
State variables and control State variable Charge or Voltage
Number of logic states 2 (binary) but quaternary logic possible
Principle of Operation Control mechanism Electrostatic actuation
Materials Base Si, CMOS-compatible metals, SiGe,
CNTs, NanoWires
Geometry Device or Circuit element Combination: MEMS capacitor +
MOSFET with 3 or 4 terminals
Patterning Lithography for top-down. In case of
CNTs bottom-up assembly
Device density as a function of feature size F ~1/(R*F^2), R=aspect ratio of
suspended structure. In short-channel
NEMFETs R can be >10
Size in units of feature size F of a gate equivalent to
a 2-input NAND gate, including contacts and
isolation and necessary peripheral circuitry
>~65F^2 (mech. anchors)
Functonal Density in terms of "gate equivalents" per
cm
2
using the primitive cell size defined above and
an appropriate value of F.
Similar to CMOS
Operating Parameters Operating temperature Room-temperature up to ~125 deg. C
Output sensing device MOSFET
Self gain gm/gd, gm depends on Cgap(VG)
Switching Energy per gate or gate equivalent @
proposed clock rate 0.5*(2/3*Cox +Cload)*Vdd^2
Static Power Dissipation per gate or gate equivalent Vdd*Ileak (Ileak=junction leakage)
Binary throughput (Gbits/nsec-cm
2
-joule)
Logic Family
Information processing basis
Universal set comprising NAND, NOR,
NOT logic gates, also pass gates
Interconnects Wire
Compatible memory Capacitor less SRAM (fast) , DRAM
(dense), also NV memory
Clock or its equivalent CMOS based clock circuits
CMOS compatible Yes
Performance Potential
Switching speed and energy
Intrinsic speed of single element
Limited by the mechanical response of
the MEMS part, <1ns @ <2V
Self Gain gm/gd, gm depends on Cgap(VG)
Interconnect Interconnect delay per micron RC
Interconnect energy as a function of distance at
proposed clock rate
CV^2
Limitations
Materials and Geometry Sources of variability gap, thickness and width of beam
(depending on the orientation- thickness
for out-of-plane, width for in-plane
movement), material properties, vdW
forces +CMOS variability sources
External parasitics access resistance, fringe capacitance
State variables and control Noise margin
Depends on the electromechanical
design, could be better than std MOSFET
QM limit For actuation: Casimir and VdW forces
This section comprises a description of the proposed device family. The section may
include textual and graphical descriptions but should be independent of (or
parameterized by) feature size F
This section comprises a list of known limiting factors for performance and
manufacturing
This section comprises an extrapolation of the technology to about the year 2020,
stipulating F=14 nm. Provide best estimate numerical values.