JOURNAL OF TELECOMMUNICATIONS, VOLUME 25, ISSUE 2, JUNE 2014

7

An Efficient 12b 30MS/s Pipelined SAR ADC in
180nm CMOS
L. Bagheriye, S. Toofan and KH. Dabbagh Sadeghipour

Abstract This paper describes the design of a 12-b 30MS/s analog to digital converter (ADC) in a 0.18m CMOS technology.
The converter pipelines a first stage 5b MDAC with a second stage 8b SAR ADC. Using SAR ADC in the first stage's sub-ADC,
instead of FLASH type, frees the ADC from an extra front-end sample-and-hold and uses only one comparator in first stage,
resulting a power efficient ADC architecture. To improve SNR, comparator with a rail-to-rail common-mode input range is used
in each stages. This ADC consumes only 10 mW and achieves an SNDR of 64.86 dB, resulting in a figure of merit (FOM) of 186
fJ/Conversion-step.
Index Terms Analog-to-digital converter, successive approximation architecture, pipeline ADC, low power

!

1 INTRODUCTION
n SoC imIemenlalions Iarge digilaI arls and more
anaIog funclions such as anaIog lo digilaI converlers
are inlegraled on one chi. ResuIling in a Iimiled budgel
for lheir lolaI heal and over dissialion. The over con-
sumlion is becoming one of lhe mosl crilicaI faclors for
eIeclronic syslems, such as vireIess syslems. An ADC
vilh a medium samIing rale (a fev lens lo hundreds of
MS/s) and a medium resoIulion is a necessary buiIding
bIock for 802.11/a/b/g vireIess nelvorks|1j. Medium
seed and medium resoIulion aIicalions have been in
lhe lerrilory of ieIine ADCs bul in ieIine ADCs lhe
Iarge over consumlion is one of lhe mosl imorlanl
issues. Oams are lhe mosl over-hungry bIocks of
ieIine slages. SeveraI melhods have been roosed lo
reduce lhe over consumlion of lhese ADCs |2-6j.
Oam sharing lechnique reduces lhe over consum-
lion by sharing one oam belveen lvo successive slag-
es. The svilched-oam lechnique reduces lhe over
consumlion by lurning lhe oam off during lhe amIi-
ficalion hase. Comaralor ased Svilched Caacilor
(CSC) circuils, overcome Iimilalions from lechnoIogy
scaIing by reIacing lhe oam in cIosed-Ioo vilh a
more over efficienl slruclure. DoubIe samIing lech-
nique reduces lhe over consumlion by exanding lhe
avaiIabIe lime for sellIing of lhe oam. ReIacing reci-
sion amIifiers by simIe over efficienl oen-Ioo slag-
es is lhe olher lechnique. Hovever, lhese lechniques aIso
suffer from some dravbacks. Oam sharing. and dou-
bIe samIing lechniques suffer from an effecl caIIed lhe
"memory effecl" vhich is caused because lhere is no lime
lo resel lhe inul and oulul nodes of lhe oam. Ior
svilched oam lechnique, because lhe oam shouId be
lurned off during lhe amIificalion hase and lhen
lurned on for lhe samIing hase, lhe sellIing lime of lhe
oam viII increase since il lakes some lime for lhe
oam lo aclive. The CSC lechnique has onIy been
shovn in siIicon in singIe-ended form, lhus is suscelibIe
lo common mode noise vhich couId be very Iarge in an
inlegraled syslem |7j. AIso a digilaI background caIibra-
lion lechnique as an enabIing eIemenl is needed lo re-
Iace recision amIifiers by simIe over-efficienl oen-
Ioo slages. Wilh advances in CMOS lechnoIogy, such as
device dimensions shrink and enhancemenl of malching
in assive devices (eseciaIIy caacilors) SAR ADC slruc-
lures have been demonslraled as feasibIe aIlernalives
since lhey are inherenlIy Iov over (onIy one comaralor
and no high gain amIifiers). Hovever SAR ADC's re-
quire severaI comarison cycIes lo comIele one conver-
sion, and lherefore have Iimiled oeralionaI seed |8j. In
lhis aer a hybrid archileclure of ieIine and SAR is
used lo achieve 12b 30MS/s vilh Iov over consum-
lion. The ieIined SAR ADC is allraclive because of ils
Iov over and area comensalion. RecenlIy fev vorks
have used ieIine of SAR ADCs archileclure|8-9j. In |8j
a haIf-gain MDAC is roosed, vhich aIong vilh lhe
Iarge resoIulion, heIs reduce lhe over consumlion of
lhe firsl-slage o-am and imroves lhe ADC Iinearily. In
|9j a singIe-ended 1.5-bil/cycIe conversion lechnique is
used lo miligale lhe comaralor offsel issue vilhoul us-
ing redundanl bil in firsl slage so omilled an exlra con-
version cycIe. In lhis vork vilh using one bil redundan-
cy in firsl slage lo miligale offsel requiring of comaralor
and sIil archileclure for lhe second slage, lhe Iov over
requiremenls are achieved. This ADC consumes onIy 10
mW from 1.8 V suIy , vilh a IOM of 186 f}/conversion-
sle.

Seclion II of lhis aer describes lhe design concel and
archileclure of roosed ieIined SAR ADC. Seclion III
resenls lhe design of key buiIding bIocks. SimuIaled
resuIls are given in seclion IV and seclion V incIudes lhe
concIusion.
L. Bagheriye is a Ph.D. student with the Department of Electrical Engineer-
ing, University of Zanjan, Zanjan, Iran
S. Toofan have been working as assistant professors with the Department of
Electrical Engineering, University of Zanjan, Zanjan, Iran
KH. Dabbagh Sadeghipour, , have been working as assistant professors with
the Department of Electrical Engineering,University of Tabriz, Tabriz 51664,
Iran.

I
8

2 PROPOSED ARCHITECTURE
A fronl-end S/H is usuaIIy required in a high-resoIulion,
high-seed ieIine ADC|8j. In lhe absence of fronl-end
S/H, for a difference in effeclive samIing lime belveen
lhe sub-ADC and MDAC of
skew
! , and an inul sinusoid
vilh frequency f
in
, and eak voIlage V
peak
, lhe maxi-
mum difference in inul voIlage samIed by lhe MDAC
and sub-ADC is given by |7j:

2
max
f
V
skew peak
i
V
n
skew
! = "
#
(1)

To ensure vide sving and noise immunily, a fuIIy differ-
enliaI archileclure is seIecled for vhoIe ADC. Iig. 1.
shovs lhe roosed ADC archileclure. The firsl slage
resoIves 5 bils (one bil redundancy) and lhe second slage
resoIves lhe remaining 8 bils. Timing of lhe ADC is
shovn in Iig. 2.
The Iarge firsl slage resoIulion has been shovn lo be very
beneficiaI for vhoIe erformance of lhe ADC|8j. In lhis
design 5bil is seIecled lo firsl slage, lhe Iimiled faclor lo
increasing lhe firsl slage resoIulion is lhe gain bandvidlh
of gain slage and consequenlIy ils over consumlion.
Due lo equalion (2) N is lhe ADC resoIulion, M is lhe
resoIulion of firsl slage, f is feed back faclor and T
s
is lhe
oam sellIing lime. Il is seen lhal vilh every increase of
firsl slage resoIulion decrease and lhe required GW,
increases so resuIling more over consumlion.
(2)
1 ( / )(2 ) ( ) ln 2 (1/ ) T
s
GBW f N M ! " #

3 Key Building Blocks
3.1 Opamp Design
Iig. 3 shovs lhe o am slruclure, lo achieve high dc
gain a foIded cascode archileclure vilh gain boosling is
used |10j. The gain boosling amIifier, AI is anolher foId-
ed cascade amIifier vilh NMOS lransislors as inul
airs and lhe AN is simiIar lo main amIifier. Conlinues
lime CMI feedback circuils, due lo lheir high seed o-
eralion is chosen for main amIifiers and gain booslers.
As deicled in Iig. 4, lhis oam achieves 82 d oen
Ioo gain. The key fealures of lhe oeralionaI amIifier
are summarized in TabIe1.
S
AMP
5b SAR !
8b SAR !
33.33ns
12ns
9.3ns

Fig. 2. Timing of the ADC


3
M
4
M
N
A
5
M
6
M
out
V
8
M
7
M
P
A
10
M
9
M
2
M
1
M
in1
V
in2
V

Fig. 3. The designed opamp



Fig. 4. Gain and phase of open loop response











Control
Block
1 u
BinaryWeighted
Capacitor Array
C C
=
Digital Error Correction
OPAMP OPAMP
Control
Block
2 u
Split Capacitor
Array
C C
=
in V S
AMP AMP
AMP
8b 5b
12b
1 2C
0
:
4
<
>
0
:
7
<
>

Fig. 1. Proposed ADC Architecture


Fig. 1. Two-stage amplifier

TABLE 1 Opamp simulation result

DC gain 82 dB
Gain-bandwidth 1.57G
Settling-time 5ns
Load cap 2pf
Power 6.5mW


9

Pr eamplifier
Latch
SR
out C
in V
ip V



Fig. 5. The structure of comparator


bp V
DD
V
on V
bn V
ip V
in V
op V
on V
DD
V
op V


Fig. 6. The proposed preamplifier circuit
3.2 COMPARATOR DESIGN
As shown in fig. 5 the comparator used in each stage,
consists of three blocks, a preamplifier, a latch and a SR
latch. A preamplifier is added to reduce the effect of kick
back noise. Fig. 6 shows the proposed preamplifier archi-
tecture. The low supply voltage inherently limits the
maximum input signal swing of an ADC, and thus may
lead to a poor peak signal-to-noise ratio (SNR ) [11]. The p
and n-type differential pairs connected in a parallel man-
ner are used to extend the common-mode input range to
the power rails. The latch circuit is the same used in [12]
and the succeeding SR latch is to storing the comparison
result for the entire clock cycle. Otherwise the compara-
tor output is always pre charged to
DD
V

at the reset
mode,
.
unnecessary signal level change will consume ex-
tra power[13].
3.3 DAC DESIGN

The linearity of the DAC, affected by the capacitor mis-
match, directly limits the performance of the ADC. The
capacitive DAC with a binary- weighted capacitor array is
used in first stage. The unit capacitor in the DAC should
be kept as small as possible for power saving. In practice,
it is usually determined by the thermal noise, design rules
and capacitor mismatch. It is important that the DAC of
the first stage of a pipeline ADC should have the linearity
specifications to meet the overall resolution of the ADC.
So in this design, mismatch is dominant over thermal
noise. For a typical metal-insulator-metal (MIM) capacitor
it has,

/ . ( / , ) A A K K
c
C C C
!
! " = = (3)


where ( / ) C C ! " is the standard deviation of capacitor
mismatch, K
!
is the matching coefficient, A is the capaci-
tor area, and K
c
is the capacitor density parameter. For
high yield, it is necessary to maintain:

3 0.5 LSB ! <
(4)

a lower bound for the mismatch-limited unit capacitor is
achieved in [14] as:


2
2
min
18.( 1). .
n
C K K
c u !
= " (5)

considering overall limitations and a suitable margin, for
MIM capacitors, the value of unit capacitor is selected
30fF for the first stage. The architecture of DAC in second
stage is the same in first stage. Because of the using high
gain opamp, the
requiring of thermal noise is sophisticated, so a smaller
unit size can be used in the second stage. For better line-
arity bootstrapped switches applied to sample input signal onto
bottom plate of the capacitor arrays in each stages[15]. In this
design, V
ref
is set to 1.5V, CMOS TG is chosen for V
ref

to benefit from its low on-resistance. NMOS switches can
properly pass a zero, so NMOS switch is employed to
ground the bottom plate. In order to achieve a fast set-
tling time in the DAC, relatively wide MOS switches is
used and the sizes of the transistors in the first-stage
comparator are tapered to drive these switches with min-
imum delay [15]. Also to prevent unnecessary energy con-
sumption and to keep the RC value the same, the sizes of the
switches are scaled down according to the driven capacitanc-
es[1]. To care about the charge injection event at the top-
plate when the switch turns off at each beginning of the
conversion, a CMOS TG is employed as a switch here.
4 SIMULATION RESULTS
The ADC has been simulated in standard 180-nm CMOS
technology with 1.8-V supply voltage. a typical 1024 points
FFT of the output spectrum in the input frequency of
10MHz. The ENOB of the proposed SARADC is
ENOB=10.8bits and the overall power consumption of the
ADC is 10mW. The resulting FOM from equation 3 is
186fJ/conv.


2
POWER
FOM
ENOB
F s
!
= (6)

The overall performance of the proposed ADC is summa-
rized in Table II, and the comparison of the this work
with some other published works is given in table III.
With considering the using technology in [8]-[9],[16], it is
2012 JOT
www.journaloftelecommunications.co.uk
10

obvious that the ADC designed in this paper also has a
good performance.

5 CONCLUSION
This paper presents 12-bit, 30MS/s, two stage pipelined
SAR ADC. First stage uses 5-bit SAR sub -ADC which
guaranty low power consumption with eliminating front-
end S/H and using only one comparator instead of 31 in
FLASH type. The second stage constructed from an 8bit
SAR ADC. In order to
better the input swing and SNR, a comparator with a rail-to-
rail common-mode input range is used. The ADC with 10
MHz input signal, consumes 10mW from a 1.8V supply and
reaches an ENOB of 10.8bits at 30MS/sec.

TABLE 2
FEATURES OF THE REALIZED ADC

















TABLE III:
COMPARISON WITH OTHER WORKS

















REFERENCES
|1j C. C. Liu, S. }. Chang, G. Y. Huang, and Y. Z. Lin, A 10-bil 50-
MS/s SAR ADC Wilh a Monolonic Caacilor Svilching Iroce-
dure, !""" $% &'()*+&,-,. /)012),34$&&/56 7'(% 896 :'% 86 6 ;;% <=>?
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;;% @=E+@8B6 A2G>@@8%
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CMOS TechnoIogies, !""" $% &'()*+&,-,. /)012),34$&&/566 7'(%8>6
:'%>B6 ;;%BE9D+BEED6 F.1BCCE%
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Conversion Technique, !""" $% &'()*+&,-,. /)012),34$&&/56 7'(% 8E6
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': /)012),3 -:* &H3,.I36 7'(% 9=6 :'% <6 . 542-5456 $2( BCC< .
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!""" $% &'()*+&,-,. /)012),34$&&/56 7'(% 8<6 :'% <6 ;;% >9D9+>9@=6 6 $2(
BC>B%
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;;% >EE<+>E<D F.1 >@@B%
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Leila Bagheriye received the B.Sc. degree in Control Engineering
from University of Tabriz, Tabriz, Iran in 2010, and the MSc degree
in Electronics Engineering form the University of Zanjan, Zanjan, Iran
in 2012. She is currently pursuing the Ph.D. degree in Electrical En-
gineering at Electrical Engineering Department, at University of Zan-
jan. Her research interests are in the area of high-speed low-power
A/D converters.
.
Siroos Toofan received the B.Sc. degree in Electronics Engineering
from Amirkabir University of Technology (Tehran Polytechnic) in
1999, and the MSc. And PhD degree in Electronics Engineering form
Technology CMOS 0.18 m
Resolution 12bits
Samplin Frequency 30MS/s
Input Range 3V, diff
SNDR(@ 10MHz) 66.78dB
SFDR(@ 10MHz) 80.56dB
Supply-voltage 1.8V
Power 10mW

References
ENOB
[bits]

Input
swing
[VP-P
diff,V
]
Fs
[MHz]
Pow
[mW]
Process
FoM
[fJ/conv]
Pipelined
SAR[8]
10.7 2 50 3.5
65nm
CMOS
52
Pipelined
SAR[9]
8.9 1.8 40 1.21
65n
CMOS
65
Pipelined
SAR[16]
(resolution
:12b)
1.8 5 4
0.18
CMOS
190
This work
Pipelined
SAR
10.8 3 30 10
0.18
CMOS
186

11

ran University of Science and Technology (IUST) in 2002 and 2008,
respectively. During 2007 to 2008, on his sabbatical leave, he was
with the VLSI group of Politechnico di Torino and in the Microelec-
tronics- Integrated Circuits Lab. of the Politechnico di Milano Univer-
sities in Italy.
He has been working as assistant professor with the Department of
Electrical Engineering, University of Zanjan, since 2009. His current
research activities include the design of CMOS Analog Integrated
Circuits, RF Integrated Circuits and Capacitive Sensors Readout
Circuits.

Khosrov Dabbagh Sadeghipour He received the B.S. and M.S.
degrees from Urmia University and Tarbiat Modarres University and
Ph.D. degree from Urmia University all with Honors in Electrical and
Electronics Engineering in 1997, 2000 and 2006 respectively. He is
currently an Assistant Professor in University of Tabriz, Tabriz, Iran.
His main research interests are high speed and low power analog to
digital convertor
and wideband mixed mode circuits design. He holds 10 Iranian pa-
tents and more than 10 papers in scientific journals or conference
proceeding.