1.

what is the difference between mealy and moore state-machines

2. How to solve setup & Hold violations in the design
To solve setup violation
1. optimizing/restructuring combination logic between the flops.
2. Tweak flops to offer lesser setup delay [D!1 "# D!$%
&. Tweak launch"flop to have better slew at the clock pin' this
will make ()"#* of launch flop to be fast there by helping fi$ing
setup violations
+. ,lay with skew [ tweak clock network delay' slow"down clock to
capturing flop and fasten the clock to launch"flop%-otherwise called as .seful"skews/
To solve 0old 1iolations
1. 2dding delay/buffer[as buffer offers lesser delay' we go for spl
Delay cells whose functionality 342' but with more delay%
2. 5aking the launch flop clock reaching delayed
&. 2lso' one can add lockup"latches [in cases where the hold time
re6uirement is very huge' basically to avoid data slip%
3. What is antenna Violation & ways to prevent it
During the process of plasma etching' charges accumulate along the metal strips. The
longer the strips are' the more charges are accumulated. 7 a small transistor gate
connected to these long metal strips' the gate o$ide can be destroyed -large electric field
over a very thin electric/ ' This is called as 2ntenna violation.
The ways to prevent is ' by making 8ogging the metal line' which is atleast one metal
above the layer to be protected. 7f we want to remove antenna violation in metal2 then
need to 8og it in metal& not in metal1. The reason being while we are etching metal2'
metal& layer is not laid out. 9o the two
pieces of metal2 got disconnected. :nly the piece of metal connected to gate have charge
to gate. ;hen we laydown metal&' the remaining portion of metal got charge added to
metal&. This is called
accumulative antenna effect.
2nother way of preventing is adding reverse Diodes at the gates
. We have multiple instances in !"#$!egister "ransfer #anguage%& do you do
anything special during synthesis stage'
;hile writing <T=-<egister Transfer language/'say in verilog or in 10D= language' we
dont write the same module functionality again and again' we use a concept called as
instantiation' where in as per the language' the instanciation of a module will behave like
the parent module in terms of functionality' where during synthesis stage we need the full
code so that the synthesis tool can study the logic ' structure and map it to the library
cells' so we use a command in synthesis ' called as >.?7*.73> which will replace the
instantiations with the real logic' because once we are in a synthesis stages we have to
visualize as real cells and no more modelling 8ust for functionality alone' we need to
visualize in"terms of physical world as well.
(. what is tie-high and tie-low cells and where it is used
Tie"high and Tie"=ow cells are used to connect the gate of the transistor to either power
or ground. 7n deep sub micron processes' if the gate is connected to power/ground the
transistor might be turned on/off due to power or ground bounce. The suggestion from
foundry is to use tie cells for this purpose. These cells are part of standard"cell library.
The cells which re6uire 1dd' comes and connect to Tie high...-so tie high is a power
supply cell/...while the cells which wants 1ss connects itself to Tie"low.
). what is the difference between latches and flip-flops based designs
=atches are level"sensitive and flip"flops are edge sensitive. latch based design and flop
based design is that latch allowes time borrowing which a tradition flop does not. That
makes latch based design more efficient. @ut at the same time' latch based design is more
complicated and has more issues in min timing -races/. 7ts 9T2 with time borrowing in
deep pipelining can be 6uite comple$.
*. What is High-Vt and #ow-Vt cells.
0vt cells are 5:9 devices with less leakage due to high 1t but they have higher delay
than low 1T' where as the low 1t cells are devices which have less delay but leakage is
high. The thereshold-t/ vloltage dictates the transistor switching speed ' it matters how
much minimum threshold voltage applied can make the transistor switching to active
state which results to how fast we can switch the trasistor. disadvantage is it needs to
maintain the transistor in a minimum subthreshold voltage level to make ir switch fast so
it leads to leakage of current inturn loss of power.
+. What is #,- mean'
=A is an 29(77 data format from (adence Design inc' to describe a standard cell library.
7t includes the design rules for routing and the 2bstract layout of the cells. =A file
contains the following'
TechnologyB layer' design rules' via"definitions' metal"capacitance
9ite B 9ite e$tension
5acros B cell descriptions' cell dimensions' layout of pins and blockages' capacitances
To get further insight to the topic' please check this
httpB//www.csee.umbc.edu/Ccpatel2/links/+1+/slides/lectD&E=A.pdf
.. what is /,- mean'
DA is an 29(77 data format from (adence Design inc.' to describe Design related
information.
10. 1teps involved in designing an optimal padring
1. 5ake sure you have corner"pads' across all the corners of the padring' This is mainly
to have the power"continuity as well as the resistance is less .
2. Ansure that the ,adring ful"fills the A9D re6uirement' 7dentifyh the power"domains'
split the domains' Ansure common ground across all the domains.
&. Ansure the padring has ful"filled the 99?-9imultaneous 9witching ?oise/ re6uirement.
+. ,lacing Transfer"cell ,ads in the cross power"domains' for different height pads' to
have rail connectivity.
F. Ansure that the design has sufficient core power"pads.
G. (hoose the Drive"strenght of the pads based on the current re6uirements' timing.
H. Ansure that there is seperate analog ground and power pads.
I. 2 ?o"(onnection ,ad is used to fill out the pad"frame if there is no re6uirement for
7/:Js.A$tra 1DD/K?D pads also could be used. Ansure that no 7nput/output pads are used
with un"connected inputs' as they consume power if the inputs float.
L. Ansure that oscillator"pads are used for clock inputs.
1D. 7n"case if the design re6uirement for source synchronous circuits' make sure that the
clock and data pads are of same drive"strength.
11. @reaker"pads are used to break the power"ring' and to isolate the power"structure
across the pads.
12. Ansure that the metal"wire connected to the pin can carry sufficient amount of the
current' check if more than one metal"layer is necessary to carry the ma$imum current
provided at the pin.
1&. 7n case if re6uired ' place pads with capacitance.
related information.
11. What is metastability and steps to prevent it.
5etastability is an unknown state it is neither Mero nor :ne.5etastability happens for the
design systems violating setup or hole time re6uirements. 9etup time is a re6uirement '
that the data has to be stable before the clock"edge and hold time is a re6uirement ' that the
data has to be stable after the clock"edge. The potential violation of the setup and hold
violation can happen when the data is purely asynchronous and clocked synchronously.
9teps to prevent 5etastability.
1. .sing proper synchronizers-two"stage or three stage/' as soon as the data is coming
from the asynchronous domain. .sing 9ynchronizers' recovers from the metastable
event.
2. .se synchronizers between cross"clocking domains to reduce the possibility from
metastability.
&. .sing aster flip"flops -which has narrower 5etastable ;indow/.
12. what is local-s2ew& global-s2ew&useful-s2ew mean'
=ocal skew B The difference between the clock reaching at the launching flop vs the clock
reaching the destination flip"flop of a timing"path.
Klobal skew B The difference between the earliest reaching flip"flop and latest reaching
flip"flop for a same clock"domain.
.seful skewB .seful skew is a concept of delaying the capturing flip"flop clock path' this
approach helps in meeting setup re6uirement with in the launch and capture timing path.
@ut the hold"re6uirement has to be met for the design.
13. What are the various timing-paths which i should ta2e care in my 1"3 runs'
1. Timing path starting from an input"port and ending at the output port-purely
combinational path/.
2. Timing path starting from an input"port and ending at the register.
&. Timing path starting from an <egister and ending at the output"port.
+. Timing path starting from an register and ending at the register.
1. What are the various components of #ea2age-power'
1. sub-threshold lea2age
"courtesy )hondker
2. gate lea2age
"courtesy )hondker
3. reverse biased drain substrate and drain substrate 4unction band-band tunnelling
1(. What are the various yield-losses in the design'
The yield loss in the design is characterized by
1. unctional yield losses' mainly caused by spot defects ' especially -shorts N opens/
2. ,arametric yield losses' due to process variations.
1). what is meant by virtual cloc2 definition and why do i need it'
1irtual clock is mainly used to model the 7/: timing specification. @ased on what clock
the output/input pads are passing the data.
or urther .nderstanding of the concept.
httpB//www.vlsichipdesign.com/images/virtualEclock.8pg
attached below..
1*. What are the various Variations which impacts timing of the design'
1+. What are the various /esign constraints used while performing 1ynthesis for a
design'
1. (reate the clocks -fre6uency' duty"cycle/.
2. Define the transition"time re6uirements for the input"ports.&
&. 9pecify the load values for the output ports
+. or the inputs and the output specify the delay values-input delay and ouput delay/'
which are
already consumed by the neighbour chip.
F. 9pecify the case"setting -in case of a mu$/ to report the timing to a specific paths.
G. 9pecify the false"paths in the design
H. 9pecify the multi"cycle paths in the design.
I. 9pecify the clock"uncertainity values-w.r.t 8itter and the margin values for setup/hold/.
1.. 1pecify few verilog constructs which are not supported by the synthesis tool.
initial' delays' real and time data types' force and release' fork 8oin.
20.what are the various capacitances with an 561-,"'7strong8
21.Vds-9ds curve for an 561-,"& with increasing Vgs.
22. :asic 6peration of an 561-,".
23. What is ;hannel length 5odulation'
"courtesy )hondker
2. what is body effect'
7ncrease in 1t-threshold voltage/ ' due to increase in 1s-voltage at source/' is called as
body effect.
2(. What is latchup in ;561 design and ways to prevent it'
To best understand the concept behind the latchup' we need to understand the concept
behind 9(<-9ilicon (ontrolled <ectifiers/' and how to model the basic transistor in an
9(< structure and on what conditions 9(< structures are created in the (5:9 design
process and its effects and what are the ways used to prevent it in the design"phase.An
SCR is an acronym for Silicon Controlled Rectifier. It works similar to a typical diode, but is
controlled similar to a bipolar transistor as far as connections go. Connection points are Anode
[A], Cathode [], and !ate [!]. "he SCR is made up of two #$%&# 'unctions with a #!ate#
attachment between them. "he gate is connected between the two $%& 'unctions with a current
waiting in the forward bias direction [( to %] and the )oltage is abo)e *%)olt. A momentary pulse to
the gate will cause the SCR to conduct and current will flow across the de)ice until the )alue
changes.
2(. What are the various design changes you do to meet design power targets'
Design with 5ulti"1DD designs' 2reas which re6uires high performance' goes with
high 1DD and areas which needs low"performance are working with low 1ddJs' by
creating 1oltage"islands and making sure that appropriate level"shifters are placed in the
cross"voltage domains
Designing with 5ulti"1tJs-threshold voltages/' areas which re6uire high
performance' goes with low 1t' but takes lot of leakage current' and areas which re6uire
low performance with high 1t cells' which has low leakage numbers' by incorporating
this design process' we can reduce the leakage power.
2s in the design ' clocks consume more amount of power' placing optimal clock"gating
cells' in the design and controlling them by the module enableJs gives a lot of power"
savings.
2s clock"treeJs always switch making sure that most number of clock"buffers are
after the clock"gating cells' this reduces the switching there by power"reduction.
7ncorporating Dynamic 1oltage N re6uency scaling -D19/ concepts based on the
application ' there by reducing the systems voltage and fre6uency numbers when the
application does not re6uire to meet the performance targets.
Ansure the design with 7<"Drop analysis and ground"bounce analysis' is with"in the
design specification re6uirement.
,lace power"switches' so that the leakage power can be reduced. related
information.
2*. what is meant by #ibrary ;haracteri<ing= "Chip designing is all about Modeling
the silicon", and how well we characterize the silicon' is all the game. 9o initially let us
assume our process technology is say >&2nm>' for e$ampleB ?ow we need to develop a
test"chip' having modules -digital N analog/' and study our silicon timings. ?ow the
toughest 8ob is to generate library views-formats specific to each tool understandable
formats/.There is a bit of timing in accuracy possible in the views across the formats.

2+. what is meant by wireload model=
7n the synthesis tool' in order to model the wires we use a concept called as >;ireload
models>' ?ow the 6uestion is what is wireload modelsB ;ireload models are statistical
based on models with respect to fanout. say for a particular technology based on our
previous chip e$perience we have a rough estimate we know if a wire goes for >n>
number of fanin then we estimate its delay as say >$> delay units. 9o a model file is
created with the fanout numbers and corresponding estimated delay values. This file is
used while performing 9ynthesis to estimate the delay for ;ires' and to estimate the
delay for cells' technology specific library model files will be available
31. what are the measures in the /esign ta2en for 5eeting 1ignal-integrity targets
2s more and more devices are getting packed' results in more congested areas' and
coupling capactiances dominating the wire"capacitance' creates 97 violations. =etJs see
now by what are all the measures we can reduce/solve it.
2s clock"tree runs across the whole chip' optimizing the design for 97' is essential
route the clock with double"pitch and triple spacing.
7n"case of 97 violation' spacing the signal nets reduces cross"talk impacts.
9hield the nets with power"nets for high fre6uency signal nets to prevent from 97.
Anable 97 aware routing ' so that the tool takes care for 97
Ansure 97 enabled 9T2 runs' and guarantee the design meeting the 97
re6uirements
<oute signals on different layers orthogonal to each other
5inimize the parallel run"length wires' by inserting buffers.
32. what are the measures ta2en in the /esign achieving better >ield
@etter yield could be achieved by reducing the possibility of manufacturability flaws.
Kuaranting the circuit performance' by reducing parametric yield' with process variations
playing a ma8or role is a big"challenge.
(reate more powerful stringent runset files with pessimistic spacing/short rules.
(heck for the areas where the design is prone to lithographic issues' like sharp
cuts and try to re"route it.
or via"reliability issues' use redundant vias' to reduce the chances for via"
breakage.
7n order to design for yield"enhancement ' design systems' which could have
optimal redundancy' like repairable memories.
:ptimal placing of de"coupling capacitances' reduces the power"surges.
Doubling the width of the non"critical nets' clock"nets can increase the yield
parameter.
Ansure that the poly"orientation are maintained.
32. what are the measures or precautions to be ta2en in the /esign when the chip
has both analog and digital portions
/esigning for 6ptimal integration of 3nalog and /igital
2s todayJs 7( has analog components also inbuilt ' some design practices are
re6uired for optimal integration.
Ansure in the floorplanning stage that the analog block and the digital block are
not siting close"by' to reduce the noise.
Ansure that there e$ists seperate ground for digital and analog ground to reduce
the noise.
,lace appropriate guard"rings around the analog"macroJs.
7ncorporating in"built D2("2D( converters' allows us to test the analog portion
using digital testers in an analog loop"back fashion.
,erform techni6ues like clock"dithering for the digital portion.
33. what are the steps incorporated for ,ngineering ;hange 6rder?,;6@
2s more and more comple$ the 7( design is ' and with lot of first time application ' is
more prone to
last minute changes' there should be provision in the design"flow to accomodate the
functional and timing bugs. The step to perform this called as Angineering change
order-A(:/.
Ansure that the design has spare functional gates well distributed across the
layout.
Ansure that the selection the spare gates' has many flavours of gates and universal
gates' so that any functionality could be achieved.
3. what are the steps performed to achieve #ithography friendly /esign
Designing for 5anufacturability re6uires validating the design full"filling lithography
rules
(hecking the layout confirming the design rules -spacing'trace"width'shorts/.
(heck for the less"congested areas and increasing the spacing of the nets.
3(. what does synthesis mean
9ynthesis is a step of mapping the <T= files -verilog format or vhdl format/ to convert it
to the technology specific cells..
3). what are the pre-reAuisties to perform synthesis
1. <T= files
2. 9ynopsys constraints file' Design constraints file' e$plaining the priorities of cost
functions like area/timing/power
&. Technology specific library files.
3. ,Bplain the 1ynthesis flow
1ynthesis !eference flow
3(. What are the various ways to reduce ;loc2 9nsertion /elay in the /esign
1. ?umber of (lock sinks
2. @alancing two different clock fre6uencies
&. ,lacement of clock sinks.
+. ,lacement of (lock gating cells
F. (lock tree buffers/inverters drive strengthJs
G. (lock Transition
H. placement of (lockgating cells and the clock sinks
I. (ombinationals cells in the path of clocks -say clock dividers' mu$es' clockgates/ ...
3). what are the various functional verification methodologies
T=5-Transaction =evel 5odelling/
=inting
<T= 9imulation - Anivronment involving B stimulus generators' monitors'
response checkers' transactors/
Kate level 9imulation
5i$ed"signal simulations
<egression
3). What does formal verification mean'
ormal verification uses 5athematical techni6uest by prooving the design through
assertions or properties. (orrectness of the design can be achieved through assertions
with out the necessity for simulations. The methods of formal verification are
1. ,Auivalence chec2ing 7n this method of checking the designs are compared based on
mathematical e6uations and compared whether they are e6ual or not .
:riginal <T= vs 5odified <T=
<T= vs ?etlist
Kolden ?etlist vs 5odified/Adited ?etlist
9ynthesis ?etlist vs ,lace and route ?etlist
<emember B ormal verification doesnt check for functionality of the <T= code. 7t
will be only checking the e6uivalence.
2. 5odel chec2ing ,roperty specification languages like ,9= or 912' are
formally analyzed to see if they are always true for a design. This can
e$haustively prove if a property is correct' but does tend to suffer from state"space
e$plosionB the time to analyse a design is directly propotional to the amount of
states.
3*. How will you time the output paths'
3+. How will you time the input paths'
3.. what is false path mean in 1"3 and in what scenarios falsepath can come'
0. what does 5ulticycle path mean in 1"3 and in what scenarios multicycle paths
can come'
1. what are source synchronous paths in 1"3'
2. assume you have defined latency specified by user both in 5aster cloc2 and in the
Cenerated cloc2 in 1"3& how the tool will behave any idea'
7f we have defined only 5aster latency and Kenerated clock with latency numbers' and
the clocks are set to propagated mode after clock"tree' then the 9tatic Timing 2nalysis
Tool' will honour the Kenerated clock source and Kenerated clock network latency
numbers only and the master clock source and master clock network latencies are
ignored.
3. 3ssume there is a specific reAuirement to preserve the logic during synthesis& how
will do it.
7f there is a re6uirement that some logic needs to be preserved then we can use a
command called setEdontEtouch or setEdontEdesign -complete module/ and convey the
message to the tool not to optimize or smash the logic.
. We have multiple instances in !"#$!egister "ransfer #anguage%& do you do
anything special during synthesis stage'
;hile writing <T=-<egister Transfer language/'say in verilog or in 10D= language' we
dont write the same module functionality again and again' we use a concept called as
instantiation' where in as per the language' the instanciation of a module will behave like
the parent module in terms of functionality' where during synthesis stage we need the full
code so that the synthesis tool can study the logic ' structure and map it to the library
cells' so we use a command in synthesis ' called as >.?7*.73> which will replace the
instantiations with the real logic' because once we are in a synthesis stages we have to
visualize as real cells and no more modelling 8ust for functionality alone' we need to
visualize in"terms of physical world as well.
(. what do you call an event and when do you call an assertion'
2ssertion based 1erification Tools' checks whether a statement holds a defined property or
not' whereas' Avent based 9imulators' checks whether there is change in any event' say
for every edge of a clock whether there is some activity in a signal or not' in case of an
asynchronous designs' checks whether a signal is enabled or not.
1% ,Bplain about setup time and hold time& what will happen if there is setup time
and hold tine violation& how to overcome this'
9et up time is the amount of time before the clock edge that the input signal needs to be
stable to guarantee it is accepted properly on the clock edge.
0old time is the amount of time after the clock edge that same input signal has to be held
before changing it to make sure it is sensed properly at the clock edge.
;henever there are setup and hold time violations in any flip"flop' it enters a state where
its output is unpredictableB this state is known as metastable state -6uasi stable state/O at
the end of metastable state' the flip"flop settles down to either J1J or JDJ. This whole
process is known as metastability
2% What is s2ew& what are problems associated with it and how to minimi<e it'
7n circuit design' clock skew is a phenomenon in synchronous circuits in which the clock
signal -sent from the clock circuit/ arrives at different components at different times.
This is typically due to two causes. The first is a material flaw' which causes a signal to
travel faster or slower than e$pected. The second is distanceB if the signal has to travel the
entire length of a circuit' it will likely -depending on the circuitJs size/ arrive at different
parts of the circuit at different times. (lock skew can cause harm in two ways. 9uppose
that a logic path travels through combinational logic from a source flip"flop to a
destination flip"flop. 7f the destination flip"flop receives the clock tick later than the
source flip"flop' and if the logic path delay is short enough' then the data signal might
arrive at the destination flip"flop before the clock tick' destroying there the previous data
that should have been clocked through. This is called a hold violation because the
previous data is not held long enough at the destination flip"flop to be properly clocked
through. 7f the destination flip"flop receives the clock tick earlier than the source flip"
flop' then the data signal has that much less time to reach the destination flip"flop before
the ne$t clock tick. 7f it fails to do so' a setup violation occurs' so"called because the new
data was not set up and stable before the ne$t clock tick arrived. 2 hold violation is more
serious than a setup violation because it cannot be fi$ed by increasing the clock period.
(lock skew' if done right' can also benefit a circuit. 7t can be intentionally introduced to
decrease the clock period at which the circuit will operate correctly' and/or to increase the
setup or hold safety margins. The optimal set of clock delays is determined by a linear
program' in which a setup and a hold constraint appears for each logic path. 7n this linear
program' zero clock skew is merely a feasible point.
(lock skew can be minimized by proper routing of clock signal -clock distribution tree/
or putting variable delay buffer so that all clock inputs arrive at the same time
3% What is slac2'
J9lackJ is the amount of time you have that is measured from when an event Jactually
happensJ and when it Jmust happenP.. The term Jactually happensJ can also be taken as
being a predicted time for when the event will Jactually happenJ.
;hen something Jmust happenJ can also be called a JdeadlineJ so another definition of
slack would be the time from when something Jactually happensJ -call this Tact/ until the
deadline -call this Tdead/.
9lack 4 Tdead " Tact.
?egative slack implies that the Jactually happenJ time is later than the JdeadlineJ time...in
other words itJs too late and a timing violation....you have a timing problem that needs
some attention.
% What is glitch' What causes it $eBplain with waveform%' How to overcome it'
The following figure shows a synchronous alternative to the gated clock using a data
path. The flip"flop is clocked at every clock cycle and the data path is controlled by an
enable. ;hen the enable is =ow' the multiple$er feeds the output of the register back on
itself. ;hen the enable is 0igh' new data is fed to the flip"flop and the register changes
its state
(% Civen only two Bor gates one must function as buffer and another as inverter'
Tie one of $or gates input to 1 it will act as inverter.
Tie one of $or gates input to D it will act as buffer.
)% What is difference between latch and flipflop'
The main difference between latch and is that latches are level sensitive while are
edge sensitive. They both re6uire the use of clock signal and are used in se6uential logic.
or a latch' the output tracks the input when the clock signal is high' so as long as the
clock is logic 1' the output can change if the input also changes. on the other hand'
will store the input only when there is a rising/falling edge of the clock.
*% :uild a =1 muB using only 2=1 muB'
/ifference between heap and stac2'
The 9tack is more or less responsible for keeping track of whatJs e$ecuting in our code
-or whatJs been >called>/. The 0eap is more or less responsible for keeping track of our
ob8ects -our data' well... most of it " weJll get to that later./.
Think of the 9tack as a series of bo$es stacked one on top of the ne$t. ;e keep track of
whatJs going on in our application by stacking another bo$ on top every time we call a
method -called a rame/. ;e can only use whatJs in the top bo$ on the stack. ;hen weJre
done with the top bo$ -the method is done e$ecuting/ we throw it away and proceed to
use the stuff in the previous bo$ on the top of the stack. The 0eap is similar e$cept that
its purpose is to hold information -not keep track of e$ecution most of the time/ so
anything in our 0eap can be accessed at any time. ;ith the 0eap' there are no constraints
as to what can be accessed like in the stack. The 0eap is like the heap of clean laundry on
our bed that we have not taken the time to put away yet " we can grab what we need
6uickly. The 9tack is like the stack of shoe bo$es in the closet where we have to take off
the top one to get to the one underneath it.
.% /ifference between mealy and moore state machine'
2/ 5ealy and 5oore models are the basic models of state machines. 2 state machine
which uses only Antry 2ctions' so that its output depends on the state' is called a 5oore
model. 2 state machine which uses only 7nput 2ctions' so that the output depends on the
state and also on inputs' is called a 5ealy model. The models selected will influence a
design but there are no general indications as to which model is better. (hoice of a model
depends on the application' e$ecution means -for instance' hardware systems are usually
best realized as 5oore models/ and personal preferences of a designer or programmer
@/ 5ealy machine has outputs that depend on the state and input -thus' the 95 has the
output written on edges/
5oore machine has outputs that depend on state only -thus' the 95 has the output
written in the state itself.
2dv and Disadv
7n 5ealy as the output variable is a function both input and state' changes of state of the
state variables will be delayed with respect to changes of signal level in the input
variables' there are possibilities of glitches appearing in the output variables. 5oore
overcomes glitches as output dependent on only states and not the input signal level.
2ll of the concepts can be applied to 5oore"model state machines because any 5oore
state machine can be implemented as a 5ealy state machine' although the converse is not
true.
5oore machineB the outputs are properties of states themselves... which means that you
get the output after the machine reaches a particular state' or to get some output your
machine has to be taken to a state which provides you the output.The outputs are held
until you go to some other state 5ealy machineB
5ealy machines give you outputs instantly' that is immediately upon receiving input' but
the output is not held after that clock cycle.
10% /ifference between onehot and binary encoding'
(ommon classifications used to describe the state encoding of an 95 are @inary -or
highly encoded/ and :ne hot.
2 binary"encoded 95 design only re6uires as many flip"flops as are needed to uni6uely
encode the number of states in the state machine. The actual number of flip"flops re6uired
is e6ual to the ceiling of the log"base"2 of the number of states in the 95.
2 onehot 95 design re6uires a flip"flop for each state in the design and only one flip"
flop -the flip"flop representing the current or >hot> state/ is set at a time in a one hot 95
design. or a state machine with L" 1G states' a binary 95 only re6uires + flip"flops
while a onehot 95 re6uires a flip"flop for each state in the design
,K2 vendors fre6uently recommend using a onehot state encoding style because flip"
flops are plentiful in an ,K2 and the combinational logic re6uired to implement a
onehot 95 design is typically smaller than most binary encoding styles. 9ince ,K2
performance is typically related to the combinational logic size of the ,K2 design'
onehot 95s typically run faster than a binary encoded 95 with larger combinational
logic blocks
11% What are different ways to synchroni<e between two cloc2 domains'
;loc2 /omain ;rossing. . .
The following section e$plains clock domain interfacing
:ne of the biggest challenges of system"on"chip -9:(/ designs is that different blocks
operate on independent clocks. 7ntegrating these blocks via the processor bus' memory
ports' peripheral busses' and other interfaces can be troublesome because unpredictable
behavior can result when the asynchronous interfaces are not properly synchronized
2 very common and robust method for synchronizing multiple data signals is a
handshake techni6ue as shown in diagram below This is popular because the handshake
techni6ue can easily manage changes in clock fre6uencies' while minimizing latency at
the crossing. 0owever' handshake logic is significantly more comple$ than standard
synchronization structures.
951-Transmitter/ asserts the re6 -re6uest/ signal' asking the receiver to accept the data
on the data bus. 952-<eceiver/ generally a slow module asserts the ack -acknowledge/
signal' signifying that it has accepted the data.
it has loop holesB when system <eceiver samples the systems Transmitter re6 line and
Transmitter samples system <eceiver ack line' they have done it with respect to their
internal clock' so there will be setup and hold time violation. To avoid this we go for
double or triple stage synchronizers' which increase the 5T@ and thus are immune to
metastability to a good e$tent. The figure below shows how this is done.
12% How to calculate maBimum operating freAuency'
13% How to find out longest path'
3ou can find answer to this in timing.ppt of presentations section on this site
1% /raw the state diagram to output a D1D for one cycle if the seAuence D0110D
shows up $the leading 0s cannot be used in more than one seAuence%'
1(% How to achieve 1+0 degree eBact phase shift'
?ever tell using inverter
a/ dcmPs an inbuilt resource in most of fpga can be configured to get 1ID degree phase
shift.
b/ @ufgds that is differential signaling buffers which are also inbuilt resource of most of
,K2 can be used.
1)% What is significance of ras and cas in 1/!35'
9D<25 receives its address command in two address words.
7t uses a multiple$ scheme to save input pins. The first address word is latched into the
D<25 chip with the row address strobe -<29/.
ollowing the <29 command is the column address strobe -(29/ for latching the second
address word.
9hortly after the <29 and (29 strobes' the stored data is valid for reading.
1*% "ell some of applications of buffer'
a/They are used to introduce small delays
b/They are used to eliminate cross talk caused due to inter electrode capacitance due to
close routing.
c/They are used to support high fanout'egBbufg
1+% 9mplement an 3E/ gate using muB'
This is the basic 6uestion that many interviewers ask. for and gate' give one input as
select line'incase if u r giving b as select line' connect one input to logic JDJ and other
input to a.
1.% What will happen if contents of register are shifter left& right'
7t is well known that in left shift all bits will be shifted left and =9@ will be appended
with D and in right shift all bits will be shifted right and 59@ will be appended with D
this is a straightforward answer
;hat is e$pected is in a left shift value gets 5ultiplied by 2 egBconsider DDDDE111D41+ a
left shift will make it DDD1E11D42I' it the same fashion right shift will Divide the value
by 2.
20%Civen the following -9-6 and rules& how deep does the -9-6 need to be to
prevent underflow or overflow'
<.=A9B
1/ fre6uency-clkE2/ 4 fre6uency-clkE@/ / +
2/ period-enE@/ 4 period-clkE2/ Q 1DD
&/ dutyEcycle-enE@/ 4 2FR
2ssume clkE@ 4 1DD50z -1Dns/
rom -1/' clkE2 4 2F50z -+Dns/
rom -2/' period-enE@/ 4 +Dns Q +DD 4 +DDDns' but we only output for
1DDDns'due to -&/' so &DDDns of the enable we are doing no output work. Therefore' 7:
size 4 &DDDns/+Dns 4 HF entries.
21% /esign a four-input E3E/ gate using only two-input E3E/ gates.
2B@asically' you can tie the inputs of a ?2?D gate together to get an inverter' so...
22%/ifference between 1ynchronous and 3synchronous reset.'
9ynchronous reset logic will synthesize to smaller flip"flops' particularly if the reset is
gated with the logic generating the d"input. @ut in such a case' the combinational logic
gate count grows' so the overall gate count savings may not be that significant.
The clock works as a filter for small reset glitchesO however' if these glitches occur near
the active clock edge' the lip"flop could go metastable. 7n some designs' the reset must
be generated by a set of internal conditions. 2 synchronous reset is recommended for
these types of designs because it will filter the logic e6uation glitches between clock.
Disadvantages of synchronous resetB
,roblem with synchronous resets is that the synthesis tool cannot easily distinguish the
reset signal from any other data signal.
9ynchronous resets may need a pulse stretcher to guarantee a reset pulse width wide
enough to ensure reset is present during an active edge of the clock[ if you have a gated
clock to save power' the clock may be disabled coincident with the assertion of reset.
:nly an asynchronous reset will work in this situation' as the reset might be removed
prior to the resumption of the clock.
Designs that are pushing the limit for data path timing' can not afford to have added gates
and additional net delays in the data path due to logic inserted to handle synchronous
resets.
2synchronous reset B
The biggest problem with asynchronous resets is the reset release' also called reset
removal. .sing an asynchronous reset' the designer is guaranteed not to have the reset
added to the data path. 2nother advantage favoring asynchronous resets is that the circuit
can be reset with or without a clock present.
Disadvantages of asynchronous resetB ensure that the release of the reset can occur within
one clock period. if the release of the reset occurred on or near a clock edge such that the
flip"flops went metastable.
23% Why are most interrupts active low'
This answers why most signals are active low
7f you consider the transistor level of a module' active low means the capacitor in the
output terminal gets charged or discharged based on low to high and high to low
transition respectively. when it goes from high to low it depends on the pull down resistor
that pulls it down and it is relatively easy for the output capacitance to discharge rather
than charging. hence people prefer using active low signals.
2%Cive two ways of converting a two input E3E/ gate to an inverter'
-a/ short the 2 inputs of the nand gate and apply the single input to it.
-b/ (onnect the output to one of the input and the other to the input signal.
2(% What are set up time & hold time constraints' What do they signify' Which one
is critical for estimating maBimum cloc2 freAuency of a circuit'
set up timeB " the amount of time the data should be stable before the application of the
clock signal' where as the hold time is the amount of time the data should be stable after
the application of the clock. 9etup time signifies ma$imum delay constraintsO hold time is
for minimum delay constraints. 9etup time is critical for establishing the ma$imum clock
fre6uency.
2)% /ifferences between /-#atch and / flip-flop'
D"latch is level sensitive where as flip"flop is edge sensitive. lip"flops are made up of
latches.
2*% What is a multipleBer'
7s a combinational circuit that selects binary information from one of many input lines
and directs it to a single output line. -2n 4#n/.
2+%How can you convert an 1! -lip-flop to a FG -lip-flop'
@y giving the feed back we can convert' i.e S*4#9 and *4#<.0ence the 9 and < inputs
will act as T and ) respectively.
2.%How can you convert the FG -lip-flop to a / -lip-flop'
@y connecting the T input to the ) through the inverter.
30%What is !ace-around problem'How can you rectify it'
The clock pulse that remains in the 1 state while both T and ) are e6ual to 1 will cause
the output to complement again and repeat complementing until the pulse goes back to D'
this is called the race around problem.To avoid this undesirable operation' the clock pulse
must have a time duration that is shorter than the propagation delay time of the "' this
is restrictive so the alternative is master"slave or edge"triggered construction.
31%How do you detect if two +-bit signals are same'
!:< each bits of 2 with @ -for e.g. 2[D% $or @[D% / and so on.the o/p of I $or gates are
then given as i/p to an I"i/p nor gate. if o/p is 1 then 24@.
32%* bit ring counterHs initial state is 0100010. 3fter how many cloc2 cycles will it
return to the initial state'
G cycles
33% ;onvert /--- into divide by 2. $not latch% What is the maB cloc2 freAuency the
circuit can handle& given the following information'
TEsetup4 Gn9 TEhold 4 2n9 TEpropagation 4 1Dn9
(ircuitB (onnect *bar to D and apply the clk at clk of D and take the :/, at *. 7t gives
fre6/2. 5a$. re6 of operationB 1/ -propagation delayUsetup time/ 4 1/1Gns 4 G2.F 50z
3%Cuys this is the basic Auestion as2ed most freAuently. /esign all the basic
gates$E6"&3E/&6!&E3E/&E6!&I6!&IE6!% using 2=1 5ultipleBer'
.sing 2B1 5u$' -2 inputs' 1 output and a select line/
-a/ ?:T
Kive the input at the select line and connect 7D to 1 N 71 to D. 9o if 2 is 1' we will get 71
that is D at the :/,.
-b/ 2?D
Kive input 2 at the select line and D to 7D and @ to 71. :/p is 2 N @
-c/ :<
Kive input 2 at the select line and 1 to 71 and @ to 7D. :/p will be 2 V @
-d/ ?2?D
2?D U ?:T implementations together
-e/ ?:<
:< U ?:T implementations together
-f/ !:<
2 at the select line @ at 7D and C@ at 71. C@ can be obtained from -a/ -g/ !?:<
2 at the select line @ at 71 and C@ at 7D
3(%E number of IE6! gates are connected in series such that the E inputs
$30&31&32......% are given in the following way= 30 & 31 to first IE6! gate and 32
& 67J of -irst IE6! to second IE6! gate and so on..... Eth IE6! gates output is
final output. How does this circuit wor2' ,Bplain in detail'
7f ?4:dd' the circuit acts as even parity detector' ie the output will 1 if there are even
number of 1Js in the ? input...This could also be called as odd parity generator since with
this additional 1 as output the total number of 1Js will be :DD.
7f ?4Aven' 8ust the opposite' it will be :dd parity detector or Aven ,arity Kenerator.
3)%3n assembly line has 3 fail safe sensors and one emergency shutdown switch."he
line should 2eep moving unless any of the following conditions arise=
-i/ 7f the emergency switch is pressed
-ii/ 7f the senor1 and sensor2 are activated at the same time.
-iii/ 7f sensor 2 and sensor& are activated at the same time.
-iv/ 7f all the sensors are activated at the same time
9uppose a combinational circuit for above case is to be implemented only with ?2?D
Kates. 0ow many minimum number of 2 input ?2?D gates are re6uiredW
?o of 2"input ?2?D Kates re6uired 4 G 3ou can try the whole implementation.
3*%/esign a circuit that calculates the sAuare of a number' 7t should not use any
multiplier circuits. 7t should use 5ultiple$ers and other logicW
This is interesting....
1X24DU141
2X241U&4+
&X24+UF4L
+X24LUH41G
FX241GUL42F
and so on
9ee a pattern yetWTo get the ne$t s6uare' all you have to do is add the ne$t odd number to
the previous s6uare that you found.9ee how 1'&'F'H and finally L are added.;ouldnJt this
be a possible solution to your 6uestion since it only will use a counter'multiple$er and a
couple of addersW7t seems it would take n clock cycles to calculate s6uare of n.
3+% How will you implement a -ull subtractor from a -ull adder'
all the bits of subtrahend should be connected to the $or gate. :ther input to the $or being
one.The input carry bit to the full adder should be made 1. Then the full adder works like
a full subtractor
3.%3 very good interview Auestion... What is difference between setup and hold
time. "he interviewer was loo2ing for one specific reason & and its really a good
answer too.."he hint is hold time doesnHt depend on cloc2& why is it so...'
9etup violations are related to two edges of clock' i mean you can vary the clock
fre6uency to correct setup violation. @ut for hold time' you are only concerned with one
edge and does not basically depend on clock fre6uency.
0%9n a 3-bit FohnsonHs counter what are the unused states'
2-power n/"2n is the one used to find the unused states in 8ohnson counter.
9o for a &"bit counter it is I"G42..nused states42. the two unused states are D1D and 1D1
1%"he Auestion is to design minimal hardware system& which encrypts +-bit parallel
data. 3 synchroni<ed cloc2 is provided to this system as well. "he output encrypted
data should be at the same rate as the input data but no necessarily with the same
phase.
The encryption system is centered around a memory device that perform a =.T -=ook"
.p Table/ conversion. This memory functionality can be achieved by using a ,<:5'
A,<:5' =290 and etc. The device contains an encryption code' which may be burned
into the device with an e$ternal programmer. 7n encryption operation' the dataEin is an
address pointer into a memory cell and the combinatorial logic generates the control
signals. This creates a read access from the memory. Then the memory device goes to the
appropriate address and outputs the associate data. This data represent the dataEin after
encryption.
1% What is an #-1! .#ist a few of its industry applications.'
=9< is a linear feedback shift register where the input bit is driven by a linear function
of the overall shift register value. coming to industrial applications' as far as 7 know' it is
used for encryption and decryption and in @79T-built"in"self"test/ based applications..
2%what is false path'how it determine in c2t' what the effect of false path in c2t'
@y timing all the paths in the circuit the timing analyzer can determine all the critical
paths in the circuit. 0owever' the circuit may have false paths' which are the paths in the
circuit which are never e$ercised during normal circuit operation for any set of inputs.
2n e$ample of a false path is shown in figure below. The path going from the input 2 of
the first 5.! through the combinational logic out through the @ input of the second
5.9 is a false path. This path can never be activated since if the 2 input of the first
5.! is activated' then 9el line will also select the 2 input of the second 5.!.
9T2 -9tatic Timing 2nalysis/ tools are able to identify simple false pathsO however they
are not able to identify all the false paths and sometimes report false paths as critical
paths. <emoval of false paths makes circuit testable and its timing performance
predictable -sometimes faster/
3%;onsider two similar processors& one with a cloc2 s2ew of 100ps and other with a
cloc2 s2ew of (0ps. Which one is li2ely to have more power' Why'
(lock skew of FDps is more likely to have clock power. This is because it is likely that
low"skew processor has better designed clock tree with more powerful and number of
buffers and overheads to make skew better.
%What are multi-cycle paths'
5ulti"cycle paths are paths between registers that take more than one clock cycle to
become stable.
or e$. 2nalyzing the design shown in fig below shows that the output 97?/(:9 re6uires
+ clock"cycles after the input 2?K=A is latched in. This means that the combinatorial
block -the .nrolled (ordic/ can take up to + clock periods -2F50z/ to propagate its
result. ,lace and <oute tools are capable of fi$ing multi"cycle paths problem.
(%>ou have two counters counting upto 1)& built from negedge /-- & -irst circuit is
synchronous and second is DrippleD $cascading%& Which circuit has a less
propagation delay' Why'
The synchronous counter will have lesser delay as the input to each flop is readily
available before the clock edge. ;hereas the cascade counter will take long time as the
output of one flop is used as clock to the other. 9o the delay will be propagating. or AgB
1G state counter 4 + bit counter 4 + lip flops =et 1Dns be the delay of each flop The
worst case delay of ripple counter 4 1D Q + 4 +Dns The delay of synchronous counter 4
1Dns only.-Delay of 1 flop/
)% what is difference between !35 and -9-6'
7: does not have address lines
<am is used for storage purpose where as fifo is used for synchronization purpose i.e.
when two peripherals are working in different clock domains then we will go for fifo.
*%"he circle can rotate cloc2wise and bac2. Kse minimum hardware to build a
circuit to indicate the direction of rotating.'
2 sensors are re6uired to find out the direction of rotating. They are placed like at the
drawing. :ne of them is connected to the data input of D flip"flop'and a second one " to
the clock input. 7f the circle rotates the way clock sensor sees the light first while D input
-second sensor/ is zero " the output of the flip"flop e6uals zero' and if D input sensor
>fires> first " the output of the flip"flop becomes high.
+% /raw timing diagrams for following circuit.'
.%9mplement the following circuits=
-a/ & input ?2?D gate using min no of 2 input ?2?D Kates
-b/ & input ?:< gate using min no of 2 inpur ?:< Kates
-c/ & input !?:< gate using min no of 2 inpur !?:< Kates
2ssuming & inputs 2'@'(W
& input ?2?DB
(onnect B
a/ 2 and @ to the first ?2?D gate
b/ :utput of first ?and gate is given to the two inputs of the second ?2?D gate -this
basically realizes the inverter functionality/
c/ :utput of second ?2?D gate is given to the input of the third ?2?D gate' whose
other input is (
--2 ?2?D @/ ?2?D -2 ?2?D @// ?2?D ( Thus' can be implemented using J&J 2"
input ?2?D gates. 7 guess this is the minimum number of gates that need to be used.
& input ?:<B
9ame as above 8ust interchange ?2?D with ?:< --2 ?:< @/ ?:< -2 ?:< @// ?:<
(
& input !?:<B
9ame as above e$cept the inputs for the second !?:< gate' :utput of the first !?:<
gate is one of the inputs and connect the second input to ground or logical JDJ
--2 !?:< @/ !?:< D// !?:< (
(0% 9s it possible to reduce cloc2 s2ew to <ero' A$plain your answer W
Aven though there are clock layout strategies -0"tree/ that can in theory reduce clock
skew to zero by having the same path length from each flip"flop from the pll' process
variations in < and ( across the chip will cause clock skew as well as a pure 0"Tree
scheme is not practical -consumes too much area/.
(1%/esign a -15 $-inite 1tate 5achine% to detect a seAuence 10110'
(2%;onvert /--- into divide by 2. $not latch%' ;hat is the ma$ clock fre6uency of the
circuit ' given the following informationW
TEsetup4 Gn9
TEhold 4 2n9
TEpropagation 4 1Dn9
(ircuitB
(onnect *bar to D and apply the clk at clk of D and take the :/, at *. 7t gives fre6/2.
5a$. re6 of operationB
1/ -propagation delayUsetup time/ 4 1/1Gns 4 G2.F 50z
(3%Cive the circuit to eBtend the falling edge of the input by 2 cloc2 pulses'The
waveforms are shown in the following figure.
(% -or the ;ircuit 1hown below& What is the 5aBimum -reAuency of
6peration'2re there any hold time violations for 2W 7f yes' how do you modify the
circuit to avoid themW
The minumum time period 4 &U2U-1U1U1/ 4 Ins 5a$imum re6uency 4 1/In4
12F50z.
2nd there is a hold time violation in the circuit'because of feedback' if you observe'
tc62U2?D gate delay is less than thold2'To avoid this we need to use even number of
inverters-buffers/. 0ere we need to use 2 inverters each with a delay of 1ns. then the hold
time value e$actly meets.
((%/esign a /-latch using $a% using 2=1 5uB $b% from 1-! #atch '
()%How to implement a 5aster 1lave flip flop using a 2 to 1 muB'
(*%how many 2 input BorHs are needed to inplement 1) input parity generator '
7t is always n"1 ;here n is number of inputs.9o 1G input parity generator will re6uire 1F
two input $orJs .
(+%/esign a circuit for finding the .Hs compliment of a :;/ number using -bit
binary adder and some eBternal logic gates'
LJs compliment is nothing but subracting the given no from L.9o using a + bit binary
adder we can 8ust subract the given binary no from 1DD1-i.e. L/.0ere we can use the 2Js
compliment method addition.
(.% what is /ifference between writebac2 and write through cache'
2 caching method in which modifications to data in the cache arenJt copied to the cache
source until absolutely necessary. ;rite"back caching is available on many
microprocessors ' including all 7ntel processors since the ID+IG. ;ith these
microprocessors' data modifications to data stored in the =1 cache arenJt copied to main
memory until absolutely necessary. 7n contrast' a write"through cache performs all write
operations in parallel "" data is written to main memory and the =1 cache simultaneously.
;rite"back caching yields somewhat better performance than write"through caching
because it reduces the number of write operations to main memory. ;ith this
performance improvement comes a slight risk that data may be lost if the system crashes.
2 write"back cache is also called a copy"back cache.
)0%/ifference between 1ynchronous&3synchronous & 9synchronous
communication'
9ending data encoded into your signal re6uires that the sender and receiver are both using
the same enconding/decoding method' and know where to look in the signal to find data.
2synchronous systems do not send separate information to indicate the encoding or
clocking information. The receiver must decide the clocking of the signal on itJs own.
This means that the receiver must decide where to look in the signal stream to find ones
and zeroes' and decide for itself where each individual bit stops and starts. This
information is not in the data in the signal sent from transmitting unit.
9ynchronous systems negotiate the connection at the data"link level before
communication begins. @asic synchronous systems will synchronize two clocks before
transmission' and reset their numeric counters for errors etc. 5ore advanced systems may
negotiate things like error correction and compression.
Time"dependent. it refers to processes where data must be delivered within certain time
constraints. or e$ample' 5ultimedia stream re6uire an isochronous transport mechanism
to ensure that data is delivered as fast as it is displayed and to ensure that the audio is
synchronized with the video.
)1% What are different ways 5ultiply & /ivide'
:inary /ivision by !epeated 1ubtraction
9et 6uotient to zero
<epeat while dividend is greater than or e6ual
to divisor
9ubtract divisor from dividend
2dd 1 to 6uotient
And of repeat block
6uotient is correct' dividend is remainder
9T:,
:inary /ivision by 1hift and 1ubtract
@asically the reverse of the mutliply by shift and add.


1et 6uotient to D
2lign leftmost digits in dividend and divisor
!epeat
9f that portion of the dividend above the
divisor is greater than or e6ual to the divisor
o "hen subtract divisor from that
portion of the dividend and
o (oncatentate 1 to the right hand end
of the 6uotient
o ,lse concatentate D to the right hand
end of the 6uotient
9hift the divisor one place right
Kntil dividend is less than the divisor
6uotient is correct' dividend is remainder
1"6J
:inary 5ultiply - !epeated 1hift
and 3dd
<epeated shift and add " starting with a result of D'
shift the second multiplicand to correspond with
each 1 in the first multiplicand and add to the
result. 9hifting each position left is e6uivalent to
multiplying by 2' 8ust as in decimal representation
a shift left is e6uivalent to multiplying by 1D.
9et result to D
<epeat
9hift 2nd multiplicand left until rightmost
digit is lined up with leftmost 1 in first
multiplicand
2dd 2nd multiplicand in that position to
result
<emove that 1 from 1st multiplicand
.ntil 1st multiplicand is zero
<esult is correct
9T:,
)2%What is a 1o; $1ystem 6n ;hip%& 319;& Lfull custom chipM& and an -JC3'
There are no precise definitions. 0ere is my sense of it all. irst' 1F years ago' people
were unclear on e$actly what 1=97 meant. ;as it FDDDD gatesW 1DDDDD gatesW was is 8ust
anything bigger than =97W 5y professor simply told me thatO 1=97 is a level of
comple$ity and integration in a chip that demands Alectronic Design 2utomation tools in
order to succeed. 7n other words' big enough that manually drawing lots of little blue' red
and green lines is too much for a human to reasonably do. 7 think that' likewise' 9o( is
that level of integration onto a chip that demands more e$pertise beyond traditional skills
of electronics. 7n other words' pulling off a 9o( demands 0ardware' 9oftware' and
9ystems Angineering talent. 9o' trivially' 9o(s aggressively combine 0;/9; on a single
chip. 5aybe more pragmatically' 9o( 8ust means that 297( and 9oftware folks are
learning a little bit more about each otherPs techni6ues and tools than they did before.
Two other interpretations of 9o( are 1/ a chip that integrates various 7, -7ntellectual
,roperty/ blocks on it and is thus highly centered with issues like <euse' and 2/ a chip
integrating multiple classes of electronic circuitry such as Digital (5:9' mi$ed"signal
digital and analog -e.g. sensors' modulators' 2/Ds/' D<25 memory' high voltage power'
etc.
297( stands for Y2pplication 9pecific 7ntegrated (ircuitZ. 2 chip designed for a specific
application. .sually' 7 think people associate 297(s with the 9tandard (ell design
methodology. 9tandard (ell design and the typical Y297( flowZ usually means that
designers are using 0ardware Description =anguages' 9ynthesis and a library of primitive
cells -e.g. libraries containing 2?D' ?2?D' :<' ?:<' ?:T' =7,"=:,' =2T(0'
2DDA<' @.A<' ,2D cells that are wired together -real libraries are not this simple'
but you get the idea../. Design usually is ?:T done at a transistor level. There is a high
reliance on automated tools because the assumption is that the chip is being made for a
9,A(77( 2,,=7(2T7:? where time is of the essence. @ut' the chip is manufactured
from scratch in that no pre"made circuitry is being programmed or reused. 297( designer
may' or may not' even be aware of the locations of various pieces of circuitry on the chip
since the tools do much of the construction' placement and wiring of all the little pieces.
ull (ustom' in contrast to 297( -or 9tandard (ell/' means that every geometric feature
going onto the chip being designed -think of those pretty chip pictures we have all seen/
is controlled' more or less' by the human design. 2utomated tools are certainly used to
wire up different parts of the circuit and maybe even manipulate -repeat' rotate' etc./
sections of the chip. @ut' the human designer is actively engaged with the physical
features of the circuitry. 0igher human crafting and less reliance on standard cells takes
more time and implies higher ?<A costs' but lowers <A costs for standard parts like
memories' processors' uarts' etc.
,K2s' or ield ,rogrammable Kate 2rrays are completely designed chips that designers
load a programming pattern into to achieve a specific digital function. 2 bit pattern
-almost like a software program/ is loaded into the already manufactured device which
essentially interconnects lots of available gates to meet the designers purposes. ,K2s
are sometimes thought of as a Y9ea of KatesZ where the designer specifies how they are
connected. ,K2 designers often use many of the same tools that 297( designers use'
even though the ,K2 is inherently more fle$ible. 2ll these things can be intermi$ed in
hybrid sorts of ways. or e$ample' ,K2s are now available that have microprocessor
embedded within them which were designed in a full custom manner' all of which now
demands Y9o(Z types of 0;/9; integration skills from the designer.
)3%What is D1canD '
9can 7nsertion and 2T,K helps test 297(s -e.g. chips/ during manufacture. 7f you know
what TT2K boundary scan is' then 9can is the same idea e$cept that it is done inside the
chip instead of on the entire board. 9can tests for defects in the chipJs circuitry after it is
manufactured -e.g. 9can does not help you test whether your Design functions as
intended/. 297( designers usually implement the scan themselves and occurs 8ust after
synthesis. 2T,K -2utomated Test ,attern Keneration/ refers to the creation of >Test
1ectors> that the 9can circuitry enables to be introduced into the chip. 0ereJs a brief
summaryB
9can 7nsertion is done by a tool and results in all -or most/ of your
designJs flip"flops to be replaced by special >9can lip"flops>. 9can flops
have additional inputs/outputs that allow them to be configured into a
>chain> -e.g. a big shift register/ when the chip is put into a test mode.
The 9can flip"flops are connected up into a chain -perhaps multiple
chains/
The 2T,K tool' which knows about the scan chain youJve created'
generates a series of test vectors.
The 2T,K test vectors include both >9timulus> and >A$pected> bit
patterns. These bit vectors are shifted into the chip on the scan chains' and
the chips reaction to the stimulus is shifted back out again.
The 2TA -2utomated Test A6uipment/ at the chip factory can put the chip
into the scan test mode' and apply the test vectors. 7f any vectors do not
match' then the chip is defective and it is thrown away.
9can/2T,K tools will strive to ma$imize the >coverage> of the 2T,K
vectors. 7n other words' given some measure of the total number of nodes
in the chip that could be faulty -shorted' grounded' >stuck at 1>' >stuck at
D>/' what percentage of them can be detected with the 2T,K vectorsW 9can
is a good technology and can achive high coverage in the LDR range.
9can testing does not solve all test problems. 9can testing typically does
not test memories -no flip"flopsS/' needs a gate"level netlist to work with'
and can take a long time to run on the 2TA.
,K2 designers may be unfamiliar with scan since ,K2 testing has
already been done by the ,K2 manufacturer. 297( designers do not have
this lu$ury and must handle all the manufacturing test details themselves.
1. what is :ody effect '
The threshold voltage of a 5:9AT is affected by the voltage which is applied to the
back contact. The voltage difference between the source and the bulk' 1@9 changes the
width of the depletion layer and therefore also the voltage across the o$ide due to the
change of the charge in the depletion region. This results in a difference in threshold
voltage which e6uals the difference in charge in the depletion region divided by the o$ide
capacitance' yieldingB.
3.What are stansdard ;ellHs'
7n semiconductor design' standard cell methodology is a method of designing 2pplication
9pecific 7ntegrated (ircuits -297(s/ with mostly digital"logic features. 9tandard cell
methodology is an e$ample of design abstraction' whereby a low"level 1=97"layout is
encapsulated into an abstract logic representation -such as a ?2?D gate/. (ell"based
methodology -the general class that standard"cell belongs to/ makes it possible for one
designer to focus on the high"level -logical function/ aspect of digital"design' while
another designer focused on the implementation -physical/ aspect. 2long with
semiconductor manufacturing advances' standard cell methodology was responsible for
allowing designers to scale 297(s from comparatively simple single"function 7(s -of
several thousand gates/' to comple$ multi"million gate devices -9o(/.
3.What are /esign !ule ;hec2 $/!;% and #ayout Vs 1chematic $#V1% '
Design <ule (heck -D<(/ and =ayout 1s 9chematic -=19/ are verification processes.
<eliable device fabrication at modern deep submicrometre -D.1& [m and below/ re6uires
strict observance of transistor spacing' metal layer thickness' and power density rules.
D<( e$haustively compares the physical netlist against a set of >foundry design rules>
-from the foundry operator/' then flags any observed violations. =19 is a process that
confirms that the layout has the same structure as the associated schematicO this is
typically the final step in the layout process. The =19 tool takes as an input a schematic
diagram and the e$tracted view from a layout. 7t then generates a netlist from each one
and compares them. ?odes' ports' and device sizing are all compared. 7f they are the
same' =19 passes and the designer can continue. ?oteB =19 tends to consider transistor
fingers to be the same as an e$tra"wide transistor. or e$ample' + transistors in parallel
-each 1 um wide/' a +"finger 1 um transistor' and a + um transistor are all seen as the
same by the =19 tool. unctionality of .lib files will be taken from spice models and
added as an attribute to the .lib file.
.What is 3ntenna effect '
The antenna effect' more formally plasma induced gate o$ide damage' is an efffect that
can potentially cause yield and reliability problems during the manufacture of 5:9
integrated circuits[1%[2%[&%[+%[F%. abs normally supply antenna rules' which are rules
that must be obeyed to avoid this problem. 2 violation of such rules is called an antenna
violation. The word antenna is somewhat of a misnomer in this conte$t\the problem is
really the collection of charge' not the normal meaning of antenna' which is a device for
converting electromagnetic fields to/from electrical currents. :ccasionally the phrase
antenna effect is used this conte$t[G% but this is less common since there are many
effects[H% and the phrase does not make clear which is meant.
.What are steps involved in 1emiconductor device fabrication '
This is a list of processing techni6ues that are employed numerous times in a modern
electronic device and do not necessarily imply a specific order.
;afer processing
;et cleans
,hotolithography
7on implantation -in which dopants are embedded in the wafer creating regions of
increased -or decreased/ conductivity/
Dry etching
;et etching
,lasma ashing
Thermal treatments
<apid thermal anneal
urnace anneals
Thermal o$idation
(hemical vapor deposition -(1D/
,hysical vapor deposition -,1D/
5olecular beam epita$y -5@A/
Alectrochemical Deposition -A(D/. 9ee Alectroplating
(hemical"mechanical planarization -(5,/
;afer testing -where the electrical performance is verified/
;afer backgrinding -to reduce the thickness of the wafer so the resulting chip can be put
into a thin device like a smartcard or ,(5(72 card./
Die preparation
;afer mounting
Die cutting
7( packaging
Die attachment
7( @onding
;ire bonding
lip chip
Tab bonding
7( encapsulation
@aking
,lating
=asermarking
Trim and form
7( testing
(.What is ;loc2 distribution networ2 '
7n a synchronous digital system' the clock signal is used to define a time reference for the
movement of data within that system. The clock distribution network distributes the clock
signal-s/ from a common point to all the elements that need it. 9ince this function is vital
to the operation of a synchronous system' much attention has been given to the
characteristics of these clock signals and the electrical networks used in their distribution.
(lock signals are often regarded as simple control signalsO however' these signals have
some very special characteristics and attributes.
(lock signals are typically loaded with the greatest fanout' travel over the greatest
distances' and operate at the highest speeds of any signal' either control or data' within
the entire synchronous system. 9ince the data signals are provided with a temporal
reference by the clock signals' the clock waveforms must be particularly clean and sharp.
urthermore' these clock signals are particularly affected by technology scaling -see
5ooreJs law/' in that long global interconnect lines become significantly more resistive as
line dimensions are decreased. This increased line resistance is one of the primary
reasons for the increasing significance of clock distribution on synchronous performance.
inally' the control of any differences and uncertainty in the arrival times of the clock
signals can severely limit the ma$imum performance of the entire system and create
catastrophic race conditions in which an incorrect data signal may latch within a register.
The clock distribution network often takes a significant fraction of the power consumed
by a chip. urthermore' significant power can be wasted in transitions within blocks' even
when their output is not needed. These observations have lead to a power saving
techni6ue called clock gating' which involves adding logic gates to the clock distribution
tree' so portions of the tree can be turned off when not needed.
(.What is ;loc2 Cating '
(lock gating is one of the power"saving techni6ues used on many synchronous circuits
including the ,entium + processor. To save power' clock gating refers to adding
additional logic to a circuit to prune the clock tree' thus disabling portions of the circuitry
where flip flops do not change state. 2lthough asynchronous circuits by definition do not
have a >clock>' the term >perfect clock gating> is used to illustrate how various clock
gating techni6ues are simply appro$imations of the data"dependent behavior e$hibited by
asynchronous circuitry' and that as the granularity on which you gate the clock of a
synchronous circuit approaches zero' the power consumption of that circuit approaches
that of an asynchronous circuit.
).What is Eetlist '
?etlists are connectivity information and provide nothing more than instances' nets' and
perhaps some attributes. 7f they e$press much more than this' they are usually considered
to be a hardware description language such as 1erilog' 10D=' or any one of several
specific languages designed for input to simulators.
5ost netlists either contain or refer to descriptions of the parts or devices used. Aach time
a part is used in a netlist' this is called an >instance.> Thus' each instance has a >master>'
or >definition>. These definitions will usually list the connections that can be made to that
kind of device' and some basic properties of that device. These connection points are
called >ports> or >pins>' among several other names.
2n >instance> could be anything from a vacuum cleaner' microwave oven' or light bulb'
to a resistor' capacitor' or integrated circuit chip.
7nstances have >ports>. 7n the case of a vacuum cleaner' these ports would be the three
metal prongs in the plug. Aach port has a name' and in continuing the vacuum cleaner
e$ample' they might be >?eutral>' >=ive> and >Kround>. .sually' each instance will have
a uni6ue name' so that if you have two instances of vacuum cleaners' one might be
>vac1> and the other >vac2>. @esides their names' they might otherwise be identical.
?ets are the >wires> that connect things together in the circuit. There may or may not be
any special attributes associated with the nets in a design' depending on the particular
language the netlist is written in' and that languageJs features.
7nstance based netlists usually provide a list of the instances used in a design. 2long with
each instance' either an ordered list of net names are provided' or a list of pairs provided'
of an instance port name' along with the net name to which that port is connected. 7n this
kind of description' the list of nets can be gathered from the connection lists' and there is
no place to associate particular attributes with the nets themselves. 9,7(A is perhaps the
most famous of instance"based netlists.
?et"based netlists usually describe all the instances and their attributes' then describe
each net' and say which port they are connected on each instance. This allows for
attributes to be associated with nets. AD7 is probably the most famous of the net"based
netlists.
).What Jhysical timing closure '
,hysical timing closure is the process by which an ,K2 or a 1=97 design with a
physical representation is modified to meet its timing re6uirements. 5ost of the
modifications are handled by AD2 tools based on directives given by a designer. The
term is also sometimes used as a characteristic' which is ascribed to an AD2 tool' when it
provides most of the features re6uired in this process. ,hysical timing closure became
more important with submicrometre technologies' as more and more steps of the design
flow had to be made timing"aware. ,reviously only logic synthesis had to satisfy timing
re6uirements. ;ith present deep submicrometre technologies it is unthinkable to perform
any of the design steps of placement' clock"tree synthesis and routing without timing
constraints. =ogic synthesis with these technologies is becoming less important. 7t is still
re6uired' as it provides the initial netlist of gates for the placement step' but the timing
re6uirements do not need to be strictly satisfied any more. ;hen a physical
representation of the circuit is available' the modifications re6uired to achieve timing
closure are carried out by using more accurate estimations of the delays.
*.What Jhysical verification '
,hysical verification of the design' involves D<(-Design rule check/' =19-=ayout
versus schematic/ (heck' !:< (hecks' A<( -Alectrical <ule (heck/ and 2ntenna
(hecks.
!:< (heck
This step involves comparing two layout databases/KD9 by !:< operation of the layout
geometries. This check results a database which has all the mismatching geometries in
both the layouts. This check is typically run after a metal spin' where in the re"spin
database/KD9 is compared with the previously taped out database/KD9.
2ntenna (heck
2ntenna checks are used to limit the damage of the thin gate o$ide during the
manufacturing process due to charge accumulation on the interconnect layers -metal'
polysilicon/ during certain fabrication steps like ,lasma etching' which creates highly
ionized matter to etch. The antenna basically is a metal interconnect' i.e.' a conductor like
polysilicon or metal' that is not electrically connected to silicon or grounded' during the
processing steps of the wafer. 7f the connection to silicon does not e$ist' charges may
build up on the interconnect to the point at which rapid discharge does take place and
permanent physical damage results to thin transistor gate o$ide. This rapid and
destructive phenomenon is known as the antenna effect. The 2ntenna ratio is defined as
the ratio between the physical area of the conductors making up the antenna to the total
gate o$ide area to which the antenna is electrically connected.
A<( -Alectrical rule check/
A<( -Alectrical rule check/ involves checking a design for all well and substrate areas for
proper contacts and spacings thereby ensuring correct power and ground connections.
A<( steps can also involve checks for unconnected inputs or shorted outputs.
*.What is 1tuc2-at fault '
2 9tuck"at fault is a particular fault model used by fault simulators and 2utomatic test
pattern generation -2T,K/ tools to mimic a manufacturing defect within an integrated
circuit. 7ndividual signals and pins are assumed to be stuck at =ogical J1J' JDJ and J!J. or
e$ample' an output is tied to a logical 1 state during test generation to assure that a
manufacturing defect with that type of behavior can be found with a specific test pattern.
=ikewise the output could be tied to a logical D to model the behavior of a defective
circuit that cannot switch its output pin.
*.What is /ifferent #ogic family '
=isted here in rough chronological order of introduction along with their usual
abbreviations of =ogic family
Q Diode logic -D=/
Q Direct"coupled transistor logic -D(T=/
Q (omplementary transistor logic -(T=/
Q <esistor"transistor logic -<T=/
Q <esistor"capacitor transistor logic -<(T=/
Q Diode"transistor logic -DT=/
Q Amitter coupled logic -A(=/ also known as (urrent"mode logic -(5=/
Q Transistor"transistor logic -TT=/ and variants
Q ,"type 5etal :$ide 9emiconductor logic -,5:9/
Q ?"type 5etal :$ide 9emiconductor logic -?5:9/
Q (omplementary 5etal":$ide 9emiconductor logic -(5:9/
Q @ipolar (omplementary 5etal":$ide 9emiconductor logic -@i(5:9/
Q 7ntegrated 7n8ection =ogic -72=/
*.What is /ifferent "ypes of 9; pac2aging '
7( are packaged in many types they areB Q @K21
Q @K22
Q @all grid array
Q (,K2
Q (eramic ball grid array
Q (er6uad
Q D7,"I
Q Die attachment
Q Dual lat ?o =ead
Q Dual in"line package
Q lat pack
Q lip chip
Q lip"chip pin grid array
Q 01*?
Q =*,
Q =and grid array
Q =eadless chip carrier
Q =ow insertion force
Q 5icro (@K2
Q 5icro =eadframe ,ackage
Q 5icro=eadrame
Q 5ini"(artridge
Q 5ulti"(hip 5odule
Q :,K2
Q ,*,
Q ,ackage on package
Q ,in grid array
Q ,lastic leaded chip carrier
Q *?
Q *,
Q *uadruple in"line package
Q <:5 cartridge
Q 9hrink 9mall":utline ,ackage
Q 9ingle in"line package
Q 9mall":utline 7ntegrated (ircuit
Q 9taggered ,in Krid 2rray
Q 9urface"mount technology
Q T:22D
Q T:&
Q T:L2
Q T*,
Q T99:,
Q Thin small"outline package
Q Through"hole technology
Q .7((
Q Mig"zag in"line package
+.What is 1ubstrate coupling '
7n an integrated circuit' a signal can couple from one node to another via the substrate.
This phenomenon is referred to as substrate coupling or substrate noise coupling.
The push for reduced cost' more compact circuit boards' and added customer features has
provided incentives for the inclusion of analog functions on primarily digital 5:9
integrated circuits -7(s/ forming mi$ed"signal 7(s. 7n these systems' the speed of digital
circuits is constantly increasing' chips are becoming more densely packed' interconnect
layers are added' and analog resolution is increased. 7n addition' recent increase in
wireless applications and its growing market are introducing a new set of aggressive
design goals for realizing mi$ed"signal systems. 0ere' the designer integrates radio
fre6uency -</ analog and base band digital circuitry on a single chip. The goal is to
make single"chip radio fre6uency integrated circuits -<7(s/ on silicon' where all the
blocks are fabricated on the same chip. :ne of the advantages of this integration is low
power dissipation for portability due to a reduction in the number of package pins and
associated bond wire capacitance. 2nother reason that an integrated solution offers lower
power consumption is that routing high"fre6uency signals off"chip often re6uires a FD:
impedance match' which can result in higher power dissipation. :ther advantages include
improved high"fre6uency performance due to reduced package interconnect parasitics'
higher system reliability' smaller package count' smaller package interconnect parasitics'
and higher integration of < components with 1=97"compatible digital circuits. 7n fact'
the single"chip transceiver is now a reality.
+.What is #atchup '
2 latchup is the inadvertent creation of a low"impedance path between the power supply
rails of an electronic component' triggering a parasitic structure' which then acts as a
short circuit' disrupting proper functioning of the part and possibly even leading to its
destruction due to overcurrent. 2 power cycle is re6uired to correct this situation. The
parasitic structure is usually e6uivalent to a thyristor -or 9(</' a ,?,? structure which
acts as a ,?, and an ?,? transistor stacked ne$t to each other. During a latchup when
one of the transistors is conducting' the other one begins conducting too. They both keep
each other in saturation for as long as the structure is forward"biased and some current
flows through it " which usually means until a power"down. The 9(< parasitic structure
is formed as a part of the totem"pole ,5:9 and ?5:9 transistor pair on the output
drivers of the gates.
1% What is latch up'
=atch"up pertains to a failure mechanism wherein a parasitic thyristor -such as a parasitic
silicon controlled rectifier' or 9(</ is inadvertently created within a circuit' causing a
high amount of current to continuously flow through it once it is accidentally triggered or
turned on. Depending on the circuits involved' the amount of current flow produced by
this mechanism can be large enough to result in permanent destruction of the device due
to electrical overstress -A:9/ .
2%Why is E3E/ gate preferred over E6! gate for fabrication'
?2?D is a better gate for design than ?:< because at the transistor level the mobility of
electrons is normally three times that of holes compared to ?:< and thus the ?2?D is a
faster gate.
2dditionally' the gate"leakage in ?2?D structures is much lower. 7f you consider tEphl
and tEplh delays you will find that it is more symmetric in case of ?2?D - the delay
profile/' but for ?:<' one delay is much higher than the other-obviously tEplh is higher
since the higher resistance p mosJs are in series connection which again increases the
resistance/.
3%What is Eoise 5argin' ,Bplain the procedure to determine Eoise 5argin
The minimum amount of noise that can be allowed on the input stage for which the
output will not be effected.
%,Bplain si<ing of the inverter'
7n order to drive the desired load capacitance we have to increase the size -width/ of the
inverters to get an optimized performance.
(% How do you si<e E561 and J561 transistors to increase the threshold voltage'
)% What is Eoise 5argin' ,Bplain the procedure to determine Eoise 5argin'
The minimum amount of noise that can be allowed on the input stage for which the
output will not be effected.
*% What happens to delay if you increase load capacitance'
delay increases.
+%What happens to delay if we include a resistance at the output of a ;561 circuit'
7ncreases. -<( delay/
.%What are the limitations in increasing the power supply to reduce delay'
The delay can be reduced by increasing the power supply but if we do so the heating
effect comes because of e$cessive power' to compensate this we have to increase the die
size which is not practical.
10%How does !esistance of the metal lines vary with increasing thic2ness and
increasing length'
< 4 - Ql/ / 2.
11%-or ;561 logic& give the various techniAues you 2now to minimi<e power
consumption'
,ower dissipation4(12f 'from this minimize the load capacitance' dc voltage and the
operating fre6uency.
12% What is ;harge 1haring' ,Bplain the ;harge 1haring problem while sampling
data from a :us'
7n the serially connected ?5:9 logic the input capacitance of each gate shares the
charge with the load capacitance by which the logical levels drastically mismatched than
that of the desired once. To eliminate this load capacitance must be very high compared
to the input capacitance of the gates -appro$imately 1D times/.
13%Why do we gradually increase the si<e of inverters in buffer design' Why not
give the output of a circuit to one large inverter'
@ecause it can not drive the output load straight away' so we gradually increase the size
to get an optimized performance.
1%What is #atch Kp' ,Bplain #atch Kp with cross section of a ;561 9nverter.
How do you avoid #atch Kp'
=atch"up is a condition in which the parasitic components give rise to the Astablishment
of low resistance conducting path between 1DD and 199 with Disastrous results.
1(% Cive the eBpression for ;561 switching power dissipation'
(12
1)% What is :ody ,ffect'
7n general multiple 5:9 devices are made on a common substrate. 2s a result' the
substrate voltage of all devices is normally e6ual. 0owever while connecting the devices
serially this may result in an increase in source"to"substrate voltage as we proceed
vertically along the series chain -1sb14D' 1sb2 D/.;hich results 1th2#1th1.
1*% Why is the substrate in E561 connected to Cround and in J561 to V//'
we try to reverse bias not the channel and the substrate but we try to maintain the
drain'source 8unctions reverse biased with respect to the substrate so that we dont loose
our current into the substrate.
1+% What is the fundamental difference between a 561-," and :F" '
7n 5:9AT' current flow is either due to electrons-n"channel 5:9/ or due to holes-p"
channel 5:9/ " 7n @TT' we see current due to both the carriers.. electrons and holes. @TT
is a current controlled device and 5:9AT is a voltage controlled device.
1.%Which transistor has higher gain. :F" or 561 and why'
@TT has higher gain because it has higher transconductance.This is because the current in
@TT is e$ponentially dependent on input where as in 5:9AT it is s6uare law.
20%Why do we gradually increase the si<e of inverters in buffer design when trying
to drive a high capacitive load' ;hy not give the output of a circuit to one large
inverterW
;e cannot use a big inverter to drive a large output capacitance because' who will drive
the big inverterW The signal that has to drive the output cap will now see a larger gate
capacitance of the @7K inverter.9o this results in slow raise or fall times .2 unit inverter
can drive appro$imately an inverter thats + times bigger in size. 9o say we need to drive a
cap of G+ unit inverter then we try to keep the sizing like say 1'+'1G'G+ so that each
inverter sees a same ratio of output to input cap. This is the prime reason behind going for
progressive sizing.
21%9n ;561 technology& in digital design& why do we design the si<e of pmos to be
higher than the nmos.What determines the si<e of pmos wrt nmos. "hough this is a
simple Auestion try to list all the reasons possible'
7n ,5:9 the carriers are holes whose mobility is less[ aprro$ half % than the electrons'
the carriers in ?5:9. That means ,5:9 is slower than an ?5:9. 7n (5:9
technology' nmos helps in pulling down the output to ground ann ,5:9 helps in pulling
up the output to 1dd. 7f the sizes of ,5:9 and ?5:9 are the same' then ,5:9 takes
long time to charge up the output node. 7f we have a larger ,5:9 than there will be more
carriers to charge the node 6uickly and overcome the slow nature of ,5:9 . @asically
we do all this to get e6ual rise and fall times for the output node.
22%Why J561 and E561 are si<ed eAually in a "ransmission Cates'
7n Transmission Kate' ,5:9 and ?5:9 aid each other rather competing with each
other. ThatJs the reason why we need not size them like in (5:9. 7n (5:9 design we
have ?5:9 and ,5:9 competing which is the reason we try to size them proportional
to their mobility.
23%3ll of us 2now how an inverter wor2s. What happens when the J561 and
E561 are interchanged with one another in an inverter'
7 have seen similar *s in some of the discussions. 7f the source N drain also connected
properly...it acts as a buffer. @ut suppose input is logic 1 :/, will be degraded 1 9imilarly
degraded DO
2%3 good Auestion on #ayouts. Cive ( important /esign techniAues you would
follow when doing a #ayout for /igital ;ircuits'
a/7n digital design' decide the height of standard cells you want to layout.7t depends upon
how big your transistors will be.0ave reasonable width for 1DD and K?D metal
paths.5aintaining uniform 0eight for all the cell is very important since this will help
you use place route tool easily and also incase you want to do manual connection of all
the blocks it saves on lot of area.
b/.se one metal in one direction only' This does not apply for metal 1. 9ay you are using
metal 2 to do horizontal connections' then use metal & for vertical connections' metal+ for
horizontal' metal F vertical etc...
c/,lace as many substrate contact as possible in the empty spaces of the layout.
d/Do not use poly over long distances as it has huge resistances unless you have no other
choice.
e/.se fingered transistors as and when you feel necessary.
f/Try maintaining symmetry in your design. Try to get the design in @7T 9liced manner.
2(%What is metastability' When7why it will occur'/ifferent ways to avoid this'
5etastable stateB 2 un"known state in between the two logical known states.This will
happen if the :/, cap is not allowed to charge/discharge fully to the re6uired logical
levels.
:ne of the cases isB 7f there is a setup time violation' metastability will occur'To avoid
this' a series of s is used -normally 2 or &/ which will remove the intermediate states.
2)%#et 3 and : be two inputs of the E3E/ gate. 1ay signal 3 arrives at the E3E/
gate later than signal :. "o optimi<e delay of the two series E561 inputs 3 and :
which one would you place near to the output'
The late coming signals are to be placed closer to the output node ie 2 should go to the
nmos that is closer to the output.
1%,Bplain <ener brea2down and avalanche brea2down'
2 thermally generated carrier -part of reverse saturation current/ falls down the 8unction
barrier and ac6uires energy from the applied potential. This carriers collides with a
crystal ion and imparts sufficient energy to disrupt a covalent bond.7n addition to the
original carrier' a new electron"hole pair has been generated. These carriers may also pick
up sufficient energy and creates still another electron"hole pair. This cumulative process
is called the 2valanche breakdown.
2 reverse electric field at the 8unction causes a strong force to be applied on a bounded
electron by the field to tear it out of its covalent bond. The new hole"electron pair which
is created increases the reverse current' called zener breakdown.
2%What is 9nstrumentation 3mplifier$93% and what are all the advantages'
2n instrumentation amplifier is a differential op"amp circuit providing high input
impedances with ease of gain ad8ustment by varying a single resistor
3% What is the fundamental difference between a 561-," and :F" '
7n 5:9AT'current flow is either due to electrons-n"channel 5:9/ or due to holes-p"
channel 5:9/
" 7n @TT' we see current due to both the carriers.. electrons and holes. @TT is a current
controlled device and 5:9AT is a voltage controlled device.
% What is the basic difference between 3nalog and /igital /esign'
Digital design is distinct from analog design. 7n analog circuits we deal with physical
signals which are continuous in amplitude and time. A$B biological data' sesimic signals'
sensor output' audio' video etc.
2nalog design is 6uite challenging than digital design as analog circuits are sensitive to
noise' operating voltages' loading conditions and other conditions which has severe
effects on performance. Aven process technology poses certain topological limitations on
the circuit. 2nalog designer has to deal with real time continuous signals and even
manipulate them effectively even in harsh environment and in brutal operating
conditions.
Digital design on the other hand is easier to process and has great immunity to noise. ?o
room for automation in analog design as every application re6uires a different design.
;here as digital design can be automated. 2nalog circuits generally deal with
instantaneous value of voltage and current-real time/. (an take any value within the
domain of specifications for the device.consists of passive elements which contribute to
the noise- thermal/ of the circuit . They are usually more sensitive to e$ternal noise more
so because for a particular function a analog design
uses lot less transistors providing design challenges over process corners and temperature
ranges. deals with a lot of device level physics and the state of the transistor plays a very
important role Digital (ircuits on the other hand deal with only two logic levels D and
1-7s it true that according to 6uantum mechanics there is a third logic levelW/ deal with lot
more transistors for a particular logic' easier to design comple$ designs' fle$ible logic
synthesis and greater speed although at the cost of greater power. =ess sensitive to noise.
design and analysis of such circuits is dependant on the clock. challenge lies in negating
the timing and load delays and ensuring there is no set up or hold violation.
(%What is ring oscillator' 3nd derive the freA of operation'
<ing oscillator circuit is a coupled inverter chain with the output being connected to the
input as feedback. The number of stages-inverters/ is always odd to ensure that there is
no single stable state-output value/. sometimes one of the stages consists of a logic gate
which is used to initialise and control the circuit. The total time period of operation is the
product of 2Qnumber of gates and gate-inverter/ delay. 2nd fre6uency of operation will
be inverse of time period.
2pplicationB used as prototype circuits for modeling and designing new semiconductor
processes due to simplicity in design and ease of use. 2lso forms a part of clock recovery
circuit.
)%What are !"#& Cate& 5etal and -9: fiBes' What is a Dsewing 2itsD'
There are several ways to fi$ an 297("based design. #rom easiest to most e$tremeB
<T= i$ "# Kate i$ "# 5etal i$ "# 7@ i$
irst' letJs review fundementals. 2 standard"cell 297( consists of at least 2 dozen
manufactured layers/masks. =ower layers conists of materialsmaking up the actual
(5:9 transistors and gates of the design. The upper &"G layers are metal layers used ti
connect everything together. 297(s' of course' are not intended to be fle$ible like an
,K2' however' important >fi$es> can be made during the manufacturing process. The
progression of possible fi$es in the manufacturing life cycle is as listed above.
2n <T= fi$ means you change the 1erilog/10D= code and you resynthesize. This
usually implies a new ,lanceN<oute. <T= fi$es would also imply new masks' etc. etc. 7n
other words " start from scratch.
2 Kate i$ means that a select number of gates and their interconections may be added or
subtracted from the design -e.g. the netlist/. This avoids resynthesis. Kate fi$es preserve
the previous synthesis effort and involve manually editing a gate"level netlist " adding
gates' removing gates' etc. Kate level fi$es affect 2== layers of the chip and all masks.
2 5etal i$ means that only the upper metal interconnect layers are affected.
(onnections may be broken or made' but new cells may not be added. 2 9ewing )it is a
means of adding a new gate into the design while only affecting the metal layers. 9ewing
)its are typically added into the initial design either at the <T= level or during synthesis
by the customer and are part of the netlist. 2 5etal i$ affects only the top layers of the
wafers and does not affect the >base> layers.
9ewing )its are modules that contain an unused mi$ of gates' flip"flops or any other cells
considered potentially useful for an unforseen metal fi$. 2 9ewing )it may be specified
in <T= by instantiating the literal cells from the vendor library. The cells in the kit are
usually connected such that each cellJs output is unconnected and the inputs are tied to
ground. (locks and resets may be wired into the larger designJs signals' or not.
2 7@ i$ -ocussed 7on @eam/ i$ is only performed on a completed chip. 7@ is a
somewhat e$otic technology where a particle beam is able to make and break connections
on a completed die. 7@ fi$es are done on individual chips and would only be done as a
last resort to repair an otherwise defective prototype chip. 5asks are not affected since it
is the final chip that is intrusively repaired.
(learly' these sorts of fi$es are tricky and risky. They are available to the 297(
developer' but must be negotiated and coordinated with the foundry. 297( designers who
have been through enough of these fi$es appreciate the value of adding test and fault"
tolerant design features into the <T= code so that 9oftware i$es can correct mior silicon
problemsS