Beruflich Dokumente
Kultur Dokumente
7, JULY 2003
1261
Brief Papers_______________________________________________________________________________
A 0.5-V 1-W Successive Approximation ADC
Jens Sauerbrey, Doris Schmitt-Landsiedel, Member, IEEE, and Roland Thewes, Member, IEEE
AbstractA successive approximation analog-to-digital converter (ADC) is presented operating at ultralow supply voltages.
The circuit is realized in a 0.18- m standard CMOS technology.
Neither lowdevices nor voltage boosting techniques are used.
and ground
All voltage levels are between supply voltage
. A passive sample-and-hold stage and a capacitor-based
digital-to-analog converter are used to avoid application of
operational amplifiers, since opamp operation requires higher
values for the lowest possible supply voltage. The ADC has
signal-to-noise-and-distortion ratios of 51.2 and 43.3 dB for supply
voltages of 1 and 0.5 V, at sampling rates of 150 and 4.1 kS/s and
power consumptions of 30 and 0.85 W, respectively. Proper
operation is achieved down to a supply voltage of 0.4 V.
Index TermsAnalog-to-digital converters (ADCs), CMOS
analog integrated circuits, low power, low supply voltage, successive approximation, switched-capacitor circuits.
I. INTRODUCTION
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TABLE I
CAPACITOR VALUES
A. Capacitor Array
in Fig. 3 are realized as multiples of
The capacitors
a unit capacitor of 20 fF. The chosen values result from the
fact that approximately 10 pF are needed to guarantee the 9-bit
linearity requirement, further, 10 pF are required to realize the
. Since small differences of the value of
shunt capacitor
referred to the value of capacitances provided by the capacitor
array only result in a small gain error but do not affect the linis realized as a nonsubdivided large-area device for
earity,
9-bit mode operation. In the 8-bit case, the shunt capacitor is
and
from the 9-bit version in
obtained by connecting
parallel (Table I).
The 9-bit mode is used when the supply voltage is large
enough for proper S&H and comparator function for a max. For smaller values of
, the
imum input voltage of
8-bit mode is used.
B. Comparator
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Fig. 6.
= 1 V.
Chip photograph.
and the S&H circuit. All clock signals are derived from an externally provided master clock.
D. S&H Circuit
The S&H circuit block diagram is given in Fig. 5. The samprovided by the SAR is divided by two and a
pling clock
nonoverlapping two-phase clock is generated. Both signals are
provided in complementary form to control the nMOS switches
and the related nMOS dummy switch devices. The sampling caand
are alternately operated in sample and in
pacitors
hold operation.
The operating point of the switch transistors determines the
minimum settling time. At low supply voltage these transistors
are no longer operated in strong inversion when switched ON.
However, a relaxation of the impact of this operating condition
is obtained due to the fact that the sampling frequency is an order
of magnitude lower than the operating frequency of the comparator. Moreover, the switching frequency is two times lower
compared to the sampling frequency since two time-interleaved
sampling paths are used.
The sampling capacitors are not integrated on-chip here since
the main goal of this work was to investigate the DAC core
behavior. We use relatively large values of 47 pF in our case
in order to suppress packaging- and bondwire-related artifacts
(i.e., crosstalk between the sampling paths which is caused by
the discrete assembly of the sampling capacitors, and the related
capacitive coupling between bondwires and between package
pins). Integration of these capacitors on-chip allows to significantly decrease their value, as will be discussed in more detail
in Section IV-C.
IV. EXPERIMENTAL RESULTS
The ADC is fabricated in a standard 0.18- m n-well CMOS
process with a single poly layer, four metal layers, and a
metalinsulatormetal capacitor (MIMCAP) option. The
threshold voltages are 0.43 V for the nMOS and 0.38 V for
the pMOS device. A chip photograph is shown in Fig. 6. Chip
area is 0.11 mm .
A. Static Measurements
Fig. 7 shows measured data of the integral nonlinearity (INL)
and the differential nonlinearity (DNL) in the 9-bit mode at
V. To evaluate these parameters in the 8-bit mode,
it is sufficient to consider only the codes from 1 to 256 in these
diagrams.
B. Dynamic Measurements
Fig. 8 shows a full-scale 200-Hz sine-wave spectrum meaV at a sampling rate of 4.1 kS/s in the
sured at
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Fig. 12.
Fig. 13.
= 47 pF).
= 1 V, sampling rate =
TABLE II
MEASURED ADC PERFORMANCE
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=0
=5
41
Fig. 16.
= 47 pF).
[10][12]. As a consequence of the converter principle, the resolution of all converters is of similar range. Concerning the minimum supply voltage however, in this work the lowest value by
far is achieved.
V. CONCLUSION
Fig. 15.
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D. Figure of Merit
As a commonly used figure of merit (FOM) for ADCs considering resolution, bandwidth, and power, we use
Sampling rate
FOM
REFERENCES
Power dissipation
(1)
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