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ADC succesive aproximation

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You are on page 1of 5

7, JULY 2003

1261

Brief Papers_______________________________________________________________________________

A 0.5-V 1-W Successive Approximation ADC

Jens Sauerbrey, Doris Schmitt-Landsiedel, Member, IEEE, and Roland Thewes, Member, IEEE

AbstractA successive approximation analog-to-digital converter (ADC) is presented operating at ultralow supply voltages.

The circuit is realized in a 0.18- m standard CMOS technology.

Neither lowdevices nor voltage boosting techniques are used.

and ground

All voltage levels are between supply voltage

. A passive sample-and-hold stage and a capacitor-based

digital-to-analog converter are used to avoid application of

operational amplifiers, since opamp operation requires higher

values for the lowest possible supply voltage. The ADC has

signal-to-noise-and-distortion ratios of 51.2 and 43.3 dB for supply

voltages of 1 and 0.5 V, at sampling rates of 150 and 4.1 kS/s and

power consumptions of 30 and 0.85 W, respectively. Proper

operation is achieved down to a supply voltage of 0.4 V.

Index TermsAnalog-to-digital converters (ADCs), CMOS

analog integrated circuits, low power, low supply voltage, successive approximation, switched-capacitor circuits.

I. INTRODUCTION

is continuously decreasing, but the

supply voltage

of the devices is not scaled in proportion

threshold voltage

due to off-state currents and the related static power

to

consumption in logic circuits [1]. In the digital world, the

is usually acceptable, however,

increasing ratio of

for analog circuits, decreased signal swings and crucial design

values

restrictions result from that trend. In particular for

below the sum of the threshold voltages of n- and pMOSFETs

), only a very limited number of circuit topologies

(

is still usable.

Specific process options as provision of low- devices help

the analog circuit designer to overcome these constraints, but

lead to increased process complexity and to increased costs.

Adapted analog design approaches which avoid such options

but provide the same performance thus represent an attractive

alternative.

Switched opamp circuits [2][5], reset-opamp circuits [6],

and circuits using bootstrapping techniques [7], [8] have been

conditions

shown to be particularly suited under low

without specific process options. In the case of the latter design

technique, however, gate voltages are applied to part of the

so that enhanced device stress

devices which exceed

occurs.

Manuscript received November 25, 2002; revised February 21, 2003.

J. Sauerbrey and R. Thewes are with Infineon Technologies AG, Corporate

Research, D-81730 Munich, Germany (e-mail: jens.sauerbrey@infineon.com).

D. Schmitt-Landsiedel is with the Institute of Technical Electronics, Technical University of Munich, D-80333 Munich, Germany.

Digital Object Identifier 10.1109/JSSC.2003.813217

converter (ADC) technique based on another approach is presented which is suitable for medium-speed/medium-resolution

converters. Similar to switched-opamp or reset-opamp circuits,

this ADC is designed in a way that only reference voltages are

switched. Contrary to switched-opamp or reset-opamp circuits,

ratio of about

which work well down to a minimum

1.5, the proposed circuit is able to be operated even at much

ratios. This is achieved using an opamp-free arlower

chitecture, a capacitor-based digital-to-analog converter (DAC),

and a passive sample-and-hold (S&H) stage.

The test circuit is realized to investigate the minimum supply

voltage for ADCs using standard digital transistors. All voltage

levels are inside the supply voltage range, and bootstrapping

techniques are avoided. The circuit is based on existing lowvoltage components from other work [5], [9]. The maximum

clock frequency at a given supply voltage is determined by design requirements of these components for their original purpose. Bandwidth optimization has not been performed in this

work, i.e., the reported data do not necessarily represent the

maximally achievable sampling rates.

II. CONVERTER PRINCIPLE

A. Basic Principle of Successive Approximation Converters

In Fig. 1, the basic architecture of a successive approximation ADC is shown. The converter consists of a S&H stage, a

comparator, a successive approximation register (SAR), and a

DAC. Using a binary search algorithm, the DAC output voltage

successively approximates the sampled input voltage

.

In each clock cycle, one bit of the digital output signal is obtained.

B. Successive Approximation Converter Based on a Charge

Redistribution Principle

In Fig. 2, a converter based on a charge redistribution principle is depicted. Binary weighted capacitors are used for the

DAC. The S&H function is realized by the DAC itself. The

switching point of the comparator is independent of the value of

1262

TABLE I

CAPACITOR VALUES

principle.

Fig. 3. Modified architecture.

the input signal. During conversion, at the comparator input posreferred to analog ground occur,

itive and negative voltages

whose magnitude is continuously decreasing with the number of

conversion steps performed within a complete conversion cycle.

Consequently, at the end of the conversion cycle, i.e., when

highest precision is demanded, both comparator inputs are operated near analog ground.

To avoid leakage currents at switch , analog ground should

and

. On the other

be adjusted in the middle between

hand, switch operation at ultralow supply voltages (e.g., under

conditions) is only possible if the

or

.

dc level of the signal to be switched is close to

Since theses requirements cannot be fulfilled simultaneously,

the approach shown in Fig. 2 is not suitable for ultralow voltage

applications.

A. Capacitor Array

in Fig. 3 are realized as multiples of

The capacitors

a unit capacitor of 20 fF. The chosen values result from the

fact that approximately 10 pF are needed to guarantee the 9-bit

linearity requirement, further, 10 pF are required to realize the

. Since small differences of the value of

shunt capacitor

referred to the value of capacitances provided by the capacitor

array only result in a small gain error but do not affect the linis realized as a nonsubdivided large-area device for

earity,

9-bit mode operation. In the 8-bit case, the shunt capacitor is

and

from the 9-bit version in

obtained by connecting

parallel (Table I).

The 9-bit mode is used when the supply voltage is large

enough for proper S&H and comparator function for a max. For smaller values of

, the

imum input voltage of

8-bit mode is used.

B. Comparator

shown in Fig. 3. The DAC simply tracks the sampled ADC

.

and

are used as reference levels.

input signal

is operated as a capacitive divider to

A shunt capacitor

adjust the signals according to the low supply voltage operating conditions of the circuit. Corresponding to 9- or 8-bit

or

is chosen as input voltage range

operation,

in all cases. This

here. Minimum input voltage equals

adjustment guarantees proper comparator operation as well as

proper S&H operation within the whole input voltage range.

In this architecture, the S&H function is no longer realized

by the capacitor array itself as in Fig. 2. A passive S&H stage is

used here. This is sufficient as the load of the S&H stage only

consists of the MOSFET gate capacitance of the input transistor

of the comparator. An advantage of this approach is that the

input capacitance of the whole converter is not determined by

the DAC capacitor array.

circuit (Fig. 4) [3] followed by inverters for signal level recovery. The input common-mode voltage range is between 0 V

or between 0 V and

, respectively (cf. Secand

tion II-C). The bias current is provided by an external resistor.

V, a current of approximately 0.3 A results

At

in the comparator input stage. Depending on the comparator

input signal, under this condition the pMOS input transistors

values between 46 and 113 mV.

are operated at

Although these transistors are not operated in strong inversion

conditions, reasonable sampling rates are

under ultralow

obtained (cf. Fig. 12) since only small capacitive loads have to

be driven by this subcircuit.

C. Successive Approximation Register

The SAR is realized in static CMOS logic. The related logic

circuit block also generates the clock signals for the comparator

1263

Fig. 6.

= 1 V.

Chip photograph.

and the S&H circuit. All clock signals are derived from an externally provided master clock.

D. S&H Circuit

The S&H circuit block diagram is given in Fig. 5. The samprovided by the SAR is divided by two and a

pling clock

nonoverlapping two-phase clock is generated. Both signals are

provided in complementary form to control the nMOS switches

and the related nMOS dummy switch devices. The sampling caand

are alternately operated in sample and in

pacitors

hold operation.

The operating point of the switch transistors determines the

minimum settling time. At low supply voltage these transistors

are no longer operated in strong inversion when switched ON.

However, a relaxation of the impact of this operating condition

is obtained due to the fact that the sampling frequency is an order

of magnitude lower than the operating frequency of the comparator. Moreover, the switching frequency is two times lower

compared to the sampling frequency since two time-interleaved

sampling paths are used.

The sampling capacitors are not integrated on-chip here since

the main goal of this work was to investigate the DAC core

behavior. We use relatively large values of 47 pF in our case

in order to suppress packaging- and bondwire-related artifacts

(i.e., crosstalk between the sampling paths which is caused by

the discrete assembly of the sampling capacitors, and the related

capacitive coupling between bondwires and between package

pins). Integration of these capacitors on-chip allows to significantly decrease their value, as will be discussed in more detail

in Section IV-C.

IV. EXPERIMENTAL RESULTS

The ADC is fabricated in a standard 0.18- m n-well CMOS

process with a single poly layer, four metal layers, and a

metalinsulatormetal capacitor (MIMCAP) option. The

threshold voltages are 0.43 V for the nMOS and 0.38 V for

the pMOS device. A chip photograph is shown in Fig. 6. Chip

area is 0.11 mm .

= 0:5 V, 200 Hz input signal

frequency, 0.125 V input signal swing, and 4.1 kS/s sampling rate (8-bit mode,

C

= 47 pF).

= 1 V, 6.4 kHz input signal

frequency, 0.5 V input signal swing, and 150 kS/s sampling rate (9-bit mode,

C

= 47 pF).

A. Static Measurements

Fig. 7 shows measured data of the integral nonlinearity (INL)

and the differential nonlinearity (DNL) in the 9-bit mode at

V. To evaluate these parameters in the 8-bit mode,

it is sufficient to consider only the codes from 1 to 256 in these

diagrams.

B. Dynamic Measurements

Fig. 8 shows a full-scale 200-Hz sine-wave spectrum meaV at a sampling rate of 4.1 kS/s in the

sured at

1264

4:1 kS=s, V = 0 dB (0.125 V), 3, 6, 10,

mode, C = 47 pF).

150 kS=s, V = 0 dB (0.5 V), 3, 6, 10,

mode, C = 47 pF).

Fig. 12.

Fig. 13.

= 47 pF).

= 1 V, sampling rate =

V at a sampling rate of 150 kS/s in 9-bit mode is

at

depicted.

Signal-to-noise-plus-distortion ratio (SNDR) versus sinusoidal input frequency at input levels between 0 and 40 dB

is shown in Figs. 10 and 11 at supply voltages of 0.5 and 1 V,

respectively.

Fig. 12 shows the maximum sampling rate and the related

power dissipation as a function of supply voltage. The sampling

rate decreases with a moderate slope from 150 to 34 kS/s for

supply voltages from 1 to 0.6 V. For smaller supply voltages, the

drop of the sampling rate is more pronounced. The maximum

clock frequency is determined by malfunction of the digital circuitry, proven by incorrect codes at higher clock rates.

is shown in Fig. 13. A

Measured SNDR as a function of

reasonable SNDR value under 9-bit mode operation is obtained

down to a supply voltage of approximately 0.6 V. In 8-bit mode,

the circuit shows proper operation down to a supply voltage of

0.4 V. There, an SNDR of 38.9 dB at a sampling rate of 0.6 kS/s

is achieved.

Characterization is performed at room temperature using

eight bonded samples from one wafer with typical process

parameters. Measured results of all chips are very similar;

differences in linearity are smaller than 0.2 LSB and deviations

of the maximum clock frequency are less than 2%. Measured

data are summarized in Table II.

TABLE II

MEASURED ADC PERFORMANCE

In this section, we estimate the impact of the value of the

when realized on-chip. The parasitic

sampling capacitors

packaging- and bondwire-related artifacts briefly discussed in

Section III-D are most prominent at high frequencies within the

specified bandwidth, so that, in general, ADC characterization is

performed using large values of the externally realized sampling

pF) to suppress these effects.

capacitors (

These parasitic effects do not show under operation with lowfrequency input signals. Fig. 14 shows SNDR versus sinusoidal

input frequency at input levels between 0 and 40 dB at

V using a sampling capacitor of 5 pF. The degradation of

the SNDR at high frequencies is obvious. At low frequencies,

however, only minor deviations compared to the data obtained

pF (Fig. 10) are obtained.

with

Fig. 15 shows the low-frequency SNDR as a function of the

used sampling capacitor value for supply voltages of 1 and 0.5 V,

1265

0 0 0 020, 030, and 040 dB (8-bit

dB (0.125 V), 3, 6, 10,

: kS=s, V

mode, C

pF).

=0

=5

41

Fig. 16.

= 47 pF).

[10][12]. As a consequence of the converter principle, the resolution of all converters is of similar range. Concerning the minimum supply voltage however, in this work the lowest value by

far is achieved.

V. CONCLUSION

Fig. 15.

at ultralow supply voltage is realized in a standard 0.18- m

CMOS technology using transistors with threshold voltages of

approximately 400 mV and avoiding bootstrapping techniques.

Test results indicate that the circuit is well suited for operation far below 1 V. Proper operation is shown down to a supply

voltage of 0.4 V, which is approximately equal to the threshold

voltages of the devices used.

pling capacitor of 5 pF independent of the

This capacitance value corresponds well with simulated results. There, a decrease of 3 dB in resolution is predicted for

a sampling capacitor of 3.6 pF. Moreover, simulation reveals

that this loss in resolution is mainly determined by comparator

kickback noise. Note that distortion due to mismatch of the two

sampling capacitors is irrelevant here, as the comparator input

.

capacitance is much smaller compared to

On the basis of these measurements and simulations, we identify a reasonable value for on-chip sampling capacitors to be of

order 310 pF.

[2] A. Baschirotto and R. Castello, A 1-V 1.8-MHz CMOS

switched-opamp SC filter with rail-to-rail output swing, IEEE J.

Solid-State Circuits, vol. 32, pp. 19791986, Dec. 1997.

[3] V. Peluso, P. Vancorenland, A. Marques, M. Steyaert, and W. Sansen, A

900-mV 40-W switched opamp

modulator with 77-dB dynamic

range, in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 1998,

pp. 6869.

[4] M. Waltari and K. Halonen, 1-V 9-bit pipelined switched-opamp

ADC, IEEE J. Solid-State Circuits, vol. 36, pp. 129134, Jan. 2001.

[5] J. Sauerbrey, T. Tille, D. Schmitt-Landsiedel, and R. Thewes, A 0.7-V

MOSFET-only switched-opamp

modulator, in IEEE Int. SolidState Circuits Conf. Dig. Tech. Papers, 2002, pp. 310311.

[6] M. Keskin, U. Moon, and G. Temes, A 1-V, 10-MHz clock-rate, 13-bit

CMOS

modulator using unity-gain-reset opamps, in Proc. Eur.

Solid State Circuits Conf. (ESSCIRC), 2001, pp. 532535.

[7] A. Abo and P. Gray, A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline

analog-to-digital converter, IEEE J. Solid-State Circuits, vol. 34, pp.

599606, May 1999.

[8] M. Dessouky and A. Kaiser, A 1-V 1-mW digital-audio

modulator

with 88-dB dynamic range using local switch bootstrapping, in Proc.

IEEE Custom Integrated Circuits Conf., 2000, pp. 1316.

[9] J. Sauerbrey and R. Thewes, Ultra low voltage switched-opamp

modulator for portable applications, in Proc. IEEE Custom Integrated

Circuits Conf., 2001, pp. 3538.

[10] S. Mortezapour and E. Lee, A 1-V 8-bit succesive approximation ADC

in standard CMOS process, IEEE J. Solid-State Circuits, vol. 35, pp.

642646, Apr. 2000.

[11] F. Kuttner, A 1.2-V 10-b 20-Msample/s nonbinary successive approximation ADC in 0.13-m CMOS, in IEEE Int. Solid-State Circuits Conf.

Dig. Tech. Papers, 2002, pp. 176177.

[12] M. Scott, B. Boser, and K. Pister, An ultra-low power ADC for distributed sensor networks, in Proc. Eur. Solid State Circuits Conf. (ESSCIRC), 2002, pp. 255258.

16

61

D. Figure of Merit

As a commonly used figure of merit (FOM) for ADCs considering resolution, bandwidth, and power, we use

Sampling rate

FOM

REFERENCES

Power dissipation

(1)

8-bit and 9-bit operation. The resulting curves show a maximum

in the range between 0.550.8 V, respectively. In this region, the

most effective operation is obtained for the used devices with

threshold voltages of about 400 mV. These data translate into a

ratio of supply voltage and threshold voltage between 1.4 and 2.

E. Comparison With Other Approaches

Also in Fig. 13, published data about low-voltage successive approximation converters from the literature are considered

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