Beruflich Dokumente
Kultur Dokumente
Andreas Ehliar
Linköping, 2009
Performance driven FPGA design with an ASIC perspective
Andreas Ehliar
Dissertations, No 1237
Copyright °
c 2008-2009 Andreas Ehliar (unless otherwise noted)
ISBN: 978-91-7393-702-3
ISSN: 0345-7524
Printed by LiU-Tryck, Linköping 2009
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Abstract
iii
falls when porting designs optimized for an FPGA to an ASIC. The focus
in this case is on systems where initial low volume production will be
using FPGAs while still keeping the option open to port the design to
an ASIC if the demand is high. This information will also be useful for
designers who want to create IP cores that can be efficiently mapped to
both FPGAs and ASICs.
Finally, a framework is also presented which allows for the creation
of custom backend tools for the Xilinx design flow. The framework is
already useful for some tasks, but the main reason for including it is to
inspire researchers and developers to use this powerful ability in their
own design tools.
iv
Populärvetenskaplig
Sammanfattning
v
hur dessa kan optimeras för FPGAer. Huvudfokus i denna del är paket-
baserade nätverk men ett kretskopplat nätverk optimerat för FPGAer un-
dersöks också.
Alla fallstudier innehåller också information om eventuella fallgropar
när kretsarna ska konverteras från en FPGA till en ASIC. I detta fall är
fokus främst på system där småskalig produktion använder FPGAer där
det är viktigt att hålla möjligheten öppen till en ASIC-konvertering om
det visar sig att efterfrågan på produkten är hög. Detta avsnitt är även av
intresse för utvecklare som vill skapa IP-kärnor som är effektiva i både
FPGAer och i ASICs.
Slutligen så presenteras ett ramverk som kan användas för att skapa
skräddarsydda backend-verktyg för det designflöde som Xilinx använ-
der. Detta ramverk är redan användbart till vissa uppgifter men den
största anledningen till att detta inkluderas är att inspirera andra forskare
och utvecklare till att använda denna kraftfulla möjlighet i sina egna
utvecklingsverktyg.
vi
Abbreviations
vii
• LUT1, LUT2, . . . , LUT6: Lookup-tables with 1 to 6 inputs
viii
Acknowledgments
There are many people who have made this thesis possible. First of all,
without the support of my supervisor, Prof. Dake Liu, this thesis would
never have been written. Thanks for taking me on as your Ph.D. student!
I would also like to acknowledge the patience with my working hours
that my fiancee, Helene Karlsson, has had during the last year. Thanks
for your understanding!
I’ve also had the honor of co-authoring publications with Johan Eilert,
Per Karlström, Daniel Wiklund, Mikael Olausson, and Di Wu.
Additionally, in no particular order1 I would like to acknowledge the
following:
ix
• All the teaching staff at Datorteknik, especially Lennart Bengtsson
who offered much valuable advice when I was given the responsi-
bility of giving the lectures in basic switching theory.
x
Contributions
• An investigation of the design tradeoffs for the data path and con-
trol path of a 32-bit microprocessor with DSP extensions optimized
for the Virtex-4 FPGA. The microprocessor is optimized for very
high clock frequencies (around 70% higher than Xilinx’ own Mi-
croblaze processor). Extra care was taken to keep the pipeline as
short as possible while still retaining as much flexibility as possible
at these frequencies. The processor should be very good for stream-
ing signal processing tasks and adequate for general purpose tasks
when compared with other FPGA optimized processors. Finally, it
is also possible to port the processor to an ASIC with high perfor-
mance.
xi
mance comparable to commercially available floating point mod-
ules for Xilinx FPGAs.
xii
Preface
This thesis presents my research from October 2003 to January 2009. The
following papers are included in the thesis:
The second paper presents an open source packet switched NoC archi-
tecture optimized for Xilinx FPGAs. It was published at FPL 2007. The
source code for this NoC is also available under an open source license
to allow other researchers to build on this work.
xiii
Paper III: Thinking outside the flow: Creating
customized backend tools for Xilinx based de-
signs
The third paper presents the PyXDL tool which allows XDL files to be
analyzed and edited from Python. It was published at FPGAWorld 2007.
The PyXDL tool is available as open source.
xiv
rounding modes and the test suite. The remaining contributions in this
paper are roughly equal.
Licentiate Thesis
The content of this thesis is also heavily based on my licentiate thesis:
Other Publications
• Flexible route lookup using range search, Andreas Ehliar, Dake Liu;
Proc of the The Third IASTED International Conference on Com-
munications and Computer Networks (CCN), 2005
• High Performance, Low Latency FPGA based Floating Point Adder and
Multiplier Units in a Virtex 4, Karlström, P. Ehliar, A. Liu, D; 24th
Norchip Conference, 2006.
xv
xvi
Contents
1 Introduction 1
1.1 Scope of this Thesis . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
I Background 5
2 Introduction to FPGAs 7
2.1 Special Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Xilinx FPGA Design Flow . . . . . . . . . . . . . . . . . . . 9
2.3 Optimizing a Design for FPGAs . . . . . . . . . . . . . . . . 10
2.3.1 High-Level Optimization . . . . . . . . . . . . . . . 10
2.3.2 Low-level Logic Optimizations . . . . . . . . . . . . 11
2.3.3 Placement Optimizations . . . . . . . . . . . . . . . 12
2.3.4 Optimizing for Reconfigurability . . . . . . . . . . . 13
2.4 Speed Grades, Supply Voltage, and Temperature . . . . . . 14
xvii
3.3.2 Guarding Against Bugs in the Designs . . . . . . . . 23
3.3.3 A Possible Bias Towards Xilinx FPGAs . . . . . . . 23
3.3.4 Online Errata . . . . . . . . . . . . . . . . . . . . . . 24
3.4 Method Summary . . . . . . . . . . . . . . . . . . . . . . . . 24
4 ASIC vs FPGA 27
4.1 Advantages of an ASIC Based System . . . . . . . . . . . . 27
4.1.1 Unit Cost . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.1.2 Higher Performance . . . . . . . . . . . . . . . . . . 28
4.1.3 Power Consumption . . . . . . . . . . . . . . . . . . 28
4.1.4 Flexibility . . . . . . . . . . . . . . . . . . . . . . . . 29
4.2 Advantages of an FPGA Based System . . . . . . . . . . . . 30
4.2.1 Rapid Prototyping . . . . . . . . . . . . . . . . . . . 30
4.2.2 Setup Costs . . . . . . . . . . . . . . . . . . . . . . . 30
4.2.3 Configurability . . . . . . . . . . . . . . . . . . . . . 31
4.3 Other Solutions . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.4 ASIC and FPGA Tool Flow . . . . . . . . . . . . . . . . . . . 33
xviii
5.11 Manual Floorplanning and Routing . . . . . . . . . . . . . 62
5.12 Pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5.13 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
xix
7.8.1 MicroBlaze . . . . . . . . . . . . . . . . . . . . . . . . 96
7.8.2 OpenRisc . . . . . . . . . . . . . . . . . . . . . . . . 96
7.9 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
7.10 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
xx
10.4.1 Hybrid Routing Mechanism . . . . . . . . . . . . . . 126
10.4.2 Packet Switched . . . . . . . . . . . . . . . . . . . . 128
10.4.3 Circuit Switched NoC . . . . . . . . . . . . . . . . . 131
10.4.4 Minimal NoC . . . . . . . . . . . . . . . . . . . . . . 131
10.4.5 Comparing the NoC Architectures . . . . . . . . . . 132
10.5 Wishbone to NoC Bridge . . . . . . . . . . . . . . . . . . . . 133
10.6 Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . 135
10.7 Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
10.8 ASIC Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
10.9 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
12 Conclusions 149
12.1 Successful Case Studies . . . . . . . . . . . . . . . . . . . . . 149
12.2 Porting FPGA Optimized Designs to ASICs . . . . . . . . . 150
xxi
xxii
Chapter 1
Introduction
Field programmable logic has developed from being small devices used
mainly as glue logic to capable devices which are able to replace ASICs
in many applications. Today, FPGAs are used in areas as diverse as flat
panel televisions, network routers, space probes and cars. FPGAs are
also popular in universities and other educational settings as their con-
figurability make them an ideal platform when teaching digital design
since students can actually implement and test their designs instead of
merely simulating them. In fact, the availability of cheap FPGA boards
mean that even amateurs can get into the area of digital design.
As a measure of the success that FPGAs enjoy, there are circa 7000
ASIC design starts per year whereas the number of FPGA design starts
are roughly 100000 [1]. However, most of the FPGA design starts are
likely to be for fairly low volume products as the unit price of FPGAs
make them unattractive for high volume production. Similarly, most of
the ASIC design starts are probably only intended for high volume prod-
ucts due to the high setup cost and low unit cost of ASICs. Even so, the
ASIC designs are likely to be prototyped in FPGAs. And if a low volume
FPGA product is successful it may have to be converted to an ASIC.
One of the motivations behind this thesis is to investigate a scenario
where an FPGA based product has been so successful that it makes sense
to convert it into an ASIC. However, there are many ways that an ASIC
and FPGA design can be optimized and not every ASIC optimization
1
2 Introduction
can be used in an FPGA and vice versa. If the FPGA design was not
designed with an ASIC in mind from the beginning, it may be hard to
create such a port. This thesis will classify and investigate various FPGA
optimizations to determine whether they make sense to use in a product
that may have to be ported to an ASIC. This part of the thesis should
also be of interest to engineers who are tasked with creating IP cores for
FPGAs if the IP cores may have to be used in ASICs.
Another motivation is simply the fact that the large success of FPGAs
of course also means that there is a large need for information about how
to optimize designs for these devices. Or, to put it another way, a de-
sire to advance the state of the art in creating designs that are optimized
for FPGAs. This effort has focused on areas where we believed that the
current state of the art could be substantially improved or substantially
better documented.
A more personal motivation is the fact that relatively little research
on FPGA optimized design is happening in Sweden. After all, it is more
likely that a freshly graduated student from a university will be involved
in VLSI design for FPGAs rather than ASICs. My hope is that this thesis
can serve as an inspiration for these students and perhaps even inspire
other researchers to look further into this interesting field.
The results in this thesis should be of interest for engineers tasked
with the creation of FPGA based stand alone systems, accelerators, and
soft processor cores.
• Microprocessors
• Networks-on-Chip
1.2 Organization 3
1.2 Organization
The first part of this thesis contains important background information
about FPGAs, FPGA optimizations, design flow, and methods. This part
also contains a comparison of the performance and area cost for different
components in both FPGAs and ASICs.
Part II contains an investigation of two microprocessors (one FPGA
friendly processor and one FPGA optimized processor). This part also
contains a description of the floating point adder and multiplier. Part III
4 Introduction
1 The electronic version of this thesis does not contain Part VI.
Part I
Background
5
Chapter 2
Introduction to FPGAs
7
8 Introduction to FPGAs
Switch matrix
Non−local
connections
Lookup Flip
table flop
available to easily connect several DSP48 blocks to each other that can be
used to build efficient FIR filters or larger multipliers for example.
In some FPGAs there are also more specialized blocks like processor
cores, Ethernet controllers, and high speed serial links.
• Place and route: First decide where all slices, memory blocks, etc
should be placed in the FPGA and then route all signals that con-
nects these components
There are also other steps that are optional but can be used in some
cases. A static timing analyzer, for example, can be used to determine
the critical path of a certain design. It can also be used to make sure that
a design is meeting the timing constraints, but this is seldom necessary
as the place and route tool will usually print a warning if the timing
constraints are not met.
There are special tools available to inspect and modify the design.
A floorplanning tool allows a designer to investigate the placement of
all components in a design and change the placement if necessary. An
FPGA editing tool can be used to view and edit the exact configuration
of a CLB and other components in terms of logic equations for LUTs,
flip-flop configuration, etc. It will also show how signals are routed in
the FPGA and can also change the routing if necessary.
10 Introduction to FPGAs
Other ways in which the design can be fine tuned is to make sure
that the algorithms are mapped to the FPGA in such a way that
adders can be efficiently combined with other components such as
muxes while keeping the number of logic levels low.
Slice
Lut
D Q X
MUXF5
R
Lut
MUXF6
Slice
Lut
Slice
Lut
X
1
MUXF5
Lut MUXF5
Lut
(a) Using four LUTs configured as 2-to-1 (b) Using two LUTs configured as or gates
muxes
design consists of a complicated data path, the entire data path could be
designed using RLOC attributes to ensure that the data path will always
be placed in a good way.
The advantage of floorplanning has been investigated in [2], and was
found to be able to improve the performance from 30% to 50%. However,
since this was published in 2000, a lot of development has happened in
regards to automatic place and route. Today, the performance increase
that can be gained from floorplanning is closer to 10% or so and it is often
enough to floorplan only the critical parts of the design [3]. It should also
be noted that it is very easy to reduce the performance of a design by a
slight mistake in the floorplanning.
Finally, if it is still not possible to meet timing even though floorplan-
ning has been explored, it might be possible to gain a little more perfor-
mance by manually routing some critical paths. The author is not aware
of any investigation into how much this will improve the performance,
but the general consensus seems to be that the performance gains are not
worth the source code maintenance nightmare that manual routing leads
to.
and the support from the design tools is rather limited. But the config-
urability of an FPGA can still be useful, even if it is not possible to re-
configure the FPGA dynamically. One example is to use a special FPGA
bitstream for diagnostic testing purposes (e.g. testing the PCB that the
FPGA is located on). While such functionality could be included in the
main design it may be better from a performance and area perspective to
use a dedicated FPGA configuration for this purpose.
85 ◦ C 65 ◦ C 45 ◦ C 25 ◦ C 0 ◦C
1.14V 323.2 324.1 325.3 326.4 329.6
1.18V 334.0 335.1 336.2 337.4 340.8
1.22V 344.5 345.7 346.9 347.9 351.4
1.26V 354.5 355.6 356.8 357.8 361.4
Table 2.2: Timing analysis using different values for supply voltage and
temperature
will not approach the worst case, we can specify a higher minimum volt-
age to the timing analyzer. Similarly, if good cooling is available, we can
specify that the FPGA will not exceed a certain temperature.
In Table 2.2, we can see the impact of these changes on a micro-
processor design in a Virtex-4 (speedgrade 12). In the upper left corner
the worst case with minimum supply voltage and maximum tempera-
ture is shown. The design will work at 323.2 MHz in all temperature and
voltage situations that the FPGA is specified for. On the other hand, if an
extremely good power and cooling solution is used, we could clock the
design at 361.4 MHz with absolutely no margin for error. This is a differ-
ence of over 10% without having to change anything in the design! It can
therefore be worthwhile to think about these values when synthesizing
a design for a certain application. Many real life designs will not need
to use the worst case values. However, results in publications are rarely,
if ever, based on other than worst case values. Therefore Table 2.2 is the
only place in this thesis where results are reported that are not based on
worst case temperature and supply voltage conditions.
16 Introduction to FPGAs
Chapter 3
Methods and Assumptions
Normally, the design flow for an FPGA based system will go through the
following design steps:
1. Idea
2. Design specification
6. Manufacturing
17
18 Methods and Assumptions
between the design specification phase and the HDL code development
phase. In fact, it is necessary to quickly identify areas that are likely to
cause performance problems and prototype these to gain the knowledge
that is necessary to continue with the design specification.
Another difference between a normal design flow and the design
flow employed in this thesis (and many other research projects) is that
a lot of effort was spent on low level optimizations with the intention of
reaching the very highest performance. This is uncommon in the indus-
try where performance that is “good enough” is generally accepted. To
know where the low level optimizations are required it is necessary to
study the output from the synthesis tool and the output from the place
and route tool. If there is something clearly suboptimal in the final netlist
it may be fixed either by rewriting the HDL code (possibly by instantiat-
ing low level FPGA primitives) or by manual floorplanning. This method
is described as “construct by correction” in [4] (which also contain a good
overview of the entire design process). Another description of the design
flow (with a focus on ASIP development) can be found in [5].
• Retiming: The tools are allowed to move flip flops to try to balance
the pipeline for maximum speed
Sometimes a synthesis bug is easy to detect, for example, if the area of the
design is significantly smaller than expected it is possible that a bug in
22 Methods and Assumptions
the optimization phase has removed logic that is actually used in the de-
sign. Sometimes bugs introduced by the synthesis or backend tools will
not have a dramatic effect on the area of a design and must be detected
by actually using the design in an FPGA. To guard against this possibil-
ity, all major designs in this thesis have been tested on at least one FPGA.
While minor bugs caused by the backend tools could still be present,
they are unlikely to ruin the conclusions of this thesis as they would be
present in fairly minor functionality of the designs that would only be
triggered under special circumstances. It should also be noted that it is
possible to simulate the synthesized netlist, which is yet another way to
detect whether the synthesis tool has done something wrong. (Bugs in
the backend tools are harder to detect.)
This situation is even worse for ASIC based design flows as it is not
practical to manufacture a small testdesign just to see if it works. In sum-
mary, we have little choice but to rely on the tools. Yet it is important to
stay on guard and not trust the tools 100%, especially when they report
odd or very odd results.
3.3 Possible Error Sources 23
studies discussed in this thesis were optimized for Xilinx FPGAs, and
often a particular Xilinx FPGA family as well. Care has been taken to
avoid an unfair bias towards Xilinx in the parts that discuss other FPGA
families but it is nevertheless possible that some bias may still be present
and it is only fair to warn the reader about this.
There is also a clear bias towards SRAM based FPGAs in this text as
FPGA families manufactured using flash and antifuse technologies are
not typically designed for high performance.
• Be wary of bugs in both the design and the CAD tools. Always
check that the reported area and performance are reasonable.
26 Methods and Assumptions
Chapter 4
ASIC vs FPGA
There are many similarities when designing a product for use with either
an FPGA or an ASIC. There are also many differences in the capabilities
of an FPGA and an ASIC. This chapter will concentrate on the most im-
portant differences.
27
28 ASIC vs FPGA
costs and therefore even higher volumes are necessary before it makes
sense to consider an ASIC.
4.1.4 Flexibility
The final main reason for using an ASIC instead of an FPGA is the flex-
ibility you gain with an ASIC. An ASIC allows the designer to imple-
ment many circuits which are either impossible or impractical to create
in the programmable logic of an FPGA. This includes for example A/D
converters, D/A converters, high density SRAM and DRAM memories,
non volatile memories, PLLs, multipliers, serializers/deserializers, and
a wide variety of sensors.
Many FPGAs do contain some specialized blocks, but these blocks are
selected to be quite general so that they are usable in a wide variety of
contexts. This also means that the blocks are far from optimal for many
users. In contrast, an ASIC designer can use a block which has been
configured with optimal parameters for the application the designer is
envisioning. This allows an ASIC designer to both save area and increase
the performance.
The ultimate in flexibility is the ability of an ASIC designer to design
either part of the circuit or the entire circuit using full custom methods.
This allows the designer to create specialized blocks which have no par-
allel in FPGAs. For example, if a designer wanted to create an image
processor with integrated image sensor, this would not be possible to do
30 ASIC vs FPGA
number of low cost prototype board available for various FPGAs. All of
this means that anyone, even hobbyists, can start using an FPGA without
having to buy any expensive tools. This is certainly not true for ASICs as
the tool cost alone can be prohibitive in many cases.
The other reason for the low setup cost is that the use of an FPGA
means that the mask costs associated with an ASIC are avoided which
can be a significant saving for a modern technology.
4.2.3 Configurability
There are two main reasons why the configurability of an FPGA is impor-
tant. The cost reason has already been briefly mentioned in Section 4.2.2.
The other reason is that it is possible to deploy bug-fixes and/or up-
grades to customers if a reconfigurable FPGA is used.
If a one time programmable FPGA, such as a member of Actel’s anti-
fuse based FPGA family, is used, this is of course not possible. It will
still be possible to change the configuration of newly produced prod-
ucts without incurring the large NRE cost associated with an ASIC mask
change though.
Another interesting possibility is the ability to reconfigure only parts
of an FPGA while the FPGA is still running, so called partial dynamic
reconfiguration. This capability is present in the Xilinx Virtex series from
Virtex-II and up. This could for example mean that a video decoding
application could have a wide variety of optimized decoding modules
stored in flash memory. As soon as the user wants to play a specific video
stream, a decoding module optimized for that particular video format is
loaded into the FPGA.
The advantage is of course that a smaller FPGA could be used. The
disadvantage is that the tool support for dynamic reconfiguration is lim-
ited at the moment. Simulating and verifying such a design is also con-
siderably more difficult. Although a large number of research publica-
tions have studied partial reconfiguration it is seldomly used in real ap-
plications yet.
32 ASIC vs FPGA
Table 4.1: Comparison of the ASIC and FPGA design flow (not including
power optimizations)
36 ASIC vs FPGA
Chapter 5
FPGA Optimizations and
ASICs
37
38 FPGA Optimizations and ASICs
The approach used in this thesis is a more practical approach that in-
tends to highlight a scenario where FPGAs are used for relatively low
volume production and where the design is later on ported to an ASIC
for high volume production, primarily for cost reduction. Although a
lower total cost could be achieved by immediately designing for an ASIC,
this is a risky move for several reasons. For example, if the market for a
product is uncertain, it can be a good idea to avoid the high NRE costs of
an ASIC since it is not certain that these costs can be recouped. Even if
there actually is a huge market for a product it can still be a good idea to
use an FPGA in the beginning due to its short time to market.
What this part of the thesis intends to highlight is the impact of var-
ious FPGA optimized constructs when the design is ported to an ASIC.
The intention is that the reader should know what the impact is on an
ASIC port when using different kinds of FPGA optimizations.
choice of speed or area did not make a large difference in the area but a
huge difference in the speed.
While it is possible to trade area for frequency in an FPGA as well,
it is seldom possible to do so for primitive constructs like adders (under
the assumption that reasonable sized adders are used).
The performance of this circuit is used as a reference for all other performance comparisons in this chapter!
5.5 Adders
Adders with more than two inputs are typically more area
ASIC
Porting efficient in ASICs than in FPGAs.
Hint
5.6 Multiplexers 45
5.6 Multiplexers
Figure 5.7: 32-bit bus with 8 master ports and 8 slave ports
Figure 5.8: 32-bit crossbar with 8 master ports and 8 slave ports (Imple-
mented with muxes)
formance of this kind of solution will also be very good, almost the same
as for just the 32-bit adder.
However, if two 2-to-1 muxes should be used, one for each operand,
the area cost will double since it is not possible to put that mux into
the same LUT as seen in Figure 5.10. Finally, if large muxes like 4-to-
1 muxes are used for both operands of the adder, the area cost of the
FPGA designs will go up significantly and the performance will drop
considerably as can be seen in Figure 5.11
There are two final examples that are interesting to mention. The first
is a rather special case which may be good to know about; the case where
5.7 Datapath Structures with Adders and Multiplexers 49
a two input and gate is used as the input for both adder operands as can
be seen in Figure 5.12. Note that this has the same area cost in Xilinx
FPGAs as a plain adder. This is because the and MULT_AND primitive
can be used for one of the and gates. A similar structure was also used
in the ALU in Microblaze where the result can be either OpB + OpA, OpB
- OpA, OpB, or OpA [30]. Without using the MULT_AND primitive it
would not be possible to get the last operation here (OpA)). Stratix III
also allows this structure to be implemented using the same amount of
resources as a plain adder because it has a dedicated adder inside each
slice and doesn’t need to use LUTs to create the adder itself. The LUTs
in the slice can therefore be used separately to create these (and other)
functions.
The other case is when an adder/subtracter is used instead of just an
adder. Figure 5.13 and Figure 5.14 shows the properties of an adder/-
subtracter without and with a 2-to-1 input mux on one of the inputs. The
plain adder/subtracter can be implemented with the same area as an
adder in all FPGAs. However, it is not possible to combine an adder/-
subtracter with a mux in most FPGAs.
Overall, it is hard to say anything definitive about the cost of these
components in an ASIC since there is a large gap between the area and
frequency of the slowest and fastest variation. What can be seen in these
50 FPGA Optimizations and ASICs
Figure 5.12: 32-bit adder with 2-input bitwise and on both operands
Figure 5.14: 32-bit add/sub with 2-to-1 mux for one operand
5.8 Multipliers 51
figures, especially the area optimized figures is that this particular kind
of FPGA optimization is not very helpful for the ASIC performance or
ASIC area. The area when optimized for area is (not surprisingly) about
the same as when combining the area of the individual components.
While a lot of performance and area can be gained in an
FPGA by merging as much functionality into one LUT
ASIC
Porting as possible, this will typically not decrease the area cost
Hint
or increase the performance of an ASIC port.
5.8 Multipliers
The most common method for multiplication in FPGAs today is to use
one of the built in multiplier blocks that are present in almost all modern
FPGAs. While some FPGAs such as the Virtex-II and Spartan-3 have
a standalone multiplier as a separate block, other FPGAs also integrate
accumulators into the same block. The later are commonly called DSP
blocks.
In many cases there are optional pipeline stages built into these multi-
pliers and the maximum performance can only be reached if these pipeline
stages are utilized. In the Spartan 3A for example, there are optional
pipeline stages before and after the combinational logic of the multiplier
whereas a DSP48 block in a Virtex-4 can contain up to 4 pipeline reg-
isters. (Although the fourth register will not increase the performance
as it is only present to easily allow for construction of large multipliers
without having to store intermediate results in flip-flops in the FPGA
fabric [31]).
As an example of how to optimize a circuit for the DSP blocks we will
study a typical MAC unit in a simple DSP processor when implemented
on a Virtex-4 or 5. The MAC unit contains a 16× 16 multiplier and four
48-bit accumulator registers. This could be implemented as seen in Fig-
ure 5.15. Unfortunately, the FPGA performance is not very good in this
case since it is not possible to use the built-in accumulation register of the
DSP48 block.
52 FPGA Optimizations and ASICs
The adder could also be pipelined, as shown in Figure 5.16. This al-
lows a high performance to be reached, but the circuit is no longer iden-
tical to the circuit in Figure 5.15. In this case it is no longer possible to
perform continuous accumulation to the same accumulation register due
to the data dependency problems introduced by the pipelined adder.
Finally, a circuit that still allows for high speed operation while hav-
ing the same capabilities as the circuit in Figure 5.15 is shown in Fig-
ure 5.17. In this circuit result forwarding is used to bypass the register
file. The performance of this circuit is much higher than the naive im-
plementation and clearly demonstrates how important it is to make sure
5.8 Multipliers 53
5.9 Memories
When synthesizing a design for ASIC that contains memories it is very
important that optimized memory blocks are used for large memories.
As an experiment, an 8 KiB memory block was synthesized with stan-
dard cells for an ASIC process (and optimized for area). The area was
5.9 Memories 55
use a dual port memory than a single port memory. There are many cases
where a dual port memory is natural to use but not strictly necessary. A
good example of this is a synchronous FIFO. While it is convenient with
a dual port memory here, it is not strictly necessary as it is possible to
use for example two single port memories and design the FIFO so that
one memory is read while the other is written and vice versa. This is
described in for example [35].
Finally, there are examples where it is not easily possible to avoid
the use of dual port memories. In such cases the cost of redesigning the
system to use single port memories has to be weighed against the area
savings such a redesign will produce.
Figure 5.18: Small register file memory with multiple read ports imple-
mented using duplication
Area cost values are relative to the values for the 32-bit adder in Figure 5.1.
Ports Spartan 3A Virtex 4 Virtex 5 Cyclone III Stratix III ASIC optimized for
Read Write Area Speed
1 1 0.50 0.50 0.25 9.8† 2.1 0.65 0.67
2 1 1.0 1.0 0.50 20† 2.1 0.78 0.83
2 2 9.5 9.5 13 11 4.5 0.95 1.1
4 2 14 14 15 16 6.1 1.2 1.4
† Area cost includes DSP blocks and/or memory blocks as described in Section 5.4.
Table 5.1: Relative area cost of an 8-bit 16 entry register file memory with
different number of ports
with one write port are caused by the use ofM9K block RAMs as the Cy-
clone III does not have distributed memory.
If many small register file memories with only one write
port and few read-ports are used in a design, the area cost
for an ASIC port will be relatively high compared to the
ASIC
Porting area cost of the FPGA version. On the other hand, if
Hint
more than one write port is required, the ASIC port will
probably be much more area efficient.
Large multiport memories are probably not going to be used in many
FPGA designs due to their extreme area cost. While such a memory
should certainly be more area efficient in an ASIC than an FPGA, the
area cost will be extremely high anyway. As an example, in a die-photo
58 FPGA Optimizations and ASICs
of an SPU in the cell processor the register file is roughly the same size as
one of the large SRAM blocks [36]. However, the RAM block is a single
port memory of 64 KiB whereas the register file has 6 read ports and 2
write ports and contains only 128 × 128 bits. The single port memory
stores around 30 times as much data as the register file while using the
same amount of die area!
There are also ways to fake a multiport memory that can be efficiently
used in both ASICs and FPGAs. One way is to use a normal memory
that has a clock signal which is running at a multiple of the regular sys-
tem clock frequency [37]. Another way is to use some sort of caching
scheme, although this implies that the memory is no longer a true multi-
port memory.
Both Fmax and area cost values are relative to the values for the 32-bit adder in Figure 5.1.
Device Relative Relative
performance area cost
Spartan 3A 0.72 8.2
Virtex 4 0.64 8.2
Virtex 5 0.51 8.2
Cyclone III 0.85 11
Stratix III 1 8.2
ASIC (Speed) 0.92 2.4
ASIC (Area) 0.19 1.5
Another issue is designs that are heavy users of the SRL16 primitive
in Xilinx FPGAs. These small 16-bit shift registers are commonly used in
delay lines or small FIFOs. As can be seen in Section 10.8, this can lead
to a huge area increase in an ASIC when compared against a design that
doesn’t use SRL16 primitives.
There are a few other considerations to take into account when using
memories in an ASIC process that are not necessary to take into account
in an FPGA. For example it might be possible to generate memories that
are optimized for speed or power consumption. For large memories it
might be a good idea to use a memory with redundancy so that a tiny
fabrication error in the memory will not cause it to fail. In an ASIC mem-
ory it is often also possible to use a write mask, which means that it is
possible to write to only certain bits in a memory word without having
to do a read-modify-write operation.
Virtex 4 0.98 1
LUT
Virtex 5 0.9 1
ASIC (Speed) 0.76 1.4
LUT
Area cost values are relative to the values for the 32-bit adder in Figure 5.1.
Pipeline Spartan 3A Virtex 4 Virtex 5 Cyclone III Stratix III ASIC optimized for
Stages Area Speed
1 260† 380† 450† 57 54 5.5 20
2 260† 380† 450† 58 77 6.1 13
3 260† 380† 450† 61 79 6.8 14
4 260† 380† 450† 60 78 7.0 13
† Area cost includes DSP blocks and/or memory blocks as described in Section 5.4.
(The constant coefficient multipliers are implemented in the fabric in the Cyclone III and Stratix III
devices and don’t use DSP blocks.)
Fmax values are relative to the values for the 32-bit adder in Figure 5.1.
Pipeline Spartan 3A Virtex 4 Virtex 5 Cyclone III Stratix III ASIC optimized for
Stages Area Speed
1 0.25 0.17 0.16 0.39 0.39 0.073 0.30
2 0.33 0.21 0.21 0.47 0.52 0.079 0.35
3 0.38 0.28 0.27 0.59 0.58 0.10 0.41
4 0.37 0.28 0.27 0.73 0.67 0.10 0.40
5.12 Pipelining
Pipelining is an important technique to improve the performance of a
digital design. In FPGAs this can be done in an area efficient manner
since there are usually a large amount of flip-flops available in an FPGA.
When porting a design to an ASIC it is seldom a drawback to have a
large number of pipeline stages as well if performance is the number one
priority. Unfortunately flip-flops can be fairly expensive in terms of area
in an ASIC which means that it may be a good idea to rewrite the design
so that fewer pipeline stages are needed. However, it is not always true
that an increased number of pipeline stages will always increase the area.
Consider for example the case outlined in Table 5.3 and Table 5.4 where
a pipeline for an eight point 1D DCT was implemented using different
number of pipeline stages. (This module was not optimized for FPGAs
in any way.) When going from one to two pipeline stages the maximum
64 FPGA Optimizations and ASICs
frequency increased by almost 15% even though the area of the new de-
sign is only 65% as large as the area of the design with a shorter pipeline.
This is probably caused by area inefficient optimizations used by the syn-
thesis tool as it is struggling to reach an unreachable performance goal.
When adding extra pipeline stages after that, the performance increases
until a plateau is reached at the third pipeline stage.
This example shows that pipelining a datapath is not guaranteed to
increase the area although it is not uncommon that the area is increased,
especially if the datapath is not a part of a critical path such as when
adding delay registers to synchronize the values in one datapath with
the values in another datapath.
While pipelining an FPGA design will certainly not hurt
the maximum frequency of an ASIC, the area of the ASIC
will often be slightly larger than necessary, especially if
ASIC
Porting the pipeline is not a part of the critical path in the ASIC.
Hint
Designs that contains huge number of delay registers will
be especially vulnerable to such area inefficiency.
5.13 Summary
There are a wide variety of issues that need to be taken into account when
porting a design from an FPGA to an ASIC. This is especially true if the
design has been optimized for a certain FPGA from the beginning with-
out any thoughts of an ASIC port.
When porting a design the most tricky areas are likely to be the ar-
chitecture around the memories and multipliers. If these have been opti-
mized for a specific FPGAs an ASIC port is likely to be suboptimal. The
other FPGA optimizations are not going to harm an ASIC port and are in
some cases even beneficial.
There are also many other issues that have not been discussed here,
like I/O, design for test, and power dissipation which it is important that
the designer takes into account as well.
Part II
65
Chapter 6
An FPGA Friendly
Processor for Audio
Decoding
Abstract: In this chapter a DSP processor specialized for audio decoding will be
described. While not specifically optimized for FPGAs, the processor is still able
to achieve a clock frequency of 201 MHz in a Virtex-4 and the performance of the
processor when decoding an MP3 bitstream is comparable to a highly optimized
commercial MP3 decoding library.
In early FPGAs soft processors were seldom used due to their large
area and the high cost of an FPGA compared to a microprocessor. Nowa-
days the situation is decidedly different and soft processors are regularly
used in anything from the smallest to the largest FPGAs. Although most
people are probably using the soft processor cores that are available from
their FPGA vendor there are also a huge amount of processors available
at for example OpenCores [39] (95 at the time of writing). There is cer-
tainly no lack of choice in the soft processor market.
67
68 An FPGA Friendly Processor for Audio Decoding
The main reason to create yet another soft core processor is because the
majority of the processors that are available are not really optimized for
FPGAs. While some processors on OpenCores probably have a decent
performance in an FPGA, none are likely to match the performance of
the FPGA optimized processors that are available from the FPGA ven-
dors. Another issue is that there does not seem to exist a credible DSP
processor that has been optimized for FPGAs.
1024 words large. It is primarily used for floating point constants. The
data memory is 16 bits wide and 8192 words can be stored in it. Totally
the chip has 343 kilobit memory.
It is not possible to read or store a 23 bit floating point value directly
to the data memory due to the difference in size. This is handled by con-
verting floating point values into a 16 bit format before they are stored
to memory. The different word lengths were chosen by profiling an MP3
decoder, which was modified to support a number of different floating
point formats.
6.2.2 Pipeline
The architecture of the processor is shown in Figure 6.1. As can be seen,
the processor has a relatively long pipeline, especially the floating point
units. Every pipeline step also does relatively little work, which means
that it should be relatively simple for a synthesis tool to map this archi-
tecture to an FPGA. (Another reason for the long pipeline was to ensure
6.2 An Example of an FPGA Friendly Processor 71
bitstream. In the case of the LiU firmware the value of 20 MIPS is reached
by constructing a synthetic bitstream where all options and values in
the bitstream have been chosen to trigger the worst case behavior of the
decoder.
As can be seen, the performance of the xi MP3 decoder using our own
firmware is efficient when compared to the Spirit MP3 Decoder [41] on
single issue processors such as the ARM9. As for the memory usage,
the use of floating point constants initially seems to drastically reduce
the amount of constant memory used. However, this is not necessar-
ily true as the Huffman decoding is implemented entirely as a program
in our decoder. (It is not clear how the Spirit MP3 decoder stores the
Huffman table but it is likely that it is stored in constant memory.) The
program memory size for our decoder is not so impressive although op-
timizing the size of the program memory was never a goal for this partic-
ular project. There is a lot that could be improved here, see Section 6.2.6
for more information. Also note that our decoder is only able to decode
MPEG1 - layer III bitstreams. A fully compliant decoder should also be
able to decoder layer I and II. This would take some additional program
memory.
When comparing the performance of our processor with the VLIW
based AudioDE processor it is also clear that an impressive performance
improvement can be gained by increasing the parallelism. There is how-
ever a rather steep increase in terms of memory area and probably core
6.2 An Example of an FPGA Friendly Processor 73
As has already been mentioned, this project was mostly aimed at demon-
strating that low precision floating point arithmetic can efficiently be
used for audio applications. Therefore a number of details were not in-
vestigated fully and could certainly be improved.
Program Size
The most important thing to improve is program memory size. One way
to improve this could be to improve the instruction encoding. If the in-
struction word could be reduced by two bits this would mean an 8%
saving in program memory size. This would be possible at the expense
of reducing the size of immediate constants and would therefore mean a
slight decrease in performance due to the need to load certain constants
into registers before use.
Another way to decrease the program memory size is to use loop
instructions instead of unrolling some code. This could probably save
around a kilobyte of program code, especially in the windowing, which
consists of large unrolled convolution loops.
However, the most major savings would come from optimizing the
Huffman decoder. Right now all Huffman tables are implemented en-
tirely in software using the read-bit-and-branch-conditionally instruc-
tion. This is very wasteful and it is likely that the size of the Huffman
tables (6.7kB) could be reduced by about half by using a memory with
custom bit width and a small Huffman decoding accelerator. This would
6.2 An Example of an FPGA Friendly Processor 75
also have the advantage of accelerating the performance of the MP3 de-
coder as well.
Processor Architecture
6.2.7 Conclusions
Although the xi processor successfully demonstrated that floating point
arithmetic is a good idea for audio processors the processor and firmware
could be improved:
2 The assembler and simulator will help the programmer with this by warning him when
• The integer pipeline and the floating point pipeline had different
lengths, making it possible to create a situation where both pipelines
are trying to write to the register file at the same time.
Abstract: In this chapter the tradeoffs that are required to design a micro-
processor with a very high clock frequency in an FPGA is described. The design
has been carefully optimized for the Virtex-4 FPGA architecture to ensure as
much flexibility as possible without making any compromises regarding a high
clock frequency. Even though the processor is more advanced than the FPGA
friendly processor described in the previous chapter, the FPGA optimizations
allows it to operate at a much higher clock frequency. With floorplanning, the
processor can achieve a clock frequency of 357 MHz in a Virtex-4, which is con-
siderably higher than other FPGA optimized processors.
77
78 A Soft Microprocessor Optimized for the Virtex-4
• Result forwarding
• Address generator
• Shifter
+/− +/−
+/− +/−
+/− +/−
+/− +
adder to select from a number of different results. Figure 7.1 shows the
maximum performance attainable with various mux configurations.
As can be seen in Figure 7.1, the performance drops drastically com-
pared to the 412.2 MHz shown in Table 7.1. This is especially true for an
adder/subtracter with muxes on both inputs (e-g). This can be mitigated
by removing the subtracter from the adder as seen in the last configura-
tion (h) in Figure 7.1. Only configuration a and h can be implemented
using one lookup-table per bit in the adder. The remaining configura-
tions suffers from additional routing and logic delays.
Unfortunately configuration h doesn’t directly support subtraction.
This can be fixed by moving the inverter used for subtraction to the pre-
vious pipeline stage as seen in Figure 7.2. Additionally, by utilizing the
Force0, Force1, InvA, and Swap signals, an arithmetic unit can be con-
structed that can handle most result forwarding operations without any
penalty as described in Table 7.2. The only operation this configuration
cannot handle is to forward the same result to both inputs since it is only
possible to feed back the result to one input of the adder. (Although this
is of little use when subtracting.)
Finally, the careful reader may have noticed that it is not possible
to forward data from any other execution unit directly to the arithmetic
unit. The lack of full forwarding is a weakness of this processor, but
the implementation of partial forwarding allows a significant increase in
clock frequency when compared to a processor with full forwarding. For
example, if full forwarding was implemented it is likely that the con-
7.1 Arithmetic Logic Unit 81
°2008
c IEEE. Reprinted from Field Programmable Logic and Applications, 2008. FPL 2008.
International Conference on , , Ehliar, A. Karlström, P. Liu, D.
Figure 7.2: An arithmetic unit that can handle the most common result
forwarding operations (Maximum frequency, 403 MHz in a Virtex-4 of
the fastest speedgrade)
Table 7.2: Forwarding operands to the arithmetic unit (The order of the
operands are destination register, OpA, OpB).
R
Execution
unit 2
R
Execution
unit 3
forwarding process.
To simplify things for the programmer, automatic result forwarding
was implemented in favor of letting the programmer handle it. Figure 7.5
shows the first experiment as a. By putting the forwarding decision into
the decode stage the result is available in the next pipeline stage. Unfor-
tunately the performance of 337 MHz for this configuration when used
in the processor was not quite satisfactory. (Mostly due to the complexity
of quickly generating the control signals required for the forwarding in
the arithmetic unit described in the previous section.)
Instead, some matching logic was moved to the pipeline stage before
the decode stage. This means that the time available for reading from
the program memory is shortened somewhat. But the performance of
the program memory readout is still satisfactory as only a single LUT is
inserted before the flip-flops. This is shown as b in the figure.
It should also be noted that the forwarding logic in the xi2 processor is
slightly more complicated than described in this section as this pipeline
stage also has to generate the Force0/Force1/Swap/InvA signals shown
in Figure 7.2. It also has to handle data from the constant memory and
immediate data from the instruction word.
The MAC unit is relatively easy to support using the DSP48 blocks
in the Virtex-4 FPGA. Hardware loop support is also relatively easy to
7.3 Address Generator 85
Top−Step*2
Step
Step − Size
Top−Step
Step
+
Size
Top
+ −
− − MSB
MSB
To memory To memory
a) 209 MHz b) 458 MHz
tmp = A - B; B = A + B; A = tmp;
7.5 Shifter
The final component in the execute pipeline stage is the shifter. Figure 7.7
shows a number of different shift configurations. a and b shows a sim-
ple 32 bit shifter and the shifter in c can shift both left and right. It is no
surprise that the version that can shift in both directions is slower. By
pipelining version c, we arrive at version d, which is barely fast enough
but lacks arithmetic right shift. Adding an arithmetic right shift to d re-
sults in the relatively slow e. As both arithmetic and logic shift is typically
required in a processor another approach is necessary. f implements e in
a different way. Instead of implicitly writing the >>> operation in Ver-
ilog, it is implemented by generating a mask that is always or:ed together
with the result of the logic right shifter in the second pipeline stage. An-
other optimization is that a second unit determines in parallel if the shift
will be longer than 32 bits. In that case the result register will be set to
zero, regardless of the result of the shift (except for arithmetic right shift
of a negative number, which is handled by the mask generation unit).
Version f is used in the processor.
7.5 Shifter 89
a b a b
op
a) 326 MHz
c) 293 MHz
a b
a b
a << b a >> b
a >> b
op
b) 331 MHz
d) 375 MHz
a b
op
a b
op
e) 283 MHz
op
SR
f) 402 MHz
1
Fetch
PC
PM
Decode
CM IR
Read operands
RF
Register forwarding
FW
Execute 2
Writeback
WB
7.6.2 Input/Output
Input and output is handled through special instructions that can write
and read to a number of I/O-ports. Only one output port and one input
port is implemented, but it is also possible to update internal registers
like the address generator registers using these instructions. The instruc-
tion word is 27 bits. In the performance numbers quoted in this thesis a
32-bit memory was used regardless of this, but if a larger program has to
be used, the reduced number of bits in the instruction word means that
3 block RAMs with 9-bit wide memory ports could be placed in parallel
instead of using 4 block RAMs.
7.6.4 Branches
Delay slots are used for all branches. Apart from that, there are no penal-
ties for a correctly predicted branch. If the branch is mispredicted there
is a penalty of either three or four cycles depending on whether it is pre-
dicted as taken or not taken. Register indirect branches always have a
penalty of four cycles.
There are only absolute branches available, but this is not a problem
as the address space for the memories is only 16 bits wide and the target
address will fit into the instruction word. Finally, there is a loop instruc-
tion that allows small loops to be implemented with a minimum of loop
overhead.
in Figure 7.8 is that the second port of the constant memory (CM) and
data memory (MEM) is connected to the address generators described in
Section 7.3. A special part of the instruction word instructs the pipeline
to replace the OpA or OpB value in Figure 7.8 with a value read from
either the constant memory or the data memory.
When this ability is used in conjunction with the MAC operation this
allows a convolution to be efficiently performed. The MAC unit itself is
also not shown in the pipeline diagram, but it is based on instantiated
DSP48 blocks. It allows for 32x32 bit multiplication and 64 bit accumu-
lation. The results are accessed by reading from special registers as de-
scribed in Section 7.6.2. The MAC unit itself contains 6 pipeline stages
and the first stage is located in the Execute 1 stage.
7.7 Performance
In the beginning of this project the author thought it unlikely that this
processor would be able to compete with established commercial FPGA
microprocessors like MicroBlaze, hence the initial focus on DSP process-
ing. However, an initial design (lacking many features/instructions)
written directly in Verilog could be synthesized to almost 400 MHz in
a Virtex-4 (speedgrade 12). At this point we realized that it may be pos-
sible to create a more general purpose microprocessor that can operate at
a much higher clock frequency than MicroBlaze. The focus shifted from
a DSP processor to a microprocessor with DSP extensions at this point.
This processor has been optimized for a specific FPGA architecture.
While it is possible to synthesize the design without any changes for the
Virtex-5 instead of the Virtex-4, the performance when doing so is not
higher than in Virtex-4. A higher performance could probably be reached
if the processor was redesigned around the 6 input LUTs of the Virtex-5.
In fact, Table 7.3 shows that the performance in a Virtex-5 is lower than
in a Virtex-4.
94 A Soft Microprocessor Optimized for the Virtex-4
7.8.1 MicroBlaze
The most natural processor to compare this work with is the MicroBlaze
from Xilinx, which has been optimized for Xilinx FPGAs. The maximum
clock frequency of the MicroBlaze is going to be around 200 MHz [52] in
a Virtex-4 of the fastest speedgrade. However, it should be noted that Mi-
croBlaze is a much more complete processor than the processor described
in this chapter. For example, MicroBlaze has better forwarding, cache
support, and support for stalling the processor when a hazard occurs.
At the same clock frequency, it is very likely that the performance of Mi-
croBlaze will be higher than the processor described here. On the other
hand, xi2 has a maximum clock frequency which is over 70% higher than
MicroBlaze. We believe that xi2 will still have a comfortable performance
advantage for many applications, especially those that involve DSP algo-
rithms.
Unfortunately the source code of MicroBlaze is not publicly available
so it is not possible to investigate how well it will perform in an ASIC.
7.8.2 OpenRisc
The OpenRisc or1200 processor is an open source 32-bit microprocessor
that is available at the OpenCores website. It has similar features to the
MicroBlaze. When a version of the or1200 processor with 8 KiB instruc-
tion and data cache + 4 KiB scratch pad memory was synthesized to a
130 nm process the maximum frequency was around 200 MHz. When
synthesized to an FPGA, the performance was around 94 MHz.
It is clear that the or1200 processor is not optimized for FPGAs, but
it is also interesting to note that the performance of our xi2 processor
7.9 Future Work 97
started in the previous chapter and try to design a processor that has
very high performance in both FPGAs and ASICs with a minimum of
customizations for each architecture.
7.10 Conclusions
We believe that the processor described in this chapter is a very promis-
ing architecture. An improved version of this processor with a cache and
a compiler may be a serious alternative to other FPGA optimized proces-
sors, especially for DSP tasks where data dependencies can usually be
avoided by careful code scheduling.
The high Fmax of this design could be reached by carefully investigat-
ing the critical paths in all parts of the processor during the entire design
flow. By tailoring the architecture around these paths it was possible to
reach 357 MHz in a Virtex-4 (speedgrade 12). However, the final solution
represents a compromise between frequency and flexibility. One of the
tradeoffs is that the pipeline of the processor is visible to the program-
mer. For example, data hazards have to be managed in software since
the processor cannot detect this and stall the processor. A good toolchain
should be able to compensate for this, but this will also mean that it will
be hard to retain binary compatibility if the processor is improved.
When the processor is ported to a 130 nm ASIC process the perfor-
mance of the processor is 500 MHz and is mostly limited by the perfor-
mance of the memory blocks. To reach this performance in the ASIC
port it was necessary to rewrite the MAC unit to avoid the limitations
enforced by the DSP48 blocks in the FPGA version.
Chapter 8
Floating point modules
Abstract: This chapter describes how floating point components can be opti-
mized for FPGAs. The focus in this chapter is to create a high speed floating
point adder and multiplier with relatively low latency. The final solution has a
maximum frequency which is higher than previous publications at a comparable
pipeline depth although this comes at a price of a larger design area. The floating
point components can be easily ported to an ASIC with only minor modifica-
tions.
99
100 Floating point modules
1 0
Normalization
Compare/Swap Compare/Select
Align Mantissa
+/−
Normalization
As a first performance test, the floating point adder and multiplier from [58]
was synthesized to a Virtex-4 (speedgrade 12). These modules are closely
based on the architecture in Figure 8.1 and 8.2. The major difference
is that the multiplier consists of four pipeline stages instead of 2. The
source code of these modules were written in VHDL and were not opti-
mized for FPGA usage. The maximum frequency of the multiplier and
adder is 207 MHz and 190 MHz respectively when synthesized with ISE
9.2. The mantissa is 16 bits and an implicit 1 is used instead of an ex-
plicit 11 . The exponent is 6 bits and a sign bit is used to represent the
signedness of the number.
1 If an implicit 1 is used, the first bit in a floating point number is assumed to be set to 1.
This is always the case with a normalized floating point number. If an explicit 1 is used, the
first 1 is stored in the mantissa which is necessary if unnormalized floating point numbers
will be used.
8.4 Optimizing the Multiplier 103
Shifted by 0 4 20
Priority
decoder 6−1 MUX
tissa should be shifted and shift the mantissa. This is quite complicated
to do efficiently in an FPGA. One way to optimize this part is by using
parallelism. A normalize unit is constructed which can only normalize
a number with up to four leading zeros. Several of these units are then
placed in parallel. A priority decoder is used to determine the first unit
with less than four leading zeros. A final mux selects the correct man-
tissa and an adjustment factor for the exponent. This is illustrated in
Figure 8.3 for a mantissa width of 23 bits.
By incorporating this three stage normalizer into our floating point
adder and extending the compare/select pipeline stage into two stages,
we have constructed a floating point adder capable of operating at 361 MHz.
In this case the width of the mantissa is 23 bits (plus the implicit 1) and
the exponent 8 bits. This can be seen in Figure 8.4.
Other optimizations include a special signal to zero out the mantissa
of the smallest number (marked with 1 in the figure) if the control signal
to the shifter (marked with 2) is too large. This means that the shifter
itself only has to consider the five least significant bits. The cost of the
special “set to zero” signal is small as an otherwise unused LUT input in
the adder is used for it as shown in Figure 8.5.
Given these optimizations, the floating point adder with 7 pipeline
stages is able to support a throughput of 361 MHz in a Virtex-4 (speed-
grade 12).
CMP
2
Align
1
Add
Normalization
°2006
c IEEE. Reprinted from Norchip Conference, 2006. 24th, High Performance, Low Latency FPGA
based Floating Point Adder and Multiplier Units in a Virtex 4, Karlström, P. Ehliar, A. Liu, D.
Carry out
Sub
Set to zero
B
A Sum
LUT
Carry in
°2006
c IEEE. Reprinted from Norchip Conference, 2006. 24th, High Performance, Low Latency FPGA
based Floating Point Adder and Multiplier Units in a Virtex 4, Karlström, P. Ehliar, A. Liu, D.
will also be much higher than our solution. (Up to 16 pipeline stages in
the adder and 11 pipeline stages in the multiplier.)
tion stage which may be caused by the fact that this part is implemented
using instantiated FPGA primitives as seen in Figure 8.5. Once this part
is replaced with code that infers the same functionality the performance
is increased from around 400 MHz to 796 MHz.
For the multiplier, the critical path is not surprisingly in the multi-
plier itself. When using DSP48 based version ported to the ASIC, the
maximum performance is 421 MHz. When replacing this version with a
DesignWare based multiplier the performance is increased significantly.
The performance and area of the ASIC port is summarized in Table 8.2.
8.8 Conclusions
Optimizing a floating point components for a specific FPGA is an inter-
esting problem with many opportunities to trade area for frequency and
vice versa. It is typically not a problem to create a high performance
floating point multiplier in an FPGA, but a floating point adder is a real
challenge, especially the normalization stage.
By liberal use of instantiated FPGA primitives it was possible to reach
a very high performance, even higher than Xilinx’ floating point adder
with the same pipeline length. The price we pay for the performance is
a higher area which means that our floating point adder is a good choice
when few but fast adders are required. Our adder would probably be a
good choice for a soft microprocessor whereas Xilinx’ adder would be a
good choice when a datapath with high throughput but modest latency
108 Floating point modules
requirement is needed.
The designs will not have very good performance in an ASIC if they
are ported directly without any modifications at all, but the performance
increases dramatically after minor modifications to the design even though
most of the design still consists of many instantiated FPGA primitives.
Part III
On-Chip Networks
109
Chapter 9
On-chip Interconnects
9.1 Buses
A bus is a simple way to connect different parts of a computer at low cost.
This was recognized early on as even the very first computers utilized
buses, such as for example the electromechanical Z3 [59].
The advantages of a bus is clear when looking at Figure 9.1. Instead
of 20 dedicated connections between each of the five components there
is only one shared bus to which all components are connected. This will
significantly reduce the complexity and cost of the system under the as-
sumption that the traffic between the components do not overload the
bus.
One assumption here is that the total number of messages that will
be sent during a certain time period does not exceed the capacity of the
bus during the same time period. In many cases, this will also mean that
messages must be buffered for a while before they can be sent over the
bus.
Traditionally, buses were implemented using three-state drivers to
111
112 On-chip Interconnects
save area but this is very rarely used for on-chip buses any longer due to
the increased verification cost and slow performance of such buses [4].
Instead, on-chip buses can be implemented by using muxes as shown in
Figure 9.2. (Unless otherwise noted, a bus in this thesis refers to a bus
implemented using multiplexers.)
Other things that will indirectly impact the performance is the num-
ber of components connected to the bus. If an on-chip bus is constructed
that has many components connected to it, it will not be able to operate
as fast as a bus with few components due to physical constraints (e.g.
wire delays).
retry the transaction later on when the requested value may be available.
This allows the bus to be used by another bus master while the value
requested by the first bus master is fetched.
A drawback with bus retries is that the bus can be saturated with
retry requests. A common way to avoid this is by using split transac-
tions. The idea is similar to how retried transactions work, but instead of
the bus master retrying the transaction, the slave will automatically send
the requested value back to the bus master using a special kind of bus
transaction.
Besides the techniques outlined above, most buses also have some
sort of error control. This can both be used to signal a link layer error
(e.g parity error or CRC error) or that the current transaction is invalid in
some way (e.g writing to a read only register).
9.1.3 Arbitration
If there is more than one potential bus master connected to a bus it is
important to make sure that only bus master is granted access to the bus
simultaneously. A popular way to solve this is to use an arbiter to which
all bus masters are connected. If a bus master needs to access the bus, it
first requests access to the bus from the arbiter which will grant access to
only bus master at a time. If more than one bus master request access at
the same time, a variety of algorithms can be used based on for example
priorities or fairness.
It is also possible to statically schedule all bus transactions at design
time. This is useful in real time systems where failure to meet a deadline
(because of for example a busy bus) can be catastrophic. The drawback
with static scheduling is that it is hard to analyze and schedule a complex
system with many components and several buses.
Graphics memory
GPIO
Bus bridge
Main memory
Consider for example the hypothetical system shown in Figure 9.3. The
system is divided so that it contains two buses instead of one. One of
the buses connects the graphics unit to the graphics memory and the
other connects the CPU to the main memory and other peripherals. This
includes a bus bridge that allows the CPU to access the graphics unit and
its memory. The idea behind this division is that the CPU rarely needs
to access graphics memory and the graphics unit rarely (or never) needs
to access main memory. In this way, the accesses done by the graphics
processor to show the screen are not noticed by the CPU except when
accessing graphics memory and vice versa.
Crossbar
9.1.5 Crossbars
9.2.2 Deadlocks
CPU
Memory
Master
Port Slave port
1
3
Accelerator 2
Slave Master
Port Port
9.2.3 Livelocks
A livelock situation is similar to a deadlock. If we modify the system
described first in Section 9.2.2 so that a module automatically releases an
allocated resource if it cannot allocate a required resource the following
situation may occur:
• X allocates a, Y allocates b
• X releases a, Y releases b
• X allocates a, Y allocates b
• ...
10.1 Introduction
At the Division of Computer Engineering we have a relatively long his-
tory of NoC research targeted to ASICs. The work described in this chap-
ter is targeted at FPGAs instead while partially building on experiences
gained from the SoCBUS [61] research project.
121
122 Network-on-Chip Architectures for FPGAs
When this case study was initiated, few FPGA based NoC seemed to
exist that really pushed an FPGA to its limits. It therefore made sense to
take a critical look at FPGAs to try to create an optimal match for NoC ar-
chitecture and FPGA architecture. The goal was to optimize fairly simple
architectures with well known behavior. In other words, this case study
focuses on FPGA optimization techniques for NoCs instead of new and
novel NoC architectures.
When the case study was initiated, statically scheduled NoCs were
deliberately excluded from the study as they are quite easy to implement
in an FPGA using for example the architecture in Figure 10.1. NoCs capa-
ble of handling dynamically changing traffic are more interesting except
for specialized applications.
10.2 Buses and Crossbars in an FPGA 123
North input
West input
Local input
South input
Schedule Counter
Memory
In Figure 10.2 a comparison is shown where the area and maximum fre-
quency of a simple crossbar and a simple bus are shown for various num-
ber of ports. A Virtex-4, speedgrade 12 was used in this comparison.
(Note that no modules are connected to this bus so Figure 10.2 shows the
ideal case where the entire FPGA can be dedicated solely to the bus.)
It is no surprise that the maximum operating frequency of the com-
ponents drop as more components are added, both for the bus and the
crossbar. And of course, while not shown in the graph, the area of the
crossbar grows extremely large as the number of ports are increased.
It should be noted that neither the bus, nor the crossbar was pipelined
in this comparison. Faster operation (at the expense of increased area)
could be had by pipelining the bus/crossbar. This example is still valid
for the majority of uses since many buses are not pipelined in practice.
124 Network-on-Chip Architectures for FPGAs
450
Bus
Crossbar
400
350
300
Maximum frequency [MHz]
250
200
150
100
50
0
4 6 8 10 12 14 16 18 20 22 24 26
Number of ports
Figure 10.2: Maximum frequency for a bus and a crossbar with various
number of ports
primitives them self. The numbers are summarized in Table 10.1. (Note
that this include cores synthesized for both speedgrade -10, -11, and -12
Virtex-4 devices.)
• Circuit switched
• Packet switched
Step 1) Step 2)
Node 9 to send a packet to Node 14 Final destination is 14
Final destination is 14
Switch C Switch C
Route B Route
Lookup Lookup B
Node 9
A A
Output port set to A
Output port set to B
Step 3)
Final destination is 14
Switch
Route
Lookup
C B
Node 14
Output port set to B A
(a) A switch performs route lookup for the current output port
Step 1)
Node 9 to send a packet to Node 14 Step 2)
Output port set to B Outpout port set to A
Final destination is 14 Final destination is 14
Switch C Switch C
Route B Route
Lookup Lookup B
Node 9
A A
Next hop set to B
Next hop set to A
Step 3)
Output port set to B
Final destination doesn’t matter
Switch
Route
Lookup
C B
Node 14
possibility for a message to be sent back to the same direction that it came
from. Given this limitation and a maximum of 32 destination nodes, the
route lookup tables can in theory handle any kind of topology with up to
32 destination nodes and any kind of deterministic routing algorithm. In
practice a routing algorithm and topology that is deadlock free, such as
the well known X-Y routing algorithm on a 2D mesh, should be used. (If
the 32 destination nodes turns out to be a limitation it should be easy to
extend this NoC to support more than 32 destination nodes if some sort
of hierarchical addressing scheme is acceptable.)
The most complex part of this switch is the input part, which is shown
in Figure 10.4. The FIFO is based on SRL16 primitives that allows a very
compact 16 entry FIFO to be constructed. As the SRL16 has relatively
slow outputs, a register is placed immediately after the SRL16. This
means that the input part has a latency of two cycles in case the FIFO
is empty and the output port is available.
10.4 Choosing a NoC Configuration 129
Route
DEST[4:0] NEXTROUTE[2:0]
Lookup
ROUTE_NORTH
CHECK
ROUTE_EAST ROUTE_WEST_TO_EAST
EMPTY
ROUTE_SOUTH
CE ADDR CE
ROUTE_WEST_TO_SOUTH
ROUTE_* signals from
Generate
STROBE FIFO the south, east, and
Read
READY ADDRESS north input ports
Enable
Signals from the north,
east, and south arbiter
°2007
c IEEE. Reprinted from Field Programmable Logic and Applications, 2007. FPL 2007.
International Conference on , An FPGA Based Open Source Network-on-Chip Architecture, Ehliar, A. Liu,
D.
Figure 10.4: A detailed view of an input port of the packet switched NoC
switch
The block named “check empty” makes sure that no spurious ROUTE_*
signals are sent to the arbiter if the FIFO is empty. By doing this, the ar-
biter will be simplified as compared to having both the ROUTE_* signals
and separate signals for WEST_EMPTY, NORTH_EMPTY, etc. In partic-
ular, it is easier to identify the case where only one input port needs to
send a packet to the output port and send the packet immediately with-
out any arbitration delay.
The block that generates the read enable signal to the input FIFO has
to consider a large number of signals and it is therefore crucial to imple-
ment that block efficiently and place it so the routing delay is minimized.
Through RLOC directives most of that logic can be placed into one CLB
in order to minimize the routing delay. Finally, the READY signal is ad-
justed for pipeline latency so that the FIFO will not overflow if the sender
does not stop sending as soon as READY goes low.
130 Network-on-Chip Architectures for FPGAs
LASTFLIT_C
LASTFLIT_B
LASTFLIT_A
Arbiter
SEL_C STROBE
SEL_B
SEL_A
A_CHOSEN
B_CHOSEN
C_CHOSEN
DAT_A[45:0]
0
DAT_B[45:0] 1
0
DAT_O[45:0]
DAT_C[45:0] 1
°2007
c IEEE. Reprinted from Field Programmable Logic and Applications, 2007. FPL 2007.
International Conference on , An FPGA Based Open Source Network-on-Chip Architecture, Ehliar, A. Liu,
D.
Figure 10.5: A view of the output part of the packet switched NoC switch
FIFO to the route look-up due to the slow output of the SRL16 elements.
The circuit switched NoC has a similar design to the SoCBUS [61] net-
work on chip architecture. The main difference between the circuit switched
and the packet switched NoC is that there are no FIFOs in the input
nodes. If the output port is occupied, a negative acknowledgment is
instead sent back to the transmitter. In this case the transmitter has to
reissue the connection request at a later time. Correspondingly, an ac-
knowledgment is sent once the packet has reached the destination.
The overall design is similar to packet switched version with the ex-
ception of the input module. In the circuit switched switch there is no
input FIFO as mentioned earlier. The arbiter is also different from the
arbiter in the packet switched version. In particular, it has to arbitrate
immediately if two or more connections arrive simultaneously to one
output port. It does this by using a fixed priority for each input port.
The critical path of the circuit switched switch is the arbiter, which
has to decide immediately if a circuit setup request should be accepted
or rejected.
Resource
utilization
(In Virtex-4)
LUTs 784 1070 633 828 396
Flip flops 448 572 452 595 368
Latency 3 3 2 2 2
(cycles)
The performance and area of the three different NoCs are shown in Ta-
ble 10.3. The resource utilization of individual modules of the NoC switches
can be found in Table 10.4. LUTs that were only used for route-thru are
also included in these numbers. ISE 10.1 was used for synthesis and
place and route. Note that the performance numbers in Table 10.3 is only
for a single switch. The performance of the NoC will also be affected
by the distance between the switches, but this will not be a huge prob-
lem since flip-flops are used on the both the inputs and outputs of the
NoC switches. An experiments on a Virtex-4 SX35 has shown that a NoC
with 12 nodes and 4 switches is not limited by the distance between the
switches even though the switches were placed in different corners of the
FPGA.
The clock frequencies of the packet switched and circuit switched net-
10.5 Wishbone to NoC Bridge 133
Table 10.4: The resource utilization of the individual parts of the switches
works are both high, although there is a relatively large gap to the upper
limit established by the NoC without congestion control. A more efficient
flow control mechanism would certainly be a welcome addition to these
NoCs although inventing such an architecture is probably non-trivial.
Due to the small difference in performance between the circuit switched
and packet switched network the packet switched network is probably
the best fit for Xilinx FPGAs.
Address generator
Wishbone Address
Read request FIFO
CE
Input FIFO
CE
Wishbone data
Route lookup
NoC
Wishbone Address
Wishbone data
°2007
c IEEE. Reprinted from Field Programmable Logic and Applications, 2007. FPL 2007. Inter-
national Conference on , An FPGA Based Open Source Network-on-Chip Architecture, Ehliar, A. Liu,
D.
Figure 10.6: Simplified view of the data flow of the Wishbone to NoC
bridge.
To avoid deadlocks, read requests have lower priority than write re-
quests and read replies. That is, the bridge will immediately service a
write request in the input FIFO. The bridge will also service a read reply
as soon as possible (by waiting for the originator of the read request to
retry the read). On the other hand, if a read request comes in from the
NoC downlink it cannot be serviced until the NoC uplink is available.
This means that read requests has to be queued in a separate queue if
10.6 Related Work 135
the NoC uplink is not available (which will happen if the FIFO in the
NoC switch the bridge is connected to is full). At the moment, the de-
signer has to make sure that the read request queue is large enough to
hold all possible incoming read requests that could be issued to a certain
Wishbone bridge over the NoC.
A big problem with the Wishbone bus in the context of bus bridges is
that the bus has been designed with a combinatorial bus in mind. While
Wishbone does provide a couple of signals for burst handling, the only
length indication for a linear burst is the fact that at least one more word
is requested. To mitigate this, the bridge has an input signal that is used
for reads to indicate the number of words to read, but this is no longer
strictly Wishbone compliant.
Another area where the bridge is not fully Wishbone compatible is the
error handling. It would be relatively easy to add support for the ERR
signal to read requests/replies. Unfortunately, writes cannot be imple-
mented using posted write requests if the ERR signal in Wishbone should
be handled correctly. The easiest way to add error handling would be to
add a status register that can be read by a master processor so that such
errors can be detected by the operating system.
In our opinion, the complexity of the bridge is not a good sign. An
interesting future research topic would be how to design a simple bus
protocol which can both serve a bus at high performance while at the
same time being easy to connect to a NoC.
10.7 Availability
The source code for the packet switched NoC can be downloaded at
http://www.da.isy.liu.se/research/soc/fpganoc/. The Wish-
bone to NoC bridge is also available for download. Hopefully this will
allow NoC researchers interested in FPGAs to easily compare their NoC
against another NoC with good performance in an FPGA.
It is interesting that the critical path is still in the read enable signal
to the FIFOs in the input ports even in the ASIC version of the packet
switched switch. However, as can be seen in the table there is little pos-
sibility to improve the ASIC timing by trading area for frequency. This is
not surprising as the switch consists mostly of muxes and flip-flops and
there is little the synthesizer can do about these.
The difference between the packet switched NoC switch and circuit
switched NoC switch is substantial in the ASIC port. This is because
the packet switched switch is using many SRL16 primitives. While this
primitive is very cost effective in an FPGA as it allows a LUT to be used
as a 16 bit shift register, it is likely to be expensive to port this to an ASIC.
In fact, since a circuit switched NoC is so much cheaper it is actually
possible to use a much more complex network with more nodes in it
if circuit switching is used instead of packet switching. Doubling the
number of switches in the network is not a problem area wise. In fact, it
is possible to both double the number of switches and the width of the
links and still use less area than the packet switched network in an ASIC
138 Network-on-Chip Architectures for FPGAs
10.9 Conclusions
It is possible to create high speed NoC switches on a Xilinx FPGA that
are both fast and relatively small. By manually instantiating FPGA prim-
itives it is possible to achieve the level of control which is needed to reach
the highest performance. Floorplanning is not a requirement to reach this
performance, but investigating the output from the placer was necessary
to understand how the design could be further optimized at many times
during the development.
In our experience, circuit switched and packet switched NoCs will
have roughly the same operating frequency and area in Xilinx devices
and the developer is therefore free to chose which to use depending on
his or her needs. However, if the design might eventually be ported to an
ASIC, the packet switched NoC will be much more expensive in terms
of area than the circuit switched NoC. In fact, in terms of area, a packet
10.9 Conclusions 139
141
Chapter 11
FPGA Backend Tools
11.1 Introduction
XDL is a file format which contains a text version of Xilinx’ proprietary
NCD file format. (The NCD file format is used for netlists created by
both the mapper and the place and route tool.) The xdl command can
be used to convert between XDL and NCD. The XDL file format is no
longer documented by Xilinx, but earlier version of ISE contained some
information about it [73].
Due to the simplicity of the file format it is quite easy to parse it in a
custom program or script. Unfortunately it is difficult to understand the
part which deals with routing as those parts require knowledge about
the FPGA which is difficult to obtain.
It is also possible to modify a netlist in XDL format to include or
143
144 FPGA Backend Tools
11.3 PyXDL
PyXDL is a library designed by us for reading and writing XDL files.
While somewhat limited at the moment, it has three demonstration pro-
grams:
• Design viewer
Synthesizer (xst)
NGC
ngdbuild
NGD
map
par
NCD (Routed)
Constraints (PCF)
PyXDL design merger
xdl
NCD (Partially
routed)
par
NCD (Routed)
°2007
c FPGAWorld.com. Reprinted from 4th annual FPGAworld Conference, Thinking outside the flow:
Creating customized backend tools for Xilinx based designs, Ehliar, A. Liu, D.
Figure 11.1: Typical design flow when utilizing the XDL file format
146 FPGA Backend Tools
147
Chapter 12
Conclusions
149
150 Conclusions
The next case study studied floating point adders and multipliers and
showed how these can be optimized for the Virtex-4. By parallelizing the
normalizer we could achieve a clock frequency of 370 MHz in the float-
ing point adder with a latency of 8 clock cycles for a complete addition.
This is faster than previous publications at the same latency in terms of
clock cycles but this speed comes at a price of higher area than previous
publications as well. Our floating point units should be a good match for
situations where low latency is important
The final case study discusses how NoC architectures can be opti-
mized for FPGAs. We find that a circuit switched network will be smaller
than a packet switched network, but the difference is relatively small on
Xilinx FPGAs when using the SRL16 primitive. This means that a packet
switched network is very attractive to use in an FPGA.
As with most other research projects, the designs described in this thesis
can not yet claim that they are finished. There are many interesting pos-
sibilities for future research here and the most important of these will be
described in this chapter.
151
152 Future Work
Finally, there are some more minor details that could be added to
the processor without too much difficulty. Interrupts could be added
fairly easily if it is acceptable that a few clock cycles are spent to make
sure that the pipeline is not executing a delayed jump. If some sort of
improved branch prediction is used, it may be possible to avoid the use
of delay slots. Automatic stalling of the processor due to hazards would
also be a nice addition and could probably be implemented using extra
bits in the instruction word (these bits may only have to be present in the
instruction cache and not in main memory).
While the floating point adder and multiplier are probably the most pol-
ished projects described in this thesis there is still much that could be
done in this research area. The most obvious improvement is to make
the units more flexible by allowing parameters to be used to specify man-
tissa width and exponent width. This is not so interesting from a research
perspective but very important from a practical perspective.
13.3 Network-on-Chip
The NoC research area is still far from mature so there is obviously much
to do here. In the implementation described in this thesis, the most im-
portant improvement is probably to improve the bus bridge by for ex-
ample reducing the area and allowing different clocks to be used on the
NoC and on the Wishbone bus.
Another interesting area is NoC friendly bus protocols as many of
todays bus protocols are not very suitable when a pipelined NoC (or bus
for that matter) is used.
Finally, adding some support for quality of service would be a nice
addition to this NoC although it is not clear if this can be done without
huge area penalties.
only small changes to the designs, more work is required in this area, es-
pecially to determine how the power consumption depends on the FPGA
optimization. If structured ASICs increase in popularity it would also be
interesting to determine the impact of FPGA optimizations when porting
an FPGA design to a structured ASIC.
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• Adders with more than two inputs are typically more area efficient
in ASICs than in FPGAs. (See Section 5.5)
• While multiplexers are very costly in an FPGA, they are quite cheap
in an ASIC. Optimizing the mux structure in the FPGA based de-
sign will have little impact on an ASIC port. (See Section 5.6)
163
technology. (See Section 5.9)
• If many small register file memories with only one write port and
few read-ports are used in a design, the area cost for an ASIC port
will be relatively high compared to the area cost of the FPGA ver-
sion. On the other hand, if more than one write port is required,
the ASIC port will probably be much more area efficient. (See Sec-
tion 5.9.2)
164
• While pipelining an FPGA design will certainly not hurt the max-
imum frequency of an ASIC, the area of the ASIC will often be
slightly larger than necessary, especially if the pipeline is not a part
of the critical path in the ASIC. Designs that contains huge number
of delay registers will be especially vulnerable to such area ineffi-
ciency. (See Section 5.12)
165
166
Part VI
Papers
167
Paper I
Paper I
Portions reprinted, with permission, from International Workshop on Multimedia Signal Processing,
2004. Using low precision floating point numbers to reduce memory cost for MP3 decoding, Eilert, J. Ehliar, A.
Liu, D. (°2004
c IEEE)
This paper has been reformatted from double column to single column format for ease of readability.
169
Abstract
The purpose of our work has been to evaluate if it is practical to use a 16-
bit floating point representation to store the intermediate sample values
and other data in memory during the decoding of MP3 bit streams. A
floating point number representation offers a better trade-off between
dynamic range and precision than a fixed point representation for a given
word length. Using a floating point representation means that smaller
memories can be used which leads to smaller chip area and lower power
consumption without reducing sound quality. We have designed and
implemented a DSP processor based on 16-bit floating point intermediate
storage. The DSP processor is capable of decoding all MP3 bit streams at
20 MHz and this has been demonstrated on an FPGA prototype.
1 Introduction
MPEG-1 layer III [1], commonly referred to as MP3, is well understood,
both on desktop systems and in embedded systems. Decoders for desk-
top systems can be implemented using either fixed point or floating point
arithmetic, whereas embedded systems typically use fixed point arith-
metic.
Embedded MP3 decoders usually have to use two 16-bit memory
words for each intermediate value to achieve the required dynamic range
and precision with fixed point arithmetic. We have investigated the feasi-
bility of using a 16-bit floating point representation to reduce the memory
cost without sacrificing sound quality. This would halve the data mem-
ory usage which would have a significant impact on power consump-
tion and chip area. Another advantage with floating point arithmetic is
that the hardware eliminates all scaling operations associated with fixed
point arithmetic which leads to shorter firmware development time.
One drawback of floating point is the complexity of the arithmetic
units. However, for a given dynamic range, the multiplier in a floating
point data path is smaller than the corresponding multiplier in a fixed
170
point data path.
In order to evaluate our floating point approach, we have used the
MPEG audio compliance test [3]. In short, a decoder can be classified as
full precision, limited accuracy, or not compliant depending on the difference
between the provided reference output and the decoded output. We have
also conducted informal listening tests since there are no formal criteria
for evaluating the quality of an MP3 decoder for an arbitrary bit stream.
171
streams could be decoded without having to saturate any intermediate
value. We did not consider hand-crafted bit streams with extreme values
but we tested more than 200 different music and speech bit streams.
In order to simplify the hardware, we used the same bias for register
values, but we had to increase the exponent to 6 bits to accommodate
larger intermediate values. The register number range is 2−42 to 221 . The
larger exponent of the registers simplified software development.
The compliance level for different sizes of the mantissa was investi-
gated and the result is given in Fig. 1. The exponent sizes used was 6 and
5 in registers and memory respectively.
172
Compliance results for different mantissa sizes
19
Memory mantissa size (Implicit leading "1." not included)
18
17
16
15
14
13
12
11
10
6 7 8 9 10 11 12 13 14 15 16 17 18 19
Register mantissa size (Implicit leading "1." not included)
2.2 Operations
An analysis of the ISO MP3 decoder shows that the following floating
point operations should be supported in hardware to implement an effi-
cient MP3 decoder.
• Add
• Subtract
• Multiply
173
These operations can be mapped to a floating point adder and a float-
ing point multiplier. All remaining operations can be reduced to these
primitives or implemented as table look-ups. Because the memory and
registers have different word lengths it is necessary to convert between
different floating point formats. The round operation converts from the
register word length to the memory word length, and the floating point
load operation expands a memory word to a register word.
3 Hardware Implementation
Each general purpose register can contain a 16-bit integer or a 23-bit float-
ing point value. In the former case, the upper 7 bits are unused. When
a floating point value is loaded from memory it is expanded from 16 to
23 bits. Before storing a floating point value it is rounded to 16 bits. The
data types are summarized in Fig. 2.
The most important reason for using these values is to avoid a config-
uration where the decoder barely meets the requirements for limited ac-
curacy. Another reason is the convenience of having a 16-bit wide mem-
ory.
174
Register integer data type:
bit: 22 21 . . . 16 15 ... 0
sign exponent mantissa
(signed) (unsigned)
bit: 15 14 . . . 10 9 ... 0
sign exponent mantissa
(signed) (unsigned)
The instruction set basically consisted of load and store from any of the
general purpose registers, register to register integer and floating point
operations, and I/O operations.
There are 16 general purpose registers. This number was decided
175
upon after studying the algorithms used in MP3 decoding. It allowed
us to keep all intermediate values in registers for the most important
algorithms.
There is a hardware stack for saving the program counter during sub-
routine calls. Conditional branches are limited to branch-if-zero, and
branch-if-not-zero.
There are a few application specific instructions. The Huffman de-
coder part is accelerated by bit access instructions, and some signal pro-
cessing parts are accelerated with a MAC (multiply-and-accumulate) in-
struction. The address generation capabilities are in most cases limited to
absolute or register indirect, but the bit access instructions and the float-
ing point MAC instruction can use the single dedicated address register
with auto-increment and modulo addressing.
The integer pipeline has five pipeline stages, and the floating point
pipeline has eight stages. The pipelines share fetch, decode, and write-
back stages. In hindsight, the pipeline could have been shorter.
RTL code for the DSP was written in VHDL and tested on an FPGA
prototype board. The estimated gate count, excluding memories, is 32500 gates
when synthesized for Leonardo Spectrum’s sample SCL05u technology.
There is room for improvement in the RTL code, especially in the instruc-
tion decoder.
4 Software Implementation
176
4.1 Algorithms
In order to achieve high performance with a deep pipeline and a limited
instruction set, algorithms had to be carefully written. Since the integer
part of a register is used as the mantissa in a floating point value, some
operations can be accelerated by manipulating the mantissa directly. For
example, integer shift and integer to floating point conversion can be
implemented by using the floating point subtract instruction.
The Huffman decoder uses a simple, one bit at a time, tree traversal
technique. This approach is memory inefficient but reasonably fast since
each tree node is one instruction.
The x4/3 calculation in the sample dequantization can be implemented
with a large look-up table with more than 8000 entries. We used a fifth
order polynomial approximation for the mantissa and a table look-up for
the exponent. Finally, a look-up table was used for small values in the
range [−15, 15] to accelerate this common case.
The 36-point inverse modified DCT, IMDCT, was implemented using
a fast IMDCT algorithm [4] and the 12-point IMDCT was implemented
using 36 floating point multiply and accumulate instructions.
The 32-point DCT used in the subband synthesis part was imple-
mented using Lee’s fast DCT algorithm [5]. With careful scheduling, the
16-point kernel could be implemented in registers only, without loading
or storing temporary values to memory.
4.2 Quality
According to the MP3 compliance test, our decoder is classified as a lim-
ited accuracy MPEG-1 Layer III decoder. The rms of the difference be-
tween our decoded output and the reference provided with the compli-
ance test is 3.2 · 10−5 which is well below the limit for limited accuracy,
1.4 · 10−4 .
Even though our decoder is not a full precision layer III decoder, in-
formal listening tests could not discern files decoded with our decoder
from files decoded with the full precision ISO MP3 decoder.
177
Typical execution profile
Bitstream parsing
Read samples
Restore samples
Calculate stereo
Reorder samples
Aliasing reduction
IMDCT
Frequency inversion
DCT
Windowing
Output PCM Floating point instructions
Misc Floating point MAC
Huffman instructions
Integer, control flow, I/O, etc
0 0.5 1 1.5 2 2.5 3 3.5 4
MIPS
Bitstream parsing
Read samples
Restore samples
Calculate stereo
Reorder samples
Aliasing reduction
IMDCT
Frequency inversion
DCT
Windowing
Output PCM Floating point instructions
Floating point MAC
Misc
Huffman instructions
Integer, control flow, I/O, etc
0 0.5 1 1.5 2 2.5 3 3.5 4
MIPS
Figure 4: Profiling of the decoder while decoding the worst case MP3 bit
stream. (19.6 MIPS in total.)
The final version of the decoder used approximately 6800 24-bit words
for program memory, 900 23-bit words for the constant memory, and
6100 16-bit words for data memory. We have not spent any time try-
ing to reduce the program memory size. More than 40% of the program
178
memory is used for the Huffman tables.
4.4 Performance
In order to measure the performance of the decoder on a typical MP3 bit
stream we used a 44.1 kHz music bit stream, with an average bit rate of
202 kbps. A profile of the decoder is shown in Fig. 3.
The time spent in the Huffman decoding and sample dequantization
is data dependent. A bit stream was constructed to trigger worst case
execution time in the data dependent parts. In our case, this consisted of
a 48 kHz bit stream using only short blocks and joint-stereo. By selecting
the right Huffman table, a maximum number of big values could be fitted
into a frame to stress the sample dequantization. The resulting worst
case execution path requires 19.6 MIPS to sustain a real time decoding
process. The worst case profile is shown in Fig. 4
5 Future Work
The focus of this work has so far been on the effects of using floating
point arithmetic. Therefore, we have not put very much effort in opti-
mizing the instruction set beyond what is needed to support the required
floating point operations. Future improvements could include hardware
assisted loops, and better address generation such as general support for
pointer auto-increment. It would be relatively easy to implement a sim-
ple Huffman accelerator unit that would both significantly reduce the
size of the Huffman tables as well as speed up the Huffman decoder.
We investigated the word lengths required for full precision, but only
in the ISO MP3 decoder, as shown in Fig. 1. It would be interesting to
verify that full precision can be achieved also in our MP3 decoder by
increasing the width of the floating point data types.
Finally, it would be very interesting to know if anything could be
gained by implementing an MP3 encoder or other audio coding stan-
dards such as Ogg Vorbis and AAC using a similar floating point scheme.
179
Program memory 6800 words (24-bit)
Data memory 6100 words (16-bit)
Constant memory 900 words (23-bit)
Clock frequency 20 MHz
Gate count 32500
MIPS cost (worst case) 19.6 MIPS
MIPS cost (typical) 14.6 MIPS
Compliance Limited accuracy
(rms is 3.2 · 10−5 )
6 Conclusions
Our MP3 decoder stores intermediate data in a 16-bit floating point for-
mat to limit memory usage. It is classified as a limited accuracy ISO/IEC
11172-3 MPEG-1 layer III decoder.
The hardware has been implemented in VHDL and it has been tested
on an FPGA prototype board. The gate count, excluding memories, is
32500 gates when synthesized for Leonardo Spectrum’s sample SCL05u
technology. A clock frequency of 20 MHz is enough to decode all bit
streams.
The performance of the decoder is summarized in Fig. 5. We see some
possible improvements that could reduce the program memory size and
increase the performance.
180
[3] ISO/IEC, “Information Technology — Coding of Moving Pictures
and Associated Audio for Digital Storage Media at up to About
1.5Mbit/s, Part 4: Compliance Testing,” 1995
[5] Lee, B., “A new algorithm to compute the discrete cosine Transform,”
IEEE Transactions on Acoustics, Speech, and Signal Processing, Vol. 32,
Iss. 6, Dec 1984
181
182
Paper II
Paper II
Portions reprinted, with permission, from Field Programmable Logic and Applications, 2007. FPL 2007.
International Conference on , An FPGA Based Open Source Network-on-Chip Architecture, Ehliar, A. Liu,
D. (°2007
c IEEE)
This paper has been reformatted from double column to single column format for ease of readability.
183
Abstract
Networks on Chip (NoC) has long been seen as a potential solution to the
problems encountered when implementing large digital hardware de-
signs. In this paper we describe an open source FPGA based NoC archi-
tecture with low area overhead, high throughput and low latency com-
pared to other published works. The architecture has been optimized
for Xilinx FPGAs and the NoC is capable of operating at a frequency
of 260 MHz in a Virtex-4 FPGA. We have also developed a bridge so that
generic Wishbone bus compatible IP blocks can be connected to the NoC.
1 Introduction
As chip manufacturing techniques continue to improve, more complex
maksystems are being designed. Designing such a large system is not
easily done however and much research from both academia and indus-
try is focused on this problem. One of the problems encountered is how
to handle the on-chip interconnections between different modules.
One promising solution to the on-chip interconnection problem is the
Networks on Chip (NoC) paradigm which has seen a lot of research
lately. A thorough review of the concepts involved in NoCs is outside
the scope of this article and we refer readers unfamiliar with the topic
to [1].
Most publications in this research area are targeting ASICs however
with only a few publications considering the problems and opportunities
of an FPGA based NoC. However, as entry level FPGAs are increasing in
size, interest in NoCs for FPGAs will also increase in both academia and
industry.
In this paper we present an open source NoC architecture. The ar-
chitecture, which is optimized for the Virtex-4 FPGA family is based
on packet switching with wormhole routing. In addition, we have also
developed a bridge which allows Wishbone compatible components to
communicate over the NoC.
184
2 Background
Networks-on-chip has been a popular research area for some time now.
An early paper that discusses the advantages of an ASIC based NoC
is [2] when compared to more traditional approaches. Other well known
ASIC based NoC research projects include the Æthereal project [3] and
the xpipes project [4].
185
Table 1: A list of the data and control signals that exist in a link between
two NoC switches.
Name and Width Description
direction
Strobe → 1 Valid data is present
Data → 36 Used as data signals
Last → 1 Last data in a transaction
Dest → 5 Address of destination node
Route → 3-4 Destination port on
the switch (one hot coded)
Ready ← 1 Signals that the remote node
is ready to receive data
The authors’ experience from SoCBUS [11] also indicates that the large
latency involved in transmitting small messages can be a huge problem
in a real system. Since it is critical to be able to handle small messages in
a system where a a standard bus is connected to a NoC, the architecture
presented in this paper is based upon packet switching. Wormhole rout-
ing is used to avoid the need for large packet buffers and to reduce the
latency.
We have mostly used 2D meshes during simulation and hardware de-
velopment although almost any topology is possible, as long as a dead-
lock free routing algorithm is used. (A discussion on deadlock free rout-
ing algorithms is outside the scope of this paper, the interested reader is
referred to for example [1].)
The signaling used on the NoC is shown in Table 1.
186
sender that no further data should be sent as soon as only a few entries
are left. This is required because the pipeline latency will cause addi-
tional entries to be written before the sender can react.
This FIFO is efficiently implemented by using the SRL16 components
of the Virtex-4. Due to the high delay in the SRL16 outputs, it is necessary
to minimize the logic between the output of the SRL16 and the following
flip-flop. Therefore, only a simple routing decision is performed in this
stage. Since our current architecture supports 32 destination nodes, one
five-input look-up table per output port is enough to make a routing
decision. Unfortunately this does not take into account that the FIFO
might be empty and contain stale destination data. In order to handle
this situation, the route look-up also has to know whether the input FIFO
is empty or not. Adding this logic increased the critical path beyond
what was deemed acceptable. Therefore, in order to shorten the critical
path of the route look-up, the NoC architecture was modified so that a
route look-up is instead performed in the previous switch. The result of
a route look-up is then sent using one hot coding to the next switch.
The other critical path of the input signal is the read enable signal
of the input FIFO. In order to keep the latency down, the read enable
signal is generated by looking at the destination port of all other input
ports. If no other input port is trying to communicate with the selected
output port and the output port is ready to send, the packet will be sent
immediately.
Once the first part of a packet is available in the input FIFO, the arbiter of
the selected output port will be notified. If the port is already busy or if
several input ports are trying to send at once, the arbiter uses round robin
arbitration to choose the next packet to be sent once the current sender is
finished. The arbitration is therefore distributed between the input port
where the read enable signal has to be generated without waiting a clock
cycle on the arbiter. If the output port is available and no other input
187
port is trying to send to this port, the arbitrator will allocate the output
port for the duration of the incoming packet.
Beside the arbiters, only one mux for each output port is needed. A
small logic depth optimization that has been done is to move a small
portion of the arbiter into the output mux. This can be done because a
4-to-1 mux only uses three of the available inputs on the two LUTs that
are required to implement such a mux. It should be noted that the output
mux is not connected to all input ports since messages are not supposed
to be routed back to the same port it arrived on.
4 Wishbone bridge
188
Table 2: The protocol used by the Wishbone bridge. A Write request
packet can contain up to N words, a read request packet will always
contain 2 words, and a read reply can contain up to M words. (M ≤ 31).
Request Word Bits Value
type
Write 0 35:34 “00” (Write request)
0 29:0 Address (in 32 bit words)
1..N 35:32 Byte select signals
1..N 31:00 Data
Read 0 35:34 “01” (Read request)
0 29:0 Address (in 32 bit words)
1 34:30 Number of requested words
1 29:26 Byte selects for non
burst read
1 25:21 Source node address
1 20:18 Request ID
Read 1..M 35 “1” (Read reply)
Reply 1..M 34:32 The request ID of this
read request
1..M 31:0 Data
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Address generator
Wishbone Address
Read request FIFO
CE
Input FIFO
CE
Wishbone data
Route lookup
NoC
Wishbone Address
Wishbone data
a given system.
4.2 Limitations
One problem in the Wishbone standard is that it is designed with a com-
binatorial bus in mind. If the bus is pipelined, it is no longer possible
to utilize Wishbone to its full potential. Wishbone provides signals for
handling burst reads but the only length indication which is provided
for a linear burst is the fact that at least one more word is requested. This
causes problems if many pipeline stages separate the slave and the mas-
ter. We have augmented the Wishbone interface with a transaction length
signal so that a read reply will contain exactly the number of words that
have been requested.
The current version of the Wishbone bridge also assumes that a slave
190
will not answer a Wishbone request with a retry or an error. Handling
these signals in a fully Wishbone compliant way would severely reduce
the performance of the NoC. As a future extension some sort of error
reporting register should be introduced to the bridge.
Also, while the bridge does not handle retries itself, it will issue a
retry to a wishbone slave if a wishbone read request is received when the
answer to a previous read request has not yet arrived. It will also issue a
retry if a wishbone write request is received when the NoC is unable to
receive further messages due to a full FIFO. The Wishbone master must
honor this request and release the bus for at least one clock cycle if any
other device is connected to the same Wishbone bus in order to avoid
deadlocks.
4.3 Testing
Both the Wishbone wrappers and the NoC architecture has been tested
in RTL simulations in different NoC configurations (different number of
nodes and switches). The largest design we have tested contains 16 NoC
switches, 32 wishbone/NoC bridges, 96 memories, and 96 transaction
generators. The NoC have also been tested on a Virtex-4 SX35 based
FPGA where we tested a four node NoC with 12 Wishbone bridges con-
nected to memories and transaction generators.
5 Results
The resource utilization of our design is shown in Table 3 and compared
with three other publications1 .
When compared to the packet switched architecture in [6], our archi-
tecture can operate at the same frequency in the same FPGA technology
whereas our switch only uses 30% of the slices (in fairness, the authors
1 Errata: A mistake was made when preparing this table. For the 4 port switch, the
number of LUTs also include the number of LUTs used as SRL16 but we forgot to take
the number of SRL16 into account for the five port switch. The 230 LUTs used as SRL16
components are missing in the figure used for the five port switch.
191
Data Virtex-II Virtex-II Virtex-4 Latency Slices LUTs Flip
width 6000-4 Pro 30-7 LX80-12 (cycles) Flops
Our 4 port switch 36 bits 166 MHz 257 MHz 272 MHz 3 431 780 452
Our 5 port switch 36 bits 151 MHz 244 MHz 260 MHz 3 659 826 615
[6] (4 ports) 32 bits 166 MHz - - 6 1464 - -
PNoC [7] (4 ports) 32 bits - 138 MHz - - 364 - -
NoCem [8] † 32 bits - 150 MHz - - - 1455‡ -
† The number of ports for this value is not stated in the paper. ‡ Not explicitly mentioned
in the paper, calculated from the size of a 2×2 NoC.
hint that their NoC could be faster but they do not give a maximum num-
ber). When compared to [7], the system is capable of operating at a sig-
nificantly higher frequency while being only slightly larger (in addition
to serving slightly wider links). The authors also do not mention how
deadlocks are avoided or handled in their design. The latency of their
NoC is also unknown.
Our NoC can also operate at a higher clock frequency than NoCem [8]
with less resource usage. However the resource usage comparison is
not completely fair since NoCem is capable of handling virtual channels
(although [8] do not mention if the reported LUT resource usage is with
or without virtual channels).
Finally, the size of the Wishbone bridge depends on the routing table
and the size of the read request FIFO, but a typical bridge with a simple
routing table and a 32-entry read request FIFO will use 450 LUTs and 429
Flip Flops.
6 Future work
Since we will release this work as open source, it is our hope that this
research project can both be a platform upon which further FPGA based
NoC research can take place.
The NoC architecture is available for use under the MIT license at
http://www.da.isy.liu.se/research/soc/fpganoc/
192
7 Conclusion
In this paper we have presented an open source Network-on-Chip ar-
chitecture optimized for the Virtex-4 FPGA. The network can operate at
over 260 MHz and the area for a NoC switch is significantly smaller than
for previous results at the same operating frequency. We have also pre-
sented a bridge which allows Wishbone compatible components to be
connected to this NoC.
References
[1] W.J. Dally and B. Towles. Principles and Practices of Interconnection
Networks. Morgan Kaufmann, 2004.
[2] William J. Dally and Brian Towles. Route packets, not wires: On-
chip interconnection networks. In Design Automation Conference,
pages 684–689, 2001.
193
[7] C. Hilton and B. Nelson. Pnoc: a flexible circuit-switched noc
for fpga-based systems. Computers and Digital Techniques, IEE
Proceedings-, 153, 2006.
[11] D. Wiklund and D. Liu. Socbus: switched network on chip for hard
real time embedded systems. Parallel and Distributed Processing Sym-
posium. Proceedings. International, 2003.
194
Paper III
Paper III
Thinking outside the flow:
Creating customized backend
tools for Xilinx based designs
°2007
c FPGAWorld.com. Reprinted from 4th annual FPGAworld Conference, Thinking outside the flow:
Creating customized backend tools for Xilinx based designs, Ehliar, A. Liu, D.
This paper has been reformatted from double column to single column format for ease of readability.
195
Abstract
This paper is intended to serve as an introduction to how to build a cus-
tomized backend tool for a Xilinx based design flow. A Python based li-
brary called PyXDL is presented which allows a user to manipulate XDL
files which contain a placed and routed design. Three different tools are
presented which uses this library, ranging from a simple resource uti-
lization viewer to a tool which will insert a logic analyzer into an already
routed design, thus avoiding a costly complete rerun of the place and
route tool.
1 Introduction
Traditionally, users are not very interested in the inner workings of the
FPGA tool chain they are using. As long as everything is working cor-
rectly there is no perceived need to invest time and effort on learning
about obscure implementation details. Although most users have prob-
ably looked at a routed design in for example Xilinx’ FPGA editor rela-
tively few users have modified such a design.
There are however large opportunities for those who are interested
in inspecting and modifying placed and routed designs. For example, a
design viewer could be constructed that not only shows the slices of the
design, like the floorplanner does, but also figures out the functionality
of a slice and shows a symbol for a mux, adder, inverter, and so on. This
will allow a user to quickly see if the synthesizer has created reasonable
logic without having to load the FPGA editor which usually shows much
more detail than necessary.
In terms of modifying a placed and routed design, most users are
probably interested in tools that are helpful for debugging a design such
as instrumenting a design to improve the visibility of internal signals.
The FPGA editor has included functionality to insert probes into a de-
sign and route those signals to external pins for a long time and the
ChipScope [1] product has improved on this functionality by allowing
196
the user to insert a full logic analyzer into the FPGA.
Finally, when the usage of partial reconfiguration of FPGAs is more
widespread it is likely that already placed and routed designs will have
to be modified before deployment.
This paper presents a simple way to write useful programs capable
of inspecting and modifying placed and routed Xilinx designs. The used
method is to use the xdl tool to translate Xilinx proprietary NCD (Native
Circuit Description) files into XDL (Xilinx Design Language) text files
which can easily be processed by an application. A Python library called
PyXDL has been developed to analyze and modify XDL files and three
different backend tools written in Python has been written to demon-
strate the capabilities of this library. The first tool can take a design and
report the resource utilization of individual modules in the design. The
second tool is a design viewer capable of showing the type of logic in
each LUT as described above. The final tool allows a logic analyzer core
to be inserted into an already routed design and present a user interface
over RS232.
While it might seem esoteric and cumbersome to write your own
backend tool the main parts of the Python library and tools described
in this paper were actually written over a period of less than two weeks
(except for the logic analyzer core which was already written for another
project where it had to be manually instantiated in the RTL source code).
It is therefore feasible for even smaller developers to write their own cus-
tomized tools and we hope that this paper might serve as an inspiration
for like-minded developers.
2 Related work
As previously mentioned, the FPGA editor included in ISE can show a
design in more detail than most users care for. It is also possible to change
the design although this is probably impractical for larger changes. There
is also a command line version of the FPGA editor available called fpga_edline
which is capable of executing scripts created by the FPGA editor.
197
Unfortunately there is no documented way to control the FPGA edi-
tor from a user written program. The included scripting support is just a
way to repeat previously defined commands, the script language is not
a complete programming language. This makes it unsuitable for an ap-
plication that needs to read data from a design as opposed to making
changes to a design at fixed locations.
A much more interesting alternative is the JBits SDK [2] from Xilinx.
This allows Xilinx designs to be manipulated from Java. In fact, it proba-
bly contains all the functionality that a user could want in terms of design
manipulation. It isn’t publicly available and users have to ask for access
to it. The main drawback is that JBits has been discontinued and there is
no support at all for newer FPGAs in it (newer than Virtex-II) and there
seems to be little interest from Xilinx to add such support. In fact, if JBits
was publicly available with support for all new FPGAs from Xilinx, there
wouldn’t have been any need to write this paper.
Finally, abits [3] is a tool similar in spirit to JBits which allows Atmel
bit streams to be manipulated.
198
net "simple_net" ,
outpin "slice1" XQ ,
inpin "slice2" BX ,
;
Figure 1: An example of a simple XDL file which shows two slices each
containing one flip flop connected by a wire.
mat is included in every XDL output file created by the xdl tool unless
the -noformat switch is given.
199
thesize, placement, and routing iteration. This is accomplished by telling
par (the place and routing tool) to only route un-routed nets and only
place unplaced instances. (The guide-file feature of par is used for this
purpose.) This flow is illustrated in Figure 2.
4.1 Constraints
One problem which occurs when merging two designs, which isn’t im-
mediately obviously when looking at the XDL files, is the constraints
files. The timing constraints in these must also be merged if reliable tim-
ing estimates is expected.
The design resource analyzer is a small tool written for a designer who
wants to know the resource utilization of a certain module or modules in
larger design. One way to figure this out is to synthesize that particular
module separately. This method may or may not work depending on the
properties of the larger design. For example, if the synthesizer can deter-
mine that only relatively few values can appear on a certain input port of
a module included in a larger design, the synthesizer could potentially
remove large parts of the module.
As hinted at in the previous section it would be better to be able to
analyze a large design directly to find the resource usage of individual
components. This is exactly what the resource analyzer script does as
shown in Figure 3. The script itself is very simple and the most complex
part is actually printing the design usage in a hierarchical and cumula-
tive fashion. This kind of XDL parsing, although easy, can still lead to
useful results. A regression test incorporating this script could for exam-
ple warn about a submodule which has grown (or shrinked) by a large
factor when compared to the previous run.
200
Source code Constraints
Synthesizer (xst)
NGC
ngdbuild
NGD
map
par
NCD (Routed)
Constraints (PCF)
PyXDL design merger
xdl
NCD (Partially
routed)
par
NCD (Routed)
Figure 2: The typical Xilinx flow augmented with the PyXDL tool to
merge a design such as a logic analyzer into a placed and routed design.
The new part of the flow is shown in gray.
201
Figure 3: Using the resource analyzer script to view the resource utiliza-
tion of various parts of a design.
The design viewer is capable of viewing a design and showing the con-
figuration of the slices. It is similar in functionality to the floorplanner.
In Figure 4 a part of an OpenRisc based design is analyzed by the design
viewer.
Putting a logic analyzers into a chip is not a new idea. Both Xilinx and
Altera already offers such products (ChipScope and SignalTap). There
are also some logic analyzers written by hobbyists available on the net
such as Fpgadbg [5].
The main idea behind this section is to show that it is easy for any
user to duplicate the main selling point of ChipScope, i.e. the capability
to insert a core into an already synthesized and routed design. While it
would be easy to create a logic analyzer core which fully mimics Chip-
Scope by connecting to the internal boundary scan primitive we did not
intend this tool to be a ChipScope clone. Instead, the intention was that
202
Figure 4: An example of the output from the design viewer when run on
a OpenRisc 1200 based design.
this tool should be useful in systems that might not easily be connected
to a PC with a ChipScope client such as remote systems. Therefore the
logic analyzer core is operated via a simple serial port interface.
An example of the output of the logic analyzer is shown in Figure 6
203
and an example of a simple GUI which allows the core to be easily in-
serted into a design is shown in Figure 7.
Implementation details
204
RS232 clk Signals to monitor
UART
Memory
8 bit MCU
Trig mask
&
Wishbone bus
5 Discussion
The applications presented in this paper shows only a few of the many
possibilities that could be tapped by a creative designer. The applications
described earlier could of course be improved by improving them. The
design viewer could be improved to show more points of interest to a
designer such as clock domain crossings, pipeline depths, and perhaps
even show some sort of design complexity metrics for different parts of
the design (a long pipeline without feedback is far less complicated and
probably easier to test and verify than a state machine with many feed-
205
back paths).
The logic analyzer could be improved by adding additional modules
to it such as counter modules for statistic gathering. Another interesting
addition would be to replace the RS232 interface with another interface
such as for example Ethernet or USB.
There are unfortunately some issues that are hard to solve in a satis-
factory fashion. The main problem is that there is very little informa-
tion available about routing. Whereas placement is relatively straight-
forward, reliably routing a design requires detailed timing information
about the internals of the FPGA, something which Xilinx hasn’t released
for modern FPGAs and most likely will not release for the foreseeable
future.
Another problem that any tool of this kind will face is that the syn-
thesized design isn’t exactly the same as the RTL source code. The vari-
ous optimizations employed by the synthesizer will remove and rename
many nets, making it harder to find the correct signal/bus to inspect.
This could be mitigated if more back-annotation information was avail-
able to the tools.
206
Figure 6: The logic analyzer user interface showing instruction fetches
on a Wishbone bus. The analyzer has been set to trigger when STB and
ACK are both asserted.
Finally, the PyXDL library has only been tested on Virtex-4 based de-
signs.
6 Conclusion
We have shown that it is easy to create powerful backend tools for a Xil-
inx based design flow such as a logic analyzer inserter. By manipulating
the design file directly a time consuming full synthesis/placement/rout-
207
Figure 7: The GUI used to insert the logic analyzer core into a design.
References
[1] Xilinx. Chipscope pro.
[3] Adam Megacz. A library and platform for fpga bitstream manipulation. Pro-
ceedings of IEEE Symposium on Field-Programmable Custom Computing Machines
(FCCM’07), 2007.
208
PyXDL example
largedes = xdl("system.xdl")
largedespcf = pcf("system.pcf")
clocknet = largedes.netsbyname["clk_i_BUFGP"]
tinydes = xdl("test.xdl")
tinydes.unplace_design()
tinydes.remove_unused_dcminsts()
tinydes.remove_inst("clk")
tinydes.remove_net("clk")
tinydes.add_prefix("TEST/")
myiob = tinydes.insts["TEST/testin"]
testinpin = tinydes.convert_input_to_internal(myiob)
oldclknet = tinydes.netsbyname["TEST/clk_BUFGP"]
209
# Remove old clock network
tinydes.remove_net("TEST/clk_BUFGP")
tinydes.remove_inst("TEST/clk_BUFGP/BUFG")
# Merge designs
largedes.mergedesign(tinydes)
largedes.add_inpin_to_net(clocknet,pin[0],pin[1])
thenet = largedesign.netsbyname["traceit/state_r_FFd1"]
largedes.add_inpin_to_net(thenet,testinpin[0],
testinpin[1])
largedespcf.addiob("TEST/testout","AC6")
par_with_guide(largedes,largedespcf,"new.ncd","tmp")
Verilog source code for a simple monitor application. testout will be asserted
if testin has ever been asserted:
module test(
input clk,
reg tmp,sample;
wire fbloop;
210
tmp <= fbloop;
end
FD monitorfd(.C(clk),.D(fbloop | sample),
.Q(fbloop));
endmodule // test
211
212
Paper IV
A High Performance
Microprocessor with DSP
Extensions Optimized for the
Paper IV
Virtex-4 FPGA
Portions reprinted, with permission from Field Programmable Logic and Applications, 2008. FPL 2008.
This paper has been reformatted from double column to single column format for ease of readability.
213
Abstract
As the use of FPGAs increases, the importance of highly optimized pro-
cessors for FPGAs will increase. In this paper we present the microarchi-
tecture of a soft microprocessor core optimized for the Virtex-4 architec-
ture. The core can operate at 357 MHz, which is significantly faster than
Xilinx’ Microblaze architecture on the same FPGA. At this frequency it
is necessary to keep the logic complexity down and this paper shows
how this can be done while retaining sufficient functionality for a high
performance processor.
1 Introduction
The use of FPGAs has increased steadily since their introduction. The
first FPGAs were limited devices, usable mainly for glue logic whereas
the capabilities of modern FPGAs allow for extremely varied use cases
in everything from high end communication and networking equipment
to consumer devices like flat screen televisions. In many cases, a soft
processor core is an important part of the design.
The main players in this market are Altera’s Nios, Xilinx’ Microblaze
and Lattice’ Mico32. All are capable microcontrollers based on a tradi-
tional RISC pipeline. However, there is little choice available if a soft DSP
processor core is needed. Some might argue that a DSP processor core
is unnecessary in an FPGA as DSP computations can instead be handled
by custom designed IP blocks. For example, a radar processing core can
easily fill an entire high end FPGA with high utilisation rate of all func-
tional units. On the other hand, it is harder to design a system which
will use a wide variety of different DSP algorithms if custom IP blocks
are used for each algorithm. As an example, a video conference system
might use a hardware accelerated video encoder and a software based
video decoder and audio codec. There are many reasons for partitioning
the design like this, including; better hardware utilization and shorter
development time due to software reuse and simplified debugging.
214
In this paper we will present a high speed soft microprocessor core
with DSP extensions optimized for the Virtex-4 FPGA family. The mi-
croarchitecture of the processor is carefully designed to allow for high
speed operation.
2 Related Work
There are many soft processor cores available for FPGA usage although
Nios II, Mico32, and Microblaze are common choices thanks to the sup-
port from their vendors.
Altera’s Nios II [1]. is a 32-bit RISC processor that comes in three
flavors; e, s, and, f with a one, five, or six pipeline stages respectively.
Xilinx’ Microblaze is a 32-bit RISC processor [2] optimized for Xilinx
FPGAs.
Lattice’ Mico32 is a 32 bit RISC processor [3] with a six stage pipeline.
The source code of Mico32 is also available under an open source license.
Besides the vendor supported processors there are a wide variety of
processor cores available, both commercial and open source. Notable
cores include OR1200 [4], Leon [5], OpenSparc [6]. These processors are
targeted at ASICs but have found a use on FPGAs as well.
3 Overview
Our main design goal was to create a high speed soft processor core
with support for common DSP operations. In addition, the processor
should be reasonable easy to program without intimate knowledge of the
pipeline. It should also be possible to write a decent compiler backend
for the processor. Finally, the processor footprint should not be excessive.
3.1 Tradeoffs
It is hard to create a processor which is both fast and easy to program.
A fast processor will have a deep pipeline, forcing the programmer (or
215
compiler) to think hard about instruction scheduling and branch penal-
ties.
On the other hand, a programmer friendly processor presents an ar-
chitecture with few surprises trading either speed or hardware complex-
ity for ease of use.
Our goal was to create a high speed processor which is still relatively
easy to program. For example, in order to increase the maximum clock
frequency our processor only has partial support for register forwarding.
The result of some instructions cannot be forwarded directly to other
execution units. Typically one or two other instructions has to be issued
before the result of an operation can be reused on another execution unit.
We feel that this is an acceptable tradeoff, based on our experience with
other processors without any forwarding at all [7].
4 Architecture
The architecture is RISC based with six pipeline stages; fetch, decode /
read operands, register forwarding, execute1, execute2, and writeback.
The processor is a 32-bit microprocessor with 16 general purpose regis-
ters. The address space is limited to 16 bits. The instruction set contains
a fairly standard set of RISC instructions.
The instruction words are 27 bits wide and up to 7 bits can be used
for immediates. Longer immediates can be handled either by a 128 entry
lookup-table or by using an extra SETHI instruction.
Special purpose registers are used for I/O and processor configura-
tion.
216
Select active unit
R
Execution
R
Execution
unit 2
R
Execution
unit 3
the result of a logic unit operation can be forwarded directly to the logic
unit.
The principle of the forwarding unit is shown in Fig. 1. To reduce
the size of the mux, the pipeline is constructed so that signals from one
pipeline stage can be or:ed together. This is accomplished by utilizing the
reset input of the flip-flops after each execution unit to set all non-active
execution unit outputs in a certain pipeline stage to zero.
The arithmetic unit (AU), shown in Fig. 2 is one of the most critical parts
of the entire processor. As mentioned earlier we could not afford to have
full register forwarding in this processor. The main reason for this is the
32 bit adder in the AU. If a large mux is inserted before the inputs to the
adder the critical path would be too long (e.g. a 32 bit adder with 4-to-1
muxes in front of each operand can be synthesized to only 290 MHz in a
Virtex-4 speedgrade 12).
217
Figure 2: The architecture of the arithmetic unit and the principles of the
final part of the register forwarding unit
However, the processor is able to forward results from the adder back
to the adder without any penalty to support a sequence of AU instruc-
tions. As can be seen in Fig. 2, the result of the addition can only be for-
warded to one of the inputs of the adder. Due to the design of a slice in a
Virtex-4 it is not possible to put a mux in front of the other operand when
only one LUT is used per bit in the adder. This complicates forwarding
since either operand has to be able to be forwarded to any input of the
adder. To solve this problem the previous pipeline stage is responsible
for ensuring that the correct operand appears on the inputs. An example
is shown in Table 1. It should also be noted that only the principles for
the register forwarding pipeline stage is shown in the figure. In our im-
218
Instruction Forwarded Control signals
sequence operand
add r2,r1,r0 - -
add r2,r1,r2 OpB Force0=1 Select=1
add r2,r2,r1 OpA Swap=1 Force0=1 Select=1
sub r2,r1,r2 OpB Force1=1 Select=1
sub r2,r2,r1 OpA Swap=1 InvA=1 Select=1
sub r2,r2,r2 Both Replace with set r2,#0
add r2,r2,r2 Both Cannot forward directly
plementation this has been merged into the same LUTs that are used to
implement the forwarding shown in Fig. 1 to reduce the logic level.
4.3 Branching
Branches always has one delay slot. If absolute addressing is used for the
jump address, the processor can immediately start executing the target
instruction after the delay slot.
The processor has 4 status flags: Z (zero), V (overflow), N (negative),
C (carry). An arithmetic or logic instruction will change these flags. The
critical path of this unit is the Z flag generation. This is performed partly
in the AU and LU units. In the AU unit, the 20 lower bits are preprocessed
in groups of four bits using five 4-input or-gates. In the LU unit, the
entire 32 bit result is preprocessed in the same way using eight 4-input
or-gates. Thanks to this preprocessing of the Z flag it is possible to start
branch condition computation one pipeline stage earlier.
Conditional jumps are statically predicted using a bit in the instruc-
tion word. A correctly predicted conditional jump has no penalty cycles.
A mispredicted jump has a penalty of either three or four cycles.
A register indirect jump always has a penalty of four cycles.
If the branch prediction was wrong, the speculatively fetched instruc-
tions are invalidated before entering the execute1 stage.
219
4.4 Memory Architecture
There are three memories in the system: program, data, and constant
memory. The program memory is 27 bits wide, the data and constant
memory is 32 bits wide. Both the constant and data memory can be ad-
dressed using address generator units described in the next section. The
constant memory is also used as a lookup table for the 128 constants de-
scribed in Section 4.
The data memory can be addressed using a value from the register
file plus an 8 bit offset in the instruction word. The adder is located in
the same pipeline stage as register forwarding. This is done to minimize
the complexity before the memory. This also means that the register used
must be written to the register file before being used for addressing mem-
ory. We believe that this is an acceptable tradeoff as one very common
usage for this addressing mode is accessing variables on the stack and
the stack pointer is unlikely to change very often.
The data memory is byte addressable which is important if high level
languages like C and C++ are used to write programs for the processor.
220
STEP-SIZE
STEP TOP-2 STEP
MSB
ADDR
Figure 3: Address generation unit
allow for a steady stream of data from the memories to the MAC unit.
The AGUs support linear and circular addressing.
For each memory access, the AGU increases the current address with
a configurable stepsize. In circular addressing, a start and end address
constrains the range of valid addresses. If the next address is located be-
yond the end address, the next address is set to CURRENT_ADDRESS +
STEPSIZE - BUFFER_SIZE, where BUFFER_SIZE is the size of the circu-
lar buffer.
A straight forward hardware implementation of this calculation
could be synthesized to 209 MHz. The next address is compared to
END_ADDRESS and, if it is too large, adjusted as described above.
Pipelining is used to improve the performance of the address gen-
erator. Due to the pipelining, the address must be compared to
END_ADDRESS-2*STEPSIZE (END_ADDRESS-STEPSIZE for the first
iteration) instead of END_ADDRESS. The pipelined address generator
is shown in Fig. 3.
221
To improve the performance of small loops typical for DSP kernels
there is also a loop instruction available which allows for up to 65535
loop iterations.
5 Results
A floorplanned version of the processor can operate at 357 MHz in a
Virtex-4 LX80, speedgrade 12 according static timing analysis. Without
floorplanning, 334 MHz is the maximum frequency. The processor uses
1197 slices, 1716 LUTs, and 1301 flip-flops. The largest parts of the pro-
cessor are the shifter (405 LUTs, 131 flip-flops) and the register forward-
ing pipeline stage (264 LUTs, 64 flip-flops).
6 Discussion
In order to reach a clock frequency of 357 MHz in a Virtex-4 FPGA, a
number of compromises had to be made. This means that the proces-
sor will have a few quirks not found in more general processors. The
most important impact of this is that the pipeline is partly visible to the
programmer.
According to [8] on Xilinx’ homepage, the Microblaze processor can
run at 160 MHz in a Virtex-4. We have, however seen figures of up to
200 MHz reported for the Microblaze on Virtex-4 [9]. Even so, our pro-
cessor has a maximum clock frequency which is is almost 80% faster than
Microblaze. In addition, it is also operating at a significantly higher fre-
quency than the Microblaze on a Virtex-5. This does not mean that all
applications will be 80% faster when running on our processor. Some
programs will require more clock cycles to run on our processor, due
to the incomplete register forwarding. However, DSP applications can
typically be rewritten to compensate for the lack of register forwarding
by proper instruction scheduling and algorithm selection. For example,
in [7], only 10% of the cycles were wasted on NOP instructions and that
222
processor has no support for register forwarding at all. A more thorough
examination of the results of incomplete forwarding can be found in [10].
We also acknowledge that standardized benchmarks are required to
fully evaluate our processor.
7 Conclusion
It is not possible to design a really fast processor in an FPGA without
some quirks. It is however possible to design a processor where the im-
pact of these quirks are reduced.
Like all high speed designs, a high speed microprocessor has to keep
the logic complexity between flip-flops at a minimum. Unlike many
other high speed designs, the pipeline also has to be short.
This paper has demonstrated a number of ways to deal with these
issues, resulting in a processor which can operate at a much higher clock
frequency than Xilinx’ Microblaze. The architectural details and trade-
offs presented here should be of interest to anyone who is interested in
processor design for FPGAs.
223
Acknowledgments
Thanks to Prof. Lars Svensson for an interesting discussion regarding the
processor described in this chapter.
References
[1] Altera. Nios II Processor Reference Handbook, 2007.
[7] J. Eilert, A. Ehliar, and Dake Liu. Using low precision floating point
numbers to reduce memory cost for mp3 decoding. Multimedia Sig-
nal Processing, 2004 IEEE 6th Workshop on, pages 119–122, 2004.
[8] Xilinx Inc. Microblaze - the industry’s most flexible embedded pro-
cessing solution, 2006.
[9] Peter Clarke. Xilinx raises soft processor clock frequency 25%, 2005.
[10] P.S. Ahuja, D.W. Clark, and A. Rogers. The performance impact
of incomplete bypassing in processor pipelines. Microarchitecture,
1995. Proceedings of the 28th Annual International Symposium on, pages
36–45, Nov-1 Dec 1995.
224
Paper V
Paper V
Department of Electrical Engineering
Linköping University
Sweden
email: {perk,ehliar,dake}@isy.liu.se
°2008
c IET. Reprinted from IET Computers & Digital Techniques, Vol. 2, No. 4, pp. 305-313, July 2008
High-performance, low-latency field-programmable gate array-based floating-point adder and multiplier units in
a Virtex 4, Karlström, P. Ehliar, A. Liu, D.
This paper has been reformatted from double column to single column format for ease of readability.
225
Abstract
There is increasing interest about floating point arithmetics in FPGAs,
thanks to the increase in their size and performance. While FPGAs are
generally good at bit manipulations and fixed point arithmetics, they
have a harder time coping with floating point arithmetics. In this paper
we describe, in detail, an architecture used to construct high performance
floating point components in a Virtex-4 FPGA. We have constructed a
floating point adder/subtracter and multiplier. Our adder/subtracter
can operate at a frequency of 377 MHz in a Virtex-4SX35 (speed grade
-12).
1 Introduction
Modern FPGAs are great assets as hardware components in small vol-
ume projects or as hardware prototyping tools. The increasing cost of
ASIC production is also a contributing factor to the increased use of
FPGAs [1].
More features are added to the FPGAs with every generation, making
it possible to perform computations at higher clock frequencies. Dedi-
cated carry chains, memories, multipliers and in the most recent FPGAs,
larger blocks aimed at DSP computations and even processors have been
incorporated into the otherwise homogenous FPGA fabric. All of these
improvements accelerate fixed point computations but no improvements
are directly aimed at improving floating point performance. Lacking any
direct support for floating point computations, it is important for design-
ers to know how to utilize the available resources as efficiently as possi-
ble.
FPGAs are not limited to just small volume production and proto-
typing. There is active research in the field of reconfigurable computing,
where processors reconfigures FPGAs (or similar devices) during run-
time to speed up critical inner loops. These systems range from multichip
systems with dedicated processors and FPGAs to solutions where the en-
226
tire system has been integrated into a single chip, [2] describes this field
in more details. Many of these solutions aims to automatically transform
C code (or code at similar level of abstraction) into FPGA configurations
to speed up critical parts of programs. In many cases the applications
might require floating point computations and it is therefore of impor-
tance to have good floating point units in the FPGA.
Floating point arithmetics is useful in applications where a large dy-
namic range is required or in rapid prototyping for applications where
the required number range has not been thoroughly investigated. Float-
ing point numbers are used extensively in modern applications, e.g. 3D
graphics, audio codecs, radar, and scientific computing. Many of these
applications are limited by the available computation power. This short-
age of computation power has started a trend of using FPGAs to boost
performance in a cost effective manner. In particular, scientific comput-
ing rely on floating point arithmetic [3].
This paper outlines one solution for integrating single precision float-
ing point computations into an FPGA. Previous solutions are either slow,
have high latency, or fail to disclose the architecture used to reach the
published performance. A solution, for single precision floating point
computing, comparable to the performance of commercial IP cores is pre-
sented, as well as the details of such an implementation. This is some-
thing not earlier done to the knowledge of the authors. For example, this
paper will present the details of a fast normalizer architecture for FPGAs
and the often overlooked aspect of the sticky bit generation, which needs
some special care to achieve timing closure.
In general, it is possible to trade higher throughput for longer latency
(in terms of clock cycles) by increasing the number of pipeline stages.
However, in many systems the point of diminishing returns are quickly
reached as the number of pipeline stages are increased. This is especially
true for algorithms with many data dependencies that cannot easily be
parallelized due to an increasing number of cycles used solely to wait for
values to be computed. Therefore, the overall goal of our design was to
balance throughput, latency, and area.
227
In summary FPGAs are becoming more and more important as com-
puting devices and will be able to replace more ASICs thus avoiding
the expensive ASIC development process. But a good FPGA fabric is
not enough, there must be good designs to configure the fabric with if
FPGAs are to be used successfully. This article intends to show good
design techniques for floating point units in FPGAs.
2 Related Work
A number of attempts at constructing floating point arithmetics in FPGAs
have been done and presented in the academia. However many of the
papers are a bit old and few targets modern FPGAs such as the Virtex-
4. This work is based on a study [4] that did not include the round to
nearest even mode, which is important for IEEE 754 compliance.
High-performance floating point arithmetics on FPGA is discussed
in [5]. Although the paper has some interesting figures about the area
versus pipeline depth tradeoff, their design seems to be a bit to general
to utilize the full potential of the FPGA. As an example, to reach a clock
frequency of 250 MHz for the adder they have to use 19 pipeline stages
on a Virtex2Pro speed grade -7.
To be fully IEEE 754 compliant the floating point unit needs to sup-
port denormalized numbers, be it either with exceptions, letting a pro-
cessor deal with these uncommon numbers or having direct support for
denormalized numbers in hardware. For a good discussion on different
strategies to handle denormalized numbers see [6]. Although it is a good
general discussion the paper does not cover any FPGA specific details.
An interesting approach to tailor floating point computations to FPGAs
are to use higher than radix-2 floating points since this maps better to the
FPGA fabric. This is better described in [7]. This makes it harder to
achieve full IEEE 754 compliance though.
Full IEEE 754 compliance requires the FPU to support round toward
nearest even, round toward −∞, round toward +∞, and round toward
zero. A more detailed discussion about rounding is presented in [8]. That
228
paper however, does not deal with any FPGA specific implementations.
A system for configuring and building floating point accelerators is
presented in [9], where the target device used is a Stratix (speed grade
5) FPGA, which is roughly comparable to the Virtex-2 Pro (speed grade
6) FPGA. Having realized this it is easy to see that their work does not
come close to the performance presented in this article. For example
their floating point adder has a latency of 5 cycles and runs at a clock
frequency of 77 MHz.
The Arénaire project [10] has published a configurable floating point
library (including elementary functions as well as addition and multipli-
cation), the latency can also be parameterized. Their modules can only
perform round to nearest and they report a clock frequency of 100 MHz
in a Virtex-II (XC2V1000-4) using the fully pipelined modules. While not
reaching the same performance as our solution, the project is still inter-
esting as it is not focused solely on basic operators such as addition and
multiplication.
The only work so far presented with performance comparable to our
results are commercial IP cores from e.g. Nallatech [11] and Xilinx [12].
But neither of these companies publish the low level techniques used in
their IP cores.
It is possible to design IEEE 754 single precision floating point arith-
metics that can run at a clock frequency of 400 MHz in a XC4VSX55-10
according to [13]. But that work targets FFT and can as such be more
aggressively optimized, therefore it can not be directly compared to our
work. The authors do not report any latency figures for their computa-
tion units either.
A quantitative performance comparison between our work and oth-
ers will be given in section 6.
229
is to use a two’s-complement representation. Another common approach
is to use a sign magnitude representation where a sign bit (S) decides the
sign and the mantissa holds the magnitude of the number. The sign of the
exponent must also be represented, a common approach to this is to store
the exponent in an excess representation. In the excess representation
the exponent is stored as a positive number from which a constant is
subtracted to form the final exponent.
Since the mantissa in a normalized binary floating point number, us-
ing the sign bit representation, always will have a single one in the MSB
position, this bit is normally not stored together with the floating point
number. This bit is referred to as an implicit one. The IEEE 754, a stan-
dard for floating point numbers [14], dictates the format presented in
Equation (2). The IEEE 754 single precision format is 32 bit wide and
uses a 23 bit fraction, an eight bit exponent represented using excess 127,
and one bit is used as a sign bit. The value zero is represented by setting
all bits to zero.
x = M · 2e (1)
S e−excess
x = (−1) · 1.M · 2 (2)
230
original LSB of the mantissa. Two of the bits, often called the guard (g)
and round (r) bit, are a buffer for bits to be shifted into and the third bit
is called the sticky bit (s) and is an or-operation of all bits shifted into
and to the right of the s bit. The new fractional number to be used in the
computations will take the form of Equation (3), where g, r, and s are the
bits described above, and the m:s are the original mantissa bits.
231
1.f1 = 1.i0 m1 m2 r1 s1 (12)
r1 = m3 (13)
s1 = m4 ∨ m5 ∨ m6 (14)
(
{f0 , r0 , s0 } if i1 = 0
{f, r, s} = (15)
{f1 , r1 , s1 } if i1 = 1
Our floating point format is similar to IEEE 754 [14]. An implicit one
is used and the exponent is excess-represented. However, we do not
handle denormalized numbers, nor do we honor NaN or Inf. The rea-
son for excluding denormalized numbers is due to the large overhead
in taking care of these numbers, especially for the multiplier. These are
commonly excluded from high performance systems, e.g. the CELL pro-
cessor does not use denormalized numbers for the single precision for-
mat in its SPUs [15].
4 Methodology
As a reference for the RTL code we implemented a C++ library for float-
ing point numbers. The number of bits in the mantissa and exponents
could be configured from 1 to 30 bits. The C++ model was later used to
generate the test vectors for the RTL test benches. Using a mantissa width
of 23 and an exponent width of 8 the C++ model was tested against the
floating point implementation used in the development PC. The only dif-
ferences occurred due to the lack of support for denormalized numbers,
Inf, and NaN.
Initial RTL code was written using Verilog adhering to the C++ model.
The performance of the initial RTL model was evaluated and the most
critical parts of the design were optimized to better fit the FPGA. This
was repeated until the performance was satisfactory and no bugs were
discovered by the test benches.
232
5 Implementation
We chose to implement the most commonly used operations, addition,
subtraction, and multiplication. In order to test these components in a
realistic environment we constructed a complex radix-2 butterfly kernel
using our components.
Our implementation always uses the round to nearest even mode.
Since this is the mode requiring the most extra hardware to implement,
implementing the other modes should not significantly affect the per-
formance or resource utilization of the circuits. See section 7 for further
information about the other rounding modes.
We have tested the floating point units on an FPGA from the Virtex-4
family (Virtex-4 SX35-10). For further details about the Virtex-4 FPGA,
see the Virtex-4 User Guide [16]. The Virtex-4 contains a number of
blocks targeted at DSP computations, these blocks are called DSP48-blocks
and are thoroughly described in the XtremeDSP user guide [17]. Xilinx’
ISE 9.1i was used to synthesize, place, and route the design.
5.1 Multiplier
A floating point multiplier is conceptually easy to construct. The new
mantissa is formed as a multiplication of the old mantissas. In order
to construct a good multiplier some FPGA specific optimizations were
needed. The 24×24 bit multiplier for the mantissa is constructed using
four of the Virtex-4’s DSP48 blocks to form a 35×35 bit multiplier with a
latency of five clock cycles. For a thorough explanation of how to con-
struct such a multiplier the reader is referred to [17]. The new exponent
is calculated with a simple addition and the new sign is computed as an
exclusive-or of the two original signs. The result of the multiplication
has to be normalized, which is a simple operation since the most signifi-
cant bit of the mantissa can only be located at one out of two bit positions
given normalized inputs to the multiplier. The exponent is adjusted ac-
cordingly in an additional adder. The final stage is the round operation,
requiring an additional adder. The rounding operation can result in a
233
Mantissa Exponent
DSP48
Multiplier
1
Normalize
Round
PostProcess
234
5.2 Adder/Subtracter
235
Exponent Mantissa
SbP SbP
Compare/Select
CMP
1'b1/0
2 SbG
Align
1
Add
ROP
Round&PostProcess
Add1?
PostProcess
236
looking at four bits of the mantissa. The first module operates on
the first four bits and outputs a normalized result assuming a one
was found in these bits. An extra output signal, shown as dotted
lines in Figure 3, is used to signal if all four bits were zero. The
second module assumes that the first four bits were all zero and
instead operates on the next four bits, outputting a normalized re-
sult. This is repeated for the remaining bits of the mantissa. Each
module also generates a value needed to correct the exponent, this
is marked as gray dotted lines in Figure 3.
2. One of the previous results, both mantissa and exponent offset value,
is selected to be the final output. If all bits were zero, a zero is gen-
erated as the final result.
237
Unnormalized mantissa Exp
Shifted by 0 4 20
Priority
6-1 MUX
decoder
The final post processing stage is used to force the outputs to zero
if needed. The mantissa is forced to zero if the overall result is zero, in
case of an underflow, or in case of a round overflow. The exponent and
sign bit is forced to zero if the overall result is zero or an underflow has
occurred.
238
ure 2. This is done so that the shifter in the align step only has to consider
the five least significant bits in the exponent difference, marked with 2 in
Figure 2. If one of the more significant bits is one, the mantissa should be
shifted so much that all its bits become zeroes. This is handled by the Set
to zero signal in Figure 4. The least significant bit however is always used
as it is since it is the sticky bit and it is needed to ensure that the result
after the rounding operation is the same as if the addition operation had
been done with infinite precision.
Carry out
Sub
Set to zero
B
A Sum
LUT
Carry in
6 Results
We have focused much of our measures and comparisons on the adder
since it is the bottleneck module in our current design. The clock frequen-
cies reported by us assumes a clock with no jitter. Xilinx’ place and route
tool was used to determine the maximum clock frequency by changing
the timing constraints until timing closure could not be achieved. The
clock frequencies reported by us is the maximum frequencies for which
239
timing closure occurred, rounded down to the nearest integer.
Table 1 list various performance metrics over different devices and
speed grades.
240
lish data for how many slices their design occupies. The number of LUTs
is in this case estimated to be twice as many as the slices since there is
two LUTs per slice in a Virtex-II. Although the comparisons here are not
completely fair they still give a good picture of how the performance of
our floating point units compare to other FPGA implementations.
LUT FF
Compare/Select 111 22
Align 134 66
Add 36 29
Normalization 436 191
Round 8 0
Other 121 121
Total 846 429
Device: XC2VP-7
USC DA
Pipeline depth 19 8
LUTs 548 760
FFs 801 516
Clock frequency (MHz) 250 278
241
Device: XC2VP-6
Nallatech DA
Pipeline depth 14 8
LUTs < 580a 758
FFs ? 517
Clock frequency (MHz) 184 278
Device: XC4VSX-10
Adder Multiplier
Xilinx DA Xilinx DA
Pipeline depth 13 8 11 8
LUTs 578 846 116 173
FFs 594 429 235 150
DSP48 — — 5 4
Clock frequency (MHz) 368 290 391 331
Device: XC5VLX-1
Adder Multiplier
Xilinx DA Xilinx DA
Pipeline depth 12 8 9 8
LUTs 429 675 88 189
FFs 561 424 117 154
DSP48E — — 3 4
Clock frequency (MHz) 395 317 450 362
242
If the application of the floating point blocks are known it is possible
to do some application specific optimizations. For example, in a butterfly
with an adder and a subtracter, operating on the same operands, the first
compare stage could be shared between these. If the application can tol-
erate it, further pipelining could increase the performance significantly.
If the latency tolerance is very high, bit serial arithmetics could probably
be used as well. In this project we tried to achieve a high throughput
while still maintaining low latency. In the end, the latency tolerated for
any unit depends on the application. If our results are better than others
with deeper but faster pipeline, or if the resource utilization is acceptable,
can not be answered without knowing the target application.
It would also be interesting to take a closer look at the Virtex-5 FPGA.
The six input LUT architecture should reduce the number of logic levels
and routing all over the design. As an example, one could investigate
if the parallel shifting modules in the normalizer should take six bits as
input since it could map well to the six input LUT architecture of the
Virtex-5 or if the fact that a 4-to-1 mux can be constructed in a six input
LUT still favors the current four bits per module architecture. The num-
bers presented for the Virtex-5 in this paper is produced using the same
design as for the Virtex-4.
Our current implementation is not fully IEEE 754 compliant as it can-
not handle Inf, NaN, denormalized numbers and some of the rounding
modes. We estimate that no extra pipeline stage is needed for the miss-
ing rounding modes, i.e. round toward zero, round toward +∞, and
round toward −∞. These can be implemented by adding a few LUTs to
a non-critical path.
Inf and NaN can be handled by a parallel data path that will check for
and generate substitute values. This will cost an extra mux in the end to
choose the right value for the outputs and this extra mux will probably
require an extra pipeline stage to avoid performance degradation. De-
normalized numbers can be handled by raising an exception and letting
a processor deal with the situation. Detection of denormalized numbers
can be done in parallel with the computation and shouldn’t require much
243
extra hardware or any extra pipeline stage.
8 Conclusion
We have shown that it is possible to achieve good floating point perfor-
mance with low latency in modern FPGAs. Our adder and multiplier
can operate at a clock frequency of 377 MHz and 440 MHz respectively
in a Virtex 4 (speed grade -12). We have also disclosed the techniques
required for achieving the results reported.
To make maximal use of an FPGA it is important to take into ac-
count the specific architecture of the targeted FPGA. We have shown
techniques for how to do this when dealing with floating point opera-
tions. One of the most important optimization we did was to perform
the normalization in a parallel fashion. The parallel normalization ap-
proach proved to be efficient since it reduced the number of pipeline
stages needed to perform the normalization operation.
References
[1] Rick Mosher. FPGA Prototyping to Structured ASIC Produc-
tion to Reduce Cost, Risk & TTM. http://www.us.design-
reuse.com/articles/13550/fpga-prototyping-to-structured-asic-
production-to-reduce-cost-risk-ttm.html.
244
[5] Gokul Govindu, L. Zhuo, S. Choi, and V. Prasanna. Analysis of
high-performance floating-point arithmetic on fpgas. In Parallel
and Distributed Processing Symposium, 2004. Proceedings. 18th Inter-
national, pages 149+, 2004.
[7] Bryan Catanzaro and Brent Nelson. Higher radix floating-point rep-
resentations for fpga-based arithmetic. In FCCM ’05: Proceedings of
the 13th Annual IEEE Symposium on Field-Programmable Custom Com-
puting Machines (FCCM’05), pages 161–170, Washington, DC, USA,
2005. IEEE Computer Society.
245
[14] IEEE. Ieee standard for binary floating-point arithmetic. Technical
report, 1985.
[16] Xilinx. Virtex-4 User Guide. Xilinx, www.xilinx.com, 2.3 edition, Au-
gust 2007.
246
Paper VI
247
Abstract
1 Introduction
FPGAs are becoming more and more common and are used in both high
and low-end systems. In some cases it is easy to meet the performance
and area goals using non-optimized generic HDL code. This is not true
as often as designers would wish and various FPGA specific tricks are
often required to either meet timing or fit the design into the selected
FPGA. If the design is intended for a high volume ASIC product where
the FPGA version is only used for prototyping it is probably not a big
problem since such a design does not usually have to be optimized for
the FPGA.
However, when the design is intended for high volume production
using FPGAs and a future ASIC port if the FPGA based product is suc-
cessful, the ease of ASIC portability is very important indeed. This is the
scenario which the rest of this paper will investigate.
There are two parts in this paper. The first part examines common
components like adders, multiplexers, and memories and compares the
performance of these components in ASICs and FPGAs. The second part
of this paper examines a variety of different FPGA optimizations and
their impact on an ASIC port.
248
2 Related work
It is surprisingly hard to find information about porting FPGA designs
to ASICs, especially when considering the impact of FPGA optimization
strategies. A brief overview of how to do an ASIC port of an FPGA de-
sign is given in [1]. Some general guidelines on how to port an ASIC de-
sign to an FPGA is available from for example Xilinx [2] and Altera [3].
While the FPGA vendors would of course like us to port ASIC designs
to FPGAs, most of the advice that is given in these references are also
applicable when creating an FPGA design which will be migrated to an
ASIC.
An interesting comparison of the performance difference between
ASIC and FPGAs is given in [4] where the performance, area and power
consumption of a 90 nm ASIC and a 90 nm FPGA is measured. It is unfor-
tunate that the benchmarks selected by the authors in this paper do not
seem to include designs that are specifically targeted and optimized for
FPGAs. There are also some publications that discuss structured ASICs
and similar solutions and how to port an FPGA design to such prod-
ucts such as for example [5], [6], and [7]. The relatively fixed structure
of these solutions means that not all of the information is applicable to a
true standard cell based ASIC port.
3 Methods
It is not our intention to crown the fastest or most area efficient FPGA
in this paper. Therefore we have decided to use performance and area
cost numbers that are relative to the performance and area cost of a 32-bit
adder in the selected technology. Another reason to use relative numbers
instead of absolute number is to protect proprietary information like the
exact size and performance of ASIC memory blocks.
One problem of this kind of comparison is that it is not really clear
what area means in an FPGA design since it can contain components
like block rams and DSP blocks in addition to LUTs and flip-flops. One
249
way to measure this would be to simply measure the silicon area of
the various components in the FPGA, which is basically what was done
in [4]. While this comparison is very interesting from an academic point
of view, it is not very useful to a VLSI designer (unless he is working for
an FPGA manufacturer).
250
time reported was selected. To find the Fmax of Altera designs, the tim-
ing were simply over constrained by setting the required frequency to 1
GHz. This approach is also recommended by Altera in [8].
Synopsys Design Compiler (A-2007.12-SP5) was used for ASIC syn-
thesis and Cadence SoC Encounter (v5.20) was used for ASIC place and
route. The selected ASIC technology is a standard cell based 130 nm
technology based on the relatively low NRE costs (this choice was made
consistent with the scenario outlined above where an FPGA based prod-
uct is ported to an ASIC for cost reasons). The timing analysis is based
upon worst case parameters.
4.1 Adders
Adders (and subtracters) are probably one of the most common compo-
nents in any digital design. It is also a component which the architecture
of most FPGAs are optimized for by the use of dedicated carry-chains.
For this reason an adder in an FPGA tends to be a pretty simple compo-
nent which is usually using one LUT per bit and there is little reason to
deviate from this template (except possibly for pipelining of very large
adders and using bit-serial adders for non-performance critical tasks).
251
Table 1: Relative area and performance of common components
Design Relative area cost (lower is better) Relative Fmax (higher is better)
(Note that all designs FPGAs ASIC4 FPGAs ASIC4
have registered outputs) 1 2 3 4 (130 nm) 1 2 3 4 (130 nm)
32-bit adder 1.0 1.0 1.0 1.0 1.0 ( 0.21) 1.0 1.0 1.0 1.0 1.0 ( 0.11)
32-bit adder/subtracter 1.0 1.0 2.0 1.0 1.9 ( 0.25) 0.97 0.90 0.82 0.81 0.89 ( 0.13)
32-bit 3 operand adder 1.9 1.9 2.0 1.0 1.3 ( 0.40) 0.86 0.82 0.77 0.89 0.74 ( 0.12)
32-bit 4 operand adder 2.9 2.9 3.0 2.0 1.7 ( 0.55) 0.62 0.58 0.77 0.82 0.69 ( 0.10)
32-bit 16-to-1 mux 8.0 5.0 10 5.0 0.57 ( 0.48) 1.5 0.92 1.3 1.7† 0.90 ( 0.31)
17x17 unsigned multiplier 18∗ 34∗ 10∗ 19∗ 3.7 ( 1.3) 1.3 0.64 0.81 0.61 0.44 ( 0.11)
19x19 unsigned multiplier 75∗ 35∗ 36∗ 37∗ 4.1 ( 1.6) 0.46 0.40 0.59 0.49 0.43 ( 0.10)
Plain 18x18 MAC unit 25∗ 35∗ 19∗ 26∗ 5.3 ( 2.4) 0.55 0.41 0.51 0.53 0.42 ( 0.08)
(pipelined adder) 29∗ 35∗ 21∗ 42∗ 5.4 ( 2.7) 0.79 0.82 0.77 0.62 0.49 ( 0.11)
(pipelined adder, forwarding) 25∗ 36∗ 24∗ 29∗ 4.9 ( 2.7) 0.75 0.72 0.63 0.62 0.49 ( 0.09)
2048x32 bit memory 74∗ 34∗ 79∗ 57∗ - ( 33‡ ) 1.5 0.72 0.75 0.92 - ( 0.53‡ )
RF (16x32 bit register file) 1.0 1.0 10∗ 2.1 2.7 ( 2.5) 2.1† 1.2† 0.74 1.0 0.93 ( 0.31)
RF (Ports: 1 read, 1 write) 2.0 1.0 10∗ 2.1 2.6 ( 2.5) 1.9† 1.1 0.73 1.2 0.93 ( 0.23)
RF (Ports: 2 read, 1 write) 4.0 2.0 20∗ 4.3 3.2 ( 3.0) 1.9† 1.0 0.74 1.0 0.89 ( 0.22)
RF (Ports: 4 read, 2 write) 50 40 59 21 5.8 ( 4.6) 0.97 0.66 0.90 1.1 0.91 ( 0.13)
4 Values in parentheses are from designs optimized for area ∗ Relative area cost
includes DSP or RAM blocks (See Section 3.1) † Exceeds maximum frequency of
clock net as reported in the datasheet. ‡ The ASIC memory block was only
optimized for area.
However, when using ASICs, the area of an adder can vary widely
depending on the timing constraints as seen in Table 1. It can also be
seen that an ASIC enjoys an advantage for situations which the FPGA is
not optimized for, such as multi-operand adders. (Although it is inter-
esting that the architecture of the Stratix III allows a 3-operand adder to
be created without any area penalty.)
4.2 Multiplexers
Multiplexers and similar structures is a very common design component.
The performance of multiplexers in an FPGA is usually high due to the
use of specialized logic in the FPGAs such as the MUXF5-8 components
in most Xilinx FPGAs. On the other hand, the area cost for multiplexers is
very high when compared to the cost of the adders as shown in Table 1.
This means that tradeoffs that are valid in an FPGA such as avoiding
the use of crossbar based SoC interconnects may no longer be valid in
an ASIC. If a SoC system is well designed, replacing a SoC bus, such
as Wishbone or AMBA, with a crossbar may be a fast way to raise the
performance of an ASIC port without a costly redesign/reverification.
252
FPGA and ASIC optimization hint
Multiplexers are very expensive in an FPGA and very cheap in an ASIC.
The performance of an ASIC can sometimes be significantly enhanced at
little area cost by adding strategically placed multiplexers, such as using
crossbars instead of buses.
253
Figure 1: MAC units mapped to DSP48E blocks
254
formation is available from Atmel for a 0.35 µm process [9]. According
to this datasheet, a dual port memory is roughly 60% larger than a single
port memory. However, the authors have seen memory blocks in more
recent technologies where the area difference is considerably larger than
this.
Regardless of the technology which is used, it is clear that it is much
more area expensive to use a dual port memory than a single port mem-
ory. Therefore it makes sense to avoid dual port memories in ASICs if
the same performance can be reached using single port memories. As an
example of this, FIFOs are usually implemented using dual port memo-
ries in an FPGA but a synchronous FIFO can be implemented using only
single port memories as described in for example [10]. If it is not easy to
avoid a dual port memory it is necessary to consider the cost and time re-
quired to redesign the system (if possible) and compare that against the
cost of the increased ASIC area that dual port memory usage will lead to.
For memories which contain read-only information it can also be a
very good idea to use a ROM compiler instead of an SRAM. Not only
does this avoid the problem of initialization, a ROM is also considerably
smaller than an SRAM. In [9] for example, a 1 kilobyte 8-bit wide ROM
is about 1/7 the size of a (single port) RAM with similar size.
255
Table 2: Pipelining a design will not necessarily increase the area
Pipeline Relative area Relative Fmax
stages Spartan3 ASIC4 Spartan3 ASIC4
1 260∗ 20 (5.5) 0.38 0.30 (0.073)
2 260∗ 13 (6.1) 0.33 0.35 (0.079)
∗
3 260 14 (6.8) 0.38 0.41 (0.10)
∗
4 260 13 (7.0) 0.37 0.40 (0.10)
4 Values in parentheses are from designs optimized for area ∗ Relative area cost
includes DSP or RAM blocks (See Section 3.1)
As can be seen in Table 1, FPGA based designs are usually fairly effi-
cient when using small single and dual-port memories. A configuration
of two read ports and one write port is also fairly efficient. As soon as
more than one write-port is used, the synthesis tool for the FPGAs are
no longer able to utilize distributed memory and has to resort to using
flip-flops with a significant area increase.
256
5.1 Deep Pipelining
Perhaps the most important tool in any digital designers toolbox is pipelin-
ing. This is even more important for an FPGA designer since flip-flops
are usually abundant in most FPGAs. Luckily pipelining is also benefi-
cial for the performance in ASICs in all but the most pathological cases.
It is not always a good idea in terms of area, although pipelining can
sometimes decrease the area of a design by enabling the use of less area
intensive circuits in for example a multiplier. As an example of how
pipelining effects the area and performance, an ASIC based 16×16 mul-
tiplier with 4 register stages was 12.6% percent larger and 37.9% faster
than the same multiplier with only 1 register stage. (All multipliers were
optimized for speed when we performed this experiment.) Adding a
pipeline stage is not guaranteed to increase the area though. This is seen
in Table 2 where an eight point 1D DCT pipeline has been synthesized
using different number of registers. The synthesis tool is clearly strug-
gling to meet timing when only one pipeline register is available.
257
Table 3: Combining an adder with other functionality
32-bit adder Relative area Relative Fmax
Spartan3 ASIC4 Spartan3 ASIC4
Plain add 1.00 1.00 (0.21) 1.00 1.00 (0.11)
One 2-to-1 mux 1.00 1.15 (0.25) 0.99 0.69 (0.14)
Two 2-to-1 mux 2.03 1.20 (0.30) 0.85 0.67 (0.14)
Two 2-input 1.97 0.82 (0.27) 0.84 0.85 (0.11)
bitwise or
Two 2-input 1.00 0.89 (0.27) 0.99 0.89 (0.11)
bitwise and
32-bit adder Relative area Relative Fmax
and subtracter Spartan3 ASIC Spartan3 ASIC
Plain add/sub 1.00 1.66 (0.25) 1.00 0.86 (0.14)
One 2-to-1 mux 2.03 1.37 (0.31) 0.82 0.69 (0.14)
Two 2-to-1 mux 2.97 1.39 (0.36) 0.85 0.64 (0.12)
4 Values in parentheses are from designs optimized for area
258
Table 4: Inferring and instantiating components
Design Relative area Relative Fmax
Virtex4 ASIC Virtex4 ASIC
Mux (Inferred) 4.38 0.57 1.3 0.95
(Instantiated) 4.50 0.64 1.3 1.07
Addsub (Inferred) 1.00 1.86 0.98 0.89
(Instantiated) 1.00 1.42 0.98 0.76
AU (Inferred) 1.19 1.05 0.9 0.69
(Instantiated) 1.19 1.30 0.89 0.73
MAC(Instantiated) 118∗ 16.2 1.19 0.40
(Rewritten) - 10.7 - 0.70
∗ Relative area cost includes DSP blocks (See Section 3.1)
Synthesis tools are getting better with each version but there are still
some cases where it may be necessary to instantiate slice primitives like
LUTs and flip-flops manually. One reason for doing this was mentioned
in the previous paragraph. Another reason is that the designer is not able
to get the synthesis tool to infer the desired logic. Once FPGA primitives
are manually instantiated the design is no longer directly portable to an
ASIC. It is on the other hand fairly easy to write a portability library with
synthesizable code for the FPGA primitives like lookup-tables, flip-flops,
carry chain primitives, etc. This allows such a design to be synthesized to
an ASIC with surprisingly good results. Table 4 shows the performance
of a few different constructs when inferred and instantiated. Note that
it is very important that the parts of the design that contain instantiated
LUTs is flattened before the optimization phase of the synthesis. Other-
wise the synthesis tool will not be able to perform almost any combina-
tional logic optimization.
As can be seen from these experiments, it is not certain whether a
certain design will be faster or slower when inferred or instantiated af-
ter it has been ported to an ASIC. Even so, it is surprising that the per-
259
formance difference between the inferred and instantiated adder/sub-
tracter (addsub) is relatively small, considering the fact that the instan-
tiated component is ripple-carry based. The synthesis tool is obviously
able to optimize the combinational paths of the ripple-carry adder so that
the final end result is an optimized adder instead of a plain ripple-carry
adder.
The arithmetic unit (AU) and MAC component are taken from a soft-
core processor optimized for the Virtex-4 [11]. While the arithmetic unit
does fairly well when ported, the MAC doesn’t. When rewriting the
MAC unit using a pipelined DesignWare multiplier, the ASIC port gains
a distinct advantage on the other hand.
260
manual routing is rarely done in practice, the same reasoning is true here
as well (although this is almost exclusively done using graphical tools).
7 Conclusions
In this paper we have discussed how important design constructs per-
form in terms of area and maximum frequency in FPGAs and ASICs. We
have also discussed how various FPGA optimization techniques can be
used. We conclude that most of these techniques are either beneficial
or relatively non-harmful for the performance and area of an ASIC port.
The most dangerous areas are memories and DSP blocks and extra care
must be taken to make sure that an ASIC port is efficient if a design has
been specifically optimized for these FPGA components.
261
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