Repeatedly used functionality/logic makes the description verbose. Commonly used logic can be separated and can be implemented with tasks/functions. Tasks and functions are used to abstract verilog code that is used in many places in the design. Tasks & functions provide the ability to execute common logic/functionality from several different places in a description. Tasks and functions are procedures. K Sivasankaran FPGA BASED SYSTEM DESIGN 2 Func t i ons Functions Afunctionislikeasubroutineor aprocedureinaprogram. It is defined separately within a module and can be called whenever necessary. Whenafunctionisdeclaredwithafunctionname, thesystemallocatesa register for it. The name of the register is that of the function; and its type (as well as size) isalsothat of thefunction. Whenafunctioniscalled, thesystemexecutesthefunctional activityand generatestheoutput. output isassignedtotheregister identifiedfor thefunction. The quantity returned by the function can be used as an operand in an assignment or inanexpression K Sivasankaran FPGA BASED SYSTEM DESIGN 4 Structure for function definition K Sivasankaran FPGA BASED SYSTEM DESIGN 5 Function properties Functions should not contain delay information. Functions must contain at least one input. Supports only input arguments. A function can call other function only. Can return only one value. Functions are declared with keyword functionand endfunction. K Sivasankaran FPGA BASED SYSTEM DESIGN 6 Function -Example module parity_chk(a,en,chk); input [7:0] a; input en; output chk; wire[7:0] a; regchk; always@(posedgeen) begin chk=pb(a) end K Sivasankaran FPGA BASED SYSTEM DESIGN 7 function pb; input [7:0]a; pb=^a; endfunction endmodule module adderfun (r,p,q,En); input [1:0] p,q; input En; output [2:0] r; reg[2:0] r,c; integer i; always @(posedgeEn) begin for(i=0;i<2;i=i+1) begin if(i==0) begin c[i]=1b0; {c[i+1b1],r[i]}= fa(p[i],q[i],c[i]); end r[2]=c[2]; end K Sivasankaran FPGA BASED SYSTEM DESIGN 8 function [1:0] ha; input a,b; ha={a&b,a^b}; endfunction function [1:0] fa; input a,b,c; reg[1:0] a1,a2,aa2; begin a1=ha(a,b); aa2=ha(a1[0],c); a2[1]= aa2[1] | a1[1] a2[0]=aa2[0]; fa=a2; end endfunction endmodule Function -Example Function calling A function is called or enabled by a function enable call that specifies the argument values passed to the function. A function call is a part of an expression i.e. an operand within an expression. Function returns the computed result in the name of the function itself. K Sivasankaran FPGA BASED SYSTEM DESIGN 9 Function calling The list of input arguments must match the order of input declarations in the function definition. Arguments are passed by value, not by reference. A function can be called more than once concurrently with each call having its own control. Variables declared within a function is static. K Sivasankaran FPGA BASED SYSTEM DESIGN 10 Task Task The role of a task in a module is similar to that of a subroutine in a program. It is defined within a module and can be called as many times as desired within a procedural block. Its scope and role are wider than those of a function. K Sivasankaran FPGA BASED SYSTEM DESIGN 12 Structure of task K Sivasankaran FPGA BASED SYSTEM DESIGN 13 Task properties Task can be used with delay, timing or event control constructs. Tasks can have zero or more arguments. Supports input, output and inout arguments. Passes the values through outputand inoutarguments to the task call. A task can call other tasks and functions as well. Tasks are declared with keyword task and endtask. K Sivasankaran FPGA BASED SYSTEM DESIGN 14 Task-Example module oness_counter; initial reg[3:0]x; x=3b000; reg[2:0]y; always #3 x= x+2b11; always @(x) initial onescounter(x,y); $monitor (t=%d, y=%b, x=%b, $time task onescounter; ,y,x); input [3:0]x; initial #30 $stop; output [2:0]y; endmodule integer i; begin y=0; for (i=0;i<=3;i=i+1) if (x[i]) y=y+1; end endtask K Sivasankaran FPGA BASED SYSTEM DESIGN 15 Task calling A task is called or enabled by a task enable statement that specifies the argument values passed to the task and the variablesthat receivetheresults. Ataskenablestatement isaprocedural statement. Thelist of argumentsmust matchtheorder of input, output and inout declarationsinthetaskdefinition. K Sivasankaran FPGA BASED SYSTEM DESIGN 16 Task calling Arguments are passed by value, not by reference. A task can be called more than once concurrently with each call having its own control. Variables declared within a task is static. Output and inout arguments in a task call must be registers. K Sivasankaran FPGA BASED SYSTEM DESIGN 17 Tasks and Functions functions can enable other function, not a task. execute in 0 simulation time. do not support delay, event or timing controls. must have at least one input argument, can have more than one input. return single value , they can not have output or inout arguments. tasks can enable other functions and tasks. execute in non 0 simulation time. can have delays, event or timing controls. can have zero or more arguments of type input, output or inout. do not return any value, but can pass multiple values thro output and inout args. K Sivasankaran FPGA BASED SYSTEM DESIGN 18 When to use tasks ? Use tasks when: there are delay, timing, or event control constructs in the procedure. OR the procedure has zero or more than one output arguments. OR the procedure has no input arguments. K Sivasankaran FPGA BASED SYSTEM DESIGN 19 When to use functions ? Use functions when: there are no delay, timing, or event control constructs in the procedure. AND the procedure returns a single value. AND there is at least one input argument. K Sivasankaran FPGA BASED SYSTEM DESIGN 20