EE 201A

Fundamentals to Computer-Aided Design of

VLSI Circuits and Systems
Instructor: Lei He
Email: LHE@ee.ucla.edu
Instructor Info
n n Email: Email: LHE@ee.ucla.edu LHE@ee.ucla.edu
n n Phone: 310-206-2037 (o) or 626-354-2381 (m) Phone: 310-206-2037 (o) or 626-354-2381 (m)
n n Office hours: MW 3-4, BH6731 Office hours: MW 3-4, BH6731
u u or email for appointments or email for appointments
n n The best way to reach me: The best way to reach me:
u u Email with EE201 in subject line Email with EE201 in subject line
Course Prerequisites
n n Official prerequisite Official prerequisite
u u EE116B EE116B VLSI System Design VLSI System Design
u u But mainly self-contained But mainly self-contained
n n Knowledge to help you appreciate more Knowledge to help you appreciate more
u u CS 180, Introduction to algorithms CS 180, Introduction to algorithms
u u EE 136, Introduction to engineering optimization EE 136, Introduction to engineering optimization
techniques techniques
EE201A Outline and Schedule
n n Circuit platforms and models (2 weeks) Circuit platforms and models (2 weeks)
u u ASIC, FPGA, and ASIC, FPGA, and uProcessor uProcessor platforms platforms
u u Timing, power and thermal modeling Timing, power and thermal modeling
n n Basics of logic and physical design algorithms (2 weeks) Basics of logic and physical design algorithms (2 weeks)
u u RTL synthesis and technology mapping RTL synthesis and technology mapping
u u Partitioning, placement and routing for ASIC and FPGA Partitioning, placement and routing for ASIC and FPGA
n n Applications of FPGA (3 weeks) Applications of FPGA (3 weeks)
u u RTL-based design for FPGA RTL-based design for FPGA
u u Dynamic configuration of FPGA Dynamic configuration of FPGA
u u Reliability and security of FPGA Reliability and security of FPGA
n n More synthesis and testing algorithms (3 weeks) More synthesis and testing algorithms (3 weeks)
u u Logic optimization and layout optimization Logic optimization and layout optimization
u u Fault model, D algorithm and design for testing Fault model, D algorithm and design for testing
Project Topics and Schedule
n n Default projects (choose one by student): Default projects (choose one by student):
u u Parallel programming of a routing algorithm Parallel programming of a routing algorithm
u u Implementing DSP algorithms on FPGA Implementing DSP algorithms on FPGA
n n Advanced or customized topics: Advanced or customized topics:
u u System reliability study using FPGA emulators for System reliability study using FPGA emulators for uP uP or or
networking networking
u u Logic reliability metrics for soft errors Logic reliability metrics for soft errors
u u Anti-cloning methods for FPGA-based systems Anti-cloning methods for FPGA-based systems
n n Project assigned 4 Project assigned 4
th th
or 5 or 5
th th
week, and due by the last day week, and due by the last day
of the quarter of the quarter
References for this Course
No textbook required No textbook required
Class Class wiki wiki web-site web-site
http://eda.ee.ucla.edu/EE201A http://eda.ee.ucla.edu/EE201A
Selected papers leading journals and conferences Selected papers leading journals and conferences
Grading Policy
n n Homework (maybe small programming Homework (maybe small programming
projects) 70% projects) 70%
n n Final project Final project 30% 30%
Who should take this course
n n It is another course It is another course
u u Discuss wide scope of knowledge Discuss wide scope of knowledge
u u But research (presentation + project) on your But research (presentation + project) on your
own focus own focus
n n For students who are motivated to For students who are motivated to
u u Learn timing, power/thermal, DFM for system Learn timing, power/thermal, DFM for system
and and ckt ckt designs designs
u u Understand CAD better Understand CAD better
u u Become a CAD professional Become a CAD professional
Related, 201C to be offered in Winter
n n Interconnect and timing modeling (3 weeks) Interconnect and timing modeling (3 weeks)
u u Interconnect extraction Interconnect extraction
u u Delay modeling and model order reduction Delay modeling and model order reduction
u u Project 1 (model order reduction in Project 1 (model order reduction in Matlab Matlab) )
n n On-chip timing and integrity (4 weeks) On-chip timing and integrity (4 weeks)
u u Stochastic static timing and noise analysis for logic and on-chip Stochastic static timing and noise analysis for logic and on-chip
interconnects interconnects
u u Process variation, stochastic timing, power and noise analysis Process variation, stochastic timing, power and noise analysis
u u Stochastic power and thermal integrity Stochastic power and thermal integrity
u u Project 2 (stochastic modeling in Project 2 (stochastic modeling in Matlab Matlab) )
n n Beyond-die signal and power integrity (3 weeks) Beyond-die signal and power integrity (3 weeks)
u u Chip-package co-design with power integrity Chip-package co-design with power integrity
u u TSV modeling for 3D IC TSV modeling for 3D IC
u u Noise analysis for high-speed signaling and other analog Noise analysis for high-speed signaling and other analog
components components