A llOMHz 70dB CMOS VARIABLE GAIN AMPLIFIER

Mohamed Mostafa, Hassan Elwan', Abdellatif Bellaour2, Brad Kramer2, and S.H.K. Embabi

Department of Electrical Engineering, Texas A&M University, College Station, TX 77843, USA
Department of Electrical Engineering, The Ohio State University, Columbus, OH 43210, USA
Wireless RF Group, Texas Instruments, Inc., Dallas, TX 75248, USA

ABSTRACT differential input voltage signal vin is converted to a

differential current through the transconductance
This paper describes a CMOS variable gain amplifier gm1/(2+gm1 (Rdeg/2)) of the two input transistors, grn1&2
(VGA) circuit that maintains a 3dB bandwidth greater than degenerated by the resistor, Rdeg.The gain of this stage is
IlOMHz throughout its gain range. The VGA provides a
Gain = RL
70dB-gain control range in 2dB steps. The gain is (1)
2
controlled digitally through a decoder. The VGA is fully
differential and is implemented in a standard 3V, 0.6 pm
-+-
Rdeg

2 Pnl
CMOS process. The overall supply current is below 6mA.
By changing the ratio of the load and degeneration resistor,
this architecture can provide both amplification and
1. INTRODUCTION attenuation. However, to achieve high precision, it is
desirable for the gain to be only a function of the ratio of
Variable gain amplifier (VGA) circuits are employed in
resistor values. Hence, a gm boosting circuit was used as
many applications in order to maximize the dynamic range
shown in Fig. 2, to minimize the gain dependency on gm.
of the overall system. VGA circuits are often employed in
The gm will be boosted by the gain of the feedback circuit
imaging circuits [l], hearing aids [2], disk drives [3,4] and
consisted of MI7and M3 and can be written as
in virtually all wireless communication systems [5]. The
automatic gain control (AGC) loop in wireless systems is
needed since the received signal power of all Where R A is~ the impedance of the current source Ib in
communication systems is unpredictable. In order to keep parallel with the cascode transistor M9.
the communication systems working under these This will significantly reduce the gain dependency on gm
conditions, a VGA is typically employed in a feedback because of the large gain of the cascode feedback circuit
loop to realize the AGC circuit, whose output signal has a architecture. The differential current generated from the
fixed magnitude for different input signal strengths. The main degeneration circuit is mirrored through M3 to M7,
specification for the linearity of the VGA is generally very and M4 to MRto the output branches where it is converted
high to maintain good overall system linearity. A to the output voltages by the load resistors, RL.
differential circuit topology for a VGA is preferred from
crosstalk perspective when used in combination with an
analog-to-digital converter (ADC). Moreover, a VGA with
an exponential gain control characteristic is desired in
applications where wide gain control range is required; i.e.,
the gain should increase linearly on a decibel scale. A
high-resolution gain control is also desirable for the VGA,
especially for wireless communication systems where
digital decision thresholds are fixed; therefore the input
amplitude to the ADC must be set to within half a bit. In
this paper a VGA that satisfies all the above desirable
features is described.

2. CIRCUIT DESCRIPTION

2.1 Differential variable gain architecture

In order to get high precision gain steps and good linearity,

a fully differential degeneration architecture is used. The
basic degeneration architecture is shown in Fig. 1. The Fig. 1. Basic degeneration differential pair

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 2.2 Current Mode Common Mode Feedback Circuit change the current mirror ratio to the output, however, this
was found to dramatically degrade the bandwidth of the
A current mode common mode feedback (CMIB) circuit VGA due to Ithe large capacitance from the array of the
is implemented in this design as shown in Fig 2. One of the current mirrors.
main advantages of the current mode CMFB architecture is In order to obtain a large dynamic range, large
its large common mode dynamic range, which is slightly bandwidth, good stability and high precision gain for the
less than the supply range. The circuit adds a scaled copy VGA, a degeneration resistor, RLdeg, is used between the
of the output currents from both the output branches output nodes iis shown in Fig. 2. This does not affect the
through M5 & Mg, at node S, compares it to ai reference stability of the VGA nor its bandwiidth (which will be only
current at node Z , and feeds the control signal back to the limited by the main load resistor). Moreover, it can be used
main amplifier. to achieve larger gain dynamic range and relax the design
The total feedback current is given by of the common mode feedback circuit.
17 TI Although, the resistor array architecture is the most
IOfl =I of +I 0- -+i " OCM
R, otAC'
, "OCM -i
R. otAC (3) commonly used idea, the use of a switch in series with a
L L
resistor will limit the accuracy of the VGA due to the error
while the reference current is caused by the finite resistance of ithe MOS switch. As a
trade off a large width MOS switch can be used, however,
'ref the large capacitance of the switch will limit the
I =2- (4) bandwidth. Hence, to overcome this trade off, only the
ref RL- output branch starting from the cascode transistors,
The factor of 2 is due to a current mirror gain from MI5 to MIl & M I ~are connected or disconnected from the output
MI6. The CMFB will adjust the biasing current in the current mirror transistors, M7 & Me,.Moreover, the switch
amplifier until v,,
= vref.
The reference current and can now have minimum width. This technique provided
satisfactory results from both accuracy and bandwidth
the feedback current are scaled down to reduce the power perspectives. It is worth noting that using the degeneration
consumption of the CMFB circuit. resistance between the output nodes for gain selection does
not affect the operation of the CMFB. The gain can now be
2.3 Gain Control Strategy given by:
In order to change the gain, it is more desirable to change
the degeneration resistor, Rd, to maintain a1 constant
bandwidth throughout all the gain stages. However, in Gain= N -
Rd
' (5)
previous work, changing the degeneration resistors limited
the gain dynamic range to 12dB [6]. Moreover, if used 2
with a higher dynamic range VGA, it can caus,e stability where N is the current mirror gain from M3 to M7.
problem [7].Another method to change the gain is to

I Ydd I

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 2.4 Gain Distribution and Architecture
3. SIMULATION RESULTS
The VGA is designed as a three stage cascaded amplifier to
achieve a large dynamic range and maintain high bandwidth. 3.1 Fabrication
The general architecture is shown in Fig. 3. The first stage has
OdB to 30dB range in lOdB steps, the second stage has OdB to The VGA will be fabricated using a standard 3V, 0.6 pm
lOdB range in 2 dB steps and the last stage has -20dB to lOdB CMOS process. However, simulation results using accurate
range in lOdB steps. This gain distribution is chosen mainly to BSIM3 models are reported as a good approximation to the
enhance the total noise figure of the VGA. The noise factor of expected measurement results.
a 3 stages VGA is given by:
3.2 Gain Response

I
The gain response for the whole dynamic range of 70dB
Where fi, and Gi are the noise factor and the gain of stage i, (from -20dB to 50dB) is shown in Fig. 4. The 3dB bandwidth
respectively. It is clear from this equation that a large gain in of the VGA is larger than 1lOMHz over the entire gain range.
the first stage will greatly reduce the noise figure of the whole This bandwidth was calculated taking into consideration a
VGA. mixer load, which usually follows the VGA in wireless
architecture. The overall gain accuracy was measured at a
single frequency of 45MHz for the total dynamic range of
70dB, and was found to be less than 0.3dB. This gain accuracy
is equivalent to an error of less than 0.43%. Fig. 5 And Fig. 6
show the error versus the VGA gain and the simulated gain
Vi-
nt versus the desired gain, respectively, while changing the gain
in 2dB steps. The advantage of the proposed architecture is
obvious in achieving precise gain steps even for a large
dynamic range.
Vin-
-
/ 6C

40

OdB to 30dB OdB to lOdB -20dB to lOdB 20

lOdB step 2dB step lOdB step 0

-20
5
Fig. 3. VGA general architecture -40

-60
2.5 Technology Consideration
-80
The input transistors were chosen to be PMOS to be able to
connect its body to the source to enhance linearity and reduce -100
distortion. This is mainly due to the use of an N-Well process.
Moreover, as PMOS transistors are less noisy than NMOS -120
transistors, it is beneficial to use the PMOS transistors in the 1o6 1OB 1os
Frequency
first stage, which contributes most of the noise. However, an
NMOS complementary design can achieve at least twice the
Fig. 4 Gain response
bandwidth when implemented on a P-Well process.

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 3.4 Distortion

The maximum differential output swing is 2.6V. The total

harmonic distortion was simulated for 30dB gain, with lMHz
input sine wave and was found to be less than -50dB for 1.5V
differential output. For the large dynamic range this VGA
delivers a good THD performance.

4. CONCLU!SION

A 70dB variable gain amplifier with 2dB steps was

implemented in standard CMOS technology. The circuit uses a
degeneration architecture with extra degeneration resistors at
the output to change the gain. It also includes a current mode
common mode feedback circuit. The 3dB bandwidth was
simulated to be more than 1 lOMHz over the entire gain range.
-041 J The VGA consumes less than 6mA from a 3V supply. The
-20 -10 0 10 20 30 40 50
Required gain equivalent input noise was 16 nV/& at 50dB gain. The
THD was greater than -50dB.
Fig. 5 Gain error versus required gain
5. ACKNOWLEDGMENT
50 I I

Support fromi Texas Instruments, Inc., Dallas is kindly

acknowledged. Special thanks for 1 3 . Maher Abuzaid for his
support

6. REFERENCES

[ l ] A. Motamed, C. Hwang, and h4. Ismail, “A Low-Voltage

Low-Power Wide-Range CMOS ’Variable Gain Amplifier,”
IEEE Trans. Circuits Syst. 11, vol. 415, no. 7, pp. 800-811, July
1998.
[2] J. Duque-Carrillo, P. Malcovati, F. Maloberti, R. Perez-
Aloe, A. Reyes, E. Sanchez-Sinencio, G. Torelli, and J.
Valverde, “VERDI: An Acoustically Programmable and
Adjustable CMOS Mixed-Mode Signal Processor for Hearing
I Aid Applications,” IEEE J. Solid-state Circuits, vol. 31, no. 5,
pp. 634-645, May 1996.
[3] R. harjani, ”A Low-Power CMOS VGA for 50 Mb/s Disk
Drive Read Clhannels,” IEEE Trans. Circuits Syst. 11, vol. 42,
-2
-20 -io 20 30 40 50
no. 6, pp. 370-376, June 1995.
Required gain [4] R. Gomez and A. Abidi, “ A 50 MHz CMOS Variable
Gain Amplifier for Magnetic Data Storage Systems,” IEEE J.
Fig. 6. VGA simulated gain versus required gain Solid-state Circuits, vol. 27, no. 6, pp. 935-939, June 1992.
[5] L. Hon, Y. Leung, and A. Buchwald, “IO-MHz 60-dB
3.3 Noise Performance Dynamic-Range 6-dB Variable Gain Amplifier,” IEEE
International Symposium on Circuits and Systems, pp. 173-
The simulated equivalent input density of while noise is 176, June 1997.
16nV/& at 50dB gain. This is equivalent to a 14dB noise [6] J. Rijns, “CMOS Low-Diistortion High-Frequency
figure for 650a input matching. This noise level will increase Variable-Gain Amplifier,” IEEE J. Solid-state Circuits, vol.
by decreasing the gain of the VGA. However, the gain of the 31, no. 7, pp. 1029-1034, July 1996.
VGA is usually adjusted to keep the output signal at the [7] E. Ibaragi, A. Hyogo, and K. Selcine, “A Design Technique
desired level, therefore, even though the input noise voltage of the CMOS Circuit with a Very Low Impedance Terminal
for Stability, “ IEEJ, 2”dAnalog VLSI Workshop Proceedings,
increases with decreasing gain, the signal to noise ratio
remains nearly constant. ECT-98-30, pp. 51-56, June 1998.

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