Design of Low Power CMOS Variable Gain

Amplifier for Hard Disk Drive Applications

A mini project report submitted

To
NATIONAL INSTITUTE OF TECHNOLOGY
(DEEMED UNIVERSITY), WARANGAL (A.P)

By

S.Kali Praveen
M.Tech (VLSI – SD)
3 rd Semester
Roll No: 260416

DEPARTMENT OF
ELECTRONICS AND COMMUNICATION ENGINEERING
NATIONAL INSTITUTE OF TECHNOLOGY
WARANGAL-506004 (A.P)

i
 CERTIFICATE

This is to certify that the Mini Project entitled “Design of Low

Power CMOS Variable Gain Amplifier for Hard Disk Drive
Applications”, is submitted by S.Kali Praveen (REG. NUMBER:
260416) to the Department of Electronics and Communication
Engineering, National Institute of Technology, Warangal , A.P., in
accordance with the regulations of NIT Deemed University.

Head of the Department Guide

Prof. N.S. Murthy Prof. K.S.R. Krishna Prasad
Department of ECE Department of ECE
National Institute of Technology, National Institute of Technology,
Warangal. Warangal.

ii
 ACKNOWLEDGEMENT

I wish to express my deep sense of gratitude to my guide Dr. K.S.R.

Krishna Prasad, Professor, Department of ECE, National Institute of
Technology, Warangal for guiding me throughout this dissertation. His constant
encouragement and invaluable suggestion have been the cause for the
successful completion of this dissertation.

I am thankful to Dr. N.S. Murthy, Professor and Head, Department of

ECE, National Institute of Technology for his support in the course of this project
work.

I would also like to thank all the teaching and non-teaching staff of the
ECE department for the constant support throughout my M.Tech thesis.

The mini project would not have been completed, but for the motivation,
encouragement and guidance that I received from several people. I express my
heartfelt appreciation and gratitude to all of them.

S.Kali Praveen
M.Tech. (VLSI System Design)
Roll no. 260416

iii
Chapter-1

Introduction
The modern magnetic hard disk-drive is a marvel of technology. The fairly
elaborate resident subsystem of analog, mixed-signal, and digital ICs, including a
microcontroller, make the modern disk drive an autonomous device which may
be directly connected over a standard interface bus to the host computer without
need of an external interface board. The disk-controller section manages the disk
address space, contains semiconductor memory buffers, formats the disk while
mapping out defective sectors, and implements error correction coding. Smart-
power ICs synthesize three-phase waveforms for the spindle-motor and the
currents for the voice-coil actuator to position the head on a disk track. The rather
sophisticated servo-control strategies to accelerate the head between tracks and
optimally place it on the sought track are implemented digitally on a
microcontroller. The ADC and DAC embedded with the microcontroller for this
control function have modest specifications of 8b to 10b resolution at 3 to 5 MHz
sample rate.

AIMS AND GOALS:

To design a VGA, the various existing architectures are studied keeping in view the
following fundamental requirements:
• The VGA should have a wide gain control range
• The required bandwidth should be maintained throughout the gain range
• The VGA should exhibit high linearity
• It should have a low noise figure and low intermodulation distortion

After arriving at the suitable architecture the VGA is designed to meet the following goals:
• The gain control range of the VGA should be high enough to handle the dynamic
range of the input signal.
• The VGA gain should be high enough to maintain the required signal level at the
output of the receiver and should have a continuous gain control.
• The Noise Figure of the VGA should be low enough to ensure that the receiver
yields the required output SNR.
• Since the VGA senses larger input levels it should have high linearity so that the
overall receiver IIP3 does not degrade
Chapter-2

Literature Survey

Variable Gain Amplifiers

Gain Varying Techniques
Fundamentally, the gain of an amplifier depends on the equivalent
transconductance Gm and the output impedance. In order to vary the gain, one
of the two parameters needs to be varied. As a result, variable gain can be
achieved by tuning bias current, emitter/source degeneration and/or loading. This
section briefly introduces and compares these design techniques together with
some other techniques that can be employed for variable gain amplifiers.
Variable Bias Current
Since device transconductance depends on the bias current, the most straight
forward way to tune the transconductance is to tune the bias current. The main
advantage is very simple, but the disadvantages include trade-off of other
parameters including noise, power, bandwidth, and linearity, which also depend
heavily on the bias current.
Variable Source Degeneration
With some emitter or source degeneration, another possible way to tune the gain
is by tuning the degeneration resistors. This can be accomplished by employing
a MOS transistor operating in its triode region as a variable resistor, whose
resistance is given by:
Fig 1:

The differential pair degenerated by the MOSFET resistor handles larger

signal better given a low power supply because the degeneration does not
impose penalty due to bias VGS - VT on voltage head room in a simple differential
pair, however the noise figure of the degenerated stage is poor.
Variable Load
Since the gain also depends on the load impedance, it is also possible to
vary the gain by tuning the load impedance. The simplest way is to use a MOS
device operated in the triode region as a variable load resistor. Like tuning bias
current, this technique is simple but suffers from the severe trade-off of the
amplifier’s performance in terms of noise, linearity and bandwidth.
Current Steering
Another interesting technique, referred to as current steering, can be
employed to realize a variable-gain amplifier. The simplified schematic is shown
in Fig. 12.3. Transistors M1-M4 are to steer the differential drain current of M5-
M6 to the output according to the control voltage VC in relation to a reference
voltage Vr.
 Fig2:
It can easily be proved that:

where α is the fraction of the drain current from M5 flowing through M1 to

the output

The key advantage of this current-steering technique is that the amplifier’s

parameters, including bias current, noise, bandwidth, and linearity, are all
independent of the control voltage and thus the gain setting. The disadvantages
include more active devices and thus more noise and more voltage headroom,
which may not be suitable for low-voltage and high-swing applications.
 It is interesting to note that the transistors M1-M4 do not need to cross
couple from each other. In this case, the voltage gain becomes:

In fact, for low supply voltage, it becomes more advantageous to steer the
currents from M2 and M3 directly to the supply without cross-coupling to the load.
As such, the current and the voltage drop across the load can be minimized, and
the load can be maximized for maximum gain without sacrificing the dc output
and the output swing. In general, to make the gain insensitive to the process
variation and temperature, it may be necessary to use resistive loads and include
resistive degeneration for the input devices M5 and M6.As always, degeneration
can also help with the linearity at a cost of gain reduction. The range of the
control voltage may be limited for a linear gain control, and a scaling network can
be added right after the actual control voltage to extend it to a full supply range. If
a linear in dB is desired, the scaling network may be more complicated, in
particular for CMOS amplifiers as compared to bipolar counterparts. Finally,
resistive degeneration can also be considered for the steering devices M1-M4 to
linearize the gain as a function of the control voltage.
Chapter-3

Problem definition and Characterization

3.1 Problem Definition:

• A Low Power Variable Gain Amplifier (VGA) is to be designed for Hard

Disk Drive (HDD) applications

3.2 Problem Characterization:

In Hard disk drive read channels, variable gain amplifiers are used to
provide constant voltage at the output of analog front-end regardless of variations
in the input voltage level. Basic block diagram of the Hard disk drive read
channel is shown in figure 3.1 below

Fig 3.1: Digital Read Channel Block Diagram

Generally Analog front-end part consists of Preamplifier, VGA and

Equalizer. The spinning micro-magnets on the induce voltage pulses of less than
1mVP-P in the coil at rates of 30 to 50Mbps.These minute voltage variations will
be amplified by a preamplifier. Typical gain values of the preamplifier are
between 10 to 50.Taking the worst case gain of 10 will give 1decade voltage
variation (10mVP-P) at the output of the preamplifier.
Equalization is done by a linear filter to reduce the effect of Inter Symbol
Interference (ISI) by shaping the input pulses. It does not affect the amplitude of
the signals. Signal variation at the input of equalizer is around 1VP-P.

Signal variations at the input and output of VGA are shown in figure 3.2 below.

Fig 3.2: Input and Output signal variations of VGA

3.2.1 VGA Requirements:

Selection of circuit topologies to implement VGA must consider the following

characteristics
• VGA should have a wide gain control range
• Required bandwidth should be maintained throughout the gain range
• VGA should exhibit high linearity
• It should have a low noise figure and low intermodulation distortion
After arriving at the suitable architecture, VGA is to be designed to meet the following
goals depending on the application:
• Gain control range of the VGA should be high enough to handle the dynamic range
of the input signal.
 • The VGA gain should be high enough to maintain the required signal level at the
output of the receiver and should have a continuous gain control.
• Noise Figure of the VGA should be low enough to ensure that the receiver yields
the required output SNR.
• Since the VGA senses larger input levels it should have high linearity so that the
overall receiver IIP3 does not degrade.
• It should have low Total Harmonic Distortion (THD)

3.2.2 Deriving System level specifications from the requirements:

Step-1: From the input and output signal variations calculate the minimum and
maximum gain values required. Assume equal common mode voltage level at
the input and output. Input signal variation of 10mVp-p for logic-1 is to be
amplified to fixed voltage level of 0.5V .It requires a minimum and maximum gain
values of 17dB and 34dB respectively. So a gain range of 15dB to 40dB is
chosen.

Minimum gain = 15dB

Maximum gain = 40dB
Gain Range =25dB

Step-2: The design is targeted for 50MbPS HDD read channel. So the time
period of the periodic bit stream is 20nsec.So the pulse duration is
10nsec.Assume that the output of VGA has to settle in less than 7.5nsec (for 2%
tolerance band), calculate the required bandwidth for VGA using the following
equation:
Settling time = 4T
Where “T” is the time constant and T=1/2*π*f.
Ö f > 85 MHz.
Ö

Band width > 85 MHz

Step-3: To Avoid ISI, group delay must not exceed half of the bit duration. So
group delay must be less than or equal to 5nsec.

Group delay < 5nsec

Step-4: Total Harmonic distortion (THD) is chosen to be -25dB to satisfy the

linearity requirements.

THD < -25dB

Step-5: Output voltage swing required is 1Vp-p.If VGA is designed for large
output swing than required linearity at the smaller voltage swing will be good.

Output swing = 2 Vp-p

Step-6: VGA is to be designed for low power applications. So the power

consumption must be less than 5mW.
3.2.3 System Level Specifications:

Parameter Specification

Minimum gain 15dB

Max Gain 40dB

Gain Range 25dB

Bandwidth 90MHz

Group delay 5nsec

THD -25dB

Output swing 2 Vp-p

Power 5mW

3.2.4 Topology Selection:

Based on the system requirements the following topology is selected. The
basic amplifying element is the differential pair with diode connected loads. A
single stage can give a gain variation of 15dB.For 25dB gain variation 2 stages
are used. Third stage is a constant gain stage and the overall circuit is fully
differential.

Fig 3.3: Complete schematic of the VGA

3.3 Deriving Block level specifications:

First and second stages:

1. For a 25dB of total gain variation, each of the first two stages has to
provide -2.5dB to +10dB (12.5dB gain variation).

Gain Variation = -2.5dB to 10dB

2. Overall circuit must provide linear phase characteristic (constant group

delay).Relationship between group delay and the bandwidth of the three
stages is shown below.

To minimize the effect of group delay on frequency, bandwidths of the first 2

stages (ω1 and ω2) must be at least 2.23 times the bandwidth (ω3)of the third
stage.
Ö ω1 and ω2 = 2.23*( Bandwidth required)
Ö ω1 and ω2 = 2.23*85MHz.
Ö ω1 and ω2 = 190MHz

Bandwidth > 190MHz

 3. Since Bandwidth required for first 2 stages is larger than the 3rd stage,
power distributed for these stages is ¾ th of total power.
Power = 3.75mW

Third stage:
1. Last stage is providing large constant gain of 20 dB to satisfy the
maximum and minimum gain requirements.
2. Bandwidth must be at least equal to 85MHz to satisfy the settling time
requirements.
3. Power allotted is 1.25mW since Bandwidth is lower.
4. Output swing must be 2 Vp-p
5. It should provide low distortion.
Chapter- 4

Design and Implementation

4.1 Introduction:
Application requires exponential gain control behavior which can be
approximated by a function with “x “being the controlling variable. This
expression is plotted in Fig. 4.1, where the y scale is in dB’s. It is possible to see
that the gain expression in eqn 1 provides the necessary exponential transfer
Characteristics and shows a good match for -0.7 < x < 0.7. Further, it can be
shown that the maximum gain range is given by eqn 2. Therefore, for a gain
range of 30 dB the value of x needs to be varied from -0.698 to +0.698.

Fig 4.1: Exponential gain versus control voltage

As just mentioned, the exponentialcharacteristics matches fairly well within

this range. Outside this region (beyond +/- 0.7) the rate of change in gain is even
more rapid.

4.2 Circuit Design

For a CMOS process the ((1 + x)/ (l - x))} function, displayed in Fig. 4.1,
can be generated by dynamically varying the saturation region transconductance
or the triode region resistance of a transistor. The triode region resistance can be
changed by altering the gate voltage of a MOS device while the saturation region
transconductance can be controlled by altering the drain-to-source current
through the device. We have selected to use the current control technique, i.e.,
we alter the transconductances of transistors to generate the desired function.
Unfortunately, the transconductance of the MOS device varies only as the square
root of the drain current such that a single gain stage would only provide 15dB of
gain variation for ‘x’ changing from -0.7 to +0.7. By varying the current through a
transistor we are altering its transconductance. Unfortunately, a change in the
transconductance also affects the bandwidth of the amplifier stage. An increase
in the bandwidth has little effect; however a reduction in the bandwidth of the
gain altering stage affects the bandwidth of the entire system. Reducing ‘x’ to
less than -0.7, therefore, reduces the overall bandwidth. Additionally, from Fig.
4.1, we note that changing ‘x’ beyond +/- 0.7 causes the system gain to vary from
the desired exponential characteristics. It, therefore, becomes necessary to use
two stages of gain control to achieve the necessary gain range.
Fig. 4.2 shows a simplified circuit schematic for the complete variable gain
amplifier. The first two stages of this circuit provide the necessary gain variation.
The third stage stabilizes the common mode voltage, provides a relatively large
fixed differential mode gain and also helps to stabilize the group delay through
the amplifier. The third stage is followed by two source follower stages to drive
external loads of 5 pF. During normal operation the VGA will be followed by other
on-chip circuitry, usually a detector and the source follower stages can be
dropped. A careful look at the first two stages will show that they are vertically
flipped mirror images of each other. For example, transistors Q7 and Q8 provide
the same functionality for the second stage as do transistors Q3 and Q4 for the
first stage. This allows the circuit topology to be extended from one variable gain
stage to n variable gain stages, where the value of n is only limited by power
consumption, circuit noise and the total phase contribution. Increasing the
number of stages increases the range of gain variability possible. For example,
four such stages could be used to provide 60dB of gain variability.

Fig 4.2 Complete schematic of Variable Gain Amplifier

4.2.1 First and Second Stages: As both the gain control stages operate
similarly we will discuss only the first stage. Transistors Q3 and Q4 are diode
connected and operate as the load transistors for the differential pair Q1 and Q2.
The gain for the first stage is controlled by the ratio of the transconductances of
Q2 and Q4 (and Q1 and Q3), {gainstage1= (gm2/gm4)}. The ratio of their
transconductances can be varied by changing the ratio of the currents that pass
through Q2 and Q4. The current flowing through Q2 and Q4 are given by
 The gain of the first stage can therefore be altered by changing the value
of the current I1 and is equal to

The left half of the gain expression given by (5) is a function of device sizes and
process parameters and is a constant during normal use. The right half has the
form .As mentioned earlier, except for the square root this
expression has the exact form we desire. To compensate for the square root we
use two stages and vary the current I1 from -0.7Ib to +0.7Ib to achieve the
necessary 30 dB of gain variation. Currently a simple class-A current amplifier is
used to generate the current I1. Alternately, a class-AB current amplifier design
can also be used and will further help reduce power consumption. However, care
must be taken to reduce crossover distortion or VGA gain hunting is likely to
occur.
U4.2.2 Offset Voltage Generator:
The voltage sources (Voff ) are included to allow the current sources of
the second and third stages to operate in the saturation region. The value of 0.4
V for this offset voltage is selected such that it is greater than the (Vgs - Vt) of the
current sources but is small enough such that it does not have much impact on
the input common mode range of the VGA. This offset voltage is generated using
a feedback scheme that provides a low impedance voltage source and is shown
in Fig. 4.3. Fig. 4.4 shows the characteristic of offset voltage generator.
Fig 4.3: Offset voltage generator

Fig 4.4: Offset voltage with load current

When the load current approaches 100 nA the offset voltage rapidly rises
to 0.4 V and then remains fairly steady even when the load current increases to
100 μA. If common mode range is not of concern then a simple diode connected
transistor can be used instead. Transistor Q32 is operated in the subthreshold
region and transistors Q31, Q33 and Q34 are operated in strong inversion.
Transistor Q34 is in the triode region and acts as a resistive load for transistor
Q32. The low resistance at this node is included to stabilize the loop by
increasing the pole frequency formed at the drains of Q32 and Q34. As soon as
the gate to source voltage of Q32 is sufficiently large (approximately equal to
Vofft) the drain current of Q32 increases and pulls up the gate of transistor Q33.
This in turn rapidly increases the gate to source voltage of transistor Q31 and
Voff does not increase beyond the desired value. The circuit in Fig. 4.3 functions
in manner that is similar to a series voltage regulator except here we fix the
voltage drop across the load transistor rather than the output voltage. Since the
necessary δ Vgs, (δ Vgs = Vgs - G), is small the turn on voltage for transistor
Q33 is approximately equal to Vtn. Using this constraint, the desired offset
voltage, Voff, can be set using (6).
Here is equal to KTIq which is approximately equal to 26mV at room
temperature, the slope factor is usually between 1.3 and 2 and is fairly
controllable. Kn is the transconductance parameter for NMOS transistors, W32,
L32, W34 and L34 are the widths and lengths of transistor Q32 and Q34. is a
process dependent parameter and is highly unpredictable. However, affects
the offset voltage only logarithmically such that a 100% variation in only
causes a 6% variation in the offset voltage. The other parameters are likely to
have much smaller variation. The loop gain for the offset voltage generator with a
load capacitance of 5 pF is shown in Fig. 4.5 and the closed loop source
impedance of the generator is shown in Fig. 4.6. The source impedance of a
diode connected, 1/gm, and transistor is also shown in Fig. 4.6. We note that the
source impedance for the offset voltage generator is lower than that for the diode
connected transistor for low frequencies and increases at higher
frequencies. This results in a slight degradation of the CMRR at these
frequencies. However, as mentioned earlier, the dc voltage drop across the diode
connected transistor is larger.
Fig 4.5:

Fig 4.6: Offset voltage generator source impedance

4.2.3 Third Stage: An expanded view of the third stage is shown in Fig. 4.7.
Previously, transistors Q11, Q12, Q15, Q16 and Q19 and Q20 were omitted from
Fig. 4.2 for clarity. Transistors Q15 and QI6 are identical in size to Q9 and Q10
and are used to cancel the Miller multiplication effect. Transistors Q19 and Q20
are primarily included to reduce the negative feedback effect of the transistors
Q15 and QI6.However, they also function to reduce the gate-to-source capacitive
loading effects of transistors and Q16.

Fig 4.7: Expanded view of third stage

Effect of negative feedback: The third stage is set to have a large gain as a
result of which the drain-to-gate capacitance (Cds) of Q9 and Q10 get Miller
multiplied and lowers the bandwidth of the second stage. Traditionally, cascoding
is used to reduce the Miller multiplication effect. Unfortunately, cascoding also
limits the maximum swing possible from the amplifier. For this reason we use the
partial negative feedback scheme to reduce Miller multiplication effects. A
simplified schematic to calculate the effective gate referred capacitance of the
third stage is shown in Fig. 4.8.

Fig 4.8: Simplified schematic for capacitance calculation

 It can be shown that the effective gate referred capacitance for this circuit
is given by eqn 7, where A is the gain of the third stage. When transistors Q9 and
Q15 are matched this equation can further be simplified to eqn 8.

In comparison, the gate referred capacitance for the regular cascode

technique is equal to 2Cgd + Cgs and the gate referred capacitance for a
noncascode non canceled circuit is equal to Cgs + (1 + A)Cgd. Unlike normal
cascoding techniques, the addition of the two extra transistors Q15 and Q16
increases the gate-to-source capacitances slightly. However, the effect of this is
much smaller than the effect caused by Miller multiplication because of the large
gain associated with the third stage. For example, for our circuit for a value of
1/gds19 = 50K the effective gate referred capacitance is only 12% larger than for
a regular cascode. As shown in (7) it is important that the two capacitances Cgd9
and Cgd15 match fairly well for complete cancellation. The gate to drain
capacitance is a function of the lateral diffusion of the drain junction and is highly
process dependent. Therefore, it is important that identical methods be used to
generate both capacitances. We use identical device sizes for this purpose. The
drain-to-gate capacitances of transistors Q15 and Q16 are used to cancel the
effects of the drain-to-gate capacitances of Q9 and Q10.
Unfortunately, transistors Q15 and Q16 also provide negative feedback
which reduces the gain of the third stage. For this reason values for gds19 and
gds20 are selected such that the transconductances of transistors Q15 and Q16
are much smaller than those of Q9 and Q10. Therefore, the gain is only reduced
slightly. The resulting effective transconductance is given by (9). Since the sizes
of Q9, Q10 and Q15, Q16 are the same their transconductance is set by the
current flowing through them. The relationship between the currents trough Q9
and Q15 are given by (10).

For our design the reduction, at extremely high frequencies the gain of the
third stage becomes sufficiently small due to its own bandwidth limitations and
the Miller multiplication effect becomes insignificant. In Fig. 4.9 we plot the gain
versus frequency for the second stage with and without our Miller cancellation
circuit. The heavy line shows the result after Miller effect cancellation and the thin
line shows the result without any cancellation. In this figure we note the reduction
in gain due to Miller multiplication and also the reduction of this multiplication
effect at higher frequencies. We also note that the plot is smoother after
cancellation, i.e. more constant group delay. The Miller multiplication effect has
been canceled but there is a slight reduction in the overall bandwidth due to the
increase in the gate-to-source capacitance. The transistors Q15 and Q16
primarily affect the high frequency ac behavior and so the overall circuit can
effectively be simplified by removing Q15, Q16, Q19 and Q20 and assuming that
the gate-to-drain capacitances of transistors Q9 and Q10 are zero and that the
effective transconductance of Q15 and Q16 are reduced slightly.
Fig 4.9:

The output stage is designed to provide a large bandwidth and large

dynamic range at low distortion. This is achieved by using transistors Q11 and
Q12 in the triode region. Two transistors are used instead of one to cancel higher
order signal distortion due to variations in threshold voltage as a result of
changes in the source to bulk voltage, (Vsb) of the load transistors. The circuit
topology also allows for some independent control of the differential mode and
common mode gain and bandwidths. The midpoint between the two transistors is
fairly constant for differential mode signals. Therefore, Cm, has no effect.
However, for common mode signals Cm, acts as an additional load.

Fig 4.10: Effect of Cm on common mode gain

 Transistors Q13 and Q14 provide common mode feedback and control the
dc voltage at the outputs of the third stage. This topology for common mode
feedback is particularly attractive for high frequency applications and provides a
number of advantages when compared to other topologies. First, the circuit does
not add any additional high impedance nodes in the circuit that can add phase
and affect the stability of the common mode feedback loop. Second, the two
transistors Q13 and Q14 operate in the triode region and provide a low
impedance node at the source nodes of transistors Q17 and Q18. The differential
mode gain for this stage is set by the triode operated transistors Q11 and Q12
and is given by eqn11.As mentioned earlier for differential mode signals Cm, has
no effect. Additionally, for differential mode signals the common mode feedback
circuit has no small-signal effect and the impedance looking into the drains of
Q17 and Q18 are high. Therefore, the primary resistive load at the outputs is
approximately equal to the inverse of the conductance of Q11 and Q12.
Therefore, the bottom half of the circuit can be replaced with a simple differential
pair with zero gate to drain capacitance and slightly lower transconductance.

The common mode gain for a completely balanced circuit is ideally zero.
However, any imbalance between the two sides results in some nonzero
common mode gain. This is illustrated in Fig. 4.10. For this simulation the
threshold voltage of transistor Q9 was altered by 10mV. We note both a nonzero
common mode gain and also the beneficial effect of adding Cm.Though a
complete analysis for common mode gain is not provided as this would entail
listing the influence of each transistor in the third stage and all of their
parameters. However, an qualitative explanation can be provided for the Vt offset
situation just mentioned. Other situations can be analyzed similarly. The common
mode gain for each half of the circuit is given by the ratio of the conductances
go/gl. Here go is the conductance of the current source IL and gl is the effective
conductance looking into the drain of transistor Q17 with the common mode
feedback circuit being functional. The low frequency value of gl is given by
(gm17gm13)/ (gds13+ gm17). The offset voltage is amplified by the gain of the
third stage and causes the two output voltages to be different. This in turn causes
the effective gl of the two halves to be different. The transconductance of Q17,
(gm17), essentially remains the same because of the extremely small change in
the current due to this change in the output voltage. Likewise, the
transconductance of Q13, also essentially remains the
same as the Vds is maintained constant by the common mode feedback effect.
However, the conductance of Q13, gds13 = (kP’*W/L)*(Vgs13-Vt-Vds13)
,changes because Vgs13 changes due to the difference in the two output
voltages. This causes the conductance looking into the drain of Q17 to be
different for that looking into the drain of Q18. Therefore, the gains of the two
halves are not equal and this results in the nonzero common mode gain.
Due to the fully differential structure of the VGA any common mode signal
at the input of the first stage is severely attenuated by the first two stages before
it gets to the out- put stage, i.e., the overall VGA has a fairly high common mode
rejection ratio (CMRR). Therefore, one of the primary purposes of the common
mode feedback circuit in the output stage is to stabilize the output voltage in the
face of process and temperature variations. The primary source of such
variations is possible changes in the threshold voltages of the transistors,
particularly those of Q9 and Q13. It also serves to reject any other common
mode signals that may arrive at the third stage via the supplies or the substrate.
Additionally, because of the complete symmetry maintained throughout the
design the power supply rejection ratio is extremely high for this circuit.

UUEffect of bandwidth on group delay: The gain of the VGA is controlled

by varying the current I1.However, these variations in the current I1.affect the
transconductances of the differential pairs and diode connected loads as well.
This change in the load transconductances also affects the bandwidth of the first
two stages. To reduce the effects of this change in bandwidth on the overall
group delay the bandwidths of the three stages are selected so that the
bandwidth of the first two stages is much larger than the bandwidth of the third
stage. Therefore, the bandwidth of the overall amplifier is dominated by that of
the third stage, which is kept constant. One of our design goals is to maintain a
fairly constant group delay through the system. In general, the variation in the
group delay is minimized by maintaining the poles close to the real axis. For a
three stage system like ours the delay through the system is given by eqn 12.
Here, w is the frequency in radians and w1, w2 and w3 are the three system
poles. The variation in the group delay with frequency cannot be made to be
equal to zero for such a system. However, it can be minimized within a frequency
band by setting the values of w2 and w3 to be approximately equal to 2.23 times
w1. This value was generated by settting w2 = w3 and finding the minimum of the
derivative of eqn 12. In our system, the third stage pole is selected to have the
lowest frequency as this pole frequency does not change with gain settings. The
poles of the other two stages are selected to be close to 2.23 times the third
stage pole.

If the bandwidths of the three stages are chosen appropriately as

discussed above group delay will be almost constant for the entire control voltage
range. So the phase characteristic will be linear with frequency.Group delay
versus control voltage and phase versus frequency characteristics are shown in
fig 4.11 and fig 4.12 respectively.
Fig 4.11:

Fig 4.12 Phase versus frequency characteristic of the VGA

Gain variation and the frequency response are typically as shown in below
figures 4.13 and 4.14 respectively.

Fig 4.13: linear in dB gain variation with control voltage

Fig 4.14: frequency response of the VGA

U4.2.4 Class A Current Amplifier:

Current amplifiers perform the same functions in the current domain that
traditional amplifiers do in the voltage domain. They provide an output current
proportional to the input current through a gain factor which is defined by a
resistance ratio. Presently, current amplifiers seem to be favorable from the point
of view of both dynamic range and closed-loop bandwidth. Indeed, a high voltage
swing is not usually required, and the bandwidth is almost independent of the
closed-loop gain, provided that one of the two feedback resistances is
maintained constant. Moreover, an important feature of current amplifiers is the
possibility of using nonlinear resistances in the feedback network, since the
voltage drop across them is the same and nonlinearities are compensated for.
In principal, a current amplifier can be implemented by using the well-
known structure shown in Fig. 4.15, where transistor MA and current generator
make up the current output stage. It is easy to find that the amplifier gain is given
by

This circuit exhibits high accuracy and linearity, but it has a very low power
conversion efficiency, since the current output stage works in a class A fashion.
Moreover, it could be difficult to match current with the quiescent current in MA,
since they are affected by different process tolerances.

Fig 4.15: Simple class A current amplifier

4.3 Design Flow:
4.3.1 First and second stages:

Specifications: Gain = 3.75dB

Gain Variation =-2.5dB to 10dB
Bandwidth > 190 MHz
Power < 1 mW

Step-1: From Power constraint calculate the value of Iss

Power = Vdd * Iss
I1=I2= Iss/2

Step -2 : From the Bandwidth specification calculate the value of gm3,4 using
the following equation:
BW = gm3,4/2πCload
Assume Cload = 10 fF Calculate the (W/L)3,4 from gm3,4 and I1,I2 values found
in step 1
Step-3: Calculate the value of (W/L)1,2 from the gain spec using the following
eqn:
Gain = gm1,2/gm3,4
Step-4: The bias current required is to be varied from +/- 0.7 I1 to achieve a gain
variation of 15dB.

4.3.2 Third stage:

Specifications:
Gain = 20dB
Bandwidth>85MHz
Power < 1.25mW
O/P voltage swing = 2Vp-p
Step-1: From the Power requirement calculate Iss using the following eqn:
Power= Vdd*Iss
I9,10=Iss/2

Step-2: From the band width specification calculate gds11 and from that
calculate (w/L)11 using the following eqns:
Assume Veff11=0.1V
BW=gds11/2 πCload
And gds11=kp’*(w/L)11* Veff11

Step-3: From the gain spec calculate (W/L)9,10 using the following eqn:
Gain = gm9,10/gds11

Step-4: Use the negative feedback by placing resistances of values

100K.Resistance is realized by MOS devices.
1/gds19,20 = 100KΩ
Assume Veff11=0.1V
gds11=Kn’*(W/L)11*Veff11
Calculate (W/L)11

Step-5: The required bias voltage is generated bye the biasing circuit consisting
of Q21 and Q22.
Assume Iss/2 in the biasing circuit and calculate the values of Q21 and Q22.

Step-6: Adjust the (W/L)13,14 to provide output common mode voltage equal to
the mid point of the power supplies.
Chapter-5

Conclusion

Different topologies of the Variable Gain Amplifiers were studied keeping

in view the application requirements. Three topologies modified gilbert cell, VGA
based on diode connected loads and a linear gain contol VGA were compared.
The VGA based differential pair with current amplifier was found to be suitable for
the given requirements. The circuit was implemented in 0.35u CMOS technology.
The following results were obtained.
• First stage is giving a gain variation of -5dB to 15dB and. Bandwidths at
maximum gain is 257MHz and BW at minimum gain is 163MHz.
• Second stage is giving a gain variation of -3dB to 7dB with maximum and
minimum bandwidths of 256MHz and 201MHz respectively.
• Third stage is giving a gain of 10dB with a bandwidth of 85MHz and the
output common mode level is stabilized at 1.3V.
• Offset voltage generator and the current amplifiers are giving satisfactory
results.