/data/study/bk/vlsi/rtl/src /data/study/bk/vlsi/rtl/lib/tcbn45gsbwp_120a/frame_o

nly_HVH_0d5_0/tcbn45gsbwp/LM /home/work/eda/synopsys/dc/libraries/syn
tcbn45gsbwpbc.db
generic.sdb
dw_foundation.sldb
leda
vcs +incdir+src +v2k +systemverilogext+sv -debug src/*.v src/sim/motion_estimati
on_testall.sv
[work@VIT-PC rtl]$ vcs +incdir+src +v2k +systemverilogext+sv -debug src/*.v src/
sim/motion_estimation_testall.sv
/home/work/eda/synopsys/vcs/bin/vcsMsgReport: line 332: /bin/basename: No such f
ile or directory
Warning-[LNX_OS_VERUN] Unsupported Linux version
Linux version '' is not supported on 'i686' officially, assuming linux
compatibility by default. Set VCS_ARCH_OVERRIDE to linux or suse32 to
override.
Please refer to release notes for information on supported platforms.
/home/work/eda/synopsys/vcs/bin/vcsMsgReport: line 332: /bin/basename: No such f
ile or directory
Warning-[LINX_KRNL] Unsupported Linux kernel
Linux kernel '3.2.0-4-686-pae' is not supported.
Supported versions are 2.4* or 2.6*.
/home/work/eda/synopsys/vcs/bin/vcs: line 1199: dc: command not found
Chronologic VCS (TM)
Version D-2010.06-SP1 -- Tue Apr 22 09:49:38 2014
Copyright (c) 1991-2010 by Synopsys Inc.
ALL RIGHTS RESERVED
This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.
Parsing design file 'src/adder.v'
Parsing design file 'src/array_utils.v'
Parsing design file 'src/comp_unit.v'
Parsing design file 'src/control_unit.v'
Parsing design file 'src/curr_mem.v'
Parsing included file 'src/array_utils.v'.
Back to file 'src/curr_mem.v'.
Parsing design file 'src/motion_estimation.v'
Parsing design file 'src/mv_calc.v'
Parsing design file 'src/ref_mem_atom.v'
Parsing included file 'src/array_utils.v'.
Back to file 'src/ref_mem_atom.v'.
Parsing design file 'src/ref_mem.v'
Parsing included file 'src/array_utils.v'.
Back to file 'src/ref_mem.v'.
Parsing design file 'src/reg_siso.v'
Parsing design file 'src/sad_calc64.v'
Parsing included file 'src/array_utils.v'.
Back to file 'src/sad_calc64.v'.
Parsing design file 'src/sad_calc_abs.v'
Parsing included file 'src/array_utils.v'.
Back to file 'src/sad_calc_abs.v'.
Parsing design file 'src/sad_calc_block_sub.v'
Parsing included file 'src/array_utils.v'.
Back to file 'src/sad_calc_block_sub.v'.
Parsing design file 'src/sad_calc_sum_list.v'
Parsing included file 'src/array_utils.v'.
Back to file 'src/sad_calc_sum_list.v'.
Parsing design file 'src/sim/motion_estimation_testall.sv'
Top Level Modules:
motion_estimation_testall
TimeScale is 1 ns / 1 ps
Starting vcs inline pass...
7 modules and 0 UDP read.
However, due to incremental compilation, no re-compilation is necessary.
/home/work/eda/synopsys/vcs/bin/vcs: line 1199: dc: command not found
/home/work/eda/synopsys/vcs/bin/vcs: line 1199: dc: command not found
/home/work/eda/synopsys/vcs/bin/vcs: line 1199: dc: command not found
/home/work/eda/synopsys/vcs/bin/vcs: line 1199: dc: command not found
/home/work/eda/synopsys/vcs/bin/vcs: line 1199: dc: command not found
ld -r -m elf_i386 -o pre_vcsobj_1_1.o --whole-archive pre_vcsobj_1_1.a --no-whol
e-archive
ld -r -m elf_i386 -o pre_vcsobj_1_2.o --whole-archive pre_vcsobj_1_2.a --no-whol
e-archive
ld -r -m elf_i386 -o pre_vcsobj_1_3.o --whole-archive pre_vcsobj_1_3.a --no-whol
e-archive
ld -r -m elf_i386 -o pre_vcsobj_1_4.o --whole-archive pre_vcsobj_1_4.a --no-whol
e-archive
ld -r -m elf_i386 -o pre_vcsobj_1_5.o --whole-archive pre_vcsobj_1_5.a --no-whol
e-archive
if [ -x ../simv ]; then chmod -x ../simv; fi
g++ -o ../simv -m32 SIM_l.o 5NrI_d.o 5NrIB_d.o pre_vcsobj_1_1.o pre_vcsob
j_1_2.o pre_vcsobj_1_3.o pre_vcsobj_1_4.o pre_vcsobj_1_5.o rmapats_mop.o rmapat
s.o /home/work/eda/synopsys/vcs/linux/lib/libvirsim.so /home/work/eda/syno
psys/vcs/linux/lib/librterrorinf.so /home/work/eda/synopsys/vcs/linux/lib/libsnp
smalloc.so /home/work/eda/synopsys/vcs/linux/lib/libvcsnew.so /home/w
ork/eda/synopsys/vcs/linux/lib/vcs_save_restore_new.o /home/work/eda/synopsys/vc
s/linux/lib/ctype-stubs_32.a -ldl -lm -lc -lpthread -ldl
../simv up to date
./simv
[work@VIT-PC rtl]$ ./simv
Chronologic VCS simulator copyright 1991-2010
Contains Synopsys proprietary information.
Compiler version D-2010.06-SP1; Runtime version D-2010.06-SP1; Apr 22 09:50 201
4
==================================================
Test '1pos'
==================================================
min_sad = x | mv_x = x | mv_y = x
Tue Apr 22 09:50:45 ICT 2014
1000: curr_addr = 0 | mv_x = 0 | mv_y = 0 | sad = 0
Current frame block
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
min_sad = 16383 | mv_x = 0 | mv_y = 0
min_sad = 0 | mv_x = 0 | mv_y = 0
Tue Apr 22 09:50:45 ICT 2014
25000: curr_addr = 4798 | mv_x = 0 | mv_y = 0 | sad = 0
Current frame block
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
Tue Apr 22 09:50:45 ICT 2014
155000: curr_addr = 0 | mv_x = 0 | mv_y = 0 | sad = 0
min_sad = 16003 | mv_x = 639 | mv_y = 479
min_sad = 15750 | mv_x = 639 | mv_y = 478
min_sad = 15497 | mv_x = 639 | mv_y = 477
min_sad = 15244 | mv_x = 639 | mv_y = 476
min_sad = 14991 | mv_x = 639 | mv_y = 475
min_sad = 14738 | mv_x = 639 | mv_y = 474
min_sad = 14485 | mv_x = 639 | mv_y = 473
min_sad = 14232 | mv_x = 639 | mv_y = 472
min_sad = 13726 | mv_x = 638 | mv_y = 475
min_sad = 13220 | mv_x = 638 | mv_y = 474
min_sad = 12714 | mv_x = 638 | mv_y = 473
min_sad = 12208 | mv_x = 638 | mv_y = 472
min_sad = 11702 | mv_x = 637 | mv_y = 474
min_sad = 10943 | mv_x = 637 | mv_y = 473
min_sad = 10184 | mv_x = 637 | mv_y = 472
min_sad = 9172 | mv_x = 636 | mv_y = 473
min_sad = 8160 | mv_x = 636 | mv_y = 472
min_sad = 7401 | mv_x = 635 | mv_y = 473
min_sad = 6136 | mv_x = 635 | mv_y = 472
min_sad = 5630 | mv_x = 634 | mv_y = 473
min_sad = 4112 | mv_x = 634 | mv_y = 472
min_sad = 3859 | mv_x = 633 | mv_y = 473
min_sad = 2088 | mv_x = 633 | mv_y = 472
min_sad = 64 | mv_x = 632 | mv_y = 472
min_sad = 63 | mv_x = 18 | mv_y = 29
min_sad = 62 | mv_x = 18 | mv_y = 28
min_sad = 61 | mv_x = 18 | mv_y = 27
min_sad = 60 | mv_x = 18 | mv_y = 26
min_sad = 59 | mv_x = 18 | mv_y = 25
min_sad = 58 | mv_x = 18 | mv_y = 24
min_sad = 57 | mv_x = 18 | mv_y = 23
min_sad = 56 | mv_x = 18 | mv_y = 22
min_sad = 54 | mv_x = 17 | mv_y = 25
min_sad = 52 | mv_x = 17 | mv_y = 24
min_sad = 50 | mv_x = 17 | mv_y = 23
min_sad = 48 | mv_x = 17 | mv_y = 22
min_sad = 46 | mv_x = 16 | mv_y = 24
min_sad = 43 | mv_x = 16 | mv_y = 23
min_sad = 40 | mv_x = 16 | mv_y = 22
min_sad = 36 | mv_x = 15 | mv_y = 23
min_sad = 32 | mv_x = 15 | mv_y = 22
min_sad = 29 | mv_x = 14 | mv_y = 23
min_sad = 24 | mv_x = 14 | mv_y = 22
min_sad = 22 | mv_x = 13 | mv_y = 23
min_sad = 16 | mv_x = 13 | mv_y = 22
min_sad = 15 | mv_x = 12 | mv_y = 23
min_sad = 8 | mv_x = 12 | mv_y = 22
min_sad = 0 | mv_x = 11 | mv_y = 22
Tue Apr 22 09:53:07 ICT 2014
614555000: curr_addr = 1 | mv_x = 11 | mv_y = 22 | sad = 0
min_sad = 16003 | mv_x = 631 | mv_y = 479
min_sad = 15750 | mv_x = 631 | mv_y = 478
min_sad = 15497 | mv_x = 631 | mv_y = 477
min_sad = 15244 | mv_x = 631 | mv_y = 476
min_sad = 14991 | mv_x = 631 | mv_y = 475
min_sad = 14738 | mv_x = 631 | mv_y = 474
min_sad = 14485 | mv_x = 631 | mv_y = 473
min_sad = 14232 | mv_x = 631 | mv_y = 472
min_sad = 13726 | mv_x = 630 | mv_y = 475
min_sad = 13220 | mv_x = 630 | mv_y = 474
min_sad = 12714 | mv_x = 630 | mv_y = 473
min_sad = 12208 | mv_x = 630 | mv_y = 472
min_sad = 11702 | mv_x = 629 | mv_y = 474
min_sad = 10943 | mv_x = 629 | mv_y = 473
min_sad = 10184 | mv_x = 629 | mv_y = 472
min_sad = 9172 | mv_x = 628 | mv_y = 473
min_sad = 8160 | mv_x = 628 | mv_y = 472
min_sad = 7401 | mv_x = 627 | mv_y = 473
min_sad = 6136 | mv_x = 627 | mv_y = 472
min_sad = 5630 | mv_x = 626 | mv_y = 473
min_sad = 4112 | mv_x = 626 | mv_y = 472
min_sad = 3859 | mv_x = 625 | mv_y = 473
min_sad = 2088 | mv_x = 625 | mv_y = 472
min_sad = 64 | mv_x = 624 | mv_y = 472
./simv -gui
dc_shell> set_dont_touch_network [find port rst]
1
dc_shell> set_dont_touch_network [find port en]
1
dc_shell> set_ideal_network [find port rst]
1
dc_shell> set_ideal_network [find port en]
1
Warning: The set_dont_touch_network command is used for clock clk, for which no
sources are specified. (UID-997)
Beginning Area-Recovery Phase (max_area 400000)
-----------------------------
ELAPSED WORST NEG TOTAL NEG DESIGN MI
N DELAY
TIME AREA SLACK SLACK RULE COST ENDPOINT
COST
--------- --------- --------- --------- --------- ------------------------- --
-------
0:06:42 241535.2 0.00 0.0 186.5
0.00
0:06:43 241535.2 0.00 0.0 186.5
0.00
0:07:21 241531.6 0.00 0.0 186.5
0.00
0:07:21 241530.6 0.00 0.0 186.5
0.00
0:07:21 241530.6 0.00 0.0 186.5
0.00
0:07:21 241530.6 0.00 0.0 186.5
0.00
0:07:21 241530.6 0.00 0.0 186.5
0.00
0:07:23 241530.6 0.00 0.0 186.5
0.00
0:07:38 229816.4 0.00 0.0 181.3
0.00
0:07:38 229816.4 0.00 0.0 181.3
0.00
0:07:38 229816.4 0.00 0.0 181.3
0.00
0:07:38 229816.4 0.00 0.0 181.3
0.00
0:07:38 229816.4 0.00 0.0 181.3
0.00
0:07:38 229816.4 0.00 0.0 181.3
0.00
0:07:42 229815.9 0.00 0.0 181.3
0.00
Warning: The set_dont_touch_network command is used for clock clk, for which no
sources are specified. (UID-997)
Loading db file '/data/study/bk/vlsi/rtl/lib/tcbn45gsbwp_120a/frame_only_HVH_0d5
_0/tcbn45gsbwp/LM/tcbn45gsbwpbc.db'
Optimization Complete
---------------------
Warning: Design 'motion_estimation' contains 2 high-fanout nets. A fanout number
of 1000 will be used for delay calculations involving these nets. (TIM-134)
Net 'ref_mem_u0/atom_gen[1].atom_instance/rst': 1962 load(s), 1 driver(s)
Net 'ref_mem_u0/atom_gen[1].atom_instance/en': 1781 load(s), 1 driver(s)
Warning: The set_dont_touch_network command is used for clock clk, for which no
sources are specified. (UID-997)
1
Current design is 'motion_estimation'.
Warning: Current implementation 'rpl' of module 'DW01_add'
was not found in the files of synthetic_library.
Implementation selection of synthetic design
'adder_WIDTH8_2_DW01_add_0' (cell 'sad_calc64_u0/adder32/adder_gen[30].a
ddition/add_1_root_add_30_2') will take longer. (SYNH-22)
Beginning Delay Optimization
----------------------------
0:04:43 224294.7 0.00 0.0 181.2
0.00
0:04:43 224294.7 0.00 0.0 181.2
0.00
0:04:43 224294.7 0.00 0.0 181.2
0.00
0:04:43 224294.7 0.00 0.0 181.2
0.00
Beginning Delay Optimization
----------------------------
0:04:43 224294.7 0.00 0.0 181.2
0.00
0:04:43 224294.7 0.00 0.0 181.2
0.00
0:04:43 224294.7 0.00 0.0 181.2
0.00
0:04:43 224294.7 0.00 0.0 181.2
0.00
Warning: The set_dont_touch_network command is used for clock clk, for which no
sources are specified. (UID-997)
Loading db file '/data/study/bk/vlsi/rtl/lib/tcbn45gsbwp_120a/frame_only_HVH_0d5
_0/tcbn45gsbwp/LM/tcbn45gsbwpbc.db'
Optimization Complete
---------------------
Warning: Design 'motion_estimation' contains 3 high-fanout nets. A fanout number
of 1000 will be used for delay calculations involving these nets. (TIM-134)
Net 'ref_mem_u0/atom_gen[20].atom_instance/clk': 30698 load(s), 1 driver(s)
Net 'ref_mem_u0/atom_gen[2].atom_instance/rst': 1962 load(s), 1 driver(s)
Net 'ref_mem_u0/atom_gen[2].atom_instance/en': 1781 load(s), 1 driver(s)
Warning: The set_dont_touch_network command is used for clock clk, for which no
sources are specified. (UID-997)
1
Current design is 'motion_estimation'.
dc_shell>
`timescale 1ns / 1ps
vcs -debug +v2k +systemverilogext+sv +incdir+src ./lib/tcbn45gsbwp_120a/verilog/
tcbn45gsbwp_120a/tcbn45gsbwp.v ./top_netlist.v ./src/sim/motion_estimation_testa
ll.sv -sdf typ:motion_estimation:top.sdf
set lib_path "lib/tcbn45gsbwp_120a/frame_only_HVH_0d5_0/tcbn45gsbwp/LM";
set ADDITIONAL_SEARCH_PATH "$lib_path";
set TARGET_LIBRARY_FILES "tcbn45gsbwpbc.db";
set_app_var search_path "$search_path $ADDITIONAL_SEARCH_PATH";
set_app_var target_library $TARGET_LIBRARY_FILES;
set_app_var link_library "* $target_library";
read_ddc ./top.ddc
create_clock -name "clk" -period 1 -waveform { 0 .5 }
set_input_delay -clock clk -add_delay -max -rise .2 "{curr_data[7]} {curr_data[
6]} {curr_data[5]} {curr_data[4]} {curr_data[3]} {curr_data[2]} {curr_data[1]} {
curr_data[0]} {ref_data[7]} {ref_data[6]} {ref_data[5]} {ref_data[4]} {ref_data[
3]} {ref_data[2]} {ref_data[1]} {ref_data[0]} {ref_data[6]} {curr_data[4]} clk e
n {ref_data[3]} {curr_data[1]} {ref_data[7]} {curr_data[5]} {ref_data[0]} {ref_d
ata[4]} {curr_data[2]} {curr_data[6]} {ref_data[1]} rst {ref_data[5]} {curr_data
[3]} {curr_data[7]} {ref_data[2]} {curr_data[0]}"
set_input_delay -clock clk -add_delay -max -fall .2 "{curr_data[7]} {curr_data[6
]} {curr_data[5]} {curr_data[4]} {curr_data[3]} {curr_data[2]} {curr_data[1]} {c
urr_data[0]} {ref_data[7]} {ref_data[6]} {ref_data[5]} {ref_data[4]} {ref_data[3
]} {ref_data[2]} {ref_data[1]} {ref_data[0]} {ref_data[6]} {curr_data[4]} clk en
{ref_data[3]} {curr_data[1]} {ref_data[7]} {curr_data[5]} {ref_data[0]} {ref_da
ta[4]} {curr_data[2]} {curr_data[6]} {ref_data[1]} rst {ref_data[5]} {curr_data[
3]} {curr_data[7]} {ref_data[2]} {curr_data[0]}"
set_input_delay -clock clk -add_delay -min -rise .1 "{curr_data[7]} {curr_data[6
]} {curr_data[5]} {curr_data[4]} {curr_data[3]} {curr_data[2]} {curr_data[1]} {c
urr_data[0]} {ref_data[7]} {ref_data[6]} {ref_data[5]} {ref_data[4]} {ref_data[3
]} {ref_data[2]} {ref_data[1]} {ref_data[0]} {ref_data[6]} {curr_data[4]} clk en
{ref_data[3]} {curr_data[1]} {ref_data[7]} {curr_data[5]} {ref_data[0]} {ref_da
ta[4]} {curr_data[2]} {curr_data[6]} {ref_data[1]} rst {ref_data[5]} {curr_data[
3]} {curr_data[7]} {ref_data[2]} {curr_data[0]}"
set_input_delay -clock clk -add_delay -min -fall .1 "{curr_data[7]} {curr_data[
6]} {curr_data[5]} {curr_data[4]} {curr_data[3]} {curr_data[2]} {curr_data[1]} {
curr_data[0]} {ref_data[7]} {ref_data[6]} {ref_data[5]} {ref_data[4]} {ref_data[
3]} {ref_data[2]} {ref_data[1]} {ref_data[0]} {ref_data[6]} {curr_data[4]} clk e
n {ref_data[3]} {curr_data[1]} {ref_data[7]} {curr_data[5]} {ref_data[0]} {ref_d
ata[4]} {curr_data[2]} {curr_data[6]} {ref_data[1]} rst {ref_data[5]} {curr_data
[3]} {curr_data[7]} {ref_data[2]} {curr_data[0]}"
Information: High fanout net 'ref_mem_u0/atom_first/N2871' is not ideal_net. (OP
T-934)
`timescale 1ns / 1ps
vcs -debug +v2k +systemverilogext+sv +incdir+src ./lib/tcbn45gsbwp_120a/verilog/
tcbn45gsbwp_120a/tcbn45gsbwp.v ./icc.v ./src/sim/motion_estimation_testall.sv -s
df typ:motion_estimation:icc.sdf