ANALYTICAL MODELING AND SIMULATION OF

SHORT-CHANNEL EFFECTS IN A FULLY DEPLETED

DUAL-MATERIAL GATE (DMG) SOI MOSFET

A dissertation submitted in partial fulfillment of

the requirement for the degree of
Master of Science (Research)

by
Anurag Chaudhry

Under the Supervision of

Dr. M. Jagadesh Kumar

to the

Department of Electrical Engineering

Indian Institute of Technology Delhi
December, 2003
 CERTIFICATE

This is to certify that the thesis entitled ANALYTICAL MODELING AND

SIMULATION OF SHORT-CHANNEL EFFECTS IN A FULLY DEPLETED

DUAL-MATERIAL GATE (DMG) SOI MOSFET being submitted by Anurag

Chaudhry to the Indian Institute of Technology, Delhi, for the award of the degree of

Master of Science (Research) in Electrical Engineering Department is a bona fide

work carried out by him under my supervision and guidance. The research reports and

the results presented in this thesis have not been submitted in parts or in full to any other

University or Institute for the award of any other degree or diploma.

Dr. M. Jagadesh Kumar

Date : 2 Dec 2003 Associate Professor
Department of Electrical Engineering
Indian Institute of Technology
New Delhi - 110016

iii
 ACKNOWLEDGEMENTS

I wish to express my sincere gratitude to my supervisor Dr. M. Jagadesh Kumar

for his invaluable guidance and advice during every stage of this endeavour. I am greatly

indebted to him for his continuing encouragement and support without which, it would

not have been possible for me to complete this undertaking successfully. His insightful

comments and suggestions have continually helped me to improve my understanding.

I am deeply indebted to Dr. Krishnan V. Pagalthivarthi for his genuine guidance

and encouragement. I am grateful to both Dr. and Mrs. Krishnan for their loving

guidance and support. Their personal living example has provided me an unfailing

direction to use my education in the service of humanity at large.

Special thanks are due to Prof. D. Nagchoudhuri for his valuable suggestions and

questions during my synopsis presentation.

I am grateful to Prof. G. S. Visweswaran for allowing me to use the laboratory

facilities at all points of time.

I would also like to express my heartfelt gratitude to my friend Vipin who has

helped me with the typing of the thesis. My special thanks to my friends Rakesh,

Partheepan, Swadesh, Ramnarayan and others, who always inspired me and particularly

helped me in difficult times. Thanks are due to Ritesh Sharma for helping me in the lab.

My sincere thanks and acknowledgements are due to my mother and brother who

have constantly encouraged me for completing this project.

Anurag Chaudhry

v
 ABSTRACT

Silicon-on-insulator (SOI) has been the forerunner of the CMOS technology in the
last decade offering superior CMOS devices with higher speed, higher density, excellent
radiation hardness and reduced second order effects for submicron VLSI applications.
Recent experimental studies have invigorated interest in fully depleted (FD) SOI devices
because of their potentially superior scalability relative to bulk silicon CMOS devices.
Many novel device structures have been reported in literature to address the challenge of
short-channel effects (SCE) and higher performance for deep submicron VLSI
integration. However, most of the proposed structures do not offer simultaneous SCE
suppression and improved circuit performance. Others involve complicated processing
not amenable for easy integration into the present CMOS technology.
Dual-Material Gate (DMG) structure offers an alternative way of simultaneous
SCE suppression and improved device performance by careful control of the material
workfunction and length of the laterally amalgamated gate materials. A physics based
analytical model of surface potential along the channel in a FD DMG SOI MOSFET is
developed by solving 2-D Poisson’s equation. The model is used to investigate the
excellent immunity against SCE offered by the DMG structure. Further the model is
used to formulate an analytical expression of the threshold voltage, Vth. The results
clearly demonstrate the scaling potential of DMG SOI devices with a desirable threshold
voltage “roll-up” observed with decreasing channel lengths.
Numerical simulation studies were used to explore and compare the novel attributes
of DMG SOI MOSFET with a conventional single-material gate (SMG) device in terms
of circuit parameters like transconductance, drain conductance, voltage gain, leakage
current, on-current and Vth “roll-up”. An optimum gate length ratio of the two gate
lengths, L1/L2 = 1, and a workfunction difference, ∆W = 0.4 eV, between them
workfunctions is pointed by the simulation studies. In conclusion, we have demonstrated
the superior attributes offered by the DMG structure in FD SOI devices by developing a
simple analytical model and extensive simulation studies. The results presented in this
work are expected to provide incentive for further experimental exploration.

vii
 TABLE OF CONTENTS

CERTIFICATE ............................................................................................................................................. iii

ACKNOWLEDGEMENTS.............................................................................................................................v
ABSTRACT ................................................................................................................................................. vii
TABLE OF CONTENTS ...............................................................................................................................ix
LIST OF TABLES .........................................................................................................................................xi
LIST OF ILLUSTRATIONS....................................................................................................................... xiii

CHAPTER I.................................................................................................................................................1
INTRODUCTION...........................................................................................................................................1
1.1. MOTIVATION FOR PRESENT RESEARCH ........................................................................................1
1.2. NATURE OF THE PROBLEM ............................................................................................................3
1.2.1 Threshold voltage model ..............................................................................................................3
1.3. RECENT RESEARCH RELEVANT TO THE PROBLEM .........................................................................5
1.4. RESEARCH PROBLEM STATEMENT ................................................................................................5
1.5. THESIS ORGANIZATION..................................................................................................................6

CHAPTER II ...............................................................................................................................................9
SHORT-CHANNEL EFFECTS IN SOI: A REVIEW ....................................................................................9
2.1. INTRODUCTION..............................................................................................................................9
2.2. SHORT-CHANNEL EFFECTS .........................................................................................................11
2.2.1 Drain-Induced Barrier Lowering (DIBL)...................................................................................11
2.2.2 Back-Gate Biasing dependence ..................................................................................................14
2.1.3 Structure dependence .................................................................................................................15
2.3. PROPOSED SOLUTIONS ................................................................................................................17
2.3.1 Thin body FD SOI with raised source and drain .......................................................................18
2.3.2 Metal Source and Drain FDSOI MOSFET ................................................................................19
2.3.3 Metal gate FDSOI ......................................................................................................................20
2.3.4 Buried Insulator engineering .....................................................................................................21
2.3.5 Graded Channel FDSOI.............................................................................................................22
2.3.6 Ground-Plane FDSOI MOSFET ................................................................................................22
2.3.7 Multiple-Gate FDSOI MOSFET.................................................................................................23
2.3.8 HALO Doped SOI.......................................................................................................................25
2.4. DUAL-MATERIAL GATE ..............................................................................................................26
2.5. SUMMARY ...................................................................................................................................27

CHAPTER III............................................................................................................................................29
TWO-DIMENSIONAL MODEL OF SURFACE POTENTIAL IN A FULLY DEPLETED (FD)
DMG SOI MOSFET......................................................................................................................................29
3.1. INTRODUCTION............................................................................................................................29
3.2. DMG SOI STRUCTURE AND ITS PARAMETERS ............................................................................29
3.3. MATHEMATICAL FORMULATION .................................................................................................30
3.4. RESULTS AND DISCUSSION ..........................................................................................................37
3.4.1 Barrier Lowering........................................................................................................................37

ix
 3.4.2 Gate-Workfunction Engineering.................................................................................................39
3.4.3 L1/L2 Ratio dependence ..............................................................................................................41
3.4.4 Body Doping...............................................................................................................................42
3.4.5 Gate-Oxide Thickness variation .................................................................................................44
3.4.6 Thin-Film Thickness variation ...................................................................................................45
3.4.7 Electric Field Profile..................................................................................................................46
3.5. SUMMARY ...................................................................................................................................47

CHAPTER IV ............................................................................................................................................49
THRESHOLD VOLTAGE MODELING AND EVIDENCE FOR SUBDUED SHORT-CHANNEL
EFFECTS ......................................................................................................................................................49
4.1. INTRODUCTION............................................................................................................................49
4.2. MATHEMATICAL FORMULATION .................................................................................................49
4.3. RESULTS AND DISCUSSION ..........................................................................................................52
4.3.1 Scaling Characteristics ..............................................................................................................52
4.3.2 Minimum Surface Potential........................................................................................................54
4.3.3 Substrate-Bias dependence.........................................................................................................55
4.3.4 Thin-film doping dependence .....................................................................................................56
4.3.5 Buried Oxide Thickness dependence ..........................................................................................58
4.3.6 Gate Material Engineering.........................................................................................................59
4.4. SUMMARY ...................................................................................................................................60

CHAPTER V..............................................................................................................................................61
TWO-DIMENSIONAL SIMULATION STUDIES......................................................................................61
5.1. INTRODUCTION............................................................................................................................61
5.2. COMPUTER SIMULATION RESULTS ..............................................................................................62
5.2.1 Performance comparison with SMG SOI MOSFET ...................................................................63
5.2.2 Scaling characteristics at a fixed high workfunction gate length, L1 .........................................66
5.2.3 Effect of L1/L2 ratio at a fixed channel length, L ........................................................................67
5.2.4 Effect of workfunction difference (∆W) at a fixed channel length, L..........................................72
5.3. SUMMARY ...................................................................................................................................75

CHAPTER VI ............................................................................................................................................77
CONCLUSIONS ...........................................................................................................................................77
APPENDICES...............................................................................................................................................81
REFERENCES..............................................................................................................................................87
LIST OF PUBLICATIONS...................................................................................................................................95

x
 LIST OF TABLES

Table Page

Table 5.1 Device parameters used for simulation of DMG and SMG 62
SOI MOSFET’s.

xi
 LIST OF ILLUSTRATIONS

Figure Page

1.1 Cross-sectional view of the bulk-Si (left) and SOI (right) CMOS 2
devices [1].

2.1 Surface potential variation along the position in channel for 0.1 V 12
and 1.5 V drain voltages (linear and saturated case).

2.2 Three mechanisms determining SCE in SOI MOSFETs [24]. 12

2.3 Comparison of schematic energy band diagrams near the bottom of 13

the body between the long and short-channel fully depleted (FD)
nMOSFET’s [24].

2.4 Effects of the three mechanisms on threshold voltage dependence on 14

gate length [24].

2.5 Short channel effect in a FD SOI NMOS device with front gate oxide 14
of 9.2 nm, buried oxide of 400 nm, thin-film of 80 nm, with back
gate bias of 0 and –5 V [16].

2.6 Threshold voltage roll-off of FD SOI NMOS device with a front gate 15
oxide of 4.5 nm and various thin-film thicknesses [37].

2.7 Threshold voltage shift versus thin-film thickness for various channel 16
doping densities, biased at (a) VDS = 0.05 V, and (b) 1.5 V [38].

2.8 Threshold voltage versus channel length of an SOI NMOS device 17

with front gate oxide of 6 nm and a thin-film of 100 nm, and buried
oxide of 100 nm and 400 nm [39].

2.9 Electric field lines from the drain [40]. 18

2.10 Comparison of device structures for (a) a conventional MOS and (b) 19
a raised source/drain thin-body transistor. Thin-body device structure
can effectively suppress sub-surface leakage current [44].

2.11 Threshold voltage versus channel length of an FD SOI NMOS device 21

using polysilicon and tantalum gates [50].

xiii
2.12 Threshold voltage roll-off due to DIBL and CS versus buried oxide 21
permittivity [52].

2.13 Graded channel SOI MOSFET [53]. 22

2.14 Ground plane under (a) source and drain edge [57] or (b) channel 23
region [58].

2.15 Double-gate, triple-gate, gate all around (GAA) and Π-gate 24

SOI MOSFETs [70].

2.16 VTH roll-off and DIBL in double, triple, quadruple and Π-gate SOI 24
MOSFETs. Device width and thickness = 30 nm [70].

2.17 Cross-section of a single-halo (SH) SOI nMOSFET [77]. 26

3.1 Cross-sectional view of an n-channel fully depleted DMG-SOI 30

MOSFET.

3.2(a) Surface channel potential profiles of DMG-SOI MOSFET for 38

different drain biases for a DMG fully depleted SOI with channel
length L = 0.2 µm as obtained from the analytical model and 2-D
MEDICI simulation. The screening effect is distinctly visible.

3.2(b) Surface channel potential profiles of SMG-SOI MOSFET for 39

different drain biases with channel length L = 0.2 µm as obtained
from the 2-D MEDICI simulation.

3.3 Surface potential versus position along channel for two different gate 40
metal workfunction differences.

3.4 Plot of surface potential versus position in channel for different gate 41
metal workfunctions φM1 and φM2 of M1 and M2, keeping the
difference (φM1 - φM2) constant.

3.5 Variation of surface potential with position in channel for different 42

combination of gate lengths L1 and L2, keeping the sum (L1+L2)
constant.

3.6(a) Surface potential plot for two different substrate doping 43

concentrations for a DMG SOI.

xiv
3.6(b) Surface potential plot for two different substrate doping 43
concentrations for a SMG SOI.

3.7 Variation of surface potential with position in channel for two 44

different front-gate oxide thicknesses.

3.8 Variation of surface potential along the channel for two different 45
thin-film thicknesses.

3.9 Variation of electric field along the channel shown for region close to 46
drain.

4.1 Threshold voltage variation with channel length compared for DMG 52
and SMG SOI devices. L1 is fixed at 0.1 µm for the DMG SOI
device and φM = 4.77 V for the SMG SOI MOS.

4.2 Threshold voltage variation with channel length for DMG SOI 53
devices.

4.3 Minimum surface potential as a function of channel length for two 54

different thin-film thicknesses as extracted from MEDICI and the
analytical model. L1 is kept fixed at 0.1 µm.

4.4 Threshold voltage variation with channel length for different 55

substrate biasing.

4.5 Threshold voltage variation with channel length for substrate biasing 56
of 0 V and -2 V with L1 fixed at 50 nm.

4.6 Threshold voltage variation with channel length for different body 57
doping density.

4.7 Vth variation with channel length for different body doping density 57
with L1 = 50 nm.

4.8 Threshold voltage variation with channel length for different buried 58
oxide thickness.

4.9 Threshold voltage variation as a function of channel length for buried 59

oxide thicknesses of 100 nm and 400 nm with L1 fixed at 50 nm.

4.10 Threshold voltage variation with gate workfunction difference at a 60

fixed channel, L = 0.5 µm for two different L1/L2 ratio.

xv
 5.1 Output characteristics compared for a DMG SOI with SMG SOI 63
MOSFET.

5.2 Gate characteristics compared for a DMG SOI with SMG SOI 64
MOSFET.

5.3(a) Electric field profile along the surface of the channel for DMG and 65
SMG SOI MOSFET's.

5.3(b) Electron velocity profile along the surface of the channel for DMG 65
and SMG SOI MOSFET's.

5.4 Comparison of threshold voltage variation with channel for DMG 66

and SMG SOI MOSFET’s.

5.5 Variation of Vth,lin, Vth,sat and VDIBL with gate length L1 for a DMG 67
SOI MOSFET at a fixed channel length, L = 0.3µm.

5.6 Variation of Ioff and Ion with gate length L1 for a DMG SOI MOSFET 68
at a fixed channel length, L = 0.3µm. L1 = 0 corresponds to SMG
SOI.

5.7(a) Variation of gm and gd with gate length L1 for a DMG SOI MOSFET 69
at a fixed channel length, L = 0.3 µm. L1 = 0 corresponds to SMG
SOI.

5.7(b) Variation of voltage gain, gm/gd, with gate length L1 for a DMG SOI 69
MOSFET at a fixed channel length, L = 0.3 µm. L1 = 0 corresponds
to SMG SOI.

5.8 Variation of Vth,lin, Vth,sat and VDIBL with gate length L1 for a DMG 70
SOI MOSFET at a fixed channel length, L = 0.2 µm.

5.9 Variation of Ioff and Ion with gate length L1 for a DMG SOI MOSFET 71
at a fixed channel length, L = 0.2 µm. L1 = 0 corresponds to SMG
SOI.

5.10(a) Variation of gm and gd with gate length L1 for a DMG SOI MOSFET 71
at a fixed channel length, L = 0.2 µm. L1 = 0 corresponds to SMG
SOI.

xvi
5.10(b) Variation of voltage gain, gm/gd, with gate length L1 for a DMG SOI 72
MOSFET at a fixed channel length, L = 0.2 µm. L1 = 0 corresponds
to SMG SOI.

5.11 Variation of Vth,lin, Vth,sat and VDIBL with workfunction difference, ∆W 73

for a DMG SOI MOSFET at a fixed channel length, L = 0.3µm.

5.12 Variation of Ioff and Ion with workfunction difference, ∆W for a DMG 74
SOI MOSFET at a fixed channel length, L = 0.3µm.

5.13 Variation of gm and gd with workfunction difference, ∆W for a DMG 74

SOI MOSFET at a fixed channel length, L = 0.3µm.

5.14 Variation of voltage gain, gm/gd, with workfunction difference, ∆W 75

for a DMG SOI MOSFET at a fixed channel length, L = 0.3 µm.

xvii
 CHAPTER I
INTRODUCTION

1.1 Motivation For Present Research

In a conventional, bulk-silicon microcircuit, the active elements are located in a

thin surface layer (less than 0.5 µm of thickness) and are isolated from the silicon body

with a depletion layer of a p-n junction. The leakage current of this p-n junction

exponentially increases with temperature, and is responsible for several serious reliability

problems. Excessive leakage currents and high power dissipation limit the operation of

microcircuits at high temperatures. Parasitic n-p-n and p-n-p transistors formed in

neighboring insulating tubs can cause latch-up failures and significantly degrade circuit

performance.

Silicon-on-insulator (SOI) technology employs a thin layer of silicon (tens of

nanometers) isolated from a silicon substrate by a relatively thick (hundreds of

nanometers) layer of silicon oxide. The SOI technology dielectrically isolates

components and in conjunction with the lateral isolation, reduces various parasitic circuit

capacitances, and thus, eliminates the possibility of latch-up failures. Figure 1.1 shows

the cross-section of the bulk and SOI MOS devices. As shown in the figure, owing to the

buried oxide isolation structure, SOI technology offers superior devices with excellent

radiation hardness and high device density. Without the reverse-biased junctions used for

isolation as in bulk CMOS, leakage current is small. In addition, for scaling devices into

deep-submicron regime, SOI devices are more suitable with their steeper subthreshold

slope which facilitates scaling of the threshold voltage for low-voltage low-power

applications.

1
 400 nm 5 – 8 nm
Field oxide 50 nm Si
Gate oxide
n+ poly p+ poly
n+ p n+ p+ n p+
n+ poly p+ poly
n+ n+ p+ p+ 100 – 200 nm Buried Oxide
p - epi n - Well

Silicon Handle Wafer

p+ Substrate

Fig. 1.1: Cross-sectional view of the bulk-Si (left) and SOI (right) CMOS devices [1].

Depending on the thickness of the silicon layer, MOSFETs will operate in fully

depleted (FD) or partially depleted (PD) regimes. When the channel depletion region

extends through the entire thickness of the silicon layer, the transistor operates in a FD

mode. PD transistors are built on relatively thick silicon layers with the depletion depths

of the fully powered MOS channel shallower than the thickness of the silicon layer. The

FD devices have several advantages compared to the PD devices: free from kink effect

[2], enhanced subthreshold swing [3], highest gains in circuit speed, reduced power

requirements and highest level of soft-error immunity [4]. Moreover it has been shown

that the total masks needed in the front-end process for FD SOI devices are less than half

that are required for bulk CMOS devices [5].

During the past decade, excellent high-speed and performance have been achieved

through improved design, use of high quality material and shrinking device dimensions

[6-7]. However, with the reduction of channel length, control of short-channel effects is

one of the biggest challenges in further down-scaling of the technology. The

predominating short-channel effects are a lack of pinch-off and a shift in threshold

voltage with decreasing channel length as well as drain induced barrier lowering (DIBL)

and hot-carrier effect at increasing drain voltage. In contrast to the bulk device, front

gate of the SOI device has better control over its active device region in the thin-film and

2
hence charge sharing effects from source/drain regions are reduced. However, the thin-

film thickness has to reduce to the order of 10 nm to significantly improve the device

performance, which becomes prohibitively difficult to manufacture and causes large

device external resistance due to shallow source/drain extension (SDE) depths.

Long et al [8-9] recently demonstrated that the application of dual-material gate

(DMG) in bulk MOSFET and HFET leads to a simultaneous transconductance

enhancement and suppression of short-channel effects due to the introduction of a step

function in the channel potential. In a DMG-MOSFET, the work function of metal gate 1

(M1) is greater than metal gate 2 (M2) i.e., φM1 > φM2 for an n-channel MOSFET and

vice-versa for a p-channel MOSFET. The aim of this work is, therefore, to study for the

first time the potential benefits offered by the DMG gate in suppressing the short-channel

effects in FD SOI MOSFETs using two-dimensional modeling and numerical simulation.

The model provides an efficient tool for further design and characterization of the novel

DMG-SOI MOSFET. The effects of varying device parameters can easily be

investigated using the simple models presented in this work.

1.2 Nature of the Problem

The present work involves two distinct features, viz. (a) Two-dimensional modeling

of surface potential and threshold voltage of a FD SOI with DMG and (b) Numerical

simulation studies using MEDICI [10] to investigate novel features offered by the DMG

in a fully depleted (FD) SOI MOSFET.

1.2.1 Threshold voltage model

One of the key parameters that characterize short-channel effects is the degradation

of the device threshold voltage with decreasing channel length. The optimization of the

3
threshold voltage reduction is very important for both process and device engineers, and

plays a major role for achieving a highly improved CMOS technology performance.

Several models for the threshold voltage of short-channel FD SOI MOSFETs have

been reported in the literature [11-16]. Veeraraghavan and Fossum [11] formulated a

charge sharing model predicting a L-1 threshold voltage dependence. The charge sharing

modeling scheme assumes a constant surface potential, regardless of any drain bias, and

therefore does not account for the drain bias associated drain induced barrier lowering

(DIBL). Additionally, because of the coupling effect between the front gate and the back

gate, the charge sharing model in [11] requires the use of a priori empirical fitting

parameters, and therefore is not well suited for circuit analysis or statistical modeling.

Woo et al. [11] and Guo et al. [14] developed short-channel threshold voltage

models by solving the two-dimensional (2D) Poisson's equation. However, due to the

complexity of the solution and complicated mathematical operations required, physical

insights into the dependence of short-channel effects on the device parameters are

masked. This dependence is an important factor needed by both process and device

engineers to optimize the device short-channel effects.

Banna et al. [15] used a quasi 2D approach and reported a threshold voltage model

but it requires the use of an empirical fitting parameter which needs additional accurate

measurements because small relative errors in measurements could give a large error in

the fitting parameter value.

In this work, a simple analytical model for the threshold voltage of short-channel

FD DMG SOI MOSFET is derived based on the approach suggested by Young [12] to

consider a parabolic trial function for the potential distribution in the silicon film.

4
1.3 Recent Research Relevant to the Problem

The concept of a Dual-Material Gate is similar to what was achieved by applying

different gate-bias in split-gate [17] structure first proposed by M. Shur. The challenge to

satisfactorily realize the split-gate FET is the inherent fringing capacitance between the

two metal gates which increases as the separation between them is reduced.

In 1999, Long et. al. [8] proposed a new gate structure called the dual material gate

(DMG)-MOSFET. Unlike the asymmetric structures employing doping engineering [18-

21] in which the channel field distribution is continuous, gate-material engineering with

different workfunctions introduces a field discontinuity along the channel, resulting in

simultaneous transport enhancement and suppressed SCEs. Zhou [22] suggested a way

in which the Hetero-Material Gate (HMG) MOSFET can be fabricated by inserting one

additional mask in the bulk CMOS processing technology and demonstrated the novel

characteristics of this new type of MOSFET by simulation studies.

However, with SOI rapidly emerging as the technology for next-generation VLSI,

the effect of DMG in submicron MOS technology remains to be investigated. In this

work, for the first time we have developed an analytical model for surface potential and

threshold voltage to aid in understanding the efficacy of DMG structure in suppressing

short channel effects in a FD SOI MOSFET. The model results are verified by numerical

simulations which are further used to extract the novel features offered by the new device

structure.

1.4 Research Problem Statement

In this dissertation, novel features offered by the introduction of a Dual-Material

Gate (DMG) in fully depleted silicon-on-insulator are studied by means of two-

5
dimensional analytical modeling and numerical simulation studies. This is accomplished

in terms of the following intermediate stages:

i) A physics based 2-D analytical model for the surface potential distribution in

the SOI thin-film of a fully depleted MOSFET is developed and verified

against numerical simulation results.

ii) Threshold voltage model for a fully-depleted DMG on SOI is developed

based on the surface potential model to show the efficacy of the DMG

structure in suppressing short-channel effects.

iii) Two-dimensional numerical simulation studies are used to investigate and

compare the benefits of DMG structure over a conventional single material

gate (SMG) in a fully-depleted SOI MOSFET.

1.5 Thesis Organization

The dissertation is divided into six chapters and its outline is described as given

below:

Chapter I: Introduction.

Fundamental concepts related to SOI devices and its advantages & disadvantages,

objectives of the project and outline of the thesis.

Chapter II: Short-channel effects in SOI: A review.

This chapter analyzes the origin and effect of the short-channel effects in SOI

MOSFETs. Various methods employed to overcome short-channel effects are also

summarized and the feasibility of dual-material gate (DMG) structure in suppressing

short-channel effects is discussed.

6
Chapter III: Two-dimensional model of the surface potential in a fully depleted

(FD) DMG-SOI MOSFET.

A physics based 2-D model for the surface potential variation along the channel in

fully depleted Dual-Material Gate silicon-on-insulator (DMG) SOI MOSFET’s is

developed. The model details the role of various MOS parameters like source/drain

and body doping concentrations, the lengths of the gate metals and their work

functions, applied drain and substrate biases, the thickness of the gate and buried

oxide in influencing the surface potential.

Chapter IV: Analytical modeling of threshold voltage and evidence for subdued

short-channel effects in thin-film DMG-SOI MOSFET.

This chapter demonstrates the development of threshold voltage model for the DMG

SOI MOSFET and illustrates the role of DMG structure in suppressing short-channel

effects.

Chapter V: Two-dimensional simulation studies.

This chapter presents the novel features offered by the DMG SOI to enhance the

MOSFET performance through 2-D numerical simulation studies. The characteristics

of DMG SOI MOSFET are compared with a conventional SMG SOI MOSFET.

Chapter VI: Conclusions.

7
 CHAPTER II
SHORT-CHANNEL EFFECTS IN SOI: A REVIEW

2.1 Introduction

In order to realize higher-speed and higher-packing density MOS integrated

circuits, the dimensions of MOSFET’s have continued to shrink according to the scaling

law proposed by Dennard et al. [23]. However, the power consumption of modern

VLSI’s has become rather significant as a result of extremely large integration. Reducing

this power is strongly desired. Choosing a lower power supply voltage is an effective

method. However, it leads to the degradation of MOSFET current driving capability.

Consequently, scaling of MOS dimensions is important in order to improve the

drivability, and to achieve higher-performance and higher-functional VLSI’s.

We can say that the story of MOSFET scaling is the history of how to prevent

short-channel effects (SCE) [24]. SCE causes the dependence of device characteristics,

such as threshold voltage, upon channel length. This leads to the scatter of device

characteristics because of the scatter of gate length produced during the fabrication

process. Moreover, SCE degrades the controllability of the gate voltage to drain current,

which leads to the degradation of the subthreshold slope and the increase in drain off-

current. Thinning gate oxide and using shallow source/drain junctions are known to be

effective ways of preventing SCE.

The detrimental short-channel effects occur when the gate length is reduced to the

same order as the channel depth. When the channel length shrinks, the absolute value of

threshold voltage becomes smaller due to the reduced controllability of the gate over the

channel depletion region by the increased charge sharing from source/drain. The

9
predominating features of SCE are a lack of pinchoff and a shift in threshold voltage with

decreasing channel length as well as drain induced barrier lowering (DIBL) and hot-

carrier effect at increasing drain voltage. Increased charge sharing from source/drain

degrades the controllability of gate voltage over channel current. This degradation is

described as charge sharing by the gate and drain electric fields in the channel depletion

layer in Poon and Yau’s model [25], which was reported as the first SCE model.

This description can be applied to conventional MOSFET’s fabricated in a bulk

silicon wafer. What about thin-film SOI MOSFET’s ? They are attractive devices for

low-power high-speed VLSI applications because of their small parasitic capacitance

[26]. Young [12] analyzed the SCE using a device simulator, and concluded that SCE is

well suppressed in thin-film SOI MOSFET’s when compared to bulk MOSFET’s. In

general, it is believed that thin-film SOI MOSFET’s have a higher immunity to SCE

compared with bulk MOSFET’s. This may be due to the difference in source/drain

junction depths between the two kinds of devices. For instance, the thickness of the

silicon film, which corresponds to the source/drain junction depth of 50–100 nm, is

common in 0.25–0.35 µm SOI MOSFET’s. It is extremely shallow compared with the

junction depth of 100–200 nm in 0.25–0.35 µm gate bulk MOSFET’s. However, to take

advantage of the ameliorated SCEs in deep-submicron fully-depleted SOI, tSi must be

considerably smaller than the source/drain junction depth (tSi ∼ 10-15 nm). Moreover,

there exits a strong coupling through the buried oxide in thin-film devices consequently,

very thin buried oxides (tb ∼ 100 nm) are needed which trade-offs with junction

capacitance considerations. Hence, for small-geometry SOI CMOS devices, short-

channel effects are important [27]-[32].

10
2.2 Short-channel effects

Short-channel effects (SCE) can be physically explained by the so-called drain-

induced barrier lowering (DIBL) effect which causes a reduction in the threshold voltage

as the channel length decreases. But, in an SOI device, SCE is also influenced by thin-

film thickness, thin-film doping density, substrate biasing, buried oxide thickness and

processing technology.

2.2.1 Drain-Induced Barrier Lowering (DIBL)

In the weak inversion regime there is a potential barrier between the source and the

channel region. The height of this barrier is a result of the balance between drift and

diffusion current between these two regions. The barrier height for channel carriers

should ideally be controlled by the gate voltage to maximize transconductance. As

indicated in Fig. 2.1, drain-induced barrier lowering (DIBL) effect [33] occurs when the

barrier height for channel carriers at the edge of the source reduces due to the influence of

drain electric field, upon application of a high drain voltage. This increases the number

of carriers injected into the channel from the source leading to an increased drain off-

current. Thus the drain current is controlled not only by the gate voltage, but also by the

drain voltage.

For device modeling purposes this parasitic effect can be accounted for by a

threshold voltage reduction depending on the drain voltage [34].

11
 2.2

2.0

1.8
Surface Potential, φ S (V)
1.6

1.4
VDS = 1.5 V
1.2

1.0
VDS = 0.1 V
0.8

0.6 barrier lowe ring

0.4

0.2
0.15 0.20 0.25 0.30 0.35 0.40 0.45

Lateral position, x (µ m)
Fig. 2.1: Surface potential variation along the position in channel for 0.1 V and 1.5 V drain
voltages (linear and saturated case).

In addition to the surface DIBL, there are two unique features determining SCEs in

thin-film SOI devices viz. (a) positive bias effect to the body due to the accumulation of

holes generated by impact ionization near the drain and (b) the DIBL effect on the barrier

height for holes at the edge of the source near the bottom, as illustrated in Fig. 2.2.

Fig. 2.2: Three mechanisms determining SCE in SOI MOSFETs [24].

12
 Holes generated near the drain due to impact ionization accumulate in the body

region, and then positively bias the body, reducing VT. This positive bias effect leads to

VT lowering for all gate lengths, including rather long gates such as 2 µm. The hole

generation rate due to impact ionization increases as gate length decreases under a fixed

value of VD. This effect is predominant in PD SOI nMOSFETs and results in so-called

floating body effects (FBE) [35], [36].

The DIBL effect on the barrier height for holes reduces the positive bias effect to

the body because the accumulated holes in the body can more easily surmount the barrier

and flow to the source. As a result fewer number of accumulated holes remain which

weakens the VT lowering. The potential near the bottom in the thin-film increases as gate

length decreases due to the drain electric field. This leads to the lowering of the barrier

height for holes at the source edge near the bottom with shorter gate lengths. Fig. 2.3

compares the schematic energy band diagrams at threshold condition between short and

long channels MOSFET’s. The comparison is done near the bottom of the thin-film from

the source to the drain. With shorter gate lengths, the barrier height for holes near the

bottom is lowered by the influence of the drain electric field, and holes accumulated in

the body region can more easily flow into the source.

Fig. 2.3: Comparison of schematic energy band diagrams near the bottom of the body between
the long and short-channel fully depleted (FD) nMOSFET’s [24].

13
 DIBL for electrons

Threshold Voltage
Accumulation of holes in body
due to impact ionization
DIBL for holes

Gate Length
Fig. 2.4: Effects of the three mechanisms on threshold voltage dependence on gate length [24].

Due to these three mechanisms, VT dependence upon gate length in FD

nMOSFET’s becomes small, as illustrated in Fig. 2.4.

2.2.2 Back-Gate Biasing dependence

Fig. 2.5 shows the short-channel effect of the FD SOI NMOS device with a front

gate oxide of 9.2 nm, a buried oxide of 400 nm, and a thin-film of 80 nm, biased at the

back gate bias of 0 and –5 V [16].

VSUB = - 5 V
Threshold Voltage (V)

VSUB = 0 V

tf = 9.2 nm
tSi = 80 nm
tbox = 400 nm
N A = 1x1017cm-3

Channel Length (µm)

Fig. 2.5: Short channel effect in a FD SOI NMOS device with front gate oxide of 9.2 nm, buried
oxide of 400 nm, thin-film of 80 nm, with back gate bias of 0 and –5 V [16].

14
 As shown in the Fig. 2.5, at a negative back gate bias of –5 V, the threshold voltage

is lifted upward as compared to the back gate bias of 0 V. The extent of the upward shift

when the back gate bias becomes negative is smaller for a device with shorter channel

length, which implies that SCE seems to improve. With a shorter channel, the

controllability over the vertical direction of the channel region from the source/drain

seems to be reduced at a more negative back gate bias, hence its back gate bias effect is

smaller.

2.2.3 Structure dependence

In addition to the drain and back gate biasing dependences, the SCE of an SOI

MOS device is also influenced by the thin-film thickness. Fig. 2.6 shows the threshold

voltage roll-off of the FD SOI NMOS device with a front gate oxide of 4.5 nm for

various thin-film thicknesses [37].

0.6
TSOI
Threshold Voltage Roll-off (V)

0.4 50 nm
40 nm
0.2 30 nm
NMOS
0

-0.2 TSOI
30 nm
-0.4 40 nm
PMOS 50 nm
-0.6
0 0.1 0.2 0.3 0.4 0.5 0.6

Gate Length (µm)

Fig. 2.6: Threshold voltage roll-off of FD SOI NMOS device with a front gate oxide of 4.5 nm
and various thin-film thicknesses [37].

15
 As shown in Fig. 2.6, when the thin-film thickness is reduced, for both NMOS and

PMOS devices, the SCE becomes smaller since the controllability of the front gate over

the active channel region is stronger and the source/drain has less influence in the

channel.

The short channel effect is also dependent on the thin-film doping density. Fig. 2.7

shows the threshold voltage shift versus the thin-film thickness of an SOI NMOS device

with a front gate oxide of 5 nm and a buried oxide of 360 nm for various channel doping

densities, biased at (a) VDS = 0.05 V, and (b) 1.5 V [38]. As shown in Fig. 2.7, when the

thin-film thickness exceeds a critical thickness the device operates in the PD regime.

Below this specific thickness the device operates in the FD regime. In the FD regime,

SCE is smaller with a lighter thin-film doping density, which is opposite to that in the PD

regime.

The influence of source/drain to the channel region via the buried oxide can also

worsen the SCE. Fig. 2.8 shows the short-channel effect of an SOI NMOS device with a

front gate oxide of 6 nm, thin-film of 100 nm for buried oxide thickness of 100 nm and

400 nm [39]. For a device with thinner buried oxide, the SCE is lessened.
∆VT(DIBL) (V)
∆VT(SCE) (V)

Silicon Thickness, tsi (nm) Silicon Thickness, tsi (nm)

Fig. 2.7: Threshold voltage shift versus thin-film thickness for various channel doping densities,
biased at (a) VDS = 0.05 V, and (b) 1.5 V [38].

16
 0.7
Gate width = 10 µm

Threshold Voltage (V)

0.6

0.5
with 100 nm Buried oxide
with 400 nm Buried oxide

0.4
0.1 1 10

Gate Length (µm)

Fig. 2.8: Threshold voltage versus channel length of an SOI NMOS device with front gate oxide
of 6 nm and a thin-film of 100 nm, and buried oxide of 100 nm and 400 nm [39].

With thinner buried oxide, the compressive stress is higher. Hence, during the

thermal process in fabrication, boron dopants in the thin film cannot diffuse easily. As a

result, the doping density of thin-film is higher and its threshold voltage is higher. As the

doping density of thin-film is raised, the SCE is reduced.

2.3 Proposed Solutions

As the gate length of the MOSFET is scaled into the sub-100-nm regime for

improved performance and density, the requirements for body-doping concentration, gate

oxide thickness, and source/drain (S/D) doping profiles to control short-channel effects

become increasingly difficult to meet when conventional device structures based on bulk

silicon substrates are employed. The heavy channel doping required to provide adequate

suppression of SCE results in degraded mobility and enhanced junction leakage. The

aggressive reduction of the gate dielectric thickness for reduced SCE and improved drive

current leads to increased direct tunneling gate leakage current and standby power

consumption, and also raises concerns regarding the gate oxide reliability.

Fig. 2.9 schematically shows the electric field lines from the drain encroaching on

the channel region.

17
 Fig. 2.9: Electric field lines from the drain [40]

As shown in the figure, the gate electrode shields the channel region from those

lines at the top of the device, but electric field lines penetrate the device laterally and

from underneath, through the buried oxide and the silicon wafer substrate causing the

undesirable DIBL for the charge carriers.

Several device structures have been proposed to alleviate the degrading effect of

SCE on performance in deep sub-micron SOI MOSFET’s as discussed below.

2.3.1 Thin body FD SOI with raised source and drain

Reduction of short-channel effects in FD SOI MOSFETs requires the use of thin

silicon films to eliminate the sub-surface leakage paths. A device structure that

implements this concept is the thin-body MOSFET [41]-[42]. In thin-body MOSFET, the

source-to-drain current is restricted to flow in a region close to the gate for superior gate

control, as illustrated in Fig. 2.10. Since it does not rely on a heavily-doped channel for

the suppression of short-channel effects, it avoids the problems of mobility degradation

due to impurity scattering and threshold voltage fluctuation due to the random variation

of the number of dopant atoms in the channel region of nanoscale transistors [43].

18
 raised
source/ L
gate
drain gate
spacer spacer

p+ n p+
p+ p+
Sub-surface SiO2
n-Si Leakage path

Fig. 2.10: Comparison of device structures for (a) a conventional MOS and (b) a raised
source/drain thin-body transistor. Thin-body device structure can effectively suppress sub-
surface leakage current [44].

The device shown in Fig. 2.10 has a thin-body on insulator structure [45], [46] and

is essentially an extension of the fully depleted SOI transistor. Since a thin source/drain

(S/D) region would contribute a high series resistance that degrades the drive current, a

raised S/D is introduced to avoid the series resistance problem. Reference [46]

demonstrated raised S/D formation by poly-Si deposition followed by an etch-back.

Nevertheless, parasitic capacitances between the raised S/D and the gate are inherent in

this device structure. This is expected to adversely impact the device speed and power

consumption. An attempt to reduce the parasitic capacitance by increasing the distance

between the raised S/D and the gate leads to an increase in series resistance.

2.3.2 Metal Source and Drain FDSOI MOSFET

Another proposed technique for reducing the source and drain resistance in thin-

film FDSOI MOSFETs consists in using metal (or silicide) source and drain. However,

the formation of Schottky barriers between the source/drain and the channel must be

avoided. The formation of a low (ideally zero) Schottky barrier is needed to insure the

formation of an ohmic contact between the source/drain and the channel. Since the

Schottky barrier varies with the applied gate bias in inversion-mode devices, it is more

19
appropriate to use accumulation-mode devices when metal source/drain structures are

used, as the surface potential remains constant when an accumulation channel is created

[47][48].

2.3.3 Metal gate FDSOI

As the transistors are aggressively scaled down to sub-80 nm, problems such as

poly-Si gate depletion, boron penetration, and high gate resistance are aggravated [49].

Alternative gate electrodes, such as metal gates, are promising to address these issues.

Fig. 2.11 shows the threshold voltage versus the channel length of an FD SOI NMOS

device with a front gate oxide of 5 nm, a thin film of 100 nm and a buried oxide of 420

nm, using polysilicon and tantalum gates [50]. The use of tantalum gate is to facilitate

the adjustment of the threshold voltage of an SOI device without raising the thin-film

doping density substantially by taking advantage of the workfunction of tantalum. By

using metal (tantalum) as the front-gate material the problem of polysilicon gate

depletion associated with polysilicon gates is removed and therefore, SCE is smaller.

For PD SOI, metal gates with workfunction of 0.1 ∼ 0.2 eV away from the silicon

band edges enable the use of relatively low halo dose. This reduces the possibility of

band-to-band tunneling without compromising performance. Whereas for an FD SOI, a

metal gate with workfunction close to the band edges would require a high channel

doping to meet the off-current specifications. The need for high doping concentration

increases Vth fluctuations due to variation in thin-film thickness in addition to serious

mobility degradation. Midgap gates are desirable for FD SOI MOSFETs in such a

scenario [51].

20
 Threshold Voltage (V)

Gate Length (µm)

Fig. 2.11: Threshold voltage versus channel length of an FD SOI NMOS device using polysilicon
and tantalum gates [50].

2.3.4 Buried Insulator engineering

Fig. 2.12 shows the variation of threshold voltage roll-off due to DIBL and charge

sharing (CS) with permittivity of buried oxide for SOI MOSFETs with channel lengths

30 nm and 500 nm [52]. The reduction of buried oxide permittivity improves the DIBL

effect due to the reduced field penetration into the buried oxide from the drain, but, it

does not affect the charge sharing significantly.

0.3
DIBL (30 nm)
Threshold voltage shift, ∆VT

0.2

0.1
CS (30 nm)

DIBL (500 nm)

0
0 5 10 15 20

Buried oxide permittivity, ε box

Fig. 2.12: Threshold voltage roll-off due to DIBL and CS versus buried oxide permittivity [52].

21
2.3.5 Graded Channel FDSOI

Fig. 2.13 shows the threshold voltage versus channel length of an FD SOI NMOS

device with a front gate oxide of 7 nm, a thin-film of 50 nm and a buried oxide of 120 nm

for a (a) uniformly doped channel and (b) graded channel [53]. In the device with graded

channel, in the centre of the channel, the doping density is the same as for the device with

uniformly doped channel whereas near source/drain regions more highly doped regions

are generated via the gate-edge (GE) implant techniques. As shown in the Fig, compared

to the uniformly doped channel, GE implanted graded channel improves the SCE

substantially, especially at large drain voltage.

Short-channel effects in PD SOI devices can be reduced by increasing the doping

density of the thin-film. However, a very high doping density of the thin-film may lead

to an undesirable excessive magnitude in the threshold voltage. Using HALO doping (a

local region with high doping density than that of the channel region) and highly non-

uniformly doped channel also reduces DIBL effects in PD SOI MOSFETs [54].

2.3.6 Ground-Plane FDSOI MOSFET

To keep electric field lines from the drain from propagating into the channel region

a ground-plane can be formed in the silicon substrate underneath the buried oxide.
Threshold Voltage, Vth (V)

Threshold Voltage, Vth (V)

Uniform Channel (GE =0) Graded Channel (GE =12 x 1012 cm-2)

VDS = 0.1 V

VDS = 0.1 V
VDS = 1.5 V
VDS = 1.5 V

Channel Length, L (µm) Channel Length, L (µm)

Fig. 2.13: Graded channel SOI MOSFET [53].

22
 (a) (b)
Fig. 2.14: Ground plane under (a) source and drain edge [57] or (b) channel region [58].

Fig. 2.14 shows that a heavily doped electric-field stop can be placed in the

substrate either underneath the boundary between channel and source/drain or underneath

the channel region itself. This field stop effectively improves SCE and subthreshold

slope. [55][56].

2.3.7 Multiple-Gate FDSOI MOSFET

To prevent the encroachment of electric field lines from the drain on the channel

region, special gate structures can be used as shown in Fig. 2.15. Such "multiple"-gate

devices include double-gate transistors, triple-gate devices such as the quantum wire [59],

the FinFET [60] and ∆-channel SOI MOSFET [61], and quadruple-gate devices such as

the gate-all-around device [29], the DELTA transistor [62][63], and vertical pillar

MOSFETs [64],[65].

Fig. 2.15: Double-gate, triple-gate, gate all around (GAA) and Π-gate SOI MOSFETs [70].

23
 The double-gate concept was first reported in 1984 [66] and has been fabricated by

several groups since then. The use of a double gate results in enhanced transconductance,

due to the volume inversion effect [30][67] and better subthreshold slope. The

fabrication process, however, is considered unpractical for commercial applications

because it uses lateral epitaxial overgrowth or the etching of a cavity underneath the

devices [29][68]. Also, since the thickness of silicon between the two gates is smaller

than the physical gate length, the most critical lithography step in printing the double-gate

transistor becomes patterning of the thin-film, rather than the physical gate length

patterning [69].

Fig. 2.16 shows the DIBL and threshold voltage roll-off as a function of gate

voltage for double, triple, quadruple and Π-gate devices. The best performance is

obtained from the quadruple gate, but Π-gate is close second. The results show the

efficient shielding of the channel by the gate electrode from the electric field lines

originating from the drain region.

500
Double Gate
DIBL (mV)

400 Triple Gate

GAA
300
Π Gate
200
DIBL
100

0
∆VT (mV)

-100
∆VT
-200

-300
20 30 40 50 60 70 80 90

Gate Length (nm)

Fig. 2.16: VTH roll-off and DIBL in double, triple, quadruple and Π-gate SOI MOSFETs. Device
width and thickness = 30 nm [70].

24
2.3.8 HALO Doped SOI

With continuous device scaling down to 100 nm channel length and less, the

HALO (or pocket) implantations have been introduced to better control the short-channel

effects. In digital applications HALO implantations have the purpose of reducing the off-

state leakage current while maximizing transistor linear and saturated drive currents.

While for analog applications it has been shown that HALO implantation is needed for

base-band applications using longer channel, it has detrimental effect for high speed

applications using minimum channel transistors in strong inversion [71]. Excessive

HALO implantation in PD SOI transistors increases the kink effect. HALO implantation

is also known to degrade the distortion characteristics when the SOI devices are used as

resistors [71]. Taur [72] demonstrated that a super-halo, a highly non-uniform 2-D

dopant profile in the channel and the body region effectively controls short-channel

effects in 25 nm MOSFET. A properly scaled super-halo is able to suppress the potential

barrier lowering both in the inversion and the body depletion region. When strong halo is

used, drain-halo (or body) band-to-band tunneling leakage can be a considerable

contributor to the total off-state leakage current at room temperature. Substrate-injection

gate current also increases in devices with stronger halo implant.

Recently, asymmetric single halo (SH) MOSFET structures have been introduced

for bulk [73]-[74] as well as for SOI MOSFETs [75]-[76] to adjust the threshold voltage

and improve the device SCE and hot carrier effects (HCE). These devices also achieve

higher drive currents by exploiting the velocity overshoot phenomenon [73], which is an

advantage in mixed mode analog/digital circuits. The schematic cross section of a typical

SH SOI n-type MOSFET is shown in Fig.2.17 [77]. It has been shown that these devices

25
 Fig. 2.17: Cross-section of a single-halo (SH) SOI nMOSFET [77].

show a marginal improvement in transconductance and lower output conductance as

compared to the conventional SOI devices. The other advantages of SH devices over

conventional SOI like absence of kink, lower inherent parasitic bipolar junction transistor

(pBJT) gain have also been reported [78]-[79].

2.4 Dual-Material Gate Structure

At very short gate length, the CMOS device operation is asymmetrical even at very

small drain bias due to a higher drain side electric field resulting in short-channel effects

like DIBL. Unconventional asymmetrical structures have been employed to reduce the

drain side electric field and its consequent impact upon the channel. Dual-Material Gate

structure employs “gate-material engineering” instead of “doping engineering” with

different workfunctions to introduce a potential step in the channel [8]. This leads to a

suppression of SCEs and an enhanced source side electric field resulting in increased

carrier transport efficiency in the channel region. And with its unique structure, DMG

offers flexibility in choosing thin-film thickness, channel doping, buried oxide thickness

26
and permittivity in short channel SOI MOSFET design. Furthermore, the DMG structure

may also be employed in symmetric structures, i.e., adding a layer of material with

different workfunction to both sides of the gate (like a LDD spacer). With the CMOS

processing technology already into the sub 100 nm regime [80], fabricating sub-100 nm

feature gate lengths should not preclude the possibility of realizing the potential benefits

and excellent immunity against SCE’s that the DMG SOI MOSFET promises.

2.5 Summary

SOI devices have been well recognized for their advantages in integrating deep

sub-micron CMOS devices. However, with the reduction of channel length, short-

channel effects are becoming increasingly important. SCE degrades the controllability of

the gate voltage over drain current due to increased charge-sharing from the drain/source

regions, which leads to the degradation of the subthreshold slope and the increase in drain

off-current. The last decade has seen increasing amount of effort focused to circumvent

the “undesirable” short-channel effects (SCE). Engineering channel doping in a

controlled way is prohibitively difficult with extremely thin-films and scarce and

randomly positioned dopant atoms, implying yield and reliability problems. On the other

hand, buried oxides thinner than 100 nm are needed to avoid coupling, which trades-off

with junction capacitance considerations. Multiple gate SOIs offer a better immunity

against SCE but they are difficult to integrate in the current CMOS fabrication

technology. Dual-Material Gate (DMG) SOI MOSFETs promise simultaneous

suppression of SCE and enhancement of average carrier velocity in the channel. A

systematic analysis of the effect of DMG on SOI is therefore, required to aid in

understanding its efficacy in suppressing SCE in deep sub-micron CMOS devices.

27
 CHAPTER III
TWO-DIMENSIONAL MODEL OF SURFACE POTENTIAL IN A
FULLY DEPLETED (FD) DMG SOI MOSFET

3.1 Introduction

In a long channel transistor, the “edge” effects along the sides of the channel can be

neglected. This aids in assuming that electric field lines are perpendicular to the surface

everywhere (i.e., they have component along y-direction only) and what is called a one-

dimensional analysis can be performed based on gradual-channel approximation.

Analyses based on such assumption fail to characterize adequately the devices with short

channels. If the channel is short (i.e., L is not much larger than the sum of the source and

drain depletion widths), a significant part of the electric field will have components along

both the y and x directions, the latter being the direction along the channel’s length. Thus

a two-dimensional analysis is needed.

A physics based 2-D model for the surface potential variation along the channel in

a fully depleted Dual-Material Gate (DMG) silicon-on-insulator MOSFET’s is developed

by solving the two-dimensional Poisson’s equation. The model details the role of various

MOS parameters like source/drain and body doping concentrations, the lengths of the

gate metals and their work functions, applied drain and substrate biases, the thickness of

the gate and buried oxide in influencing the surface potential. It is simple in its

functional form and lends itself to efficient computation.

3.2 DMG-SOI structure and its parameters

A schematic cross-sectional view of a fully depleted (FD) DMG SOI MOSFET

implemented using the 2-D device simulator MEDICI [10] is shown in Fig. 3.1 with gate

29
 Gate
L1 L2
Source Drain
M1 M2
tf

tSi
n+ n+
tb
Burried oxide
x

p substrate
y

Substrate
Fig. 3.1: Cross-sectional view of an n-channel fully depleted DMG-SOI MOSFET.

metals M1 and M2 of lengths L1 and L2, respectively. The doping in the p type body and

n+ source/drain regions is kept at 6 x 1016cm-3 and 5 x 1019cm-3 respectively. Typical

values of front-gate oxide thickness, buried-oxide thickness and thin-film thickness are

5 nm, 450 nm and 150 nm respectively.

3.3 Mathematical Formulation

Assuming that the impurity density in the channel region is uniform and the

influence of charge carriers and fixed oxide charge on the electrostatics of the channel

can be neglected, the potential distribution in the silicon thin-film, before the onset of

strong inversion can be expressed as

d 2φ ( x, y ) d 2φ ( x, y ) qN A
+ = for 0 ≤ x ≤ L, 0 ≤ y ≤ t Si (3.1)
dx 2 dy 2 ε Si

30
where NA is the film doping concentration, ε Si is the dielectric constant of silicon, tSi is the

film thickness and L is the device channel length. The potential profile in the vertical

direction, i.e., the y-dependence of φ ( x, y ) can be approximated by a simple parabolic

function as proposed by Young [12] for fully depleted SOI MOSFET’s.

φ ( x, y ) = φS ( x ) + c1 ( x ) y + c2 ( x ) y 2 (3.2)

where φS ( x ) is the surface potential and the arbitrary coefficients c1 ( x ) and c2 ( x )

are functions of x only. In the DMG structure, since the gate is divided into two parts the

potential under M1 and M2 can be written as

φ1 ( x, y ) = φS1 ( x ) + c11 ( x ) y + c12 ( x ) y 2 for 0 ≤ x ≤ L1 , 0 ≤ y ≤ tSi (3.3)

φ2 ( x, y ) = φS 2 ( x ) + c21 ( x ) y + c22 ( x ) y 2 for L1 ≤ x ≤ L1 + L2 , 0 ≤ y ≤ tSi (3.4)

The Poisson’s equation is solved separately under the two gate regions using the

following boundary conditions.

1. Electric flux at the gate/front-oxide interface is continuous for both the metal gates.

dφ1 ( x, y ) ε ox φS 1 ( x ) − VGS 1
'

= for Metal1 (3.5)

dy y =0
ε Si tf

d φ 2 ( x, y ) ε ox φS 2 ( x ) − VGS 2
'

= for Metal2 (3.6)

dy y =0
ε Si tf

where ε ox is the dielectric constant of the oxide, t f is the gate oxide thickness, and

VGS' 1 = VGS − VFB1, f and VGS' 2 = VGS − VFB 2, f

where VGS is the gate-to-source bias voltage, VFB1, f and VFB 2, f are the front-channel

flat-band voltages of metal 1 and metal 2, respectively.

31
2. Electric flux at the interface of buried oxide and the back-channel is continuous for

both the metal gates.

dφ1 ( x, y ) ε ox VSUB − φ B ( x )
'

= for Metal1 (3.7)

dy y =tSi
ε Si tb

d φ 2 ( x, y ) ε ox VSUB − φB ( x )
'

= for Metal2 (3.8)

dy y =tSi
ε Si tb

where tb is the buried oxide thickness, φB ( x ) is the potential function along the

B = VSUB − VFB ,b , where, VSUB is the substrate

'
back-side oxide-silicon interface, and VSU

bias and VFB ,b is the back-channel flat-band voltage.

3. Surface potential at the interface of the two dissimilar metals is continuous

φ1 ( L1 , 0 ) = φ2 ( L1 , 0 ) (3.9)

4. Electric flux at the interface of the two dissimilar metals is continuous

dφ1 ( x, y ) d φ ( x, y )
= 2 (3.10)
dx x= L
dx x= L
1 1

5. The potential at the source end is

φ1 ( 0, 0 ) = φS1 ( 0 ) = Vbi (3.11)

6. The potential at the drain end is

φ2 ( L1 + L2 , 0 ) = φS 2 ( L1 + L2 ) = Vbi + VDS (3.12)

where Vbi = ( Eg 2 ) + VT ln ( N A ni ) is the built-in potential across the body-source

junction.

The constants c11 ( x ) , c12 ( x ) , c21 ( x ) and c22 ( x ) in equations (3.3) and (3.4) can

be deduced from the boundary conditions (3.5) – (3.12) as described.

32
 From (3.3), (3.5) and (3.7) we can obtain the following relations for the region

under metal 1:

φ S 1 ( x ) + c11 ( x ) tSi + c12 ( x ) tSi2 = φ B ( x ) (3.13)

ε ox φS 1 ( x ) − VGS 1  φ ( x ) − VG' S 1 
'
ε ox
c11 ( x ) = = C f  S1  where C f = (3.14)
ε Si tf  ε Si  tf

ε ox VSUB − φ B ( x )  VSUB − φB ( x ) 
' '
ε ox
c11 ( x ) + 2c12 ( x ) tSi = = Cb   where Cb = (3.15)
ε Si tb  tb  tb

Similarly for the region under metal 2, we obtain the following expressions using

(3.4), (3.6), and (3.8):

φ S 2 ( x ) + c21 ( x ) tSi + c22 ( x ) tSi2 = φ B ( x ) (3.16)

ε ox φ S 2 ( x ) − VGS 2  φ S 2 ( x ) − VG' S 2 
'
ε ox
c21 ( x ) = = Cf   where C f = (3.17)
ε Si tf  ε Si  tf

ε ox VSUB − φ B ( x )  V ' −φ ( x) 
'
ε ox
c21 ( x ) + 2c22 ( x ) tSi = = Cb  SUB B  where Cb = (3.18)
ε Si tb  tb  tb

Region under metal 1

Solving (3.13)-(3.15) for c12 ( x ) , we get

C C   C C 
'
VSUB + VGS' 1  f + f  − φS 1 ( x ) 1 + f + f 
c12 ( x ) =  Cb CSi   Cb CSi 
 C 
tSi2 1 + 2 Si 
 Cb 

where CSi = ε Si tSi .

Thus substituting the values of c11 ( x ) and c12 ( x ) in (3.3) and using φ1 ( x, y ) in

(3.1) we obtain the potential distribution as

33
 d 2φ S1 ( x )
− αφ S 1 ( x ) = β1 (3.19)
dx 2

where

2 (1 + C f Cb + C f CSi )
α= and
tSi2 (1 + 2 CSi Cb )

qN A  C f Cb + C f CSi   1 
β1 = − 2VGS' 1  2  − 2VSUB  2
'

ε Si  tSi (1 + 2 CSi Cb )   tSi (1 + 2 CSi Cb ) 

The above equation is a simple second-order non-homogenous differential equation

with constant coefficients which has a solution of the form

β1
φS 1 ( x ) = A exp ( λ1 x ) + B exp ( λ2 x ) − (3.20)
α

where λ1 = α and λ2 = − α . Now using the boundary condition (3.11) we obtain

β1
A+ B − = Vbi (3.21)
α

Region under metal 2

Solving (3.16)-(3.18) for c22 ( x ) , we get

C C   C C 
'
VSUB + VGS' 2  f + f  − φS 2 ( x ) 1 + f + f 
c22 ( x ) =  Cb CSi   Cb CSi 
 C 
tSi2 1 + 2 Si 
 Cb 

Thus substituting the values of c21 ( x ) and c22 ( x ) in (3.4) and using φ2 ( x, y ) in

(3.1), we obtain the expression of the form

d 2φ S 2 ( x )
− αφ S 2 ( x ) = β 2 (3.22)
dx 2

where α is same as previously defined and β 2 is

34
 qN A  C f Cb + C f CSi   1 
β2 = − 2VGS' 2  2  − 2VSUB  2
'

ε Si  tSi (1 + 2 CSi Cb )   tSi (1 + 2 CSi Cb ) 

The above equation is a simple second-order non-homogenous differential equation

with constant coefficients which has a solution of the form

β2
φ S 2 ( x ) = C exp ( λ1 ( x − L1 ) ) + D exp ( λ2 ( x − L1 ) ) − (3.23)
α

where λ1 = α and λ2 = − α . Now using boundary condition (3.12) we obtain

β2
Vbi + VDS = C exp ( λ1 L2 ) + D exp ( λ2 L2 ) − (3.24)
α

Using boundary conditions (3.9) and (3.10) we get the following expressions

A exp ( λ1 L1 ) + B exp ( λ2 L1 ) + (σ 1 − σ 2 ) = C + D (3.25)

Aλ1 exp ( λ1 L1 ) + Bλ2 exp ( λ2 L1 ) = Cλ1 + Dλ2 (3.26)

where

qN A  C f Cb + C f CSi   1 
σ 1 = − β1 α = − VGS' 1   − VSUB
'

 1 + C f Cb + C f CSi 
(3.27)
ε Si  1 + C f Cb + C f CSi 
   

qN A  C f Cb + C f CSi   1 
and σ 2 = − β 2 α = − VGS' 2   − VSUB
'

 1 + C C + C C 
(3.28)
ε Si  1+ C C + C C 
 f b f Si   f b f Si 

Solving (3.25) and (3.26), we obtain the relationship among the coefficients A, B, C

and D as

C = A exp ( λ1 L1 ) +
(σ 1 − σ 2 ) and
2

D = B exp ( λ2 L1 ) +
(σ 1 − σ 2 )
2

Now solving for A, B, C and D we obtain

35
  (Vbi − σ 2 + VDS ) − exp ( −λ1 ( L1 + L2 ) ) (Vbi − σ 1 ) − (σ 1 − σ 2 ) cosh ( λ1 L2 ) 
A=  exp ( −λ1 ( L1 + L2 ) )
 1 − exp ( −2 λ1 ( L1 + L 2 ) ) 
(Vbi − σ 1 ) − (Vbi − σ 2 + VDS ) exp ( −λ1 ( L1 + L2 ) ) + (σ 1 − σ 2 ) cosh ( λ1L2 ) exp ( −λ1 ( L1 + L2 ) )
B=
1 − exp ( −2λ1 ( L1 + L2 ) )
(σ − σ 2 )
C = A exp ( λ1 L1 ) + 1 and D = B exp ( λ2 L1 ) + 1
(σ − σ 2 )
2 2

It can be theoretically demonstrated that the expression for surface potential

obtained for a dual-material gate FD SOI MOSFET can be easily reduced to the form

presented in [12]. On increasing L1 ( L1 → L and L2 → 0 ) and substituting

σ 1 = σ 2 = −σ f in (3.20) leads to the same expression as derived by Young for a single

material gate (SMG) FD SOI MOSFET.

Analogous statement can be made for the case when L1 → 0 . In that case C and D

reduce to A and B respectively (as σ 1 = σ 2 ) and L1 + L2 can be substituted as L. Again

equation (3.20) can be used to characterize the surface potential variation along the front-

channel. So the model yields consistent results for the case of an ordinary single material

gate structure when either of the gate metal lengths approach zero.

The concept of drain-induced barrier-lowering (DIBL) can be illustrated by the

channel surface potential. Since the sub-threshold leakage current often occurs at the

position of minimum surface potential, therefore, the influence of DIBL on the sub-

threshold behavior of the device can be monitored by the minimum surface potential.

DIBL can be demonstrated by plotting the surface potential minima as a function of the

position along the channel for different drain bias conditions. Due to the co-existence of

the two dissimilar gate metals, M1 and M2, having a finite workfunction difference, the

position of minimum surface potential, xmin, will be solely determined by the gate metal

36
M1. The minimum potential of the front-channel can be calculated from (3.20) by

solving

dφ S 1 ( x )
=0
dx x = x
min

where the minima occurs at

1  B
xmin = ln   (3.29)
2λ1  A 

and φS1,min = 2 AB + σ 1 (3.30)

The electric field pattern along the channel determines the electron transport

velocity through the channel. The electric field component in the x–direction, under the

metal gate M1 is given as

dφ1 ( x, y ) dφ S 1 ( x )
E1 ( x ) = = = Aλ1 exp ( λ1 x ) + Bλ2 exp ( λ2 x ) (3.31)
dx y =0
dx

Similarly the electric field pattern, in x–direction, under gate M2 is given as

d φ2 ( x, y ) dφS 2 ( x )
E2 ( x ) = = = C λ1 exp ( λ1 ( x − L1 ) ) + Dλ2 exp ( λ2 ( x − L1 ) ) (3.32)
dx y =0
dx

3.4 Results and Discussion

To verify the proposed analytical model, the 2-D device simulator MEDICI was

used to simulate the surface potential distribution within the silicon thin-film and

compare with the results predicted by the analytical model.

3.4.1 Barrier Lowering

In Fig. 3.2, the calculated and simulated values of surface potential are plotted

against the horizontal distance x for L = 0.2 µm at different drain biases. It is seen from

37
the figure that due to the presence of the dual-material gate there is no significant change

in the potential under the gate M1 even as the drain bias is increased. Hence, the channel

region under M1 is “screened” from the changes in the drain potential, i.e., the drain

voltage is not absorbed under M1 but under M2. As a consequence, VDS has only a very

small influence on drain current after saturation and the drain conductance is reduced. It

is evident from the figure that there is a negligible shift in the point of the minimum

potential and it lies almost at the interface of the two metal gates irrespective of the

applied drain bias. Therefore, DIBL is considerably reduced for the DMG-SOI

MOSFET. The model predictions correlate well with the simulation results proving the

accuracy of our proposed analytical model.

S M1 M2 D

3.0
VDS = 1.75 V

VGS = 0.15 V
NA = 6 x 1016 cm-3
Surface Potential (in volts)

L = 0.2 µm
2.0 φM1 = 4.77 V VDS = 0.95 V
φM2 = 4.1 V

VDS = 0.25 V

1.0

MEDICI
Model
0.0
0.0 0.05 0.10 0.15 0.20
Position in channel (in µm)
Fig. 3.2(a): Surface channel potential profiles of DMG-SOI MOSFET for different drain biases
with channel length L = 0.2 µm as obtained from the analytical model and 2-D MEDICI
simulation. The screening effect is distinctly visible.

38
 3.0
VGS = 0.15 V VDS = 1.75 V
NA = 6 x 1016 cm-3
L = 0.2 µm

Surface Potential (in volts)

φM = 4.1 V

2.0 VDS = 0.95 V

VDS = 0.25 V

1.0

VDS = 1.75
VDS = 0.95
VDS = 0.25
0.0
0.0 0.05 0.10 0.15 0.20
Position in channel (in µm)
Fig. 3.2(b): Surface channel potential profiles of SMG-SOI MOSFET for different drain biases
with channel length L = 0.2 µm as obtained from the 2-D MEDICI simulation.

It is evident from Fig. 3.2(b) that with increasing drain bias the channel potential

minima shifts substantially thus lowering the barrier for the charge carriers in a

conventional SMG SOI device.

3.4.2 Gate-Workfunction Engineering

Fig. 3.3 shows the variation of surface potential along the channel for two different

workfunction values of gate metal M1. As it can be seen from the figure, choosing a gate

metal M1 with a higher workfunction leads to a better control of the channel potential

minima by M1. Therefore, more the step potential in the channel more will be the

screening of the control gate, M1, against the drain potential variation.

The proposed two-dimensional model incorporates the dependence of channel

surface potential on the workfunction difference between the two gate metals M1 and

M2. This dependence of surface potential on the difference in workfunction of the two

39
 1.5 VGS = 0.15 V
VDS = 0.25 V
L = 0.2 µm
Surface Potential (in volts) φM2 = 4.1 V
NA = 6 x 1016 cm-3
1.0

φM1 = 4.77 V
φM1 = 5.1 V

0.5

MEDICI
Model
0.0
0.0 0.05 0.10 0.15 0.20

Position in channel (in µm)

Fig. 3.3: Surface potential versus position along channel for two different gate metal
workfunction differences.

gate materials can lend great flexibility in choosing the gate materials for a Dual-Material

Gate (DMG) SOI in case the absolute values do not exercise a significant influence on

the variation of surface potential along the channel. Fig. 3.4 shows the variation of

surface potential along the channel for two different gate metal workfunctions φM1 and

φM2 of M1 and M2, keeping the difference (φM1 - φM2) constant. It is evident from the

figure that the minima and the slope of the surface potential at the interface are not the

same for the two different cases depicted. Upon careful observation it is evident that the

surface potential dependence on workfunction of the two gate materials is not restricted

to the difference between the workfunctions, rather it depends directly on the absolute

value of the gate material workfunction. Thus, gate-material engineering employed to

alleviate the SCE in a FD DMG SOI MOSFET has to be carefully monitored.

40
 1.5 VGS = 0.15 V
VDS = 0.25 V
L = 0.2 µm
Surface Potential (in volts) NA = 6 x 1016 cm-3
φM1 - φM2 = 0.67 V
1.0

1
φM1 = 4.67 V
1
φM2 = 4.0 V
2
φM1 = 4.77 V
0.5 2
φM2 = 4.1 V

MEDICI
Model
0.0
0.0 0.05 0.10 0.15 0.20

Position in channel (in µm)

Fig. 3.4: Plot of surface potential versus position in channel for different gate metal
workfunctions φM1 and φM2 of M1 and M2, keeping the difference (φM1 - φM2) constant.

3.4.3 L1/L2 Ratio dependence

Fig. 3.5 shows the variation of surface potential with the normalized channel

position for different combination of gate lengths L1 and L2 of M1 and M2, respectively,

keeping the sum of total gate length, (L1+L2), to be constant. As it is seen from the figure

the position of minimum surface potential, lying under M1 is shifting toward the source

as the length of gate M1 is reduced. This causes the peak electric field in the channel to

shift more towards the source end and thus there is a more uniform electric field profile in

the channel. Moreover, it is observed that the channel potential minima for the three

cases are not the same. This happens because as L1 increases, a portion of the channel

controlled by the gate metal with larger workfunction [81] is increased.

41
 1.5 VGS = 0.15 V
VDS = 0.25 V
L = 0.2 µm
φM1 = 4.77 V
Surface Potential (in volts) φM2 = 4.1 V
NA = 6 x 1016 cm-3
1.0
1
2 1 L1/L2 = 0.08/0.12
3
2 L1/L2 = 0.10/0.10
0.5
3 L1/L2 = 0.12/0.08

MEDICI
Model
0.0
0.0 0.05 0.10 0.15 0.20

Position in channel (in µm)

Fig. 3.5: Variation of surface potential with position in channel for different combination of gate
lengths L1 and L2, keeping the sum (L1+L2) constant.

This also leads to a desirable Vth “roll-up” with decreasing channel length as

discussed in section 4.3.1. The validity of the approach developed to model the surface

potential and electric field in the channel for different combinations of L1 and L2 of M1

and M2 is verified with the aid of 2-D simulation results.

3.4.4 Body Doping

Fig. 3.6 shows the surface potential variation with the normalized channel position

for different body doping concentrations. As can be seen from the figure that as the

doping concentration increases, the shielding of the channel region under the gate M1 is

increased with an increase in the channel potential step. Hence DIBL decreases and the

immunity of DMG SOI MOSFET to SCE is consequently enhanced. This feature of

DMG is contrary to the behaviour observed for a SMG SOI device as shown in

Fig. 3.6(b) and thus allows for easy scalability of the DMG SOI devices.

42
 1.5
VGS = 0.15 V
VDS = 0.25 V
L = 0.2 µm
φM1 = 4.77 V
Surface Potential (in volts) φM2 = 4.1 V
1.0
NA = 6 x 1016 cm-3

NA = 1 x 1017 cm-3

0.5

MEDICI
Model
0.0
0.0 0.05 0.10 0.15 0.20

Position in channel (in µm)

Fig. 3.6(a): Surface potential plot for two different body doping concentrations for a DMG SOI.

1.5
VGS = 0.15 V
VDS = 0.25 V
L = 0.2 µm
φM = 4.1 V
Surface Potential (in volts)

1.0 NA = 1 x 1017 cm-3

NA = 6 x 1016 cm-3

0.5

0.0
0.0 0.05 0.10 0.15 0.20

Position in channel (in µm)

Fig. 3.6(b): Surface potential plot for two different body doping concentrations for a SMG SOI.

43
3.4.5 Gate-Oxide Thickness variation

Fig. 3.7 depicts the variation of the surface potential with the channel position for

different values of oxide thickness for DMG FD SOI MOSFET. The magnitude of the

potential step increases as the work function difference increases. According to the

figure, the step voltage increases as the oxide thickness decreases. As the step voltage

increases so is the screening of region under M1 from drain voltage variation and

therefore, more reduction in DIBL. On the other hand, with increasing oxide thickness,

M1 and M2 lose their control over the channel, which leads to increase in the DIBL.

Therefore, continuous scaling down of the oxide thickness reduces DIBL but on the

other hand, oxide thickness cannot be scaled down to very small values otherwise

tunneling through the thin oxide and hot-carrier effects become prominent.

1.5 VGS = 0.15 V

VDS = 0.25 V
L = 0.3 µm
φM1 = 4.77 V
Surface Potential (in volts)

φM2 = 4.1 V
NA = 6 x 1016 cm-3 tf = 50 A
1.0

tf = 100 A

0.5

MEDICI
Model
0.0
0.0 0.05 0.10 0.15 0.20 0.25 0.30

Position in channel (in µm)

Fig. 3.7: Variation of surface potential with position in channel for two different front-gate oxide
thicknesses.

44
3.4.6 Thin-Film Thickness variation

When the thin-film thickness is reduced the controllability of the front-gate over

the surface channel becomes stronger in comparison to the influence exerted by the

source/drain. Fig. 3.8 shows the variation of surface potential along the channel length

for two different thin-film thicknesses. On careful observation, it is visible that the step

potential induced by the dual-material gate structure increases as the thin-film thickness

is scaled to 50 nm. This increase in step potential ensures better screening of the “control

gate” M1 and hence reduced SCE.

With the scaling of SOI devices into the 0.1 µm regime thin-film thicknesses of the

order of 10-25 nm are required to circumvent the “unacceptable” SCE’s. Manufacturing

such thin-film becomes more and more challenging because of the intrinsic variation in

1.5 VGS = 0.15 V

VDS = 0.25 V
L = 0.3 µm
φM1 = 4.5 V
Surface Potential (in volts)

φM2 = 4.1 V tSi = 500 A

NA = 6 x 1016 cm-3
1.0

tSi = 1500 A

0.5

MEDICI
Model
0.0
0.0 0.05 0.10 0.15 0.20 0.25 0.30

Position in channel (in µm)

Fig. 3.8: Variation of surface potential along the channel for two different thin-film thicknesses.

45
the thickness across a wafer as well as the high parasitic source/drain resistance

associated with very thin silicon films [82]. In such a scenario Dual-Material Gate

(DMG) offers an alternative way of engineering to avoid the SCE’s.

3.4.7 Electric Field Profile

In Fig. 3.9, the electric distribution near the drain is shown for SMG and DMG FD

SOI MOSFET’s with a channel length L = 0.4 µm. It is evident from the figure that the

presence of a lower function gate at the drain side reduces the peak electric field

considerably. This reduction of the electric field experienced by the carriers in the

channel can be interpreted as the reduction of the hot-carrier effect at the drain end.

Therefore, further scaling of oxide thickness is possible in the DMG structure. As shown

in the figure the results from the analytical model are in close proximity of the simulation

results.

500 DMG-SOI φM1 = 4.77 V

φM2 = 4.1 V
450 L1 = 0.1 µm
400 L2 = 0.3 µm
Electric Field (kV/cm)

350
SMG-SOI φM = 4.77 V
300 L = 0.4 µm

250
200
150
100 MEDICI (DMG)
50 Model (DMG)
MEDICI (SMG)
0
0.30 0.32 0.34 0.36 0.38 0.40

Position in channel (in µm)

Fig. 3.9: Variation of electric field along the channel shown for region close to drain.

46
3.5 Summary

A two-dimensional analytical model of surface potential for a fully depleted dual-

material gate (DMG) SOI MOSFET is developed by solving the 2-D Poisson’s equation

with appropriate boundary conditions. Expressions for electric field and minimum

surface potential in the channel are derived based on the model developed for surface

potential. The effect of various MOS parameters like body doping concentration, the

lengths of the gate metals and their work functions, applied drain biases, the thickness of

the gate oxide and buried oxide on the surface potential is studied. The results predicted

by the model are validated by comparing with 2-D MEDICI simulations. The calculated

values of the surface potential in the silicon thin-film obtained from the proposed model

correlate well with the simulated results. The results unambiguously establish that the

incorporation of DMG structure in a FD SOI MOSFET leads to subdued short-channel

effects due to a step-function in the channel potential profile. The shift in the surface

channel potential minima position is negligible with increasing drain biases. The electric

field in the channel at the drain end is also reduced leading to reduced hot-carrier effect.

A significant result pointed by this formulation is the tunability of the surface potential by

“gate-material engineering”, i.e., the dependence of surface potential on the difference

between the gate material workfunctions and the lengths of the two gate metals, which

offers another degree of freedom for the SOI transistor design.

47
 CHAPTER IV
THRESHOLD VOLTAGE MODELING AND EVIDENCE FOR SUBDUED
SHORT-CHANNEL EFFECTS

4.1 Introduction

A qualitative notion of threshold voltage, Vth, is the gate-source voltage at which an

inversion channel forms, which can then conduct a high drain current. With the

continued down-scaling of all geometries to achieve the projected high packing density in

submicron MOS devices, threshold voltage reduces with decreasing channel length.

Therefore, the optimization of the threshold voltage reduction is very important for both

process and device engineers, and plays a major role for achieving a highly improved

CMOS technology performance.

One of the key parameters that characterizes short-channel effects (SCE) is the

degradation of the device threshold voltage with decreasing channel length. In this

chapter an analytical expression of threshold voltage is derived for a fully depleted DMG

SOI MOSFET based on the two-dimensional surface potential model developed in the

last chapter. The mathematical formulation aids in quick visualization of the importance

of various device parameters on the performance of a DMG SOI device and allows for a

good grip on the underlying device physics. The efficacy of the DMG structure in

subduing the short-channel effects (SCE) is also studied in relation to various device

parameters.

4.2 Mathematical Formulation

Threshold voltage, Vth , is that value of the gate voltage VGS at which a conducting

channel is induced at the surface of SOI MOSFET. In a fully depleted thin-film SOI, it is

49
desirable that the front channel turns on before the back channel. Therefore, the

threshold voltage is taken to be that value of gate source voltage for whichφS ,min = 2φF ,

where φF is the difference between the extrinsic Fermi level in the bulk region and the

intrinsic Fermi level. In the case of DMG structure, due to the co-existence of metal

gates, M1 and M2, with different work functions, the surface potential minima is solely

determined by the metal gate with higher work function. So the threshold voltage is

defined as the value of VGS at which the minimum surface potential φS 1,min equals 2φ F .

Hence we can determine the value of threshold voltage as the value of VGS by solving:

φS 1,min = 2 AB + σ 1 (4.1)

Reproducing (3.30) here for convenience, we have

φS1 ( x ) = A exp ( λ1 x ) + B exp ( λ2 x ) + σ 1

where the constants A and B are

 (Vbi − σ 2 + VDS ) − exp ( −λ1 ( L1 + L2 ) ) (Vbi − σ 1 ) − (σ 1 − σ 2 ) cosh ( λ1 L2 ) 

A=  exp ( −λ1 ( L1 + L2 ) )
 1 − exp ( −2λ1 ( L1 + L2 ) ) 
(Vbi − σ 1 ) − (Vbi − σ 2 + VDS ) exp ( −λ1 ( L1 + L2 ) ) + (σ 1 − σ 2 ) cosh ( λ1L2 ) exp ( −λ1 ( L1 + L2 ) )
B=
1 − exp ( −2λ1 ( L1 + L2 ) )
When Cb << C f and CSi , i.e. buried oxide capacitance (Cb) is negligible in

comparison to the front oxide capacitance (Cf) and thin-film capacitance (CSi), we can

approximate σ 1 and σ 2 (refer 3.27 and 3.28) as

Cb ' qN AtSi Cb ' qN AtSi

σ1 ≈ VSUB − + VGS' 1 and σ2 ≈ VSUB − + VGS' 2
Cf Cf Cf Cf

We can simplify the expressions of A and B by substituting as follows

Cb ' qN AtSi Cb ' qN AtSi

u= VSUB − − VFB1 and v= VSUB − − VFB 2
Cf Cf Cf Cf

50
 { }
Vbi1 = Vbi 1 − exp ( −λ1 ( L1 + L2 ) ) + VDS − ( u − v ) cosh ( λ1 L2 ) − v + u exp ( −λ1 ( L1 + L2 ) )

{ }
Vbi 2 = Vbi exp ( λ1 ( L1 + L2 ) ) − 1 − VDS + ( u − v ) cosh ( λ1 L2 ) + v − u exp ( λ1 ( L1 + L2 ) )

A=
(
Vbi1 − VGS 1 − exp ( −λ1 ( L1 + L2 ) ) )
2sinh ( λ1 ( L1 + L2 ) )

B=
(
Vbi 2 + VGS exp ( λ1 ( L1 + L2 ) ) − 1 )
2sinh ( λ1 ( L1 + L2 ) )

Upon solving for Vth , we obtain an expression for the threshold voltage as

Vth =
( −Vφ1 + Vφ21 − 4ξVφ 2 ) (4.2)
2ξ

where

ξ = exp ( λ1 ( L1 + L2 ) ) - sin 2 h ( λ1 ( L1 + L2 ) ) − 2 + exp ( −λ1 ( L1 + L2 ) )

( ) (
Vφ 1 = Vbi1 1 − exp ( λ1 ( L1 + L2 ) ) + sin 2 h ( λ1 ( L1 + L2 ) ) ( 4φF − 2u ) − Vbi 2 1 − exp ( −λ1 ( L1 + L2 ) ) )
Vφ 2 = Vbi1Vbi 2 − sin 2 h ( λ1 ( L1 + L2 ) ) ( 2φF − u )
2

The dependence of Vth on the length and material workfunction of the two gate

metals is a significant result of the above formulation. This feature which is unique to

DMG SOI lends another degree of freedom towards controlling and engineering the

threshold voltage of ultrasmall SOI transistor design.

The formulation of surface potential, however, assumed the absence of mobile

charge carriers in the channel to simplify the subsequent analysis. Therefore, the

threshold voltage expression derived is not strictly based on the common notion of Vth

which indicates a physical background of moderate inversion, i.e., the transition between

weak and strong inversion. A more rigorous analysis involves solving the 2-D Poisson’s

51
equation taking the mobile carrier density into account (in addition to the depletion

charge) but that would lead to a computationally inefficient analytical model requiring

the use of fitting parameters.

4.3 Results and Discussion

To verify the proposed analytical expression, the calculated values of threshold

voltage from the model are compared with those obtained from 2-D MEDICI [10]

simulation extracted from the commonly used maximum transconductance method.

4.3.1 Scaling Characteristics

In Fig. 4.1, the calculated values of threshold voltage as a function of channel-

length are compared with those obtained from MEDICI simulations.

0.7
MEDICI (DMG)
Model (DMG)
MEDICI (SMG)
0.6
Threshold Voltage (V)

0.5

0.4

0.3 VDS = 0.05 V DMG: φM1 = 4.77 V

NA = 6 x 1016 cm-3 φM2 = 4.1 V
L1 = 0.1 µm
0.2 SMG: φM = 4.77 V

0.1
0.1 0.2 0.4 0.6 0.8 1.0
Channel Length (in µm)
Fig. 4.1: Threshold voltage variation with channel length compared for DMG and SMG SOI
devices. L1 is fixed at 0.1 µm for the DMG SOI device and φM = 4.77 V for the SMG SOI MOS.

52
 It is seen that the threshold voltage obtained from the analytical model tracks the

simulation values very well but with an insignificant negative offset of approximately 20-

50 mV. This less than 10% discrepancy in the results is due to the neglect of the

inversion layer charge at threshold at the front interface [83]. As shown in the figure

threshold voltage rolls-off for a conventional single material gate (SMG) SOI (even with

a higher workfunction) in contrast to Vth roll-up for a fully depleted DMG SOI MOSFET.

This is due to the presence of two different gate metals having a finite workfunction

difference and carefully chosen gate lengths.

Fig. 4.2 shows the threshold voltage variation as a function of channel length for

DMG SOI MOSFET with L1 fixed at 50 nm. It is evident from the figure that the benefit

of Vth roll-up extends well up to 100 nm channel length.

0.6

0.5
Threshold Voltage (V)

0.4

0.3

VDS = 0.05 V
0.2
φM1 = 4.77 V
φM2 = 4.1 V MEDICI
0.1 L1 = 0.05 µm Model
NA = 6 x 1016 cm-3

0
0.05 0.10 0.15 0.20 0.25 0.30 0.35
Channel Length (in µm)
Fig. 4.2: Threshold voltage variation with channel length for DMG SOI device compared
between MEDICI simulations and model prediction. L1 is kept fixed at 50 nm.

53
4.3.2 Minimum Surface Potential

The variation of the front-channel minimum potential as a function of channel

length L (=L1+L2) for fully depleted DMG SOI with silicon thin-film thickness tSi = 100

nm and 50 nm is shown in Fig. 4.3. In a fully depleted (FD) MOSFET, the minimum

channel potential is sensitive to thin-film thickness. But as observed from the figure, the

dependence of minimum channel potential on thin-film thickness, tSi, and consequently

threshold voltage, is effectively reduced due to the co-existence of gate materials having

a finite workfunction difference in a DMG SOI MOSFET.

1.0
VDS = 0.05 V φM1 = 4.5 V
VGS = 0.15 V φM2 = 4.1 V
Minimum Surface Potential (V)

NA = 6 x 1016 cm-3 L1 = 0.1 µm

0.8
tSi = 500 A
tSi = 1000 A

0.6

MEDICI
Model

0.4
0 0.2 0.4 0.6 0.8 1.0
Channel Length (in µm)
Fig. 4.3: Minimum surface potential as a function of channel length for two different thin-film
thicknesses as extracted from MEDICI and the analytical model. L1 is kept fixed at 0.1 µm.

54
4.3.3 Substrate-Bias dependence

Fig. 4.4 shows the variation of threshold voltage with channel length for two

different substrate biases obtained from the analytical expression and 2-D simulations. It

is observed from the figure that in contrast to a SMG, the Vth “rolls-up” with decreasing

channel length is due to the DMG structure. As shown in the figure at a negative back

gate bias of –2 V, the threshold voltage is lifted upward as compared to a back gate bias

of 0 V. The extent of the upward shift when the back gate bias becomes negative is

smaller for a device with shorter channel length due to a reduced control by source/drain

over the channel region at a negative bias. Fig. 4.5 shows the threshold voltage variation

with decreasing channel length with L1 fixed at 50 nm. It is seen that Vth “rolls-up” at a

negative substrate bias even with technology scaled to 100 nm. This is due to the co-

existence of the two different gate materials in a DMG SOI.

0.7 VDS = 0.05 V tb = 400 nm

φM1 = 4.77 V tSi = 50 nm
0.6 φM2 = 4.1 V tf = 5 nm
L1 = 0.1 µm NA = 6 x 1016 cm-3
Threshold Voltage (V)

0.5

0.4

0.3 MEDICI (VSUB = -2.0 V)

Model (VSUB = -2.0 V)
MEDICI (VSUB = 0 V)
0.2

0.1
0.1 0.2 0.3 0.4 0.5 0.6
Channel Length (in µm)
Fig. 4.4: Threshold voltage variation with channel length for different substrate biasing.

55
 0.6
MEDICI (VSUB = -2 V)
MEDICI (VSUB = 0 V)
Model (VSUB = -2 V)
0.5
Threshold Voltage (V)

0.4

0.3

0.2
VDS = 0.05 V tb = 400 nm
φM1 = 4.77 V tSi = 50 nm
0.1 φM2 = 4.1 V tf = 5 nm
L1 = 0.05 µm NA = 6 x 1016 cm-3

0
0.05 0.10 0.15 0.20 0.25 0.30 0.35
Channel Length (in µm)

Fig. 4.5: Threshold voltage variation with channel length for substrate biasing of 0 V and -2 V
with L1 fixed at 50 nm.

4.3.4 Thin-film doping dependence

Fig. 4.6 shows the threshold voltage variation with decreasing channel length

obtained from the value calculated using the analytical expression and MEDICI

simulation for two different body doping densities. As shown in the figure, threshold

voltage increases with increased body doping and a “roll-up” in the characteristics is

observed at decreasing channel lengths. This can be attributed to the presence of two

different gate materials having a finite workfunction difference and properly engineered

gate lengths. Fig. 4.7 shows the thin-film doping density dependence of threshold

voltage as the gate length is scaled down to 0.01µm for a DMG SOI MOSFET. As

shown in the figure, Vth increases with increase in body doping density.

56
 0.7
MEDICI (NA = 1 x 1017 cm-3)
17 -3
Model (NA = 1 x 10 cm )
16 -3
MEDICI (NA = 6 x 10 cm )
0.6
Threshold Voltage (V)
0.5

0.4

0.3
VDS = 0.05 V tb = 400 nm
VSUB =0V tSi = 50 nm
0.2 φM1 = 4.77 V tf = 5 nm
φM2 = 4.1 V L1 = 0.1 µm
0.1
0.1 0.2 0.3 0.4 0.5 0.6
Channel Length (in µm)
Fig. 4.6: Threshold voltage variation with channel length for different body doping density.

0.6 17
MEDICI (NA = 1x 10 cm )
-3

MEDICI (NA = 6x 1016 cm-3)

17 -3
Model (NA = 1x 10 cm )
0.5
Threshold Voltage (V)

0.4

0.3

0.2
VDS = 0.05 V tb = 400 nm
VSUB =0V tSi = 50 nm
0.1 φM1 = 4.77 V tf = 5 nm
φM2 = 4.1 V L1 = 0.05 µm

0
0.05 0.10 0.15 0.20 0.25 0.30 0.35
Channel Length (in µm)
Fig. 4.7: Vth variation with channel length for different body doping density with L1 = 50 nm.

57
4.3.5 Buried Oxide Thickness dependence

As the buried oxide is scaled the influence of source/drain on the channel region via

the buried oxide worsens the SCE in conventional SMG MOSFETs due to increased

coupling. Fig. 4.8 shows the short-channel effect suppression in a fully depleted DMG

SOI MOSFET for two different buried oxide thicknesses of 100 nm and 400 nm. As

shown in the figure for both buried oxide thicknesses, Vth rolls-up at shorter channel

lengths. This is in contrast to the threshold voltage behavior for a SMG SOI device

which rolls-off even for reduced buried oxide thickness at shorter channel length. Also,

reducing the buried oxide can lead to increased junction capacitance. Thus the DMG

structure lends another degree of flexibility in the design of deep submicron SOI

transistor design by offering the alternative of gate material engineering to subdue the

undesirable SCE. Fig. 4.9 confirms that this flexibility in design is valid for even 100 nm

0.7 VDS = 0.05 V tSi = 50 nm

VSUB = 0 V tf = 5 nm
0.6 φM1 = 4.77 V L1 = 0.1 µm
φM2 = 4.1 V NA = 6 x 1016 cm-3
Threshold Voltage (V)

0.5

0.4

0.3
Model (tb=100 nm)
MEDICI (tb=100 nm)
0.2 MEDICI (tb=400 nm)

0.1
0.1 0.2 0.3 0.4 0.5 0.6
Channel Length (in µm)
Fig. 4.8: Threshold voltage variation with channel length for different buried oxide thickness.

58
 0.6
MEDICI (tb = 100 nm)
MEDICI (tb = 400 nm)
Model (tb = 100 nm)
Threshold Voltage (V) 0.5

0.4

0.3

0.2 tSi = 50 nm
VDS = 0.05 V
VSUB =0V tf = 5 nm
φM1 = 4.77 V L1 = 0.05 µm
0.1
φM2 = 4.1 V NA = 6 x 1016 cm-3

0
0.05 0.10 0.15 0.20 0.25 0.30 0.35
Channel Length (in µm)

Fig. 4.9: Threshold voltage variation as a function of channel length for buried oxide thicknesses
of 100 nm and 400 nm with L1 fixed at 50 nm.

process technology with Vth easily controlled in a DMG SOI MOSFET.

4.3.6 Gate Material Engineering

The dual-material gate (DMG) structure offers the benefit of SCE suppression in a

SOI device by virtue of gate material engineering, i.e., engineering the length and

workfunction of the two gate metals. Fig. 4.10 shows the variation of threshold voltage

with workfunction difference at a fixed channel length of L = 0.5 µm for two L1/L2 ratios

as predicted by the analytical expression and the 2-D numerical simulations. As shown

in the figure, threshold voltage increases with increasing workfunction difference. For a

fixed workfunction difference, threshold voltage is higher for a higher L1/L2 ratio due to

the increased proportion of the channel region controlled by a higher wokfunction gate.

59
 1.0 VDS = 0.05 V
0.9 φM2 = 4.1 V
L1/L2 = 2/3
L = 0.5 µm

Threshold Voltage (V)

0.8
tSi = 50 nm
0.7
tf = 5 nm
0.6 NA = 6 x 1016 cm-3 L1/L2 = 1/4
0.5
0.4
0.3
MEDICI
0.2 Model
0.1
0
0 0.2 0.4 0.6 0.8 1.0
Gate Workfunction Difference (eV)
Fig. 4.10: Threshold voltage variation with gate workfunction difference at a fixed channel,
L = 0.5 µm for two different L1/L2 ratio.

4.4 Summary

An analytical expression of threshold voltage for a fully depleted DMG SOI

MOSFET is formulated based on the 2-D physical model of surface potential developed

earlier. The effect of various device parameters like gate length scaling, body doping

density, the lengths of the gate metals and their work functions, substrate biasing, the

thickness of the buried oxide on the threshold voltage is studied. The results predicted by

the model are compared with 2-D simulations [9]. The results clearly demonstrate the

excellent immunity against SCE offered by the DMG structure with a Vth roll-up with

decreasing channel lengths visible down to 0.1 µm. Moreover the immunity against SCE

is possible by a new way of “gate material engineering” which lends a tremendous

flexibility in deep submicron SOI design. The results provide incentive to further

investigate the potential benefits of a DMG SOI over a conventional SOI MOSFET for its

possible integration in the CMOS technology as discussed in the following chapter.

60
 CHAPTER V
TWO-DIMENSIONAL SIMULATION STUDIES

5.1 Introduction

The peak of the electric field underneath the gate offers certain advantages, such as

increased lifetime of the device; minimization of the ability of the localized charges to

raise drain resistance [84]; and more control of gate over the conductance of the channel

so as to increase the gate transport efficiency. In a field effect transistor, the electric field

in the channel peaks near the drain. As a result, electrons enter into the channel with a

low initial velocity, gradually accelerating towards the drain. The maximum electron

drift velocity is reached near the drain. Another undesirable phenomenon is the hot-

carrier injection into the gate due to high drain side electric field.

In a DMG structure, gate is composed of two different materials with a finite

workfunction difference, amalgamated laterally. This leads to a creation of a step in the

channel potential profile and a more uniform electric field pattern along the channel. The

electric field distribution in the channel is modified such that the field near the source

becomes larger causing a more rapid acceleration of the electrons. Thus the average

carrier transport velocity in the channel is increased which leads to enhanced

performance by the DMG SOI MOSFET. Numerical simulation studies using MEDICI

[10] are employed to explore the unique features of a DMG SOI and compare with those

of a compatible single material gate (SMG) SOI MOSFET in terms of threshold voltage

variation with decreasing channel length, drain-induced barrier-lowering (DIBL),

leakage current, drive current, transconductance, drain conductance and voltage gain with

the purpose of uncovering their potential benefits for VLSI integration.

61
5.2 Computer Simulation Results

Computer experiments are designed to explore the characteristics of DMG SOI

with respect to those of a compatible single material gate (SMG) SOI MOSFET. The

major target parameters for comparison are as follows. The linear threshold voltage

(Vth,lin) is based on the maximum-gm method (linear extrapolation of ID – VGS to zero) at

VDS = 0.05 V. The saturation threshold voltage (Vth,sat) is based on a modified constant-

current method at VDS = 1 V [85]. The saturation current (Ion) is the drain current at VDS =

VGS = 1 V. The leakage current (Ioff) is the drain current at VGS = 0 V and VDS = 1 V (or

VDS = 0.05 V, as stated). The transconductance, gm, is extracted from the slope of ID-VGS

at VGS = VDS = 1 V. The drain conductance (gd) is extracted from the slope of ID - VDS

between VDS = 0.75 V and 1.25 V at VGS = 1 V. Fully depleted dual-material gate

(DMG) and single-material gate (SMG) SOI NMOS device structures are created and

simulated by the two-dimensional (2-D) device simulator MEDICI [10] with the device

parameters summarized in Table 5.1.

Table 5.1: Device parameters used for simulation of DMG and SMG SOI MOSFET’s.

Device parameters DMG SMG

Front gate oxide thickness, tf 5 nm 5 nm

Body doping, NA 6 x 1016cm-3 3.591 x 1017cm-3

Thin-film thickness, tSi 50 nm 50 nm

Buried oxide thickness, tb 400 nm 400 nm

Workfunction of M1 4.5 eV -

Workfunction of M2 4.1 eV -

Workfunction of SMG gate - 4.1 eV

62
5.2.1 Performance comparison with SMG SOI MOSFET

Output characteristics of the DMG and SMG SOI devices are compared for the

same channel length, L = 0.2 µm in Fig. 5.1. The workfunction of the gate metal for

SMG SOI is chosen as 4.1 eV. Choosing a body doping as NA = 6 x 1016 cm-3 for the

SMG SOI yields a threshold voltage, Vth = -0.059 V which is not suitable for performance

comparison. The body doping of SMG SOI device is thus chosen as NA = 3.591 x 1017

cm-3 which yields the same threshold voltage, Vth = 0.229 V for both the DMG and SMG

MOSFETs as shown in Fig. 5.2.

It is evident from Fig. 5.1 that the DMG SOI achieves a simultaneous reduction in

output conductance and an enhanced transconductance compared to the SMG SOI

MOSFET. This leads to an increased voltage gain. This unique feature of the DMG SOI

is not easily achievable by doping engineering [18].

1.0 L1 = 0.1 µm
L2 = 0.1 µm
φM1 = 4.5 V
0.8 φM2 = 4.1 V
ID (mA/µm)

VGS = 1.5 V
0.6

0.4
VGS = 1.0 V
0.2
DMG
VGS = 0.5 V SMG
0
0 0.4 0.8 1.2 1.6
VDS (Volts)
Fig. 5.1: Output characteristics compared for a DMG SOI with SMG SOI MOSFET.

63
 80 VDS = 50 mV
L1 = 0.1 µm
L2 = 0.1 µm
60 φM1 = 4.5 V
φM2 = 4.1 V
ID (µA/µm)
40

20
DMG
SMG
0
0 0.25 0.5 0.75 1.0
VGS (Volts)
Fig. 5.2: Gate characteristics compared for a DMG SOI with SMG SOI MOSFET.

To probe the physical mechanisms responsible for the improved performance of the

DMG SOI MOSFET, surface electric field and electron velocity profiles across the

channel for the DMG and SMG SOI are shown in Fig. 5.3. In a DMG SOI, the electric-

field discontinuity at the interface of the two gate metals (one-half of the channel for gate

lengths, L1 and L2, chosen) causes the overall channel field to be increased at the source

side, resulting in larger average velocity for the electrons entering the channel from the

source. The potential step also forces the channel field to redistribute mostly at the drain

side as the drain bias is increased (from 0.75 to 1 V). This screening effect is responsible

for the observed reduction in DIBL and channel length modulation (CLM). Also shown

in Fig. 5.3 are the comparisons with SMG SOI device having body doping same as that of

the DMG SOI MOSFET. It is evident from the figure that the enhanced source-side

electric field leads to an increased electron velocity in the channel for a DMG SOI

device.

64
 300 VGS = 0.8 V SMG (NA = 3.591 x 1017 cm-3)

Surface Electric Field (kV/cm)

L1 = 0.1 µm SMG (NA = 6 x 1016 cm-3)
DMG (NA = 6 x 1016 cm-3)
250 L2 = 0.1 µm
φM1 = 4.5 V
φM2 = 4.1 V
200

150 VDS = 1 V

100

50 VDS = 0.75 V

0
0 0.05 0.1 0.15 0.2
Position along channel (µm)
Fig. 5.3(a): Electric field profile along the surface of the channel for DMG and SMG SOI
MOSFET's.

1.6x107 VGS = 0.8 V

Mean Electron Velocity (cm/s)

L1 = 0.1 µm
L2 = 0.1 µm
1.2x107 φM1 = 4.5 V VDS = 1.0 V
φM2 = 4.1 V

8x106 VDS = 0.75 V

4x106
SMG (NA = 3.591 x 1017 cm-3)
SMG (NA = 6 x 1016 cm-3)
DMG (NA = 6 x 1016 cm-3)
0
0 0.05 0.1 0.15 0.2
Position along channel (µm)
Fig. 5.3(b): Electron velocity profile along the channel surface for DMG and SMG SOI
MOSFET's.

65
5.2.2 Scaling characteristics at a fixed high workfunction gate length, L1

Scaling characteristics are studied for different values of the metal M1 length L1,

with all other parameters taking their nominal values as summarized in Table 5.1. The

most significant improvement over the SMG SOI is the Vth roll-up for the DMG SOI

device as shown in Fig. 5.4. With the proper control over gate metal M1 length, L1,

threshold voltage will not be sensitive to the gate length, a desirable feature in deep-

submicron technology. The Vth roll-up is due to an increase in the portion of larger

workfunction gate M1, i.e., increase of L1/L2 ratio as L decreases (at fixed L1). The gate

M1 is the main control gate whereas M2 serves as the screen gate and with increasing

L1/L2 ratio as L decreases, Vth increases. The Vth roll-up also leads to a lower Ioff for the

DMG SOI MOSFET.

0.35 DMG SOI : L1 = 0.1 µm -0.02

φM1 = 4.5 V
φM2 = 4.1 V
0.30
-0.03
Threshold voltage, Vth (V)
Threshold voltage, Vth (V)

0.25
-0.04
0.20

0.15 -0.05

0.10
DMG
SMG (φM = 4.1 V) -0.06
0.05 SMG (φM = 4.5 V)

0 -0.07
0.1 0.2 0.3 0.4 0.5 0.6
Channel Length (µm)
Fig. 5.4: Comparison of threshold voltage variation with channel for DMG and SMG SOI
MOSFET’s.

66
5.2.3 Effect of L1/L2 ratio at a fixed channel length, L

At a fixed channel length L = L1 + L2, the location of the potential step can be tuned

for different values of the L1/L2 ratio. This feature is investigated with L1 ranging from 0

(SMG) to 0.25 µm at a fixed L = 0.3 µm for the target parameters of Vth,lin, Vth,sat, VDIBL,

Ion, Ioff, gm, gd, and gm/gd.

It is observed from Fig. 5.5 that as L1 increases (L1/L2 increases) threshold voltage

increases. This leads to a lowering of VDIBL and a consequent reduction in the influence

of drain electric field on the channel. However, as L1 increases saturation current

decreases although leakage current also decreases as shown in Fig. 5.6. This is mainly

due to the elevated threshold voltage at increasing L1.

0.35 L1+ L2 = 0.3 µm

100
φM1 = 4.5 V
0.3 φM2 = 4.1 V
80

DIBL, Vth,lin - Vth,sat (mV)

Threshold voltage, Vth (V)

0.25
60
0.2

0.15 40

0.1
Vth,lin
20
0.05 Vth,sat
DIBL
0 0
0 0.05 0.1 0.15 0.2 0.25 0.3
M1 gate length, L1 (µm)

Fig. 5.5: Variation of Vth,lin, Vth,sat and VDIBL with gate length L1 for a DMG SOI MOSFET at a
fixed channel length, L = 0.3µm.

67
 10-4 0.5
L1+ L2 = 0.3 µm
Off-state Leakage current, Ioff (A/µm) 10-5
φM1 = 4.5 V

Saturation current, I on (mA/µm)

φM2 = 4.1 V
0.4
10-6

0.3
10-7

10-8
0.2

10-9
Ioff (VDS = 50mV) 0.1
10-10 Ioff (VDS = 1 V)
Ion (VDS = 1 V)
10-11 0
0 0.05 0.1 0.15 0.2 0.25 0.3
M1 gate length, L1 (in µm)
Fig. 5.6: Variation of Ioff and Ion with gate length L1 for a DMG SOI MOSFET at a fixed channel
length, L = 0.3µm. L1 = 0 corresponds to SMG SOI.

As shown in Fig. 5.7(a), it is seen that as L1 increases the drain conductance, gd,

continues to decrease. With a larger portion of the channel being “screened” by the gate

M1, the influence of drain bias upon the channel current reduces. Fig. 5.7(a) also shows

the variation of transconductance, in saturation, for different values of L1 in a fully

depleted DMG SOI MOSFET. It is observed that gm is higher for a DMG SOI as

compared to the SMG (L1=0). However, with L1 → L, it theoretically lead to an SMG

SOI with a larger workfunction gate, consequently, gd increases and gm decreases as the

gate overdrive decreases due to elevated threshold voltage. Fig. 5.7(b) shows the

variation of voltage gain, gm/gd as function of M1 gate length, L1.

68
 100 L1 + L2 = 0.3µm
520
VGS = 1.0 V
500
80

480

gm (in µS/µm)
gd (in µS/µm)

60
460
40
440

20
gm 420
gd

0 400
0 0.05 0.1 0.15 0.2 0.25 0.3
M1 gate length, L1 (in µm)
Fig. 5.7(a): Variation of gm and gd with gate length L1 for a DMG SOI MOSFET at a fixed
channel length, L = 0.3 µm. L1 = 0 corresponds to SMG SOI.

20 φM1 = 4.5 V
φM2 = 4.1 V
L1 + L2 = 0.3µm
16 VDS = VGS = 1.0 V
Voltage gain, gm/gd

12

0
0 0.05 0.1 0.15 0.2 0.25 0.3
M1 gate length, L1 (in µm)
Fig. 5.7(b): Variation of voltage gain, gm/gd, with gate length L1 for a DMG SOI MOSFET at a
fixed channel length, L = 0.3 µm. L1 = 0 corresponds to SMG SOI.

69
 From Figs. 5.5-5.7 it is observed that the optimum ratio of gate metal lengths, L1

and L2, for both logic and analog circuits application is L1/L2 = 1. With L1/L2 = 1, we get

a reduced DIBL, lower off-state current, higher gm, reduced off-state current, Ioff and a

higher voltage gain, gm/gd, in comparison to a SMG SOI MOSFET. This conclusion is

based on the simulations done for a channel length, L = 0.3 µm DMG SOI MOSFET.

Figs. 5.8-5.10 plot the threshold voltage variation, on/off-current variation, gm and

gd variation and voltage gain variation versus the channel region under gate M1, L1, for a

DMG SOI device with channel length, L = 0.2 µm. The curves show behavior similar to

that observed for L = 0.3 µm. It is seen from Figs. 5.8-5.10 that a gate length ratio,

L1/L2 = 1, is most beneficial for VLSI circuit applications.

0.35 L1+ L2 = 0.2 µm 160

φM1 = 4.5 V
0.30 φM2 = 4.1 V

DIBL, Vth,lin - Vth,sat (mV)

Threshold voltage, Vth (V)

140
0.25

0.20
120
0.15

0.10
100
DIBL
0.05 Vth,lin
Vth,sat

0 80
0 0.05 0.1 0.15 0.2
M1 gate length, L1 (µm)
Fig. 5.8: Variation of Vth,lin, Vth,sat and VDIBL with gate length L1 for a DMG SOI MOSFET at a
fixed channel length, L = 0.2 µm.

70
 10-4 0.5
L1+ L2 = 0.2 µm

Off-state Leakage current, Ioff (A/µm)

φM1 = 4.5 V

Saturation current, I on (mA/µm)

10-5 φM2 = 4.1 V
0.4

10-6
0.3
10-7
0.2
10-8

Ioff (VDS=50mV) 0.1

10-9 Ioff (VDS=1V)
Ion (VDS=1V)

10-10 0
0 0.05 0.1 0.15 0.2
M1 gate length, L1 (in µm)
Fig. 5.9: Variation of Ioff and Ion with gate length L1 for a DMG SOI MOSFET at a fixed channel
length, L = 0.2 µm. L1 = 0 corresponds to SMG SOI.

120 580
L1 + L2 = 0.2µm
VGS = 1.0 V
100
560

80
gm (in µS/µm)
gd (in µS/µm)

540
60
520
40

500
20 gd
gm

0 480
0 0.05 0.1 0.15 0.2
M1 gate length, L1 (in µm)
Fig. 5.10(a): Variation of gm and gd with gate length L1 for a DMG SOI MOSFET at a fixed
channel length, L = 0.2 µm. L1 = 0 corresponds to SMG SOI.

71
 15

Voltage gain, gm/gd 12

L1 + L2 = 0.2 µm
3 VDS = VGS = 1.0 V

0
0 0.05 0.1 0.15 0.2
M1 gate length, L1 (in µm)
Fig. 5.10(b): Variation of voltage gain, gm/gd, with gate length L1 for a DMG SOI MOSFET at a
fixed channel length, L = 0.2 µm. L1 = 0 corresponds to SMG SOI.

5.2.4 Effect of workfunction difference (∆W) at a fixed channel length, L

At a fixed ratio of gate metal lengths, L1/L2 = 1, the effect of metal M1

workfunction on the performance of the DMG SOI MOSFET is studied by varying its

values. The workfunction of metal M2 is kept fixed at 4.1 eV. The results are shown in

Figs. 5.11-5.14. Like the L1/L2 ratio dependence, threshold voltage increases with

increasing workfunction difference between the two gate materials. This is due to the

increased workfunction of the gate M1. A minimum VDIBL occurs at ∆W = 0.4 eV as

shown in Fig. 5.11.

72
 0.8 L1 = 0.15 µm
100
L2 = 0.15 µm
0.7 φM2 = 4.1 V
80

DIBL, Vth,lin - Vth,sat (mV)

Threshold voltage, Vth (V)
0.6

0.5 60
0.4
40
0.3

0.2
Vth,lin
20
0.1 Vth,sat
DIBL
0 0
0 0.2 0.4 0.6 0.8 1.0
Workfunction Difference, ∆W (eV)
Fig. 5.11: Variation of Vth,lin, Vth,sat and VDIBL with workfunction difference, ∆W for a DMG SOI
MOSFET at a fixed channel length, L = 0.3µm.

A significant result of this investigation is the tunability of the threshold voltage by

“gate workfunction engineering” which provides another degree of freedom for

ultrasmall SOI MOSFET design. On-/off-state currents also exhibit behavior similar to

the L1/L2 ratio variation as shown in Fig. 5.12. As a result of increased Vth at increasing

∆W, Ioff as well as Ion decrease. Increased ∆W (i.e., larger potential step at the metal gate

interface) also favours gd reduction as shown in Fig. 5.13. Whereas, gm decreases after

∆W = 0.4 eV due to reduced overdrive voltage available at the elevated threshold voltage

for a fixed gate bias. Fig. 5.14 shows the voltage gain, gm/gd as function of workfunction

difference, ∆W. As shown in the figure, voltage gain increases with increasing

workfunction difference but this trade-offs with elevated Vth, reduced Ion and reduced gm

at higher ∆W. Thus a ∆W = 0.4 eV is most suitable for VLSI circuit applications.

73
 10-5 0.4
L1 = 0.15 µm
L2 = 0.15 µm

Off-state Leakage current, Ioff (A/µm)

10-6
φM2 = 4.1 V

Saturation current, Ion (mA/µm)

10-7
0.3
10-8

10-9
0.2
10-10
10-11
0.1
10-12
Ioff (VDS = 50mV)
10-13 Ioff (VDS = 1 V)
Ion (VDS = 1 V)
10-14 0
0 0.2 0.4 0.6 0.8 1.0
Workfunction Difference, ∆W (eV)
Fig. 5.12: Variation of Ioff and Ion with workfunction difference, ∆W for a DMG SOI MOSFET at
a fixed channel length, L = 0.3µm.

80 L1 = 0.15 µm 500
L2 = 0.15 µm
φM2 = 4.1 V
480
60
gm (in µS/µm)
gd (in µS/µm)

460
40
440

20
420
gm
gd

0 400
0 0.2 0.4 0.6 0.8 1.0
Workfunction Difference, ∆W (eV)
Fig. 5.13: Variation of gm and gd with workfunction difference, ∆W for a DMG SOI MOSFET at
a fixed channel length, L = 0.3µm.

74
 40

30
Voltage gain, gm/gd

20

L1 = 0.15 µm
10 L2 = 0.15 µm
φM2 = 4.1 V
VDS = VGS = 1.0 V

0
0 0.2 0.4 0.6 0.8 1.0
Workfunction Difference, ∆W (eV)
Fig. 5.14: Variation of voltage gain, gm/gd, with workfunction difference, ∆W for a DMG SOI
MOSFET at a fixed channel length, L = 0.3 µm.

The results thus obtained for a fully depleted DMG SOI MOSFET point out an

optimum metal gate length ratio, L1/L2 = 1 and a workfunction difference, ∆W = 0.4 eV.

5.3 Summary

The novel properties of fully depleted dual-material gate (DMG) SOI MOSFET

have been studied in the context of its potential integration in the current CMOS

technology. The unique features of the DMG which are not easily available in the

conventional SOI devices include: Vth “roll-up”, reduced DIBL and simultaneous

transconductance enhancement and SCE suppression which can be controlled by gate

material engineering.

One of the difficulties in integrating DMG structure in the present CMOS

technology maybe its asymmetric structure, but Zhou [22] suggested two fabrication

75
procedures requiring only one additional mask step. Moreover, the proposed DMG SOI

may also be employed in symmetric structures (like a LDD spacer). With the CMOS

processing technology already into the sub-100 nm regime [80], fabricating a 50 nm

feature gate length should not preclude the possibility of realizing the potential benefits

and excellent immunity against SCE’s that the DMG SOI MOSFET promises.

76
 CHAPTER VI
CONCLUSIONS

The conclusions derived from the present work are divided into three categories,

namely, (a) Surface Potential Model for a fully depleted (FD) dual-material gate (DMG)

SOI MOSFET, (b) Analytical expression for Threshold voltage, and (c) 2-D numerical

simulation studies.

a) Surface Potential Model

Analytical model of surface potential along the channel in a FD DMG SOI MOS

device is modeled by solving the 2-D Poisson’s equation using a parabolic

approximation. The conclusions are:

1. The model predicts the creation of a step in the channel potential profile due to

the co-existence of two different gate materials having a finite workfunction

difference and controllable gate lengths. The existence of mobile carriers is

neglected.

2. The shift in the surface channel potential minima position is negligible with

increasing drain biases. This leads to excellent immunity against short-channel

effects (SCE) like drain-induced barrier lowering (DIBL) and channel length

modulation (CLM).

3. The electric field in the channel at the drain end is lowered leading to reduced

hot-carrier effect.

4. The channel potential profile can be tuned by “gate-material engineering”, i.e., the

dependence of surface potential on the difference between the gate material

workfunctions and the lengths of the two gate metals.

77
 5. The model includes the effect of various MOS parameters like body doping

concentration, applied drain and substrate biases, the thickness of thin-film, gate

oxide and buried oxide.

b) Threshold Voltage

An analytical threshold voltage expression is derived based on the surface potential

model. The conclusions are:

1. Threshold voltage, Vth, rolls-up with decreasing channel length in a DMG SOI

down to 0.1 µm by carefully engineering the length and workfunction of the gate

materials.

2. Minimum channel potential and consequently Vth sensitivity to thin-film thickness

of a DMG SOI is reduced in comparison to a single material gate (SMG) SOI.

3. The effect of various MOS parameters like body doping density, applied substrate

bias, the thickness of thin-film, gate oxide and buried oxide on the threshold

voltage can be visualized with the help of the analytical expression.

c) Two-dimensional simulation studies

2-D MEDICI simulations were used to explore and compare the novel attributes

offered by the DMG structure with a conventional SMG SOI in terms of Vth variation

with decreasing channel length, drain-induced barrier-lowering (DIBL), leakage current,

drive current, transconductance, drain conductance and voltage gain. The conclusions

are:

1. The unique features of the DMG are: Vth roll-up with decreasing channel length,

reduced DIBL and simultaneous transconductance enhancement and SCE

suppression. These features can be controlled by a new way of gate material

78
 engineering.

2. A gate length ratio of L1/L2 = 1 and a workfunction difference of ∆W = 0.4 eV is

found to be optimum for both logic and analog applications for a FD DMG SOI

MOSFET.

SCOPE FOR FUTURE WORK

This problem has several possible extensions that could be attempted as ongoing

research work. Some specific recommendations based on the present work are as

follows:

1. The present study can be well extended to partially depleted DMG SOI

MOSFETs.

2. A lot of scope lies in studying the effect of DMG structure on devices employing

wide bandgap materials like SiC.

3. Experimental results can provide further confirmation of the efficacy of the DMG

structure on SOI devices.

79
 APPENDIX A

COMMENT Fully depleted DMG-SOI with channel length L = 0.2 µm

COMMENT Specify a Rectangular Mesh

MESH SMOOTH=1

COMMENT X-mesh: gate length of 0.2 µm.

X.MESH X.MAX=0.25 H1=0.05
X.MESH X.MIN=0.25 H1=0.01 X.MAX=0.45
X.MESH X.MIN=0.45 H1=0.05 WIDTH=0.25

COMMENT Y-mesh: gate oxide of 5 nm, thin-film thickness of 50 nm.

Y.MESH N=1 L=-0.0150
Y.MESH N=4 L=0
Y.MESH DEPTH=0.05 H1=0.0125
Y.MESH DEPTH=0.5 H1=0.0250
Y.MESH DEPTH=.5 H1=0.250

COMMENT Eliminate Some Unnecessary Substrate Nodes

ELIMIN COLUMNS Y.MIN=0.05 X.MIN=0.3 X.MAX=0.8

COMMENT Specify Oxide and Silicon Regions

REGION SILICON
REGION OXIDE IY.MAX=4
REGION OXIDE Y.MIN=.05 Y.MAX=0.5

COMMENT Electrode Definition

ELECTR NAME=Gate1 X.MIN=.25 X.MAX=0.35 IY.MIN=1 IY.MAX=3
ELECTR NAME=Gate2 X.MIN=.35001 X.MAX=0.45 IY.MIN=1 IY.MAX=3
ELECTR NAME=Substrate BOTTOM
ELECTR NAME=Source X.MAX=.2 IY.MAX=4
ELECTR NAME=Drain X.MIN=0.5 IY.MAX=4

COMMENT Specify impurity profile in the source/drain and body region

PROFILE P-TYPE N.PEAK=6E16 UNIFORM OUT.FILE=DMGSOI1DS_20
PROFILE N-TYPE N.PEAK=5E19 UNIFORM Y.MAX=.05 X.MIN=0 X.MAX=.25
PROFILE N-TYPE N.PEAK=5E19 Y.MAX=.05 X.MIN=.45 UNIFORM

PLOT.2D GRID TITLE="INITIAL GRID" FILL SCALE

COMMENT Gate workfunction specification

CONTACT NAME=Gate1 WORKFUNC=4.77
CONTACT NAME=Gate2 WORKFUNC=4.1

COMMENT Specify Physical Models to use

MODELS CONMOB SRFMOB CONSRH FLDMOB AUGER BGN

81
COMMENT Symbolic Factorization, Solve, Regrid on Potential
SYMB CARRIERS=0
METHOD ICCG DAMPED
SOLVE

REGRID POTEN IGNORE=OXIDE RATIO=1.0 MAX=1 SMOOTH=1

+ IN.FILE=DMGSOI1DS_20
+ OUT.FILE=DMGSOI1MS_20
PLOT.2D GRID TITLE="SOI-NMOSFET - POTENTIAL REGRID" FILL SCALE

COMMENT Solve using Refined Grid save solution for later use
SYMB CARRIERS=0
SOLVE OUT.FILE=DMGSOI1S_20

PLOT.2D BOUND TITLE="SOI-NMOSFET - IMPURITY CONTOURS" FILL SCALE

+ DEPLETIO
CONTOUR DOPING LOG MIN=16 MAX=20 DEL=.5 COLOR=2
CONTOUR DOPING LOG MIN=-16 MAX=-15 DEL=.5 COLOR=1 LINE=2

PLOT.2D BOUND TITLE="DMG-SOI" FILL SCALE DEPLETIO

CONTOUR ELECTRON COLOR=2
CONTOUR HOLES COLOR=4

COMMENT Plot the potential at top and bottom Si/SiO2 interface at zero bias
PLOT.1D POTENTIA CURVE COLOR=4 X.START=0.0 X.END=.7 Y.START=0.0
+ Y.END=0.0 TITLE="SURFACE POTENTIAL DISTRIBUTION"

PLOT.1D POTENTIA CURVE COLOR=2 X.START=0.0 X.END=.7 Y.START=.05

+ Y.END=0.05 TITLE="BOTTOM POTENTIAL DISTRIBUTION" UNCHANGE

82
 APPENDIX B

COMMENT Drain Characteristics for a DMG SOI with channel length, L = 0.2 µm.

COMMENT Read in Simulation Mesh

MESH IN.FILE=DMGSOI1MS_20

COMMENT Read in Initial Solution

LOAD IN.FILE=DMGSOI1S_20

COMMENT Do a Poisson Solve only to Bias the Gate

SYMB CARRIERS=0
METHOD ICCG DAMPED CONT.STK=8
SOLVE V(Gate1)=0 V(Gate2)=0

COMMENT Use Newton's Method and Solve for Electrons

SYMB NEWTON CARRIERS=1 ELECTRONS

COMMENT Set-up logfile for I-V data

LOG OUT.FILE=DMGSOI1DI_20

COMMENT Ramp the Drain Voltage

SOLVE V(DRAIN)=0 ELEC=DRAIN VSTEP=.25 NSTEP=6

COMMENT Plot IDS vs. VDS

PLOT.1D Y.AXIS=I(DRAIN) X.AXIS=V(DRAIN) CURVE COLOR=4
+ TITLE="DRAIN CHARACTERISTICS " IN.FILE=DMGSOI1DI_20

83
 APPENDIX C

COMMENT Gate Characteristics for a 0.2 µm DMG SOI MOSFET.

COMMENT Read in Simulation Mesh

MESH IN.FILE=DMGSOI1MS_20

COMMENT Read in Saved Solution

LOAD IN.FILE=DMDSOI1S_20

COMMENT Use Newton's Method for the solution

SYMB NEWTON CARRIERS=1 ELECTRONS

COMMENT Setup logfile for IV data

LOG OUT.FILE=DMDSOI1GI_20

COMMENT Solve for VDS =0.05 V and then Ramp the Gate
SOLVE V(DRAIN)=0.05
SOLVE V(GATE1)=0 V(GATE2)=0 ELEC=(Gate1,Gate2) VSTEP=.05 NSTEP=25

COMMENT Plot IDS vs VGSand save the data

PLOT.1D Y.AXIS=I(DRAIN) X.AXIS=V(Gate1) CURVE COLOR=2
+ TITLE="GATE CHARACTERISTICS" OUT.FILE=gate

COMMENT Extract MOS parameters like the linear threshold voltage, channel length, etc.
EXTRACT MOS.PARA IN.FILE=DMDSOI1GI_20 GATE=Gate1

84
 APPENDIX D

COMMENT Extraction of Surface Electric Field, Mean Electron Velocity and Potential.

COMMENT Read in Simulation Mesh

MESH IN.FILE=DMGSOI1MS_20

COMMENT Read in Saved Solution

LOAD IN.FILE=DMGSOI1S_20

COMMENT Use Newton's Method for the solution

SYMB NEWTON CARRIERS=1 ELECTRONS
METHOD ICCG DAMPED STACK=10

COMMENT Set-up logfile for IV data

LOG OUT.FILE=DMGSOI1EI_20

COMMENT Solve for VDS =1 V and VGS = 0 V

SOLVE V(Gate1)=0 V(Gate2)=0 V(Substrate)=0.0 V(DRAIN)=1

COMMENT Plot Surface Electric Field

PLOT.1D E.FIELD CURVE COLOR=2 X.START=0.25 X.END=.45 Y.START=0.0
+ Y.END=0.0 TITLE="ELECTRIC FIELD DISTRIBUTION"

COMMENT Plot Mean Electron Velocity in the channel

PLOT.1D ELE.VEL CURVE COLOR=2 X.START=0.25 X.END=.45 Y.START=0.0
+ Y.END=0.0 TITLE="AVERAGE VELOCITY DISTRIBUTION"

COMMENT Plot Surface Potential

PLOT.1D POTENTIA CURVE COLOR=2 X.START=0.25 X.END=.45 Y.START=0.0
+ Y.END=0.0 TITLE="SURFACE POTENTIAL DISTRIBUTION"

85
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 LIST OF PUBLICATIONS
1. “Two-dimensional analytical modeling of Fully Depleted Dual-Material Gate
(DMG) SOI MOSFET and Evidence for Diminished Short-channel Effects,”
Accepted subject to appropriate revision in IEEE Transactions on Electron
Devices, 2003.
2. “Analysis of Short-Channel Effects in SOI MOSFETs for sub-100nm CMOS
Technology,” Accepted in the Proc. of the 12th International Workshop on Physics
of Semiconductor Devices, IWPSD-2003, December 16th – 20th.
3. “Exploring the Novel Characteristics of Fully Depleted Dual-Material Gate
(DMG) SOI MOSFET using Two-Dimensional Numerical Simulation Studies,”
Accepted in the Proc. of the 17th International Conference on VLSI Design,
January 5th – 9th, 2004.
4. “Investigation of the Novel Attributes of a Fully Depleted (FD) Dual-Material
Gate (DMG) SOI MOSFET,” Accepted subject to appropriate revision in IEEE
Transactions on Electron Devices, 2003.
5. “Controlling short-channel effects in deep submicron SOI MOSFETs for
improved reliability: A Review,” Revised manuscript under review with IEEE
Transactions on Device and Materials Reliability, 2003.

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