XLX s6 Lx75t Dev-Ug Reva032811

Xilinx
Spartan
-6 LX75T
Development Kit
User Guide

Copyright 2011 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other brands are property of their respective owners.

Avnet Electronics Marketing 2 of 36 Rev A 1.0 03/29/2011

Table of Contents

1.0 Introduction ............................................................................................................................................................................... 5
1.1 Description ............................................................................................................................................................................ 5
1.2 Board Features ..................................................................................................................................................................... 5
1.3 Test Files .............................................................................................................................................................................. 5
1.4 Reference Designs ............................................................................................................................................................... 6
1.5 Ordering Information ............................................................................................................................................................. 7
2.0 Functional Description .............................................................................................................................................................. 8
2.1 Xilinx Spartan-6 LX75T FPGA .............................................................................................................................................. 9
2.2 GTP Interface ....................................................................................................................................................................... 9
2.2.1 GTP Reference Clock Inputs .......................................................................................................................................... 10
2.2.2 PCI Express x1 Add-in Card .......................................................................................................................................... 11
2.2.2.1 PCIe Configuration Timing ......................................................................................................................................... 12
2.2.3 GTP on FMC Expansion Connector JX1 ........................................................................................................................ 12
2.3 Memory............................................................................................................................................................................... 12
2.3.1 DDR3 SDRAM Interface................................................................................................................................................. 12
2.3.2 Numonyx Flash Interface ............................................................................................................................................... 17
2.3.3 SPI Flash Interface ......................................................................................................................................................... 18
2.4 Clock Sources .................................................................................................................................................................... 18
2.4.1 CDCM61001 Programmable LVDS Clock Synthesizer .................................................................................................. 20
2.4.1.1 CDCM61001 Clock Generation ................................................................................................................................. 21
2.4.1.2 CDCM61001 Programming Mode .............................................................................................................................. 22
2.5 Communication ................................................................................................................................................................... 22
2.5.1 10/100 Ethernet PHY ..................................................................................................................................................... 22
2.5.2 USB-RS232 .................................................................................................................................................................... 23
2.6 User Switches ..................................................................................................................................................................... 23
2.7 User LEDs .......................................................................................................................................................................... 24
2.8 Configuration ...................................................................................................................................................................... 24
2.8.1 Configuration Modes ...................................................................................................................................................... 24
2.8.2 JTAG Chain .................................................................................................................................................................... 24
2.9 Expansion Connectors ....................................................................................................................................................... 25
2.9.1 FMC Low Pin Count (LPC) Interface .............................................................................................................................. 25
2.9.2 Avnet Mini Expansion Port (MXP) .................................................................................................................................. 30
2.9.3 PMOD Headers .............................................................................................................................................................. 30
2.10 EEPROM with SHA ............................................................................................................................................................ 31
2.11 MAX1409 ADC/DAC/RTC .................................................................................................................................................. 31
2.12 Power ................................................................................................................................................................................. 32
2.12.1 FPGA I/O Voltage (VCCO) ........................................................................................................................................ 33
2.12.2 FPGA Reference Voltage (Vref) ................................................................................................................................ 33
2.12.3 GTP Voltage Regulators (AVCC, AVCCPLL, VTTRX, VTTTX, AVTTRCAL) ............................................................. 33
2.13 Thermal Management ........................................................................................................................................................ 34
3.0 Test Designs ........................................................................................................................................................................... 34
3.1 Factory Test ........................................................................................................................................................................ 34
Appendix A ........................................................................................................................................................................................... 35


Figures

Figure 1 - Spartan-6 LX75T FPGA Development Board Picture ................................................................................................................ 6
Figure 2 - Spartan-6 LX75T FPGA Development Board Block Diagram .................................................................................................... 8
Figure 3 - GTP Ports on the Spartan-6 LX75T Development Board ......................................................................................................... 10
Figure 4 - GTP Clock Sources on the Spartan-6 LX75T development board ........................................................................................... 10
Figure 5 - PCI Express x1 Interface ......................................................................................................................................................... 11
Figure 6 - DDR3 SDRAM Interface MCB4............................................................................................................................................. 13
Figure 7- DDR3 SDRAM Interface MCB5.............................................................................................................................................. 14
Figure 8 - Flash Interface ......................................................................................................................................................................... 17
Figure 9 - S6LX75T Development Board SPI Flash Interface .................................................................................................................. 18
Figure 10 - Clock Nets Connected to Global Clock Inputs........................................................................................................................ 19
Figure 11 - CDCM61001 Clock Synthesizer ............................................................................................................................................. 21
Figure 12 - 10/100 Mb/s Ethernet Interface .............................................................................................................................................. 22
Figure 13 - JTAG Chain on the Spartan-6 PCI Express Board ................................................................................................................. 24
Figure 14 FMC LPC Connector Pinout .................................................................................................................................................. 26
Figure 15 - FMC LPC Connector JX1 Block Diagram .............................................................................................................................. 27
Figure 16 - Power Supply Bock Diagram.................................................................................................................................................. 33
Figure 17 - Board Jumpers, Headers, Connectors ................................................................................................................................... 35


Tables

Table 1 - Ordering Information ................................................................................................................................................................... 7
Table 2 - XC6SLX75T FPGA Features ...................................................................................................................................................... 9
Table 3 - Communications Standards Supported by the Spartan-6 GTP ................................................................................................... 9
Table 4 - GTP Placement Names ............................................................................................................................................................... 9
Table 5 - GTP Pin Locations for PCI Express .......................................................................................................................................... 11
Table 6 - GTP Pin Assignments for FMC Connectors .............................................................................................................................. 12
Table 7 - FPGA Pin Locations for MCB4 DDR3 SDRAM ......................................................................................................................... 15
Table 8 - FPGA Pin Locations for MCB5 DDR3 SDRAM ......................................................................................................................... 16
Table 9 - Flash Interface Pin Locations .................................................................................................................................................... 17
Table 10 - On-Board Clock Sources ......................................................................................................................................................... 20
Table 11 - Clock Socket "U5" Pin-out ....................................................................................................................................................... 20
Table 12 - CDCM61001 Clock Synthesizer Pin Description ..................................................................................................................... 21
Table 13 - CDCM61001 Common Application Settings ............................................................................................................................ 22
Table 14 - Ethernet PHY U7 Pin Locations ............................................................................................................................................ 23
Table 15 - USB-to-RS232 Pin Locations .................................................................................................................................................. 23
Table 16 - Push Button Pin Locations ...................................................................................................................................................... 23
Table 17 - DIP Switch Pin Locations ........................................................................................................................................................ 24
Table 18 - LED Pin Locations ................................................................................................................................................................... 24
Table 19 Setting the Configuration Mode JP3 ..................................................................................................................................... 24
Table 20 FMC LPC Connector Signals ................................................................................................................................................. 25
Table 21 FMC LPC Connector JX1 Pin Locations ................................................................................................................................. 30
Table 22 Mini-Expansion Port (MXP) Pin Connections ......................................................................................................................... 30
Table 23 Peripheral Module Pin Connections J4 ................................................................................................................................ 31
Table 24 Peripheral Module Pin Connections J6 ................................................................................................................................ 31
Table 25 SHA-1 EEPROM Pin Connections ......................................................................................................................................... 31
Table 26 MAX1409 Pin Assignments J10 .......................................................................................................................................... 31
Table 27 MAX1409 Pin Connections ..................................................................................................................................................... 32
Table 28 I/O Bank Voltages ................................................................................................................................................................... 33
Table 29 - Typical Current Measurements per MGT Tile.......................................................................................................................... 34


1.0 Introduction
The purpose of this manual is to describe the functionality and contents of the Spartan-6 FPGA LX75T Development Kit from Avnet
Electronics Marketing. This document includes instructions for operating the board, descriptions of the hardware features and
explanations of the test code programmed in the on-board SPI flash.
1.1 Description
The Spartan-6 LX75T FPGA Development Kit provides a complete hardware environment for designers to accelerate their
time to market. The kit delivers a stable platform to develop and test designs targeted to the advanced Xilinx FPGA family.
The installed Spartan-6 LX75T device offers a prototyping environment to effectively demonstrate the enhanced benefits of
leading edge Xilinx FPGA solutions. Reference designs are included with the kit to exercise standard peripherals on the
evaluation board for a quick start to device familiarization.

1.2 Board Features
FPGA
Xilinx Spartan-6 XC6SLX75T-3FGG676C FPGA

I/O Connectors
One FMC LPC general-purpose I/O expansion connectors
One MXP User I/O connector
Two PMOD connectors

RocketIO GTP Transceiver Connectors
One transceiver supplied on an FMC connectors for use by an expansion module
One PCI Express add-in card interface (1 lanes @ 2.5 Gbps)

Memory
256 MB DDR3 SDRAM components (2 banks of 128 MB x 16)
32 MB Parallel Flash (x16)
1 Kb EEPROM with SHA-1 Engine

Communication
USB-RS232 Port
10/100 Ethernet port

Power
Regulated 5.0V, 3.3V, 2.5V, 1.5V and 1.2V supply voltages derived from the PCI Express slot or an external 12 V
supply
SSTL2 Termination Regulators
Point of Load Regulators for MGT supply rails

Configuration
16 MB Multi-bit (x4) SPI Flash
Xilinx Parallel Cable IV or Platform USB Cable support for JTAG Programming/Configuration

Other
Four User LEDs
Four User Push Buttons
Four User DIP Switches
ADC/DAC/RTC combination device

1.3 Test Files
The configuration SPI flash on the Spartan-6 FPGA LX75T development board comes programmed with a factory test
example design. Additional test files that can be used to verify the functionality of the peripherals on the board can be found
on the Avnet Electronics Marketing Design Resource Center (DRC) web site: www.em.avnet.com/spartan6lx75t-pcie. The
test design listed below is discussed in Section 3.0.

Factory Test


1.4 Reference Designs
Reference designs that demonstrate some of the potential applications of the Spartan-6 LX75T FPGA Development Board
can be downloaded from the Avnet Design Resource Center (www.em.avnet.com/spartan6lx75t-pcie). The reference
designs include all of the source code and project files necessary to implement the designs. See the PDF document included
with each reference design for a complete description of the design and detailed instructions for running a demonstration on
the development board. Check the DRC periodically for updates and new designs.

Figure 1 - Spartan-6 LX75T FPGA Development Board Picture



1.5 Ordering Information
The following table lists the evaluation kit part numbers and available software options.
Internet link at www.em.avnet.com/spartan6lx75t-pcie and www.em.avnet.com/spartan6atom

Part Number Hardware
AES-S6PCIE-LX75T-G
Xilinx Spartan-6 LX75T Development Kit populated with an
XC6SLX75T-FGG676C
-3 speed grade device
AES-S6NITX-LX75T-G Nano-ITX/Spartan-6 FPGA Development Kit
AES-S6NITX-LX75T-AOK-G
Spartan-6 LX75T add-on kit for Intel Starter Kit (Emerson NITX-315
SBC with Intel Atom E640 processor
Table 1 - Ordering Information


2.0 Functional Description
A high-level block diagram of the Spartan-6 LX75T development board is shown below followed by a brief description of each sub-
section.
Spartan-6
LX75T
FG676
(348 I/O)
DIP Switches
(4 I/O)
User LEDs
(4 I/O)
10/100 PHY
(18 I/O)
Communication Ports
Push Switches
(4 I/O)
JTAG Port
Miscellaneous I/O
128 MB DDR3 SDRAM
(x16, 48 I/O)
Memory Interfaces
128 MB DDR3 SDRAM
(x16, 48 I/O)
GTP Interfaces
PCI-Express x1
(1 I/O, 1 GTP)
USB-RS232 Bridge
(2 I/O)
2x PMOD
(16 I/O)
SHA-1 EEPROM
(1 I/O)
Clock Sources
LVTTL OSC
@ 100 MHz
LVTTL OSC Socket
MXP USER I/O
(35 I/O)
SPI ADC/DAC/RTC
(5 I/O)
FMC LPC Slot
(84 I/O, 1 GTP)
C
o
n
n
e
c
t
o
r
Voltage Regulators
5.0V
(MXP I/O)
3.3V
(PMOD, FPGA)
2.5V
(FMC, FPGA)
1.5V
(DDR3, FPGA)
1.2V
(MGT_CORE)
LVTTL OSC
@ 40 MHz
16 MB Multi-bit SPI Flash
(x4, 6 I/O)
Configuration & User Storage
1.2V
(MGT_TERM)
0.75V
(DDR3_REF)
32 MB BPI Flash
(x16, 46 I/O)
User Storage

Figure 2 - Spartan-6 LX75T FPGA Development Board Block Diagram


2.1 Xilinx Spartan-6 LX75T FPGA
The Spartan-6 LX75T FPGA devices available in the FG676 package have four embedded memory controller blocks, one
embedded PCI Express Endpoint Block and six Clock Management Tiles (each tile contains two DCMs and one PLL).

Device
Number of
Slices
BlockRAM
(Kb)
DSP48A1
Slices
GTP
Transceivers
I/O Pins
XC6SLX150T 11,662 3096 132 8 348
Table 2 - XC6SLX75T FPGA Features
The Spartan-6 LX75T PCI Express Development Board uses production silicon devices. The pin-out used for the PCI Express
interface supports the Xilinx recommended pin-out for production silicon.
2.2 GTP Interface
The RocketIO GTP Transceiver is a full-duplex serial transceiver for point-to-point transmission applications. Up to 8
transceivers are available on a single Spartan-6 LX75T FPGA. The transceiver block is designed to operate at any serial bit
rate in the range of 614 Mb/s to 3.125 Gb/s per channel , including the specific bit rates used by the communications standards
listed in the following table. Only the -3 speed grade part is capable of 3.125 Gb/s. The -2 speed grade part is capable of 2.7
Gb/s. Multiple channels can be bonded together for increased data throughput. The data width of the FPGA fabric interface i s
programmable (one or two bytes) allowing the parallel data frequency to be tailored to the user application. The table below
lists a sub-set of protocols supported by the Spartan-6 GTP.

Standards
Channels (# of
transceivers)
I/O Bit Rate (Gb/s)
PCI Express 1, 2, 4 2.5
SFI-5 1 2.488 3.125
OC-12 1 0.622
OC-48 1 2.488
Fibre Channel 1
1.06
2.12
Gigabit Ethernet 1 1.25
10-Gbit Fibre Channel 4 3.1875
Infiniband 1, 4 2.5
HD-SDI 1
1.485
1.4835
Serial ATA 1
1.5
3.0
Serial Rapid I/O 1, 4
1.25
2.5
3.125
Aurora (Xilinx protocol) 1, 2, 3, 4, 0.100 3.75
Table 3 - Communications Standards Supported by the Spartan-6 GTP

The Spartan-6 LXT transceivers are grouped into tiles with two transceivers per tile. The two transceivers in each tile share a
single PLL and other resources involving the reset and power control. A trailing number 0 or 1 is used to distinguish
between the two transceivers in the tile. These transceiver tiles are physically located into a single column on the die. Each
tile has a placement name associated to its X-Y coordinate on the die. For example, GTP_Dual_X0Y0 is the first tile in the
column. The GTP_Dual placement name is used in the User Constraint File (UCF) to map specific tiles on the device to those
instantiated in a HDL design.

GTP
Interface
Lanes
Number
S6LX150T
FMC - GTP_Dual_X0Y0 MGT245_0
PCI Express 0 GTP_Dual_X0Y1 MGT101_0
Table 4 - GTP Placement Names

The following figure shows the two RocketIO transceiver ports used on the Spartan-6 LX75T development board. The GTP
tiles are depicted in their actual locations.

SPARTAN 6
LX75T
FPGA
G
T
P
1
0
1
TXP
TXN
RXP
RXN
G
T
P
2
4
5
TXP
TXN
RXP
RXN
PCIe
x1
FMC

Figure 3 - GTP Ports on the Spartan-6 LX75T FPGA Development Board

2.2.1 GTP Reference Clock Inputs
Each GTP_Dual tile has a reference clock input that can also be used by any adjacent dual tile. Several of these reference
clock inputs are supplied by on-board clock sources while others are supplied externally. A single programmable LVDS
synthesizer is used to provide variable clock sources to the dedicated GTP clock inputs. This synthesizer provides reference
clock frequencies that support the full range of line rates. PCI Express applications use the 100 MHz reference clock provided
over the card edge. The following figure shows the clock sources provided to the dedicated GTP clock inputs.

SPARTAN 6
GTPREFCLKP_101_0
GTPREFCLKN_101_0
GTPREFCLKP0_245
GTPREFCLKN0_245
GTPREFCLKP1_245
GTPREFCLKN1_245
PCIe_REFCLK_P
PCIe_REFCLK_N
CLKSYN0_REFCLK_P
CLKSYN0_REFCLK_N
CDCM60001
FMC_DP0_M2C_P
FMC_DP0_M2C_N
JX1
PCIe Edge
Connector

Figure 4 - GTP Clock Sources on the Spartan-6 LX75T FPGA Development Board


2.2.2 PCI Express x1 Add-in Card
One of the GTP transceivers is connected to the PCI Express card edge interface. PCI Express is an enhancement to the PCI
architecture where the parallel bus has been replaced with a scalable, fully serial interface. The differences in the electrical
interface are transparent to the software so existing PCI software implementations are compatible. Use of the Spartan-6
LX75T development board in a PCI Express application requires the implementation of the PCI Express protocol in the FPGA.
The PCI Express Endpoint Block embedded in the Spartan-6 FPGA implements the PCI Express protocol and the physical
layer interface to the GTP ports. This block must be instantiated in the user design. For more information, see the Spartan-6
FPGA Integrated Endpoint Block for PCI Express User Guide on the Xilinx web site.
Refer to UG654 documentation on the Xilinx website for more details.
The PCI Express electrical interface on the Spartan-6 LX75T development board consists of 1 lane, having a unidirectional
transmit and receive differential pair. It supports first generation data rate of 2.5 Gbps. In addition to the data lane there is a
100MHz reference clock that is provided from the system slot. In order to work in open systems, add-in cards must use the
reference clock provided over the PCI Express card edge to be frequency locked with the host system.
There is also a side band signal from the PCI Express card edge that connects to a regular I/O pin on the Spartan-6 FPGA.
The PERST# signal is an active low reset signal provided by the host PCI Express slot. The following figure shows the PCI
Express interface to the Spartan-6 FPGA.
Spartan-6
LX75T
FPGA
MGT_DUAL
X0Y1
MGT101
PCI EXPRES
EDGE
CONNECTOR
PETp0
PETn0
PERp0
PERn0
FPGA I/0
CREFCLKp
CREFCLKn
CPERST#

Figure 5 - PCI Express x1 Interface
Since this interface is only one lane wide, the PRSNT1# and PRSNT2# signals for Lane 0 are hard wired together in hardware.
The PRSNT2# on the host connector is pulled-up on the host motherboard. There is a single PRSNT1# pin that is pulled-low
or tied to GND on the host motherboard. The add-in card connects the PRSNT1# pin to the PRSNT2# pin for the widest lane
option in most applications, which effectively pulls the corresponding PRSNT2# pin low. This indicates to the host controller the
lane width supported by the add-in card. In this application, the widest lane option is lane 0, and the corresponding PRSNT2#
signal is use to connect to PRSNT1#.
The PCI Express transmit lanes are AC coupled (DC blocking capacitors are included in the signal path) on the development
board as required by the PCI Express specification.

GTP Instance Net Name
Connector
Pin #
Spartan-6
Pin #

GTP_Dual_X0Y1

PCIe_RX0P P1.B14 D7
PCIe_RX0N P1.B15 C7
PCIe_TX0P P1.A16 B6
PCIe_TX0N P1.A17 A6
Table 5 - GTP Pin Locations for PCI Express


2.2.2.1 PCIe Configuration Timing
The Spartan-6 LX75T PCI Express Development Board meets the 200ms configuration time requirement for ATX based PC
systems when configuring from the on boards SPI flash. It is recommended that the FPGAs USRCLK input be used instead of
the default FPGA_CCLK for configuration. Additionally, the SPI flash is a multi-bit device which supports SPI x4 data transfers.

To take advantage of the SPI flash x4 capability during configuration the following option in BitGen must be set:

-g spi_buswidth:4

Please note that the bit file generated from setting this option will not configure the FPGA when configuring over JTAG. The
rendered bit file needs to be converted to an MCS file and used to program the SPI flash. Also please note that the x4 option
is not active during flash programming using the release of iMPACT 12.4. Only during configuration of the FPGA will the SPI
flash operate in x4 mode, decreasing the configuration time dramatically.

The Spartan-6 USRCLK input is sourced by the 40MHz clock oscillator U5 and is pin AC14 on the FPGA.

A Bitgen option must be set for this input to be used. Use the following Bitgen switch to enable this USRCLK input to be the
configuration clock:

- g ExtMasterCclk_en:yes

2.2.3 GTP on FMC Expansion Connector JX1
One GTP transceiver is brought out to the board-to-board connector labeled JX1 on the board for use by FMC daughter
cards. The MGT245 transceiver is directly connected to JX1 pins C6 and C7 (RX+ and RX-) and pins C2 and C3 (TX+ and
TX-). The user must evaluate whether AC coupling is required on the daughter card to safely interface with the Spartan-6 GTP
transceiver. The MGT245 tile is GTP_Dual X0Y0 on the LX75T device.

GTP Instance Net Name
Connector
pin#
Spartan-6
pin#

GTP_Dual_X0Y0

FMC1_C_DP0_C2M_p JX1.C2 AE7
FMC1_C_DP0_C2M_n JX1.C3 AF7
FMC1_C_DP0_M2C_p JX1.C6 AC8
FMC1_C_DP0_M2C_n JX1.C7 AD8
Table 6 - GTP Pin Assignments for FMC Connectors

2.3 Memory
The Spartan-6 LX75T development board is populated with both high-speed RAM and non-volatile ROM to support various
types of applications. Each development board has three memory interfaces:
1) DDR3 BANK 1: 128 MB x16 DDR3 SDRAM (MCB4)
2) DDR3 BANK 2: 128 MB x16 DDR3 SDRAM (MCB5)
3) 32 MB non-volatile flash

2.3.1 DDR3 SDRAM Interface
Two Micron DDR3 SDRAM devices, part number MT41J64M16JT-15E:G, make up the two DDR3 memory banks. Each bank
implements a 16-bit data bus. Each device provides 128 MB of memory on a single IC and is organized as 8 Megabits x 16 x 8
banks (1 Gb). The Spartan-6 LX75T development board can support larger devices with addressing support for up to 128 MB
(two 512-Megabit devices). The device has an operating voltage of 1.5 V and the interface is JEDEC Standard SSTL_15
(Class I for unidirectional signals, Class II for bidirectional signals). The -15E speed grade supports 1.5 ns cycle times with a 9
clock read latency (DDR3-1333). The following figures show a high-level block diagram of the DDR3 SDRAM interface on the
development board.


Spartan-6
LX75T
MCB4
64M x 16
DDR3
Data[15:0]
BA[1:0]
Addr[12:0]
UDQM
LDQM
UDQS
UDQS_n
LDQS
LDQS_n
CS_n
RAS_n
CAS_n
WE_n
CLKE
CLK
CLK_n
ODT
RESET_n

Figure 6 - DDR3 SDRAM Interface MCB4


Spartan-6
LX75T
MCB5
64M x 16
DDR3
Data[15:0]
BA[1:0]
Addr[12:0]
UDQM
LDQM
UDQS
UDQS_n
LDQS
LDQS_n
CS_n
RAS_n
CAS_n
WE_n
CLKE
CLK
CLK_n
ODT
RESET_n

Figure 7- DDR3 SDRAM Interface MCB5

The DDR3 signals are connected to I/O Banks 4 and 5 of the Spartan-6 LXT FPGA. Each memory device is dedicated to its
own bank on the FPGA and is controlled by each banks memory controller independently of the other bank. The supply pins
(VCCO) for the DDR3 banks (Bank 4 and Bank 5) are connected to 1.5 Volts. This supply rail can be measured at the test
point labeled 1.5 V. The reference voltage pins (VREF) for the DDR3 banks is connected to the reference output of the
National Semiconductor LP2998 1.5 amp LDO. This device provides the supply voltage and reference voltage necessary for
the SSTL_15 I/O standard. The termination voltage is 0.75 Volts and can be measured at the test point labeled
DDR_TERM_0.75V. The LP2998 also supplies the DDR3 termination voltage of 0.75 V and can be measured at the test point
labeled DDR_TERM_0.75V.

The following guidelines were used in the design of the DDR3 interface to the Spartan-6 LXT FPGA. These guidelines are
based on Micron recommendations and board level simulation.
50 ohm* controlled trace impedance
Dedicated data bus with matched trace lengths (+/- 50 mils)
Memory clocks and data strobes routed differentially
Parallel termination following the memory device connection on shared signals (control, address)
50 ohm* pull-up resistor to the termination supply (0.75V) on clock signals
Termination supply that can both source and sink current
* Ideal impedance values. Actual may vary.
All DDR3 signals are compliant to the Xilinx recommended and MIG generated pin out.

The following tables contain the FPGA pin numbers used for the DDR3 SDRAM interfaces.

NET NAME SPARTAN-6 PIN

DDR3_A0
L7
DDR3_D0 H3
DDR3_A1
L6
DDR3_D1 H1
DDR3_A2
K10
DDR3_D2 G2
DDR3_A3
M8
DDR3_D3 G1
DDR3_A4
J7
DDR3_D4 D3
DDR3_A5
L4
DDR3_D5 D1
DDR3_A6
L3
DDR3_D6 E2
DDR3_A7
L10
DDR3_D7 E1
DDR3_A8
C2
DDR3_D8 J2
DDR3_A9
C1
DDR3_D9 J1
DDR3_A10
J9
DDR3_D10 K3
DDR3_A11
E3
DDR3_D11 K1
DDR3_A12
K8
DDR3_D12 M3

DDR3_D13 M1
DDR3_BA0
B2
DDR3_D14 N2
DDR3_BA1
B1
DDR3_D15 N1
DDR3_BA2
G3

DDR3_UDM0 J4

DDR3_LDM0 J3
DDR3_ODT
M6

DDR3_RST# E4
DDR3_WE#
G4
DDR3_RAS#
L9
DDR3_UDQS0
L2
DDR3_CAS#
L8
DDR3_UDQS0#
L1
DDR3_CKE
K9
DDR3_LDQS0
F3
DDR3_CLK0
K5
DDR3_LDQS0#
F1
DDR3_CLK0#
J5
Table 7 - FPGA Pin Locations for MCB4 DDR3 SDRAM



DDR3_A0
C25
DDR3_D0 G25
DDR3_A1
C26
DDR3_D1 G26
DDR3_A2
E24
DDR3_D2 H24
DDR3_A3
K21
DDR3_D3 H26
DDR3_A4
G23
DDR3_D4 E25
DDR3_A5
M18
DDR3_D5 E26
DDR3_A6
M19
DDR3_D6 D24
DDR3_A7
E23
DDR3_D7 D26
DDR3_A8
H21
DDR3_D8 K24
DDR3_A9
H22
DDR3_D9 K26
DDR3_A10
F22
DDR3_D10 J25
DDR3_A11
K19
DDR3_D11 J26
DDR3_A12
C24
DDR3_D12 L25

DDR3_D13 L26
DDR3_BA0
L19
DDR3_D14 N25
DDR3_BA1
K20
DDR3_D15 N26
DDR3_BA2
J22

DDR3_UDM0 J23

DDR3_LDM0 J24
DDR3_ODT
K22

DDR3_RST# K18
DDR3_WE#
J20
DDR3_RAS#
F23
DDR3_UDQS0
M24
DDR3_CAS#
G24
DDR3_UDQS0#
M26
DDR3_CKE
D23
DDR3_LDQS0
F24
DDR3_CLK0
B25
DDR3_LDQS0#
F26
DDR3_CLK0#
B26
Table 8 - FPGA Pin Locations for MCB5 DDR3 SDRAM


2.3.2 Numonyx Flash Interface
The Flash memory consists of a single 32 MB Numonyx (currently Micron) device in a 64 ball BGA package, part number
PC28F256M29EWH. The PC28F device is an asynchronous memory that also supports a synchronous-burst read mode for
high-performance applications. The PC28F device has a 100 nanosecond access time. The PC28F flash connects to pins in
Bank 3 of the Spartan-6 FPGA. The Flash I/O voltage (VIO) is set to 3.3 V to match the VCCO voltage of Bank 3. The
following figure shows a high-level block diagram of the PC28F flash interface on the development board.
Flash
Addr [24:0]
Data [15:0]
RST#
BYTE#
CE#
OE#
WE#
WP#
GND
1
VCC
A[24:0]

D[15:0]
Spartan-6
3.3V
VCCQ
3.3V 3.3V
JP1

Figure 8 - Flash Interface

The following table contains the FPGA pin numbers for the Flash interface.
Net Name Spartan-6 Pin # Net Name Spartan-6 Pin #
FLASH_A0 AB3 FLASH_D0 AB1
FLASH_A1 AE1 FLASH_D1 Y1
FLASH_A2 AA4 FLASH_D2 Y3
FLASH_A3 W5 FLASH_D3 W3
FLASH_A4 AB4 FLASH_D4 R2
FLASH_A5 AD3 FLASH_D5 T1
FLASH_A6 AE2 FLASH_D6 R3
FLASH_A7 AB5 FLASH_D7 R1
FLASH_A8 V7 FLASH_D8 AA2
FLASH_A9 U7 FLASH_D9 Y5
FLASH_A10 U3 FLASH_D10 U4
FLASH_A11 T6 FLASH_D11 V5
FLASH_A12 U8 FLASH_D12 R4
FLASH_A13 U9 FLASH_D13 R6
FLASH_A14 M9 FLASH_D14 M10
FLASH_A15 N7 FLASH_D15 P10
FLASH_A16 N4
FLASH_A17 AC4 FLASH_CE# AA3
FLASH_A18 AD1 FLASH_WE# V6
FLASH_A19 AC1 FLASH_OE# AA1
FLASH_A20 AC3 FLASH_RST# Y6
FLASH_A21 AC2 FLASH_BYTE# N9
FLASH_A22 R9
FLASH_A23 P8
FLASH_A24 N5
Table 9 - Flash Interface Pin Locations


2.3.3 SPI Flash Interface
The Spartan-6 LX75T development board utilizes on-board Numonyx multi-bit (x4) SPI flash device, part number
N25Q128A13BSE40F, to configure the FPGA quickly using the Master Serial / SPI configuration mode. When configuring the
FPGA, the flash clock is sourced by the FPGA CCLK pin. To speed up configuration times for PCI Express applications a 40
MHz User Clock is connected to the USERCLK input in Bank 2. If the USERCCLK is not used to configure the Spartan-6
FPGA for PCI Express applications the board might not be recognized on the bus at the time the host PC powers up and
enumerates the PCI Express bus.

A Bitgen option must be set for this input to be used. Use the following Bitgen switch to enable this USRCLK input to be the
configuration clock:

- g ExtMasterCclk_en:yes

This device also has the ability to configure the FPGA using multi-bit mode. The device supports a four bit parallel interface to
the FPGA.

To take advantage of the SPI flash x4 capability during configuration the following option in BitGen must be set:

-g spi_buswidth:4

Please note that the bit file generated from setting this option will not configure the FPGA when configuring over JTAG. The
rendered bit file needs to be converted to an MCS file and used to program the SPI flash. Also please note that the x4 option
is not active during flash programming using the release of iMPACT 12.4. Only during configuration of the FPGA will the SPI
flash operate in x4 mode, decreasing the configuration time dramatically.

The Spartan-6 USRCLK input is sourced by the 40MHz clock oscillator U5 and is pin AC14 on the FPGA.

The figure below shows the interface between the SPI flash and the Spartan-6 FPGA.

Spartan-6
LX75T SPI
Flash
(x4)
CCLK
DQ0
DQ1
DQ2
DQ3
CS#
Jumper
Header
JP3
M0
M1

Figure 9 - Spartan-6 LX75T FPGA Development Board SPI Flash Interface

To configure the FPGA using the SPI flash the configuration mode for the FPGA must be set to Master Serial/SPI mode. This
is accomplished by placing a jumper across pins 1-3 on JP3. This pulls the M0 mode pin input on the Spartan-6 FPGA to a
logic level 1 and leaves the M1 mode input pin tied to a logic 0 (M[1:0] = 01). This is the default jumper setting from the
factory.
2.4 Clock Sources
The Spartan-6 LX75T development board includes all of the necessary clocks on the board to implement high-speed logic and
RocketIO transceiver designs. The clock sources described in this section are used to derive the required clocks for the
memory and communications devices, and the general system clocks for the logic design. For a description of the GTP
reference clock sources, see Section 2.2.1.
The following figure shows the clock nets connected to the I/O banks containing the global clock i nput pins on the Spartan-6
LX75T FPGA. Ten out of the sixteen global clock inputs of the Spartan-6 FPGA are utilized on the board.


Spartan-6 FG676
Bank 0
MII Clocks
Expansion Clocks
F
M
C
1
-
C
L
K
0
-
M
2
C
_
P
F
M
C
1
-
C
L
K
0
-
M
2
C
_
N
Expansion Clocks
E
T
H
_
R
X
_
C
L
K
E
T
H
_
T
X
_
C
L
K
F
P
G
A
-
U
S
E
R
C
C
L
K
Bank 1
Bank 2 Bank 3
F
M
C
1
-
C
L
K
1
-
M
2
C
_
P
F
M
C
1
-
C
L
K
1
-
M
2
C
_
N
F
M
C
1
-
L
A
0
1
-
C
C
_
P
F
M
C
1
-
L
A
0
1
-
C
C
_
N
F
M
C
1
-
L
A
0
0
-
C
C
_
P
F
M
C
1
-
L
A
0
0
-
C
C
_
N
LVTTL OSC
Socket
F
M
C
1
-
L
A
1
7
-
C
C
_
P
F
M
C
1
-
L
A
1
7
-
C
C
_
N
F
M
C
1
-
L
A
1
8
-
C
C
_
P
F
M
C
1
-
L
A
1
8
-
C
C
_
N
LVTTL OSC
@100MHz
LVTTL OSC
@40MHz

Figure 10 - Clock Nets Connected to Global Clock Inputs


The on-board 100 MHz oscillator provides the system clock input to the global clock tree. This single-ended, 100 MHz clock
can be used in conjunction with the Spartan-6 Clock Management Tiles (CMTs) to generate the various logic clocks and the
clocks forwarded to the DDR3 SDRAM devices. The interface clocks supplied by the communications devices are derived
from dedicated crystal oscillators.
Additionally, there is an on-board TI CDCM610021LVDS clock synthesizer that is connected to GTP_Dual tile X0Y0 to give
the user the ability to source that and adjacent tiles with a wide range of frequencies. The CDCM61001 clock synthesizer is
explained in detail in Section 2.4.1.

Reference# Frequency Derived Interface Clock
Derived
Frequency
Spartan-6 pin#
U6 100 MHz CLK_100MHZ 100 MHz T3
U5 40 MHz FPGA_USRCLK 40 MHz AC14
U16 User Defined CLK_SOCKET User Defined U23
U17 25 MHz
CLK_SYN0_P 21.25 1360
MHz
AC12 (GTP X0Y0)
CLK_SYN0_N AD12 (GTP X0Y0)
Y1 25 MHz
ETH_RX_CLK 2.5, 25 MHz R7
ETH_TX_CLK 2.5, 25 MHz V4
Table 10 - On-Board Clock Sources

In addition to the 100 MHz and 40 MHz oscillators, an 8-pin DIP clock socket is provided on the board so the user can supply
their own oscillator of choice. The socket is a single-ended, LVTTL or LVCMOS compatible clock input to the FPGA that can
be used as an alternate source for the system clock.

Signal Name Socket pin#
Enable 1
GND 4
Output 5
VDD 8
Table 11 - Clock Socket "U5" Pin-out

2.4.1 CDCM61001 Programmable LVDS Clock Synthesizer
The Spartan-6 LX150T PCI Express Development Board design uses the TI CDCM61002 LVDS frequency synthesizer for
generating various clock frequencies. A list of features included in the CDCM61002 device is shown below.

Output frequency range: 43.75 MHz to 683.264 MHz
RMS period jitter: 0.509 ps @ 625 MHz
Output rise and fall time: 255 ps (maximum)
Output duty cycle: varies dependant on output frequency

The following figure shows a high-level block diagram of the CDCM61001 programmable clock synthesizer. Inputs OS0 and
OS1 are hard wired to use the LVDS mode of the CDCM61001 device.


CDCM61001
U3
PR[1:0]
OD[2:0]
PR
OD
OS0
OS1
3.3V
OUT0_P
OUT0_N
CLK_SYN0_P
CLK_SYN0_N
SW8
SW9
CE
RST_N
U17
XIN
25MHz
SPARTAN-6
GTP_DUAL
X0Y0
GTP_245_1

Figure 11 - CDCM61001 Clock Synthesizer

Signal Name Direction Pull up/Pull down Description
PR[1:0] Input Pull up Prescaler and Feedback divider control pins.
OD[2:0] Input Pull up Output divider control pins.
OS[1:0] Input Pull up Output type select control pins.
CE Input Pull up Chip enable.
RST_N Input Pull up Device reset (active low).
XIN Input Pull up Parallel resonant crystal/LVCMOS input.
OUT0 P/N Input Differential output pair.
Table 12 - CDCM61001 Clock Synthesizer Pin Description

2.4.1.1 CDCM61001 Clock Generation

The CDCM61001 output clocks are generated based on the following formula (assuming the crystal clock input is 25 MHz):
FOUT = (FIN) (FD) / OD
Equation Variables:
FOUT = Output Frequency
FIN = Clock Input Frequency
FD = Feedback Divider Value
OD = Output Divider Value

Please refer to the CDCM61001 datasheet for detailed tables regarding the Feedback Divider and Output Divider values. The
CDCM61001 FD and OD values are programmed via dipswitches SW8 and SW9. These dipswitches should be configured
prior to powering up the board.

The following table shows how to set the dipswitches for a common application. All the values are based on a 25 MHz crystal
clock input to the CDCM61001 device.

Interconnect
Technology
OUT0
and
OUT1
(MHz)
PR1 PR0 OD2 OD1 OD0
SATA 150 0 0 0 1 1
GigE 125 1 1 0 1 1
10 GigE 156.25 1 0 0 1 1
12 GigE 187.5 0 1 0 0 1
Table 13 - CDCM61001 Common Application Settings

2.4.1.2 CDCM61001 Programming Mode
The Spartan-6 LX75T PCI Express Development Board allows programming of the PR and OD values in parallel mode. This
is the only mode allowed by the device. In parallel mode, PR and OD values are programmed into the device upon the release
of the master reset signal (rising edge of the MR_N signal). The switches should be set into the correct position prior to turning
on power to the board. Should the switch settings change after power up the board will have to be power cycled to reset the
device.
2.5 Communication
The Spartan-6 LXT FPGA has access to Ethernet and RS232 physical layer transceivers for communication purposes.
Network access is provided by a single 10/100 Mb/s Ethernet PHY device, which is connected to the Spartan-6 via a standard
MII interface. The PHY device connects to the outside world with a standard RJ45 connector. The connector is located on the
PCI faceplate.

Serial port communication to the embedded MicroBlaze processor or FPGA fabric is provided through a Cypress USB-RS232
transceiver.

2.5.1 10/100 Ethernet PHY
The PHY device is a National DP83848J PHYTER . The PHY is connected to a Tyco RJ-45 jack with integrated magnetics
(part number: 5-1840406-8). The jack also integrates two LEDs that indicate a valid link and the link speed. The PHY clock is
generated from a 25 MHz crystal. The following figure shows a high-level block diagram of the interface to the DP83848J
Ethernet PHY.

data_tx[3:0]
clk_tx
control_tx
data_rx[3:0]
clk_rx
control_rx
25MHz
Crystal
phy_reset
T
r
a
n
s
m
i
t
R
e
c
e
i
v
e
1
0
/
1
0
0
M
a
g
n
e
t
i
c
s
R
J
4
5
C
o
n
n
e
c
t
o
r
National DP83848J 10/100
PHY Spartan-6 FPGA
TD+
TD-
RD+
RD-

Figure 12 - 10/100 Mb/s Ethernet Interface


The PHY device has the address 0b00001 by default. PHY address 0b00000 puts the device into MII Isolate Mode. The
default mode(s) that the DP83848J operates on the Spartan-6 LX75T Development Board is as follows:
MII Mode
Auto MDIX Enabled

The following tables provide the Spartan-6pin assignments for the Ethernet PHY interfaces.

Net Name Spartan-6 pin # Net Name Spartan-6 pin #
FPGA_ETH_MDC R10
FPGA_ETH _MDIO P1 FPGA_ETH _RST# P6
FPGA_ETH _TX_EN U1 FPGA_ETH _CRS T8
FPGA_ETH _COL W1
GMII_ FP_TX_CLK V4

FPGA_ETH _TX_D0 U2 FPGA_ETH _RX_D0 R5
FPGA_ETH _TX_D1 P3 FPGA_ETH _RX_D1 T4
FPGA_ETH _TX_D2 V1 FPGA_ETH _RX_D2 U5
FPGA_ETH _TX_D3 W2 FPGA_ETH _RX_D3 V3

GMII_ FP_RX_DV R8 GMII_ FP_RX_CLK R7
GMII_ FP_RX_ER Y9

Table 14 - Ethernet PHY U7 Pin Locations

2.5.2 USB-RS232
The Spartan-6 LX75T PCI Express Development Board Implements a Cypress CP2102 device that provides a USB-to-RS232
bridge. The USB physical interface is brought out on a USB Micro-AB connector labeled J3.

The USB-to-RS232 bridge interface connects to the Spartan-6 FPGA through the following pins:

Net Name Spartan-6 Pin #
USB_RS232_RXD N19
USB_RS232_TXD N20
Table 15 - USB-to-RS232 Pin Locations

2.6 User Switches
Four momentary closure push buttons have been installed on the board and connected to the FPGA. These buttons can be
programmed by the user and are ideal for logic reset and similar functions. Pull down resistors hold the signals low until the
switch closure pulls them high (active high signals).

Net Name Reference
Spartan-6
Pin #
SWITCH_PB1 SW2 AA23
SWITCH_PB2 SW3 T22
SWITCH_PB3 SW4 AD24
SWITCH_PB4 SW5 P26
Table 16 - Push Button Pin Locations

A FOUR-position dipswitch (SPST) has been installed on the board and connected to the FPGA. These switches provide
digital inputs to user logic as needed. The signals are pulled low by 4.75K ohm resistors when the switch is open and tied high
to 3.3 V when closed as shown in the following table.


Net Name Reference
Voltage when
closed
Spartan-6
Pin #
SWITCH0 SW7 1
3.3V
T20
SWITCH1 SW7 2 U20
SWITCH2 SW7 3 R21
SWITCH3 SW7 4 V20
Table 17 - DIP Switch Pin Locations
2.7 User LEDs
Four discrete LEDs are installed on the board and can be used to display the status of the internal logic. These LEDs are
connected as shown below and are lit by forcing the associated FPGA I/O pin to a logic 1 and are off when the pin is either
low (0) or not driven.

Net Name Reference
Spartan-6
Pin #
LED0 D5 P24
LED1 D4 T19
LED2 D3 AB26
LED3 D2 AC26
Table 18 - LED Pin Locations
2.8 Configuration
The Spartan-6 LX75T development board supports several methods of configuring the FPGA. The possible configuration
sources include Boundary-scan (JTAG cable), and Master Serial/SPI from the configuration PROMs. The blue LED labeled
DONE on the board illuminates to indicate when the FPGA has been successfully configured.

2.8.1 Configuration Modes
Upon power-up the FPGA will be enabled in a configuration mode defined by the jumpers on JP3. The default configuration
mode is JTAG mode when no jumpers are installed. JTAG device configuration can occur at any time regardless of the mode
jumpers configuration. Placing a jumper across pins 1-3 place the FPGA in Master Serial/SPI mode and will allow the FPGA to
configure from the SPI flash if the flash is programmed with a Xilinx MCS image. The following table shows the two
configuration modes that are supported:

Config Mode M1 M0
JTAG x x
Master Serial/SPI 0 1
Table 19 - Setting the Configuration Mode JP3

2.8.2 JTAG Chain
The Spartan-6 LX75T development board has three devices/connectors in the JTAG chain: the Spartan-6 LX75T FPGA, SPI
flash, and the FMC connector. The following figure shows a high-level block diagram of the JTAG Chain on the development
board.

J1
JP2

Figure 13 - JTAG Chain on the Spartan-6 PCI Express Board


Configuring the JTAG chain to exclude or include the FMC connector can be done using a jumper on JP2 to connect the
TDO/TDI paths as desired as shown in the diagram above.

Programming the Spartan-6 FPGA via Boundary-scan mode requires a JTAG download cable. The Spartan-6 LX75T
development board has a single connector to support the ribbon cable connection of the Parallel Cable IV and Platform Cable
USB. The connector is labeled J1. For more information about JTAG download cables, perform a search on the Xilinx web
page http://www.xilinx.com using the key words Programming Cables.
2.9 Expansion Connectors
The Spartan-6 LX75T development board provides expansion capabilities for customized user application daughter cards and
interfaces over one low pin count (LPC) FPGA Mezzanine Card (FMC) expansion connector. For more details regarding FMC
please view the FPGA Mezzanine Card specification at http://www.vita.com/fmc.html.

2.9.1 FMC Low Pin Count (LPC) Interface

The FMC specification defines the LPC interface to be a 160-pin connector arranged in a 4x40 array. The LPC connector is
populates 160 of the 400 possible positions. The HPC (High Pin Count) version of the connector has all positions populated.

The FMC LPC configuration implemented on the Spartan-6 LX75T development board uses one LPC connector (SAMTEC
part number ASP-134603-01), for a total of 136 user I/Os. The connector is referenced as JX1 on the board.

The FMC specification defines five user signal types: Differential I/O, Differential Clock Inputs, Differential Clock Outputs, MGT
I/O, and MGT Clock Inputs. Because the FPGA I/Os can be configured for either single-ended or differential use, the
differential I/Os defined in the FMC specification can serve a dual role. All the differential I/O signals can be configured as
either differential pairs or single-ended signals, as required by the end application. In providing differential signaling, higher
performance LVDS interfaces can be implemented between Spartan-6 LX75T development board and an FMC LPC module.
Connection to high speed A/Ds, D/As, and flat panel displays are possible with this signaling configuration. Applications that
require single-ended signals only can use each differential pair as two single-ended signals, for a total of 68 single-ended I/O
per LPC connector.

Net Names Signal Description
Pins per
Connector
FMC_LA**_P/N 34 Differential I/O Pairs 68
Total User I/O 68

FMC_CLK0_C2M_P/N
1 Differential Clock Pair (Carrier to
Mezzanine)
2
FMC_CLK0_M2C_P/N
1 Differential Clock Pair (Mezzanine to
Carrier)
2
Total Clock I/O 4

FMC_DP0_M2C_P/N 1 MGT Receive Differential Data Pair 2
FMC_DP0_C2M_P/N 1 MGT Transmit Differential Data Pair 2
FMC_GBTCLK0_M2C_P/N 1 MGT Differential Clock Pair 2
Total MGT I/O 6
Table 20 - FMC LPC Connector Signals



Figure 14 - FMC LPC Connector Pinout

Note: For the FMC LPC, the connector columns K, J, F, E, B, and A are not used and not shown in the above table.

The SAMTEC connector plug on the board (CC-LPC-10 part number: ASP-134603-01) mates with the SAMTEC low pin count
receptacle (MC-LPC-10 part number: ASP-134604-01), located on FMC modules.

FMC JX1 is connected to Bank 0 and Bank 2 of the S6LX75T FPGA.

Since the FMC connector is connected to the I2C bus a geographical address must be given to the connector. The GA[1:0]
inputs provide a means to give the connector an I2C address. For JX1 the address is hard wired to 0x00 by tying these inputs
low through pull-down resistors.

The following diagram and table shows how FMC LPC connector JX1 is connected to the Spartan-6 LX75T FPGA.

LA[2:16]_<P|N>, LA[19:26]_<P|N>
VADJ
VREF_A_M2C
FMC LPC Connector
Spartan-6 FPGA
B
a
n
k

0
F
P
G
A

I
O
V
C
C
I
O
VADJ
(2.5V)
GBTCLK0_M2C_<P|N>
M
G
T

R
e
f

C
l
o
c
k

I
n
p
u
t
DP0_M2C_<P|N>
DP0_C2M_<P|N>
RX
TX M
G
T
s
GA[0:1]
SCL
SDA
TDI
F
P
G
A

J
T
A
G
TMS
TCK
TRST_L
TDO
3P3V AUX
3P3V
12P0V
PRSNT_L
PG_C2M
B
a
n
k

3
PD Straps
F
P
G
A

G
l
o
b
a
l

C
l
o
c
k

I
n
p
u
t
s
LA[27:33]_<P|N>
VADJ
VREF_A_M2C
B
a
n
k

2
F
P
G
A

I
O
V
C
C
I
O
VADJ
(2.5V)
F
P
G
A

G
l
o
b
a
l

C
l
o
c
k

I
n
p
u
t
s
LA17_<P|N>_CC
LA18_<P|N>_CC
CLK0_M2C_<P|N>
LA00_<P|N>_CC
LA01_<P|N>_CC
CLK1_M2C_<P|N>
NC
NC

Figure 15 - FMC LPC Connector JX1 Block Diagram


Spartan-6
Pin
Location
Schematic
Net Name
FMC Connector
Pin Location
(JX1)
FMC Connector
Symbol
Name
- GND C1 GND
AE7 FMC1_DP0_C2M_P C2 DP0_C2M_P
AF7 FMC1_DP0_C2M_N C3 DP0_C2M_N
- GND C4 GND
- GND C5 GND
AC8 FMC1_DP0_M2C_P C6 DP0_M2C_P
AD8 FMC1_DP0_M2C_N C7 DP0_M2C_N
- GND C8 GND
- GND C9 GND
C21 FMC1_LA06_P C10 LA06_P
B21 FMC1_LA06_N C11 LA06_N
- GND C12 GND
- GND C13 GND
H18 FMC1_LA10_P C14 LA10_P
H19 FMC1_LA10_N C15 LA10_N
- GND C16 GND
- GND C17 GND
H9 FMC1_LA14_P C18 LA14_P
G9 FMC1_LA14_N C19 LA14_N
- GND C20 GND
- GND C21 GND
FMC1_LA18_CC_P C22 LA18_P_CC
FMC1_LA18_CC_N C23 LA18_N_CC
- GND C24 GND
- GND C25 GND
AA21 FMC1_LA27_P C26 LA27_P
AB21 FMC1_LA27_N C27 LA27_N
- GND C28 GND
- GND C29 GND
N18 SCL_0 C30 SCL
N17 SDA_0 C31 SDA
- GND C32 GND
- GND C33 GND
- PULL-DOWN C34 GA0
- +12.0V C35 12P0V
- - C36 GND
- +12.0V C37 12P0V
- - C38 GND
- FMC_3.3V C39 3P3V
- - C40 GND
- FMC1_VIO (PULL-UP) D1 PG_C2M
- GND D2 GND
- GND D3 GND
AE11 FMC1_GBTCLK0_M2C_P D4 GBTCLK0_M2C_P
AF11 FMC1_GBTCLK0_M2C_N D5 GBTCLK0_M2C_N
- GND D6 GND
- GND D7 GND
B14 FMC1_LA01_CC_P D8 LA01_P_CC
A14 FMC1_LA01_CC_N D9 LA01_N_CC
- GND D10 GND
D21 FMC1_LA05_P D11 LA05_P
D22 FMC1_LA05_N D12 LA05_N
- GND D13 GND
H17 FMC1_LA09_P D14 LA09_P
G17 FMC1_LA09_N D15 LA09_N
- GND D16 GND
K12 FMC1_LA13_P D17 LA13_P
J12 FMC1_LA13_N D18 LA13_N
- GND D19 GND
AE13 FMC1_LA17_CC_P D20 LA17_P_CC
AF13 FMC1_LA17_CC_N D21 LA17_N_CC
- GND D22 GND
B5 FMC1_LA23_P D23 LA23_P
A5 FMC1_LA23_N D24 LA23_N
- GND D25 GND
B4 FMC1_LA26_P D26 LA26_P
A4 FMC1_LA26_N D27 LA26_N
- GND D28 GND
A24 JTAG_TCK D29 TCK
G21
(Jumper JP2)
FPGA_TDO D30 TDI
- FMC1_TDO D31 TDO
- FMC_3.3V D32 3P3VAUX

F21 JTAG_TMS D33 TMS
N6 FMC_TRST_L D34 TRST_L
- PULLD-DOWN D35 GA1
- FMC_3.3V D36 3P3V
- GND D37 GND
- FMC_3.3V D38 3P3V
- GND D39 GND
- FMC_3.3V D40 3P3V
- GND G1 GND
E13 FMC1_CLK1_M2C_P G2 CLK1_M2C_P
D13 FMC1_CLK1_M2C_N G3 CLK1_M2C_N
- GND G4 GND
- GND G5 GND
B12 FMC1_LA00_CC_P G6 LA00_P_CC
A12 FMC1_LA00_CC_N G7 LA00_N_CC
- GND G8 GND
B23 FMC1_LA03_P G9 LA03_P
A23 FMC1_LA03_N G10 LA03_N
- GND G11 GND
F20 FMC1_LA08_P G12 LA08_P
E20 FMC1_LA08_N G13 LA08_N
- GND G14 GND
J16 FMC1_LA12_P G15 LA12_P
J17 FMC1_LA12_N G16 LA12_N
- GND G17 GND
J11 FMC1_LA16_P G18 LA16_P
G11 FMC1_LA16_N G19 LA16_N
- GND G20 GND
H8 FMC1_LA20_P G21 LA20_P
G8 FMC1_LA20_N G22 LA20_N
- GND G23 GND
G6 FMC1_LA22_P G24 LA22_P
F5 FMC1_LA22_N G25 LA22_N
- GND G26 GND
G16 FMC1_LA25_P G27 LA25_P
F17 FMC1_LA25_N G28 LA25_N
- GND G29 GND
AD4 FMC1_LA29_P G30 LA29_P
AF4 FMC1_LA29_N G31 LA29_N
- GND G32 GND
AA7 FMC1_LA31_P G33 LA31_P
AA6 FMC1_LA31_N G34 LA31_N
- GND G35 GND
Y12 FMC1_LA33_P G36 LA33_P
AA12 FMC1_LA33_N G37 LA33_N
- GND G38 GND
- FMC1_VIO G39 VADJ_2.5V
- GND G40 GND
- FMC1_VREF_A_M2C H1 VREF_A_M2C
P5 FMC1_PRSNT_M2C_L H2 PRSNT_M2C_L
- GND H3 GND
C13 FMC1_CLK0_M2C_P H4 CLK0_M2C_P
A13 FMC1_CLK0_M2C_N H5 CLK0_M2C_N
- GND H6 GND
C3 FMC1_LA02_P H7 LA02_P
B3 FMC1_LA02_N H8 LA02_N
- GND H9 GND
B22 FMC1_LA04_P H10 LA04_P
A22 FMC1_LA04_N H11 LA04_N
- GND H12 GND
G19 FMC1_LA07_P H13 LA07_P
F19 FMC1_LA07_N H14 LA07_N
- GND H15 GND
J15 FMC1_LA11_P H16 LA11_P
H15 FMC1_LA11_N H17 LA11_N
- GND H18 GND
H12 FMC1_LA15_P H19 LA15_P
G13 FMC1_LA15_N H20 LA15_N
- GND H21 GND
F7 FMC1_LA19_P H22 LA19_P
F6 FMC1_LA19_N H23 LA19_N
- GND H24 GND
E6 FMC1_LA21_P H25 LA21_P
E5 FMC1_LA21_N H26 LA21_N
- GND H27 GND
A3 FMC1_LA24_P H28 LA24_P

A2 FMC1_LA24_N H29 LA24_N
- GND H30 GND
AD6 FMC1_LA28_P H31 LA28_P
AF6 FMC1_LA28_N H32 LA28_N
- GND H33 GND
W8 FMC1_LA30_P H34 LA30_P
W7 FMC1_LA30_N H35 LA30_N
- GND H36 GND
W14 FMC1_LA32_P H37 LA32_P
Y13 FMC1_LA32_N H38 LA32_N
- GND H39 GND
- FMC1_VIO H40 VADJ_2.5V
Table 21 - FMC LPC Connector JX1 Pin Locations

2.9.2 Avnet Mini Expansion Port (MXP)

One 40-pin, 0.254 mm pitch, MXP header supports Avnet Mini Expansion Modules and general-purpose prototyping User
I/Os. 35 FPGA I/Os are connected to a 0.1 2 x 20-pin header J5. Signal names and connector pin/FPGA pin connections are
identified in Table 22.The I/Os Vcco is 3.3 V.

FPGA pin
#
I/O Signal
Connector
Pin #
Connector
Pin #
I/O Signal
FPGA
Pin #
n/a GND 1 2 +5 V n/a
n/a +3.3 V 3 4 MXP_SE_0 L24
Y21 MXP_DIFF_0_P 5 6 MXP_DIFF_0_N AA22
W17 MXP_DIFF_1_P 7 8 MXP_DIFF_1_N W18
U15 MXP_DIFF_2_P 9 10 MXP_DIFF_2_N V16
V11 MXP_DIFF_3_P 11 12 MXP_DIFF_3_N V10
W20 MXP_DIFF_4_P 13 14 MXP_DIFF_4_N Y20
Y17 MXP_DIFF_5_P 15 16 MXP_DIFF_5_N AA17
AA10 MXP_DIFF_6_P 17 18 MXP_DIFF_6_N AB21
AA9 MXP_DIFF_7_P 19 20 MXP_DIFF_7_N AB9
AB22 MXP_DIFF_8_P 21 22 MXP_DIFF_8_N AC22
AC5 MXP_DIFF_9_P 23 24 MXP_DIFF_9_N AD5
R23 MXP_SE_1 25 26 MXP_SE_2 T23
P22 MXP_SE_3 27 28 MXP_SE_4 P21
U22 MXP_SE_5 29 30 MXP_SE_6 R20
R19 MXP_SE_7 31 32 MXP_SE_8 R18
U21 MXP_SE_9 33 34 MXP_SE_10 U19
V21 MXP_SE_11 35 36 MXP_SE_12 AA24
AB24 MXP_SE_13 37 38 MXP_SE_14 AC23
n/a GND 39 40 GND n/a
Table 22 - Mini-Expansion Port (MXP) Pin Connections

2.9.3 PMOD Headers

Two vertical, 12-pin (2 x 6 female) Peripheral Module (PMOD) headers (J4, J6) are interfaced to the FPGA, with each header
providing 3.3 V power, ground, and eight I/Os. These headers may be utilized as general-purpose I/Os or may be used to
interface to PMODs. J4 and J6 are placed in close proximity (09-centers) on the PCB in order to support dual PMODs.
Tables 23 and 24 provide the connector and FPGA pin-out. For Digilent PMODs see:
http://www.digilentinc.com/Products/Catalog.cfm?Nav1=Products&Nav2=Peripheral&Cat=Peripheral


FPGA
pin #
I/O Signal
Connector
Pin #
Connector
Pin #
I/O Signal
FPGA
Pin #
L23 FPGA_PMOD2_P1 1 2 FPGA_PMOD2_P2 T24
V24 FPGA_PMOD2_P3 3 4 FPGA_PMOD2_P4 W25
- GND 5 6 +3.3V_LS1 -
R24 FPGA_PMOD2_P7 7 8 FPGA_PMOD2_P8 T26
V26 FPGA_PMOD2_P9 9 10 FPGA_PMOD2_P10 W26
- GND 11 12 +3.3V_LS1 -
Table 23 - Peripheral Module Pin Connections J4

FPGA
pin #
I/O Signal
Connector
Pin #
Connector
Pin #
I/O Signal
FPGA
Pin #
Y24 FPGA_PMOD1_P1 1 2 FPGA_PMOD1_P2 AA25
AC25 FPGA_PMOD1_P3 3 4 FPGA_PMOD1_P4 AE25
- GND 5 6 +3.3V_LS1 -
Y26 FPGA_PMOD1_P7 7 8 FPGA_PMOD1_P8 AA26
AD26 FPGA_PMOD1_P9 9 10 FPGA_PMOD1_P10 AE26
- GND 11 12 +3.3V_LS1 -
Table 24 - Peripheral Module Pin Connections J6

2.10 EEPROM with SHA
The Spartan-6 LX75T development board has a 1 Kb EEPROM that implements the ISO/IEC 10118-3 Secure Hash Algorithm
(SHA-1) for added FPGA design security. The Maxim DS28E01-100 is the device used and is referenced as U10 on the PCB.
The DS28E01-100 is connected to the Spartan-6 FPGA with only one bidirectional signal. The table below lists the signal
name and the FPGA pin assigned to it.

FPGA Pin # I/O Signal
N24 SHA1_PROM
Table 25 - SHA-1 EEPROM Pin Connections

2.11 MAX1409 ADC/DAC/RTC
The Spartan-6 LX75T development board has a Maxim MAX1409 on board. The MAX1409 is a low power, multi-channel
Data Acquisition System (DAS). The MAX1409 is a 20-pin version of the DAS family with a differential 4:1 input
multiplexer to the ADC, one auxiliary analog input, and one 10-bit force/sense DAC. It also features a real-time clock.
Refer to the manufacturers data sheet for more details on this device.

The input and output channels of the MAX1409 are connected to the 4-pin headerJ10 for the user to access. There is
no signal filtering or gain circuitry on the Spartan-6 LX75T development board. All signal filtering or gain optimizations must
occur off-board.

The table below shows the pin-out of J10

J10 Pin # Signal Name
1 GND
2 MAX1409_IN
3 MAX1409_OUT
4 GND
Table 26 - MAX1409 Pin Assignments J10


The table below shows the connections between the MAX1409 communication and control signals and the Spartan-6 FPGA.

FPGA Pin # Signal Name
P19 DAC_SCLK
N21 DAC_DIN
N22 DAC_DOUT
N23 DAC_CS#
P17 DAC_WAKE#
Table 27 - MAX1409 Pin Connections

2.12 Power
The Spartan-6 LX75T development board requires a 12 V DC power input. This can be obtained from:

Optional 12 V DC, 60 W power supply (PN: AES-SLP-12V5A-G, requires adapter cable on next line)
Optional adapter cable (PN: AES-S6PCIE-PS6C-G)
The 12 V rail of the PCI Express edge connector
The adapter cable to connect the LX75T board to the Emerson NITX-315 SBC (included in AES-S6NITX-LX75T-AOK-G
and AES-S6NITX-LX75T-G kits)

Please note that power over the PCI Express connector is limited to 6 W. When powered from the optional external 12 V
supply 60 W of power is available. The current requirements for the board are application specific.

All of the voltage rails used on the board are derived from the 12 V source, either directly or indirectly. They are 5.0V, 3.3V,
FMC_3.3V, 2.5, 1.5V and 1.2V, MGT_CORE_1.2V, MGT_TERM_1.2V, DDR_REF (0.75V), and DDR_TERM (0.75V).

The main power switch to for the development board is SW1 and must be turned ON to supply any power to the board.

The figure below shows a high-level block diagram of the main power supplies on the development board.


PCI
Express
Card
Edge
Spartan-6
FG676
DDR3
12V 5.0V
1.5V
TPS54317
1.2V @ 3A
(MGT_TERM)
TPS54317
1.2V @ 3A
(MGT_CORE)
4-pin
ATX Connector
J2
TPS54320
1.5V @3A
TPS54320
1.2V @ 3A
TPS65251
3.3V @ 3A
FMC_3.3V @ 2A
5.0V @ 2A
LP2998
DDR_TERM_0.75V
DDR_REF_0.75V
2.5V
2.5V
1.2V
3.3V
3.3V 1.2V
1.2V
FMC
JX1
GTP
1.5V
3.3V
FMC_3.3V
MXP
TPS54320
2.5V @ 3A
12V

Figure 16 - Power Supply Bock Diagram

2.12.1 FPGA I/O Voltage (VCCO)

The following table shows how the Spartan-6 FPGA banks are powered.

Bank # 1.5 V 2.5 V 3.3 V
0 x
1 x
2 x
3 x
4 x
5 x
Table 28 - I/O Bank Voltages

2.12.2 FPGA Reference Voltage (Vref)
The Spartan-6 LX75T development board provides the reference voltage of +0.75 V to Banks 4 and 5 which are connected to
the DDR3 memory interfaces.

2.12.3 GTP Voltage Regulators (AVCC, AVCCPLL, VTTRX, VTTTX, AVTTRCAL)
The Spartan-6 LX75T development board provides point-of-load regulation for the GTP supplies with high-precision, low drop-
out linear regulators from Texas Instruments. The TPS54317 regulators provide up to 3.0 amps of current. The low input
voltage requirement minimizes the voltage drop across the regulator saving the added cost of thermal solutions in most
applications. The adjustable output range, down to 0.9V, makes the TPS54317 switchers a good fit for the low voltage GTP
supplies. The small 5.15 mm x 4.15 mm PQFP packages are ideal for space limited applications like PCI form-factor add-in
cards. The following figure shows a high-level block diagram of the GTP power supplies.

The following table contains estimated current utilization for the GTP rails based on the Spartan-6 datasheet.


Net Name MGT Rails
Current Consumption per tile
Min Typical Max
MGT_TERM_1.2V
MGTVTTTX - 27.4 -
MGTVTTRX - 13.6 -
MGT_CORE_1.2V
MGTAVCC - 40.4 -
MGTAVCCPLL - 28.7 -
Table 29 - Typical Current Measurements per MGT Tile
2.13 Thermal Management
The Spartan-6 LX75T FPGA on the development board may require a heat sink to keep the junction temperate within the
operating limits of the device. A heat sink requirement will be a function of the application in which the Spartan-6 LX75T FPGA
is being used for. The amount of power that needs to be dissipated is design dependent. The main contributors to the overal l
power are utilization, frequency and the number of active RocketIO transceivers. The Spartan-6 LX75T development board
does not come with a heat sink. Aavid is a known supplier that has provided heat sink solutions for Xilinx FPGAs in the past.
More information is available on Aavids web site: http://www.aavidthermalloy.com/products/bga/index.shtml.

3.0 Test Designs

This section describes the factory test design that is pre-programmed into the configuration SPI flash and also provided on the Design
Resource Center (DRC) web site: www.em.avnet.com/spartan6lx75t-pcie. The factory test design is used to verify some of the
functionality of the board and may require additional test apparatus.

If the SPI flashed has been erased or modified, the MCS image file containing the test design is available on the Design Resource
Center web site: www.em.avnet.com/spartan6lx75t-pcie. The SPI flash can be re-programmed by using the Xilinx iMPACT software.
The Factory test design available on the DRC web site use a terminal session as the user interface. Using a straight-through serial
cable, connect the Spartan-6 LX75T development board to a PC. Open a terminal session and configure it for 9600 baud, 8 data bits,
no parity, 1 stop bit and no flow control (9600-8-N-1-N).
3.1 Factory Test
The Factory Test verifies the electrical connectivity of the DDR3 SDRAM, flash memory, FMC LPC Connector, MXP
connector, the PMOD interface connectors and the user LEDs, buttons and switches. The user can initiate the tests by typing
test <enter> in a terminal session configured as shown in Section 3.0. Some of the tests require user inputs and observation
(watching the LEDs and pressing the switches). Some of the tests require special test fixtures and/or apparatus for the tests to
complete that are not included in the Spartan-6 LX75T Development Board kit. The cumulative results are displayed at the
completion of test processes. Individual tests can be executed by typing help at the prompt and then typing the proper
command for the desired test.

NOTE: The factory test code is executed from the MCB4 DDR3 interface. Executing the factory test for the DDR3
interface on MCB4 will overwrite the factory test code and cause it to stop executing. A power-on reset or pushing the
PROG button will restore the factory test code.

The factory test also provides a means to test the Ethernet interface. The Ethernet interface is enabled upon configuration of
the FPGA with the factory test. The Ethernet Test design provides the user with the ability to ping the Spartan-6 LX75T
development board to verify network connectivity via the on-board National 10/100 Mbps Ethernet PHY. The National PHY
supports auto-MDIX mode, which allows either a straight-through or a cross-over Ethernet cable to be used. The default IP
address of the board is 192.168.1.10. To ping the board, plug an Ethernet cable into the RJ45 connector labeled J7. Then
change the IP address and the subnet of the PC its connected to by configuring the network adapter settings to the following:

IP Address: 192.168.1.1
Subnet Mask: 255.255.255.0

Power up the Spartan-6 FPGA LX75T development board. Then open a command shell on the PC (Start Menu -> Run, cmd)
and type ping 192.168.1.10. You will see four replies to the ping request.


Appendix A

This section provides a description of the jumper settings for the Spartan-6 LX75T development board. The board is ready to use out of
the box with the default jumper settings. The following figure depicts a map of the component side of the board with
Jumper/Header/Connector locations detailed. The jumper sites are colored pink below.

Figure 17 - Board Jumpers, Headers, Connectors

JP1 WP Flash Write-protect Enable, install a shunt in the 2:3 position to protect programmed data in the Flash memory. Default:
JP1: 1-2, read/write enabled (unprotected).

JP2 JTAG JP2 is used to include or exclude the FMC connector JX1 in the JTAG chain. When the jumper is placed in the 1-2
position only the FPGA is included in the chain. When the jumper is placed in the 2-3 position both the FPGA and the FMC connector
are included in the JTAG chain. Default: JP2: 1-2.

JP3 Selects the FPGA configuration mode. When a jumper is placed across pins 1-3 Master Serial/SPI mode is selected. If the SPI
flash is programmed with a compatible configuration image the FPGA will configure from the SPI flash. No other jumper selections are
valid on this jumper. JTAG configuration overrides any and all configuration modes.

J1 JTAG A ribbon cable connector used by the Xilinx Parallel Cable IV and Platform Cable USB.

J2 4-pin ATX power connector. 12 V only.

J3 Micro-USB jack. This interface provides a UART interface to the FPGA via a USB cable.

J4 and J6 PMOD expansion connectors.

J5 MXP Expansion header.

J7 Ethernet 10/100 RJ-45 jack.

J8 SUSP Placing a jumper enable the FPGAs suspend feature.
Spartan-6
U13
LED0 LED3
RJ45
Connector
J7
DDR3
U8
SW7
SW8 SW9
F
M
C

L
P
C

C
o
n
n
e
c
t
o
r
J
X
1
J
P
2
J10
J
T
A
G
J
1
ATX
PWR
J2
JP3
JP1
USB-
RS232
Connector
J3
SW1
Flash
U2
M
X
P
J
5
DDR3
U14
P
M
O
D
J
4
P
M
O
D
J
6
SW2 SW3 SW4 SW5 SW6
J
P
8
J
P
9


J9 HSWAP Enables pull-ups on the Spartan-6 I/O pins during configuration. Install a jumper to enable the configuration pull-ups.
Default: Open; pull-ups disabled.

JX1 FMC LPC expansion connector.

J10 MAX1409 interface header.

SW1 POWER Main power switch for the board.

SW2-SW5 User push buttons.

SW6 PROG Depressing and releasing this switch will force the FPAG to reconfigure itself from the SPI flash.

SW7 This four-position DIP-switch can be used as GPIO to the Spartan-6 FPGA. The switch(s) logic level is default LOW until the
switch is toggled. When toggled ON, the logic level to the IO pin is HIGH (3.3 V).

SW8 and SW9 PR[1:0] and OD[2:0] These switches control the output frequency of the CDM61002 LVDS clock synthesizer. Refer
to section 2.4.1 for more details.

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